; -------------------------------------------------------------------------------- ; @Title: OMAP4430 On-Chip Peripherals ; @Props: Released ; @Author: KAM, KRU, LEM, SLA ; @Changelog: ; 2011-02-03 ; 2011-04-20 ; 2011-08-31 ; 2011-12-13 ; 2012-04-18 ; @Manufacturer: TI - Texas Instruments ; @Doc: XML GENERATED ; @Core: Cortex-A9 ; @Chip: OMAP4430 ; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: peromap4430app.per 7398 2016-10-27 13:54:53Z askoncej $ config 16. 8. ; ; WARNING: EXPORT NOTICE ; ; Recipient agrees to not knowingly export or re-export, directly or ; indirectly, any product or technical data (as defined by the U.S., EU, and ; other Export Administration Regulations) including software, or any ; controlled product restricted by other applicable national regulations, ; received from Disclosing party under this Agreement, or any direct ; product of such technology, to any destination to which such export or ; re-export is restricted or prohibited by U.S. or other applicable laws, ; without obtaining prior authorisation from U.S. Department of Commerce ; and other competent Government authorities to the extent required by ; those laws. This provision shall survive termination or expiration of this ; Agreement. ; ; According to our best knowledge of the state and end-use of this ; product or technology, and in compliance with the export control ; regulations of dual-use goods in force in the origin and exporting ; countries, this technology is classified as follows: ; ; US ECCN: 3E991 ; EU ECCN: EAR99 ; ; And may require export or re-export license for shipping it in compliance ; with the applicable regulations of certain countries. ; ; base ad:0x00000000 tree "Core Registers (Cortex-A9MPCore)" width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x0++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" textline " " bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x200++0x0 line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register" rgroup.long c15:0x300++0x0 line.long 0x0 "TLBTR,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries" bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128" textline " " bitfld.long 0x0 0. " nU ,Unified or Separate TLBs" "Unified,Separate" rgroup.long c15:0x500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 8.--11. " ClusterID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "0,1,2,3" rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..." bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported" bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Not supported,Supported,?..." rgroup.long c15:0x0020++0x00 line.long 0x00 "ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..." tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " PARON ,Parity On" "Disabled,Enabled" bitfld.long 0x00 8. " ALIOW ,Enable allocation in one cache way only" "Disabled,Enabled" bitfld.long 0x00 7. " EXCL ,Exclusive cache Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SMP ,Signals if the Cortex-A9 processor is taking part in coherency or not" "0,1" bitfld.long 0x00 3. " FOZ ,Full Of Zero mode Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DP1 ,L1 Dside prefetch Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PH2 ,L2 prefetch hint Enable" "Disabled,Enabled" bitfld.long 0x00 0. " FW ,Cache and TLB maintenance broadcast" "Disabled,Enabled" group.long c15:0x201++0x0 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x11++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 6. " nET ,Not early termination" "Not early,Early" bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" textline " " bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group.long c15:0x111++0x0 line.long 0x0 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted" bitfld.long 0x00 16. " PLE ,NS accesses to the Preload Engine resources control" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register" "No,Yes" bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted" group.long c15:0x0311++0x00 line.long 0x00 "VCR,Virtualization Control Register" bitfld.long 0x00 8. " AMO ,Abort Mask Override" "0,1" bitfld.long 0x00 7. " IMO ,IRQ Mask Override" "0,1" bitfld.long 0x00 6. " IFO ,FIQ Mask Override" "0,1" group.long c15:0xf++0x0 line.long 0x00 "PCR,Power Control Register" bitfld.long 0x00 8.--10. " MCL ,Max Clock Latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EDCG ,Enable Dynamic Clock Gating" "Disabled,Enabled" textline " " group.long c15:0x000c++0x00 line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address" group.long c15:0x10c++0x00 line.long 0x0 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address" rgroup.long c15:0x1C++0x0 line.long 0x0 "ISR,Interrupt status Register" bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending" bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending" bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending" group.long c15:0x11c++0x0 line.long 0x00 "VIR,Virtualization Interrupt Register" bitfld.long 0x00 8. " VA ,Virtual Abort" "0,1" bitfld.long 0x00 7. " VI ,Virtual IRQ" "0,1" bitfld.long 0x00 6. " VF ,Virtual FIQ" "0,1" tree.end width 0x0d tree "Memory Management Unit" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" textline " " group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address" bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" textline " " bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address" bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" textline " " bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable" bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable" bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000" textline " " group.long c15:0x3--0x3 line.long 0x0 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" hexmask.long 0x00 0.--31. 1. " DFA ,Data Fault Address" group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " SD ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" hexmask.long 0x00 0.--31. 1. " IFA ,Instruction Fault Address" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" hexmask.long 0x00 0.--31. 1. " DAFS ,Data Auxiliary Fault Status" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,AuxiliaryInstruction Fault Status Register" hexmask.long 0x00 0.--31. 1. " IAFS ,Instruction Auxiliary Fault Status" textline " " group.long c15:0xa++0x0 line.long 0x0 "TLBLR,TLB Lockdown Register" bitfld.long 0x0 28.--29. " VICTIM ,Victim Value Increments after Each Tabel Walk" "0,1,2,3" bitfld.long 0x0 0. " P ,Lockdown by Victim or Set Associative Region of TLB" "Associative,Lockdown" group.long c15:0x0047++0x00 line.long 0x00 "PAR,PA Register" hexmask.long 0x00 12.--31. 0x1000 " PA ,Physical Adress" bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable" textline " " bitfld.long 0x00 9. " NS ,Non-secure" "Not secured,Secured" bitfld.long 0x00 7. " SH ,Shareable attribute" "Non-shareable,Shareable" textline " " bitfld.long 0x00 4.--6. " Inner ,Signals region inner attributes" "Noncacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back allocate,Write-through,Write-back" bitfld.long 0x00 2.--3. " Outer ,Signals region outer attributes for normal memory type" "Noncacheable,Write-back allocate,Write-through,Write-back" textline " " bitfld.long 0x00 1. " SS ,Supersection Enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " F ,Translation Successful" "Successful,No successful" textline " " group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attribute 7" "Outer,Inner" bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attribute 6" "Outer,Inner" textline " " bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attribute 5" "Outer,Inner" bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attribute 4" "Outer,Inner" textline " " bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attribute 3" "Outer,Inner" bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attribute 2" "Outer,Inner" textline " " bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attribute 1" "Outer,Inner" bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attribute 0" "Outer,Inner" textline " " bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " group.long c15:0x400f++0x0 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long 0x00 0.--31. 1. " CBA ,Configuration Base Address" textline " " rgroup.long c15:0x000d++0x00 line.long 0x00 "FCSEIDR,FCSE PID Register" hexmask.long.byte 0x00 25.--31. 0x02 " PID ,Process for Fast Context Switch Identification and Specification" group.long c15:0x10d++0x0 line.long 0x0 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID" hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID" group.long c15:0x020d++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRURW ,User Read/Write Thread ID" group.long c15:0x030d++0x00 line.long 0x00 "TPIDRURO,User Read-only Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRURO ,User Read-only Thread ID" group.long c15:0x040d++0x00 line.long 0x00 "TPIDRPRW,Privileged Only Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRPRW ,Privileged Only Thread ID" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 18.--20. " CType7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 15.--17. " CType6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 12.--14. " CType5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 9.--11. " CType4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 6.--8. " CType3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 3.--5. " CType2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 0.--2. " CType1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words" group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction" tree.end width 12. tree "System Performance Monitor" group.long c15:0xC9++0x0 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled" group.long c15:0x1C9++0x0 line.long 0x0 "PMCNTENSET,Count Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x2C9++0x0 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x3C9++0x0 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. " P4 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4C9++0x0 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 5. " P5 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 4. " P4 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" textline " " eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x5C9++0x0 line.long 0x0 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--5. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,CNT4,CNT5,?..." group.long c15:0xD9++0x0 line.long 0x00 "PMCCNTR,Cycle Count Register" hexmask.long 0x00 0.--31. 1. " CCNT ,Cycle Count" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Select Register" hexmask.long.byte 0x00 0.--7. 1. " EVCNT ,Event to count" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" hexmask.long 0x00 0.--31. 1. " PMNX ,Event Count" group.long c15:0xE9++0x0 line.long 0x0 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled" group.long c15:0x1E9++0x0 line.long 0x0 "PMINTENSET,Interrupt Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2E9++0x0 line.long 0x0 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" tree.end width 8. tree "Preload Engine" rgroup.long c15:0x000b++0x00 line.long 0x00 "PLEIDR,PLE ID Register" bitfld.long 0x00 16.--20. " FIFOS ,PLE FIFO size" "Not present,Reserved,Reserved,Reserved,4,Reserved,Reserved,Reserved,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,?..." bitfld.long 0x00 0. " PEP ,Preload Engine presence" "Not present,Present" rgroup.long c15:0x020b++0x00 line.long 0x00 "PLEASR,PLE Activity Status Register" bitfld.long 0x00 0. " R ,PLE Channel running" "Not running,Running" rgroup.long c15:0x040b++0x00 line.long 0x00 "PLEFSR,PLE FIFO Status Register" bitfld.long 0x00 0.--4. " AE ,Number of available entries in the PLE FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x001b++0x00 line.long 0x00 "PLEUAR,Preload Engine User Accessibility Register" bitfld.long 0x00 0. " U ,User accessibility" "Not permited,Permited" group.long c15:0x011b++0x00 line.long 0x00 "PLEPCR,Preload Engine Parameters Control Register" hexmask.long.word 0x00 16.--29. 1. " BSM ,Block size mask" hexmask.long.byte 0x00 8.--15. 1. " BNM ,Block number mask" hexmask.long.byte 0x00 0.--7. 1. " WS ,PLE wait states" tree.end tree "NEON" rgroup.long c15:0x000f++0x00 line.long 0x00 "NEON,NEON busy Register" bitfld.long 0x00 0. " Busy ,NEON busy" "Not busy,Busy" tree.end width 0xb width 9. tree "Debug Registers" tree "Jazelle Register" group.long c14:0x7000++0x0 line.long 0x00 "JIDR,Jazelle ID Register" bitfld.long 0x00 28.--31. " ARCH ,Architecture code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DESIGN ,Implementor code of the designer of the subarchitecture" textline " " hexmask.long.byte 0x00 12.--19. 1. " SAMAJ ,The subarchitecture code" bitfld.long 0x00 8.--11. " SAMIN ,The subarchitecture minor code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6. " TRTBFR ,Format of the Jazelle Configurable Opcode Translation Table Register" "0,1" bitfld.long 0x00 0.--5. " TRTBSZ ,Size of the Jazelle Configurable Opcode Translation Table Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long c14:0x7001++0x0 line.long 0x00 "JOSCR,Jazelle OS Control Register" bitfld.long 0x00 1. " CV ,Configuration Valid" "Not valid,Valid" bitfld.long 0x00 0. " CD ,Configuration Disabled" "No,Yes" group.long c14:0x7002++0x0 line.long 0x00 "JMCR,Jazelle Main Configuration Register" bitfld.long 0x00 31. " nAR ,Not Array Operations" "Disabled,Enabled" bitfld.long 0x00 30. " FP ,Floating-point opcodes handler" "VM implementation,VFP instructions" bitfld.long 0x00 29. " AP ,Array Pointer" "Handler,Pointer" textline " " bitfld.long 0x00 28. " OP ,Object Pointer" "Handler,Pointer" bitfld.long 0x00 27. " IS ,Index Size" "8 bits,16 bits" bitfld.long 0x00 26. " SP ,Static Pointer" "Handler,Pointer" textline " " bitfld.long 0x00 0. " JE ,Jazelle Enable" "Disabled,Enabled" group.long c14:0x7003++0x0 line.long 0x00 "JPR,Jazelle Parameters Register" bitfld.long 0x00 17.--21. " BSH ,Bounds SHift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " sADO ,Signed Array Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " ARO ,Array Reference Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " STO ,STatic Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ODO ,Object Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long c14:0x7004++0x0 line.long 0x00 "JCOTTRR,Jazelle Configurable Opcode Translation Table Register" bitfld.long 0x00 10.--15. " OPCODE ,Bottom bits of the configurable opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " OPERATION ,Code for the operation" "0,1,2,3,4,5,6,7,8,9,?..." tree.end width 11. tree "Processor Identifier Registers" rgroup c14:0x340--0x340 line.long 0x00 "CPUID,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup c14:0x341--0x341 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DMinLine ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." textline " " bitfld.long 0x00 14.--15. " L1_Ipolicy ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " IMinLine ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup c14:0x343--0x343 line.long 0x00 "TLBTYPE,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILsize ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLsize ,Specifies the number of unified or data TLB lockable entries" textline " " bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128" bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate" rgroup c14:0x348--0x348 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..." rgroup c14:0x349--0x349 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..." rgroup c14:0x34a--0x34a line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..." rgroup c14:0x34c--0x34c line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..." textline " " bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..." rgroup c14:0x34d--0x34d line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup c14:0x34e--0x34e line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." rgroup c14:0x34f--0x34f line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup c14:0x350--0x350 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..." rgroup c14:0x351--0x351 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..." rgroup c14:0x352--0x352 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..." rgroup c14:0x353--0x353 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..." rgroup c14:0x354--0x354 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..." tree.end tree "Coresight Management Registers" width 0xC textline " " group c14:0x3c0--0x3c0 line.long 0x0 "ITCTRL,Integration Mode Control Register" bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group c14:0x3e8--0x3e8 line.long 0x0 "CLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set" group c14:0x3e9--0x3e9 line.long 0x0 "CLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared" wgroup c14:0x3ec--0x3ec line.long 0x0 "LAR,Lock Access Register" hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key" rgroup c14:0x3ed--0x3ed line.long 0x0 "LSR,Lock Status Register" bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed" bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored" textline " " bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required" width 0xc rgroup c14:0x3ee--0x3ee line.long 0x0 "AUTHSTATUS,Authentication Status Register" bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented" bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented" bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented" bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented" bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled" width 0xc rgroup c14:0x3f2--0x3f2 line.long 0x0 "DEVID,Device Identifier" bitfld.long 0x00 0.--3. " PCSAMPLE ,Level of Program Counter sampling support (DBGPCSR and DBGCIDSR)" "Not implemented,DBGPCSR,Both,?..." rgroup c14:0x3f3--0x3f3 line.long 0x0 "DEVTYPE,Device Type" hexmask.long.byte 0x0 4.--7. 1. " STPC ,Sub Type: Processor Core" hexmask.long.byte 0x0 0.--3. 1. " MCDL ,Main Class: Debug Logic" rgroup c14:0x3f8--0x3f8 line.long 0x0 "PID0,Peripherial ID0" hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]" rgroup c14:0x3f9--0x3f9 line.long 0x0 "PID1,Peripherial ID1" hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]" hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]" rgroup c14:0x3fa--0x3fa line.long 0x0 "PID2,Peripherial ID2" hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " JEPCD ,JEP 106 ID code" "Not used,Used" textline " " hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]" rgroup c14:0x3fb--0x3fb line.long 0x0 "PID3,Peripherial ID3" hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd" hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified" rgroup c14:0x3f4--0x3f4 line.long 0x0 "PID4,Peripherial ID4" bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" rgroup c14:0x3fc--0x3fc line.long 0x0 "COMPONENTID0,Component ID0" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3fd--0x3fd line.long 0x0 "COMPONENTID1,Component ID1" hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)" hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble" rgroup c14:0x3fe--0x3fe line.long 0x0 "COMPONENTID2,Component ID2" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3ff--0x3ff line.long 0x0 "COMPONENTID3,Component ID3" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" tree.end textline " " width 0x7 rgroup c14:0x000--0x000 line.long 0x0 "DIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x0 16.--19. " Version ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,ARMv7 no ext.,?..." textline " " bitfld.long 0x0 15. " DEVID_IMP ,Debug Device ID Register DBGDEVID implemented" "Not implemented,Implemented" bitfld.long 0x0 14. " NSUHD_IMP ,Secure User halting debug implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 13. " PCSR_IMP ,Program Counter Sampling Register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " SE_IMP ,Security Extensions implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 4.--7. " Variant ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " Revision ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x7 group c14:0x22--0x22 line.long 0x0 "DSCR,Debug Status and Control Register" bitfld.long 0x0 30. " DTRRXfull ,The DTRRX Full Flag" "Empty,Full" bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full" textline " " bitfld.long 0x00 27. " DTRRXfull_l ,The DTRRX Full Flag 1" "Empty,Full" bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full" textline " " bitfld.long 0x0 25. " PIPEADV ,Sticky Pipeline Advance" "No effect,Instruction retired" bitfld.long 0x0 24. " INSTRCOMPL_L ,Latched Instruction Complete" "Executing,Not executing" textline " " bitfld.long 0x0 20.--21. " EXTDCCMODE ,External DCC access mode" "Non-blocking,Stall,Fast,?..." bitfld.long 0x0 19. " ADADISCARD ,Asynchronous Data Aborts Discarded" "Not discarded,Discarded" textline " " bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured" bitfld.long 0x0 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disabled" "No,Yes" textline " " bitfld.long 0x0 16. " SPIDDIS ,Secure Privileged Invasive Debug Disabled" "No,Yes" bitfld.long 0x0 15. " MDBGEN ,Monitor Debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled" bitfld.long 0x0 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " UDCCDIS ,User mode access to Comms Channel disable" "No,Yes" bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "No,Yes" textline " " bitfld.long 0x0 10. " DbgAck ,Force Debug Acknowledge" "Not forced,Forced" bitfld.long 0x0 8. " UND_l ,Sticky Undefined Instruction" "No exception,Exception" textline " " bitfld.long 0x0 7. " ADABORT_l ,Sticky Asynchronous Data Abort" "Not aborted,Aborted" bitfld.long 0x0 6. " SDABORT_l ,Sticky Synchronous Data Abort" "Not aborted,Aborted" textline " " bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Halt request,Breakpoint,Asynchronous Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited" textline " " bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state" width 0x7 if (((data.long(c14:0x00))&0x01000)==0x00000) group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled" bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" else group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled" bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled" bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" endif ;rgroup c14:0x1++0x1 ; line.long 0x0 "DRAR,Debug ROM Address Register" ; hexmask.long 0x0 12.--31. 0x1000 " DBROMPA ,Debug bus ROM physical address" ; bitfld.long 0x0 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid" ; line.long 0x4 "DSAR,Debug Self Address Offset Register" ; hexmask.long 0x4 12.--31. 0x1000 " DBSAOV ,Debug bus self-address offset value" ; bitfld.long 0x4 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid" ;hgroup c14:0x50++0x0 ; hide.long 0x0 "DTR,Data Transfer Register" ; in width 0x7 hgroup c14:0x020--0x020 hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register" in group c14:0x023--0x023 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" wgroup c14:0x21++0x00 line.long 0x00 "ITR,Instruction Transfer Register" hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute" wgroup c14:0x24++0x00 line.long 0x00 "DRCR,Debug Run Control Register" bitfld.long 0x00 4. " CBIUR , Cancel Bus Interface Unit Requests" "Not canceled,Canceled" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared" bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested" rgroup c14:0xc4++0x00 line.long 0x00 "PRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 2. " HNDLR ,Hold non-debug logic reset" "No reset,Reset" bitfld.long 0x00 1. " WRR ,Warm reset request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high" hgroup c14:0xc5++0x00 hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register" in tree.end width 6. tree "Breakpoint Registers" group c14:0x40++0x00 line.long 0x00 "BVR0,Breakpoint Value Register 0" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group c14:0x50++0x00 line.long 0x00 "BCR0,Breakpoint Control Register 0" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x41++0x00 line.long 0x00 "BVR1,Breakpoint Value Register 1" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group c14:0x51++0x00 line.long 0x00 "BCR1,Breakpoint Control Register 1" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x42++0x00 line.long 0x00 "BVR2,Breakpoint Value Register 2" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group c14:0x52++0x00 line.long 0x00 "BCR2,Breakpoint Control Register 2" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x43++0x00 line.long 0x00 "BVR3,Breakpoint Value Register 3" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group c14:0x53++0x00 line.long 0x00 "BCR3,Breakpoint Control Register 3" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x44++0x00 line.long 0x00 "BVR4,Breakpoint Value Register 4" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group c14:0x54++0x00 line.long 0x00 "BCR4,Breakpoint Control Register 4" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x45++0x00 line.long 0x00 "BVR5,Breakpoint Value Register 5" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group c14:0x55++0x00 line.long 0x00 "BCR5,Breakpoint Control Register 5" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end width 6. tree "Watchpoint Control Registers" group c14:0x60++0x00 line.long 0x00 "WVR0,Watchpoint Value Register 0" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group c14:0x70--0x70 line.long 0x0 "WCR0,Watchpoint Control Register 0" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x61++0x00 line.long 0x00 "WVR1,Watchpoint Value Register 1" hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1" group c14:0x71--0x71 line.long 0x0 "WCR1,Watchpoint Control Register 1" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x62++0x00 line.long 0x00 "WVR2,Watchpoint Value Register 2" hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2" group c14:0x72--0x72 line.long 0x0 "WCR2,Watchpoint Control Register 2" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x63++0x00 line.long 0x00 "WVR3,Watchpoint Value Register 3" hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3" group c14:0x73--0x73 line.long 0x0 "WCR3,Watchpoint Control Register 3" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x006--0x006 line.long 0x0 "WFAR,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction" tree.end width 0xb width 9. base ad:(d.l(c15:0x400f)) tree "Snoop Control Unit (SCU)" group.long 0x00++0x03 line.long 0x00 "SCUCR,SCU Control Register" bitfld.long 0x00 6. " ICSE ,IC standby enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCUSE ,SCU standby enable" "Disabled,Enabled" bitfld.long 0x00 4. " FADTP0E ,Force all Device to port0 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SCUSLE ,SCU Speculative linefills enable" "Disabled,Enabled" bitfld.long 0x00 2. " SCURPE ,SCU RAMs Parity enable" "Disabled,Enabled" bitfld.long 0x00 1. " AFE ,Address filtering enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SCUE ,SCU enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SCUCON,SCU Configuration Register" bitfld.long 0x00 14.--15. " RAM3 ,Cortex-A9 CPU3 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 12.--13. " RAM2 ,Cortex-A9 CPU2 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 10.--11. " RAM1 ,Cortex-A9 CPU1 Tag RAM Size" "16KB,32KB,64KB,?..." textline " " bitfld.long 0x00 8.--9. " RAM0 ,Cortex-A9 CPU0 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 7. " MOD3 ,CPU3 Mode" "AMP,SMP" bitfld.long 0x00 6. " MOD2 ,CPU2 Mode" "AMP,SMP" textline " " bitfld.long 0x00 5. " MOD1 ,CPU1 Mode" "AMP,SMP" bitfld.long 0x00 4. " MOD0 ,CPU0 Mode" "AMP,SMP" bitfld.long 0x00 0.--1. " NUM ,CPU Number" "CPU0,CPU0-CPU1,CPU0-CPU2,CPU0-CPU3" group.long 0x08++0x03 line.long 0x00 "SCUSTAT,SCU CPU Power Status Register" bitfld.long 0x00 24.--25. " STAT3 ,CPU3 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 16.--17. " STAT2 ,CPU2 Status" "Normal,Reserved,Dormant,Powered-off" textline " " bitfld.long 0x00 8.--9. " STAT1 ,CPU1 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 0.--1. " STAT0 ,CPU0 Status" "Normal,Reserved,Dormant,Powered-off" wgroup.long 0x0c++0x03 line.long 0x00 "INV,SCU Invalidate All Register" bitfld.long 0x00 12.--15. " WAY3 ,Cortex-A9 CPU3 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " WAY2 ,Cortex-A9 CPU2 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " WAY1 ,Cortex-A9 CPU1 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " WAY0 ,Cortex-A9 CPU0 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x03 line.long 0x00 "FSAR,Filtering Start Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FSA ,Filtering start address" group.long 0x44++0x03 line.long 0x00 "FEAR,Filtering End Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FEA ,Filtering end address" group.long 0x50++0x03 line.long 0x00 "SAC,SCU Access Control Register" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" group.long 0x54++0x03 line.long 0x00 "SSAC,SCU Secure Access Control Register" bitfld.long 0x00 11. " GCPU3 ,Global timer for CPU3" "Secure only,Secure/Non-secure" bitfld.long 0x00 10. " GCPU2 ,Global timer for CPU2" "Secure only,Secure/Non-secure" bitfld.long 0x00 9. " GCPU1 ,Global timer for CPU1" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 8. " GCPU0 ,Global timer for CPU0" "Secure only,Secure/Non-secure" bitfld.long 0x00 7. " TCPU3 ,Private timer for CPU3 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 6. " TCPU2 ,Private timer for CPU2 Access" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 5. " TCPU1 ,Private timer for CPU1 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 4. " TCPU0 ,Private timer for CPU0 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" tree.end width 0xb width 8. tree "Timer and Watchdog Blocks" base ad:(d.l(c15:0x400f))+0x600 group.long 0x00++0xb "Timer" line.long 0x00 "TLR,Timer Load Register" line.long 0x04 "TCR,Timer Counter Register" line.long 0x08 "TCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " AREL ,Auto reload" "Single shot,Auto-reload" bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "TISR,Timer Interrupt Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x20++0x13 "Watchdog" line.long 0x00 "WLR,Watchdog Load Register" line.long 0x04 "WCR,Watchdog Counter Register" line.long 0x08 "WCONR,Watchdog Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " WDM ,WD Mode" "Timer,Watchdog" bitfld.long 0x08 2. " ITEN ,IT Enable" "Disabled,Enabled" bitfld.long 0x08 1. " AREL ,Auto-Reload" "Single shot,Auto-reload" textline " " bitfld.long 0x08 0. " WEN ,Watchdog Enable" "Disabled,Enabled" line.long 0x0c "WISR,Watchdog Interrupt Status Register" eventfld.long 0x0C 0. " EFLAG ,Event Flag" "0,1" line.long 0x10 "WRSR,Watchdog Reset Sent Register" eventfld.long 0x10 0. " RFLAG ,Reset Flag" "No effect,Reset" wgroup.long 0x34++0x3 line.long 0x00 "WDR,Watchdog Disable Register" base ad:(d.l(c15:0x400f))+0x200 group.long 0x00++0xb "Global Timer" line.long 0x00 "GTLCR,Lower 32-bit Timer Counter Register" line.long 0x04 "GTUCR,Upper 32-bit Timer Counter Register" line.long 0x08 "GTCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "GTSR,Timer Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x10++0xb line.long 0x00 "GTLCOMR,Lower 32-bit Comparator Register" line.long 0x04 "GTUCOMR,Upper 32-bit Comparator Register" line.long 0x08 "GTINCR,Auto-increment Register for Comparator" tree.end width 11. tree.open "Interrupt Controller (PL-390)" width 17. base AD:0x48241000 tree "Distributor Interface" if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" else rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" endif rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..." hexmask.long.word 0x00 12.--23. 1. " REV_NUM ,Returns the revision number of the GIC" textline " " hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure) width 17. tree "Group/Security Registers" group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x0E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x0F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)==0x1F) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1" else hgroup.long 0x00FC++0x03 hide.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end endif width 24. tree "Set/Clear Enable Registers" group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)==0x1F) group.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled" else hgroup.long 0x017C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 22. tree "Set/Clear Pending Registers" group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Disabled,Enabled" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Disabled,Enabled" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Disabled,Enabled" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Disabled,Enabled" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Disabled,Enabled" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Disabled,Enabled" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Disabled,Enabled" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Disabled,Enabled" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Disabled,Enabled" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Disabled,Enabled" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Disabled,Enabled" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Disabled,Enabled" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Disabled,Enabled" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Disabled,Enabled" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Disabled,Enabled" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Disabled,Enabled" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Disabled,Enabled" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Disabled,Enabled" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Disabled,Enabled" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Disabled,Enabled" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Disabled,Enabled" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Disabled,Enabled" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Disabled,Enabled" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Disabled,Enabled" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Disabled,Enabled" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Disabled,Enabled" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Disabled,Enabled" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Disabled,Enabled" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Disabled,Enabled" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Disabled,Enabled" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Disabled,Enabled" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)==0x1F) group.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Disabled,Enabled" else hgroup.long 0x027C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 24. tree "Set/Clear Active Registers" rgroup.long 0x0300++0x03 line.long 0x0 "GICD_ICDABR0,Active Status Register 0" bitfld.long 0x00 31. " ASB31 ,Active Status Bit 31" "Not active,Active" bitfld.long 0x00 30. " ASB30 ,Active Status Bit 30" "Not active,Active" bitfld.long 0x00 29. " ASB29 ,Active Status Bit 29" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB28 ,Active Status Bit 28" "Not active,Active" bitfld.long 0x00 27. " ASB27 ,Active Status Bit 27" "Not active,Active" bitfld.long 0x00 26. " ASB26 ,Active Status Bit 26" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB25 ,Active Status Bit 25" "Not active,Active" bitfld.long 0x00 24. " ASB24 ,Active Status Bit 24" "Not active,Active" bitfld.long 0x00 23. " ASB23 ,Active Status Bit 23" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB22 ,Active Status Bit 22" "Not active,Active" bitfld.long 0x00 21. " ASB21 ,Active Status Bit 21" "Not active,Active" bitfld.long 0x00 20. " ASB20 ,Active Status Bit 20" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB19 ,Active Status Bit 19" "Not active,Active" bitfld.long 0x00 18. " ASB18 ,Active Status Bit 18" "Not active,Active" bitfld.long 0x00 17. " ASB17 ,Active Status Bit 17" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB16 ,Active Status Bit 16" "Not active,Active" bitfld.long 0x00 15. " ASB15 ,Active Status Bit 15" "Not active,Active" bitfld.long 0x00 14. " ASB14 ,Active Status Bit 14" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB13 ,Active Status Bit 13" "Not active,Active" bitfld.long 0x00 12. " ASB12 ,Active Status Bit 12" "Not active,Active" bitfld.long 0x00 11. " ASB11 ,Active Status Bit 11" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB10 ,Active Status Bit 10" "Not active,Active" bitfld.long 0x00 9. " ASB9 ,Active Status Bit 9" "Not active,Active" bitfld.long 0x00 8. " ASB8 ,Active Status Bit 8" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB7 ,Active Status Bit 7" "Not active,Active" bitfld.long 0x00 6. " ASB6 ,Active Status Bit 6" "Not active,Active" bitfld.long 0x00 5. " ASB5 ,Active Status Bit 5" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB4 ,Active Status Bit 4" "Not active,Active" bitfld.long 0x00 3. " ASB3 ,Active Status Bit 3" "Not active,Active" bitfld.long 0x00 2. " ASB2 ,Active Status Bit 2" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB1 ,Active Status Bit 1" "Not active,Active" bitfld.long 0x00 0. " ASB0 ,Active Status Bit 0" "Not active,Active" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" bitfld.long 0x00 31. " ASB63 ,Active Status Bit 63" "Not active,Active" bitfld.long 0x00 30. " ASB62 ,Active Status Bit 62" "Not active,Active" bitfld.long 0x00 29. " ASB61 ,Active Status Bit 61" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB60 ,Active Status Bit 60" "Not active,Active" bitfld.long 0x00 27. " ASB59 ,Active Status Bit 59" "Not active,Active" bitfld.long 0x00 26. " ASB58 ,Active Status Bit 58" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB57 ,Active Status Bit 57" "Not active,Active" bitfld.long 0x00 24. " ASB56 ,Active Status Bit 56" "Not active,Active" bitfld.long 0x00 23. " ASB55 ,Active Status Bit 55" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB54 ,Active Status Bit 54" "Not active,Active" bitfld.long 0x00 21. " ASB53 ,Active Status Bit 53" "Not active,Active" bitfld.long 0x00 20. " ASB52 ,Active Status Bit 52" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB51 ,Active Status Bit 51" "Not active,Active" bitfld.long 0x00 18. " ASB50 ,Active Status Bit 50" "Not active,Active" bitfld.long 0x00 17. " ASB49 ,Active Status Bit 49" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB48 ,Active Status Bit 48" "Not active,Active" bitfld.long 0x00 15. " ASB47 ,Active Status Bit 47" "Not active,Active" bitfld.long 0x00 14. " ASB46 ,Active Status Bit 46" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB45 ,Active Status Bit 45" "Not active,Active" bitfld.long 0x00 12. " ASB44 ,Active Status Bit 44" "Not active,Active" bitfld.long 0x00 11. " ASB43 ,Active Status Bit 43" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB42 ,Active Status Bit 42" "Not active,Active" bitfld.long 0x00 9. " ASB41 ,Active Status Bit 41" "Not active,Active" bitfld.long 0x00 8. " ASB40 ,Active Status Bit 40" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB39 ,Active Status Bit 39" "Not active,Active" bitfld.long 0x00 6. " ASB38 ,Active Status Bit 38" "Not active,Active" bitfld.long 0x00 5. " ASB37 ,Active Status Bit 37" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB36 ,Active Status Bit 36" "Not active,Active" bitfld.long 0x00 3. " ASB35 ,Active Status Bit 35" "Not active,Active" bitfld.long 0x00 2. " ASB34 ,Active Status Bit 34" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB33 ,Active Status Bit 33" "Not active,Active" bitfld.long 0x00 0. " ASB32 ,Active Status Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_ICDABR1,Active Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" bitfld.long 0x00 31. " ASB95 ,Active Status Bit 95" "Not active,Active" bitfld.long 0x00 30. " ASB94 ,Active Status Bit 94" "Not active,Active" bitfld.long 0x00 29. " ASB93 ,Active Status Bit 93" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB92 ,Active Status Bit 92" "Not active,Active" bitfld.long 0x00 27. " ASB91 ,Active Status Bit 91" "Not active,Active" bitfld.long 0x00 26. " ASB90 ,Active Status Bit 90" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB89 ,Active Status Bit 89" "Not active,Active" bitfld.long 0x00 24. " ASB88 ,Active Status Bit 88" "Not active,Active" bitfld.long 0x00 23. " ASB87 ,Active Status Bit 87" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB86 ,Active Status Bit 86" "Not active,Active" bitfld.long 0x00 21. " ASB85 ,Active Status Bit 85" "Not active,Active" bitfld.long 0x00 20. " ASB84 ,Active Status Bit 84" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB83 ,Active Status Bit 83" "Not active,Active" bitfld.long 0x00 18. " ASB82 ,Active Status Bit 82" "Not active,Active" bitfld.long 0x00 17. " ASB81 ,Active Status Bit 81" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB80 ,Active Status Bit 80" "Not active,Active" bitfld.long 0x00 15. " ASB79 ,Active Status Bit 79" "Not active,Active" bitfld.long 0x00 14. " ASB78 ,Active Status Bit 78" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB77 ,Active Status Bit 77" "Not active,Active" bitfld.long 0x00 12. " ASB76 ,Active Status Bit 76" "Not active,Active" bitfld.long 0x00 11. " ASB75 ,Active Status Bit 75" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB74 ,Active Status Bit 74" "Not active,Active" bitfld.long 0x00 9. " ASB73 ,Active Status Bit 73" "Not active,Active" bitfld.long 0x00 8. " ASB72 ,Active Status Bit 72" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB71 ,Active Status Bit 71" "Not active,Active" bitfld.long 0x00 6. " ASB70 ,Active Status Bit 70" "Not active,Active" bitfld.long 0x00 5. " ASB69 ,Active Status Bit 69" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB68 ,Active Status Bit 68" "Not active,Active" bitfld.long 0x00 3. " ASB67 ,Active Status Bit 67" "Not active,Active" bitfld.long 0x00 2. " ASB66 ,Active Status Bit 66" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB65 ,Active Status Bit 65" "Not active,Active" bitfld.long 0x00 0. " ASB64 ,Active Status Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_ICDABR2,Active Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" bitfld.long 0x00 31. " ASB127 ,Active Status Bit 127" "Not active,Active" bitfld.long 0x00 30. " ASB126 ,Active Status Bit 126" "Not active,Active" bitfld.long 0x00 29. " ASB125 ,Active Status Bit 125" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB124 ,Active Status Bit 124" "Not active,Active" bitfld.long 0x00 27. " ASB123 ,Active Status Bit 123" "Not active,Active" bitfld.long 0x00 26. " ASB122 ,Active Status Bit 122" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB121 ,Active Status Bit 121" "Not active,Active" bitfld.long 0x00 24. " ASB120 ,Active Status Bit 120" "Not active,Active" bitfld.long 0x00 23. " ASB119 ,Active Status Bit 119" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB118 ,Active Status Bit 118" "Not active,Active" bitfld.long 0x00 21. " ASB117 ,Active Status Bit 117" "Not active,Active" bitfld.long 0x00 20. " ASB116 ,Active Status Bit 116" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB115 ,Active Status Bit 115" "Not active,Active" bitfld.long 0x00 18. " ASB114 ,Active Status Bit 114" "Not active,Active" bitfld.long 0x00 17. " ASB113 ,Active Status Bit 113" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB112 ,Active Status Bit 112" "Not active,Active" bitfld.long 0x00 15. " ASB111 ,Active Status Bit 111" "Not active,Active" bitfld.long 0x00 14. " ASB110 ,Active Status Bit 110" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB109 ,Active Status Bit 109" "Not active,Active" bitfld.long 0x00 12. " ASB108 ,Active Status Bit 108" "Not active,Active" bitfld.long 0x00 11. " ASB107 ,Active Status Bit 107" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB106 ,Active Status Bit 106" "Not active,Active" bitfld.long 0x00 9. " ASB105 ,Active Status Bit 105" "Not active,Active" bitfld.long 0x00 8. " ASB104 ,Active Status Bit 104" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB103 ,Active Status Bit 103" "Not active,Active" bitfld.long 0x00 6. " ASB102 ,Active Status Bit 102" "Not active,Active" bitfld.long 0x00 5. " ASB101 ,Active Status Bit 101" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB100 ,Active Status Bit 100" "Not active,Active" bitfld.long 0x00 3. " ASB99 ,Active Status Bit 99" "Not active,Active" bitfld.long 0x00 2. " ASB98 ,Active Status Bit 98" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB97 ,Active Status Bit 97" "Not active,Active" bitfld.long 0x00 0. " ASB96 ,Active Status Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_ICDABR3,Active Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" bitfld.long 0x00 31. " ASB159 ,Active Status Bit 159" "Not active,Active" bitfld.long 0x00 30. " ASB158 ,Active Status Bit 158" "Not active,Active" bitfld.long 0x00 29. " ASB157 ,Active Status Bit 157" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB156 ,Active Status Bit 156" "Not active,Active" bitfld.long 0x00 27. " ASB155 ,Active Status Bit 155" "Not active,Active" bitfld.long 0x00 26. " ASB154 ,Active Status Bit 154" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB153 ,Active Status Bit 153" "Not active,Active" bitfld.long 0x00 24. " ASB152 ,Active Status Bit 152" "Not active,Active" bitfld.long 0x00 23. " ASB151 ,Active Status Bit 151" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB150 ,Active Status Bit 150" "Not active,Active" bitfld.long 0x00 21. " ASB149 ,Active Status Bit 149" "Not active,Active" bitfld.long 0x00 20. " ASB148 ,Active Status Bit 148" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB147 ,Active Status Bit 147" "Not active,Active" bitfld.long 0x00 18. " ASB146 ,Active Status Bit 146" "Not active,Active" bitfld.long 0x00 17. " ASB145 ,Active Status Bit 145" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB144 ,Active Status Bit 144" "Not active,Active" bitfld.long 0x00 15. " ASB143 ,Active Status Bit 143" "Not active,Active" bitfld.long 0x00 14. " ASB142 ,Active Status Bit 142" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB141 ,Active Status Bit 141" "Not active,Active" bitfld.long 0x00 12. " ASB140 ,Active Status Bit 140" "Not active,Active" bitfld.long 0x00 11. " ASB139 ,Active Status Bit 139" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB138 ,Active Status Bit 138" "Not active,Active" bitfld.long 0x00 9. " ASB137 ,Active Status Bit 137" "Not active,Active" bitfld.long 0x00 8. " ASB136 ,Active Status Bit 136" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB135 ,Active Status Bit 135" "Not active,Active" bitfld.long 0x00 6. " ASB134 ,Active Status Bit 134" "Not active,Active" bitfld.long 0x00 5. " ASB133 ,Active Status Bit 133" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB132 ,Active Status Bit 132" "Not active,Active" bitfld.long 0x00 3. " ASB131 ,Active Status Bit 131" "Not active,Active" bitfld.long 0x00 2. " ASB130 ,Active Status Bit 130" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB129 ,Active Status Bit 129" "Not active,Active" bitfld.long 0x00 0. " ASB128 ,Active Status Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_ICDABR4,Active Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" bitfld.long 0x00 31. " ASB191 ,Active Status Bit 191" "Not active,Active" bitfld.long 0x00 30. " ASB190 ,Active Status Bit 190" "Not active,Active" bitfld.long 0x00 29. " ASB189 ,Active Status Bit 189" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB188 ,Active Status Bit 188" "Not active,Active" bitfld.long 0x00 27. " ASB187 ,Active Status Bit 187" "Not active,Active" bitfld.long 0x00 26. " ASB186 ,Active Status Bit 186" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB185 ,Active Status Bit 185" "Not active,Active" bitfld.long 0x00 24. " ASB184 ,Active Status Bit 184" "Not active,Active" bitfld.long 0x00 23. " ASB183 ,Active Status Bit 183" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB182 ,Active Status Bit 182" "Not active,Active" bitfld.long 0x00 21. " ASB181 ,Active Status Bit 181" "Not active,Active" bitfld.long 0x00 20. " ASB180 ,Active Status Bit 180" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB179 ,Active Status Bit 179" "Not active,Active" bitfld.long 0x00 18. " ASB178 ,Active Status Bit 178" "Not active,Active" bitfld.long 0x00 17. " ASB177 ,Active Status Bit 177" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB176 ,Active Status Bit 176" "Not active,Active" bitfld.long 0x00 15. " ASB175 ,Active Status Bit 175" "Not active,Active" bitfld.long 0x00 14. " ASB174 ,Active Status Bit 174" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB173 ,Active Status Bit 173" "Not active,Active" bitfld.long 0x00 12. " ASB172 ,Active Status Bit 172" "Not active,Active" bitfld.long 0x00 11. " ASB171 ,Active Status Bit 171" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB170 ,Active Status Bit 170" "Not active,Active" bitfld.long 0x00 9. " ASB169 ,Active Status Bit 169" "Not active,Active" bitfld.long 0x00 8. " ASB168 ,Active Status Bit 168" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB167 ,Active Status Bit 167" "Not active,Active" bitfld.long 0x00 6. " ASB166 ,Active Status Bit 166" "Not active,Active" bitfld.long 0x00 5. " ASB165 ,Active Status Bit 165" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB164 ,Active Status Bit 164" "Not active,Active" bitfld.long 0x00 3. " ASB163 ,Active Status Bit 163" "Not active,Active" bitfld.long 0x00 2. " ASB162 ,Active Status Bit 162" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB161 ,Active Status Bit 161" "Not active,Active" bitfld.long 0x00 0. " ASB160 ,Active Status Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_ICDABR5,Active Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" bitfld.long 0x00 31. " ASB223 ,Active Status Bit 223" "Not active,Active" bitfld.long 0x00 30. " ASB222 ,Active Status Bit 222" "Not active,Active" bitfld.long 0x00 29. " ASB221 ,Active Status Bit 221" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB220 ,Active Status Bit 220" "Not active,Active" bitfld.long 0x00 27. " ASB219 ,Active Status Bit 219" "Not active,Active" bitfld.long 0x00 26. " ASB218 ,Active Status Bit 218" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB217 ,Active Status Bit 217" "Not active,Active" bitfld.long 0x00 24. " ASB216 ,Active Status Bit 216" "Not active,Active" bitfld.long 0x00 23. " ASB215 ,Active Status Bit 215" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB214 ,Active Status Bit 214" "Not active,Active" bitfld.long 0x00 21. " ASB213 ,Active Status Bit 213" "Not active,Active" bitfld.long 0x00 20. " ASB212 ,Active Status Bit 212" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB211 ,Active Status Bit 211" "Not active,Active" bitfld.long 0x00 18. " ASB210 ,Active Status Bit 210" "Not active,Active" bitfld.long 0x00 17. " ASB209 ,Active Status Bit 209" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB208 ,Active Status Bit 208" "Not active,Active" bitfld.long 0x00 15. " ASB207 ,Active Status Bit 207" "Not active,Active" bitfld.long 0x00 14. " ASB206 ,Active Status Bit 206" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB205 ,Active Status Bit 205" "Not active,Active" bitfld.long 0x00 12. " ASB204 ,Active Status Bit 204" "Not active,Active" bitfld.long 0x00 11. " ASB203 ,Active Status Bit 203" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB202 ,Active Status Bit 202" "Not active,Active" bitfld.long 0x00 9. " ASB201 ,Active Status Bit 201" "Not active,Active" bitfld.long 0x00 8. " ASB200 ,Active Status Bit 200" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB199 ,Active Status Bit 199" "Not active,Active" bitfld.long 0x00 6. " ASB198 ,Active Status Bit 198" "Not active,Active" bitfld.long 0x00 5. " ASB197 ,Active Status Bit 197" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB196 ,Active Status Bit 196" "Not active,Active" bitfld.long 0x00 3. " ASB195 ,Active Status Bit 195" "Not active,Active" bitfld.long 0x00 2. " ASB194 ,Active Status Bit 194" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB193 ,Active Status Bit 193" "Not active,Active" bitfld.long 0x00 0. " ASB192 ,Active Status Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_ICDABR6,Active Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" bitfld.long 0x00 31. " ASB255 ,Active Status Bit 255" "Not active,Active" bitfld.long 0x00 30. " ASB254 ,Active Status Bit 254" "Not active,Active" bitfld.long 0x00 29. " ASB253 ,Active Status Bit 253" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB252 ,Active Status Bit 252" "Not active,Active" bitfld.long 0x00 27. " ASB251 ,Active Status Bit 251" "Not active,Active" bitfld.long 0x00 26. " ASB250 ,Active Status Bit 250" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB249 ,Active Status Bit 249" "Not active,Active" bitfld.long 0x00 24. " ASB248 ,Active Status Bit 248" "Not active,Active" bitfld.long 0x00 23. " ASB247 ,Active Status Bit 247" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB246 ,Active Status Bit 246" "Not active,Active" bitfld.long 0x00 21. " ASB245 ,Active Status Bit 245" "Not active,Active" bitfld.long 0x00 20. " ASB244 ,Active Status Bit 244" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB243 ,Active Status Bit 243" "Not active,Active" bitfld.long 0x00 18. " ASB242 ,Active Status Bit 242" "Not active,Active" bitfld.long 0x00 17. " ASB241 ,Active Status Bit 241" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB240 ,Active Status Bit 240" "Not active,Active" bitfld.long 0x00 15. " ASB239 ,Active Status Bit 239" "Not active,Active" bitfld.long 0x00 14. " ASB238 ,Active Status Bit 238" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB237 ,Active Status Bit 237" "Not active,Active" bitfld.long 0x00 12. " ASB236 ,Active Status Bit 236" "Not active,Active" bitfld.long 0x00 11. " ASB235 ,Active Status Bit 235" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB234 ,Active Status Bit 234" "Not active,Active" bitfld.long 0x00 9. " ASB233 ,Active Status Bit 233" "Not active,Active" bitfld.long 0x00 8. " ASB232 ,Active Status Bit 232" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB231 ,Active Status Bit 231" "Not active,Active" bitfld.long 0x00 6. " ASB230 ,Active Status Bit 230" "Not active,Active" bitfld.long 0x00 5. " ASB229 ,Active Status Bit 229" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB228 ,Active Status Bit 228" "Not active,Active" bitfld.long 0x00 3. " ASB227 ,Active Status Bit 227" "Not active,Active" bitfld.long 0x00 2. " ASB226 ,Active Status Bit 226" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB225 ,Active Status Bit 225" "Not active,Active" bitfld.long 0x00 0. " ASB224 ,Active Status Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_ICDABR7,Active Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" bitfld.long 0x00 31. " ASB287 ,Active Status Bit 287" "Not active,Active" bitfld.long 0x00 30. " ASB286 ,Active Status Bit 286" "Not active,Active" bitfld.long 0x00 29. " ASB285 ,Active Status Bit 285" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB284 ,Active Status Bit 284" "Not active,Active" bitfld.long 0x00 27. " ASB283 ,Active Status Bit 283" "Not active,Active" bitfld.long 0x00 26. " ASB282 ,Active Status Bit 282" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB281 ,Active Status Bit 281" "Not active,Active" bitfld.long 0x00 24. " ASB280 ,Active Status Bit 280" "Not active,Active" bitfld.long 0x00 23. " ASB279 ,Active Status Bit 279" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB278 ,Active Status Bit 278" "Not active,Active" bitfld.long 0x00 21. " ASB277 ,Active Status Bit 277" "Not active,Active" bitfld.long 0x00 20. " ASB276 ,Active Status Bit 276" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB275 ,Active Status Bit 275" "Not active,Active" bitfld.long 0x00 18. " ASB274 ,Active Status Bit 274" "Not active,Active" bitfld.long 0x00 17. " ASB273 ,Active Status Bit 273" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB272 ,Active Status Bit 272" "Not active,Active" bitfld.long 0x00 15. " ASB271 ,Active Status Bit 271" "Not active,Active" bitfld.long 0x00 14. " ASB270 ,Active Status Bit 270" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB269 ,Active Status Bit 269" "Not active,Active" bitfld.long 0x00 12. " ASB268 ,Active Status Bit 268" "Not active,Active" bitfld.long 0x00 11. " ASB267 ,Active Status Bit 267" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB266 ,Active Status Bit 266" "Not active,Active" bitfld.long 0x00 9. " ASB265 ,Active Status Bit 265" "Not active,Active" bitfld.long 0x00 8. " ASB264 ,Active Status Bit 264" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB263 ,Active Status Bit 263" "Not active,Active" bitfld.long 0x00 6. " ASB262 ,Active Status Bit 262" "Not active,Active" bitfld.long 0x00 5. " ASB261 ,Active Status Bit 261" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB260 ,Active Status Bit 260" "Not active,Active" bitfld.long 0x00 3. " ASB259 ,Active Status Bit 259" "Not active,Active" bitfld.long 0x00 2. " ASB258 ,Active Status Bit 258" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB257 ,Active Status Bit 257" "Not active,Active" bitfld.long 0x00 0. " ASB256 ,Active Status Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_ICDABR8,Active Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" bitfld.long 0x00 31. " ASB319 ,Active Status Bit 319" "Not active,Active" bitfld.long 0x00 30. " ASB318 ,Active Status Bit 318" "Not active,Active" bitfld.long 0x00 29. " ASB317 ,Active Status Bit 317" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB316 ,Active Status Bit 316" "Not active,Active" bitfld.long 0x00 27. " ASB315 ,Active Status Bit 315" "Not active,Active" bitfld.long 0x00 26. " ASB314 ,Active Status Bit 314" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB313 ,Active Status Bit 313" "Not active,Active" bitfld.long 0x00 24. " ASB312 ,Active Status Bit 312" "Not active,Active" bitfld.long 0x00 23. " ASB311 ,Active Status Bit 311" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB310 ,Active Status Bit 310" "Not active,Active" bitfld.long 0x00 21. " ASB309 ,Active Status Bit 309" "Not active,Active" bitfld.long 0x00 20. " ASB308 ,Active Status Bit 308" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB307 ,Active Status Bit 307" "Not active,Active" bitfld.long 0x00 18. " ASB306 ,Active Status Bit 306" "Not active,Active" bitfld.long 0x00 17. " ASB305 ,Active Status Bit 305" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB304 ,Active Status Bit 304" "Not active,Active" bitfld.long 0x00 15. " ASB303 ,Active Status Bit 303" "Not active,Active" bitfld.long 0x00 14. " ASB302 ,Active Status Bit 302" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB301 ,Active Status Bit 301" "Not active,Active" bitfld.long 0x00 12. " ASB300 ,Active Status Bit 300" "Not active,Active" bitfld.long 0x00 11. " ASB299 ,Active Status Bit 299" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB298 ,Active Status Bit 298" "Not active,Active" bitfld.long 0x00 9. " ASB297 ,Active Status Bit 297" "Not active,Active" bitfld.long 0x00 8. " ASB296 ,Active Status Bit 296" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB295 ,Active Status Bit 295" "Not active,Active" bitfld.long 0x00 6. " ASB294 ,Active Status Bit 294" "Not active,Active" bitfld.long 0x00 5. " ASB293 ,Active Status Bit 293" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB292 ,Active Status Bit 292" "Not active,Active" bitfld.long 0x00 3. " ASB291 ,Active Status Bit 291" "Not active,Active" bitfld.long 0x00 2. " ASB290 ,Active Status Bit 290" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB289 ,Active Status Bit 289" "Not active,Active" bitfld.long 0x00 0. " ASB288 ,Active Status Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_ICDABR9,Active Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" bitfld.long 0x00 31. " ASB351 ,Active Status Bit 351" "Not active,Active" bitfld.long 0x00 30. " ASB350 ,Active Status Bit 350" "Not active,Active" bitfld.long 0x00 29. " ASB349 ,Active Status Bit 349" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB348 ,Active Status Bit 348" "Not active,Active" bitfld.long 0x00 27. " ASB347 ,Active Status Bit 347" "Not active,Active" bitfld.long 0x00 26. " ASB346 ,Active Status Bit 346" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB345 ,Active Status Bit 345" "Not active,Active" bitfld.long 0x00 24. " ASB344 ,Active Status Bit 344" "Not active,Active" bitfld.long 0x00 23. " ASB343 ,Active Status Bit 343" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB342 ,Active Status Bit 342" "Not active,Active" bitfld.long 0x00 21. " ASB341 ,Active Status Bit 341" "Not active,Active" bitfld.long 0x00 20. " ASB340 ,Active Status Bit 340" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB339 ,Active Status Bit 339" "Not active,Active" bitfld.long 0x00 18. " ASB338 ,Active Status Bit 338" "Not active,Active" bitfld.long 0x00 17. " ASB337 ,Active Status Bit 337" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB336 ,Active Status Bit 336" "Not active,Active" bitfld.long 0x00 15. " ASB335 ,Active Status Bit 335" "Not active,Active" bitfld.long 0x00 14. " ASB334 ,Active Status Bit 334" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB333 ,Active Status Bit 333" "Not active,Active" bitfld.long 0x00 12. " ASB332 ,Active Status Bit 332" "Not active,Active" bitfld.long 0x00 11. " ASB331 ,Active Status Bit 331" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB330 ,Active Status Bit 330" "Not active,Active" bitfld.long 0x00 9. " ASB329 ,Active Status Bit 329" "Not active,Active" bitfld.long 0x00 8. " ASB328 ,Active Status Bit 328" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB327 ,Active Status Bit 327" "Not active,Active" bitfld.long 0x00 6. " ASB326 ,Active Status Bit 326" "Not active,Active" bitfld.long 0x00 5. " ASB325 ,Active Status Bit 325" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB324 ,Active Status Bit 324" "Not active,Active" bitfld.long 0x00 3. " ASB323 ,Active Status Bit 323" "Not active,Active" bitfld.long 0x00 2. " ASB322 ,Active Status Bit 322" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB321 ,Active Status Bit 321" "Not active,Active" bitfld.long 0x00 0. " ASB320 ,Active Status Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_ICDABR10,Active Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" bitfld.long 0x00 31. " ASB383 ,Active Status Bit 383" "Not active,Active" bitfld.long 0x00 30. " ASB382 ,Active Status Bit 382" "Not active,Active" bitfld.long 0x00 29. " ASB381 ,Active Status Bit 381" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB380 ,Active Status Bit 380" "Not active,Active" bitfld.long 0x00 27. " ASB379 ,Active Status Bit 379" "Not active,Active" bitfld.long 0x00 26. " ASB378 ,Active Status Bit 378" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB377 ,Active Status Bit 377" "Not active,Active" bitfld.long 0x00 24. " ASB376 ,Active Status Bit 376" "Not active,Active" bitfld.long 0x00 23. " ASB375 ,Active Status Bit 375" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB374 ,Active Status Bit 374" "Not active,Active" bitfld.long 0x00 21. " ASB373 ,Active Status Bit 373" "Not active,Active" bitfld.long 0x00 20. " ASB372 ,Active Status Bit 372" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB371 ,Active Status Bit 371" "Not active,Active" bitfld.long 0x00 18. " ASB370 ,Active Status Bit 370" "Not active,Active" bitfld.long 0x00 17. " ASB369 ,Active Status Bit 369" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB368 ,Active Status Bit 368" "Not active,Active" bitfld.long 0x00 15. " ASB367 ,Active Status Bit 367" "Not active,Active" bitfld.long 0x00 14. " ASB366 ,Active Status Bit 366" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB365 ,Active Status Bit 365" "Not active,Active" bitfld.long 0x00 12. " ASB364 ,Active Status Bit 364" "Not active,Active" bitfld.long 0x00 11. " ASB363 ,Active Status Bit 363" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB362 ,Active Status Bit 362" "Not active,Active" bitfld.long 0x00 9. " ASB361 ,Active Status Bit 361" "Not active,Active" bitfld.long 0x00 8. " ASB360 ,Active Status Bit 360" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB359 ,Active Status Bit 359" "Not active,Active" bitfld.long 0x00 6. " ASB358 ,Active Status Bit 358" "Not active,Active" bitfld.long 0x00 5. " ASB357 ,Active Status Bit 357" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB356 ,Active Status Bit 356" "Not active,Active" bitfld.long 0x00 3. " ASB355 ,Active Status Bit 355" "Not active,Active" bitfld.long 0x00 2. " ASB354 ,Active Status Bit 354" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB353 ,Active Status Bit 353" "Not active,Active" bitfld.long 0x00 0. " ASB352 ,Active Status Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_ICDABR11,Active Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" bitfld.long 0x00 31. " ASB415 ,Active Status Bit 415" "Not active,Active" bitfld.long 0x00 30. " ASB414 ,Active Status Bit 414" "Not active,Active" bitfld.long 0x00 29. " ASB413 ,Active Status Bit 413" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB412 ,Active Status Bit 412" "Not active,Active" bitfld.long 0x00 27. " ASB411 ,Active Status Bit 411" "Not active,Active" bitfld.long 0x00 26. " ASB410 ,Active Status Bit 410" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB409 ,Active Status Bit 409" "Not active,Active" bitfld.long 0x00 24. " ASB408 ,Active Status Bit 408" "Not active,Active" bitfld.long 0x00 23. " ASB407 ,Active Status Bit 407" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB406 ,Active Status Bit 406" "Not active,Active" bitfld.long 0x00 21. " ASB405 ,Active Status Bit 405" "Not active,Active" bitfld.long 0x00 20. " ASB404 ,Active Status Bit 404" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB403 ,Active Status Bit 403" "Not active,Active" bitfld.long 0x00 18. " ASB402 ,Active Status Bit 402" "Not active,Active" bitfld.long 0x00 17. " ASB401 ,Active Status Bit 401" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB400 ,Active Status Bit 400" "Not active,Active" bitfld.long 0x00 15. " ASB399 ,Active Status Bit 399" "Not active,Active" bitfld.long 0x00 14. " ASB398 ,Active Status Bit 398" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB397 ,Active Status Bit 397" "Not active,Active" bitfld.long 0x00 12. " ASB396 ,Active Status Bit 396" "Not active,Active" bitfld.long 0x00 11. " ASB395 ,Active Status Bit 395" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB394 ,Active Status Bit 394" "Not active,Active" bitfld.long 0x00 9. " ASB393 ,Active Status Bit 393" "Not active,Active" bitfld.long 0x00 8. " ASB392 ,Active Status Bit 392" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB391 ,Active Status Bit 391" "Not active,Active" bitfld.long 0x00 6. " ASB390 ,Active Status Bit 390" "Not active,Active" bitfld.long 0x00 5. " ASB389 ,Active Status Bit 389" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB388 ,Active Status Bit 388" "Not active,Active" bitfld.long 0x00 3. " ASB387 ,Active Status Bit 387" "Not active,Active" bitfld.long 0x00 2. " ASB386 ,Active Status Bit 386" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB385 ,Active Status Bit 385" "Not active,Active" bitfld.long 0x00 0. " ASB384 ,Active Status Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_ICDABR12,Active Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" bitfld.long 0x00 31. " ASB447 ,Active Status Bit 447" "Not active,Active" bitfld.long 0x00 30. " ASB446 ,Active Status Bit 446" "Not active,Active" bitfld.long 0x00 29. " ASB445 ,Active Status Bit 445" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB444 ,Active Status Bit 444" "Not active,Active" bitfld.long 0x00 27. " ASB443 ,Active Status Bit 443" "Not active,Active" bitfld.long 0x00 26. " ASB442 ,Active Status Bit 442" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB441 ,Active Status Bit 441" "Not active,Active" bitfld.long 0x00 24. " ASB440 ,Active Status Bit 440" "Not active,Active" bitfld.long 0x00 23. " ASB439 ,Active Status Bit 439" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB438 ,Active Status Bit 438" "Not active,Active" bitfld.long 0x00 21. " ASB437 ,Active Status Bit 437" "Not active,Active" bitfld.long 0x00 20. " ASB436 ,Active Status Bit 436" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB435 ,Active Status Bit 435" "Not active,Active" bitfld.long 0x00 18. " ASB434 ,Active Status Bit 434" "Not active,Active" bitfld.long 0x00 17. " ASB433 ,Active Status Bit 433" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB432 ,Active Status Bit 432" "Not active,Active" bitfld.long 0x00 15. " ASB431 ,Active Status Bit 431" "Not active,Active" bitfld.long 0x00 14. " ASB430 ,Active Status Bit 430" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB429 ,Active Status Bit 429" "Not active,Active" bitfld.long 0x00 12. " ASB428 ,Active Status Bit 428" "Not active,Active" bitfld.long 0x00 11. " ASB427 ,Active Status Bit 427" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB426 ,Active Status Bit 426" "Not active,Active" bitfld.long 0x00 9. " ASB425 ,Active Status Bit 425" "Not active,Active" bitfld.long 0x00 8. " ASB424 ,Active Status Bit 424" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB423 ,Active Status Bit 423" "Not active,Active" bitfld.long 0x00 6. " ASB422 ,Active Status Bit 422" "Not active,Active" bitfld.long 0x00 5. " ASB421 ,Active Status Bit 421" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB420 ,Active Status Bit 420" "Not active,Active" bitfld.long 0x00 3. " ASB419 ,Active Status Bit 419" "Not active,Active" bitfld.long 0x00 2. " ASB418 ,Active Status Bit 418" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB417 ,Active Status Bit 417" "Not active,Active" bitfld.long 0x00 0. " ASB416 ,Active Status Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_ICDABR13,Active Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" bitfld.long 0x00 31. " ASB479 ,Active Status Bit 479" "Not active,Active" bitfld.long 0x00 30. " ASB478 ,Active Status Bit 478" "Not active,Active" bitfld.long 0x00 29. " ASB477 ,Active Status Bit 477" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB476 ,Active Status Bit 476" "Not active,Active" bitfld.long 0x00 27. " ASB475 ,Active Status Bit 475" "Not active,Active" bitfld.long 0x00 26. " ASB474 ,Active Status Bit 474" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB473 ,Active Status Bit 473" "Not active,Active" bitfld.long 0x00 24. " ASB472 ,Active Status Bit 472" "Not active,Active" bitfld.long 0x00 23. " ASB471 ,Active Status Bit 471" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB470 ,Active Status Bit 470" "Not active,Active" bitfld.long 0x00 21. " ASB469 ,Active Status Bit 469" "Not active,Active" bitfld.long 0x00 20. " ASB468 ,Active Status Bit 468" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB467 ,Active Status Bit 467" "Not active,Active" bitfld.long 0x00 18. " ASB466 ,Active Status Bit 466" "Not active,Active" bitfld.long 0x00 17. " ASB465 ,Active Status Bit 465" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB464 ,Active Status Bit 464" "Not active,Active" bitfld.long 0x00 15. " ASB463 ,Active Status Bit 463" "Not active,Active" bitfld.long 0x00 14. " ASB462 ,Active Status Bit 462" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB461 ,Active Status Bit 461" "Not active,Active" bitfld.long 0x00 12. " ASB460 ,Active Status Bit 460" "Not active,Active" bitfld.long 0x00 11. " ASB459 ,Active Status Bit 459" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB458 ,Active Status Bit 458" "Not active,Active" bitfld.long 0x00 9. " ASB457 ,Active Status Bit 457" "Not active,Active" bitfld.long 0x00 8. " ASB456 ,Active Status Bit 456" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB455 ,Active Status Bit 455" "Not active,Active" bitfld.long 0x00 6. " ASB454 ,Active Status Bit 454" "Not active,Active" bitfld.long 0x00 5. " ASB453 ,Active Status Bit 453" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB452 ,Active Status Bit 452" "Not active,Active" bitfld.long 0x00 3. " ASB451 ,Active Status Bit 451" "Not active,Active" bitfld.long 0x00 2. " ASB450 ,Active Status Bit 450" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB449 ,Active Status Bit 449" "Not active,Active" bitfld.long 0x00 0. " ASB448 ,Active Status Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_ICDABR14,Active Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" bitfld.long 0x00 31. " ASB511 ,Active Status Bit 511" "Not active,Active" bitfld.long 0x00 30. " ASB510 ,Active Status Bit 510" "Not active,Active" bitfld.long 0x00 29. " ASB509 ,Active Status Bit 509" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB508 ,Active Status Bit 508" "Not active,Active" bitfld.long 0x00 27. " ASB507 ,Active Status Bit 507" "Not active,Active" bitfld.long 0x00 26. " ASB506 ,Active Status Bit 506" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB505 ,Active Status Bit 505" "Not active,Active" bitfld.long 0x00 24. " ASB504 ,Active Status Bit 504" "Not active,Active" bitfld.long 0x00 23. " ASB503 ,Active Status Bit 503" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB502 ,Active Status Bit 502" "Not active,Active" bitfld.long 0x00 21. " ASB501 ,Active Status Bit 501" "Not active,Active" bitfld.long 0x00 20. " ASB500 ,Active Status Bit 500" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB499 ,Active Status Bit 499" "Not active,Active" bitfld.long 0x00 18. " ASB498 ,Active Status Bit 498" "Not active,Active" bitfld.long 0x00 17. " ASB497 ,Active Status Bit 497" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB496 ,Active Status Bit 496" "Not active,Active" bitfld.long 0x00 15. " ASB495 ,Active Status Bit 495" "Not active,Active" bitfld.long 0x00 14. " ASB494 ,Active Status Bit 494" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB493 ,Active Status Bit 493" "Not active,Active" bitfld.long 0x00 12. " ASB492 ,Active Status Bit 492" "Not active,Active" bitfld.long 0x00 11. " ASB491 ,Active Status Bit 491" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB490 ,Active Status Bit 490" "Not active,Active" bitfld.long 0x00 9. " ASB489 ,Active Status Bit 489" "Not active,Active" bitfld.long 0x00 8. " ASB488 ,Active Status Bit 488" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB487 ,Active Status Bit 487" "Not active,Active" bitfld.long 0x00 6. " ASB486 ,Active Status Bit 486" "Not active,Active" bitfld.long 0x00 5. " ASB485 ,Active Status Bit 485" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB484 ,Active Status Bit 484" "Not active,Active" bitfld.long 0x00 3. " ASB483 ,Active Status Bit 483" "Not active,Active" bitfld.long 0x00 2. " ASB482 ,Active Status Bit 482" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB481 ,Active Status Bit 481" "Not active,Active" bitfld.long 0x00 0. " ASB480 ,Active Status Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_ICDABR15,Active Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" bitfld.long 0x00 31. " ASB543 ,Active Status Bit 543" "Not active,Active" bitfld.long 0x00 30. " ASB542 ,Active Status Bit 542" "Not active,Active" bitfld.long 0x00 29. " ASB541 ,Active Status Bit 541" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB540 ,Active Status Bit 540" "Not active,Active" bitfld.long 0x00 27. " ASB539 ,Active Status Bit 539" "Not active,Active" bitfld.long 0x00 26. " ASB538 ,Active Status Bit 538" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB537 ,Active Status Bit 537" "Not active,Active" bitfld.long 0x00 24. " ASB536 ,Active Status Bit 536" "Not active,Active" bitfld.long 0x00 23. " ASB535 ,Active Status Bit 535" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB534 ,Active Status Bit 534" "Not active,Active" bitfld.long 0x00 21. " ASB533 ,Active Status Bit 533" "Not active,Active" bitfld.long 0x00 20. " ASB532 ,Active Status Bit 532" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB531 ,Active Status Bit 531" "Not active,Active" bitfld.long 0x00 18. " ASB530 ,Active Status Bit 530" "Not active,Active" bitfld.long 0x00 17. " ASB529 ,Active Status Bit 529" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB528 ,Active Status Bit 528" "Not active,Active" bitfld.long 0x00 15. " ASB527 ,Active Status Bit 527" "Not active,Active" bitfld.long 0x00 14. " ASB526 ,Active Status Bit 526" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB525 ,Active Status Bit 525" "Not active,Active" bitfld.long 0x00 12. " ASB524 ,Active Status Bit 524" "Not active,Active" bitfld.long 0x00 11. " ASB523 ,Active Status Bit 523" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB522 ,Active Status Bit 522" "Not active,Active" bitfld.long 0x00 9. " ASB521 ,Active Status Bit 521" "Not active,Active" bitfld.long 0x00 8. " ASB520 ,Active Status Bit 520" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB519 ,Active Status Bit 519" "Not active,Active" bitfld.long 0x00 6. " ASB518 ,Active Status Bit 518" "Not active,Active" bitfld.long 0x00 5. " ASB517 ,Active Status Bit 517" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB516 ,Active Status Bit 516" "Not active,Active" bitfld.long 0x00 3. " ASB515 ,Active Status Bit 515" "Not active,Active" bitfld.long 0x00 2. " ASB514 ,Active Status Bit 514" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB513 ,Active Status Bit 513" "Not active,Active" bitfld.long 0x00 0. " ASB512 ,Active Status Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_ICDABR16,Active Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" bitfld.long 0x00 31. " ASB575 ,Active Status Bit 575" "Not active,Active" bitfld.long 0x00 30. " ASB574 ,Active Status Bit 574" "Not active,Active" bitfld.long 0x00 29. " ASB573 ,Active Status Bit 573" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB572 ,Active Status Bit 572" "Not active,Active" bitfld.long 0x00 27. " ASB571 ,Active Status Bit 571" "Not active,Active" bitfld.long 0x00 26. " ASB570 ,Active Status Bit 570" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB569 ,Active Status Bit 569" "Not active,Active" bitfld.long 0x00 24. " ASB568 ,Active Status Bit 568" "Not active,Active" bitfld.long 0x00 23. " ASB567 ,Active Status Bit 567" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB566 ,Active Status Bit 566" "Not active,Active" bitfld.long 0x00 21. " ASB565 ,Active Status Bit 565" "Not active,Active" bitfld.long 0x00 20. " ASB564 ,Active Status Bit 564" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB563 ,Active Status Bit 563" "Not active,Active" bitfld.long 0x00 18. " ASB562 ,Active Status Bit 562" "Not active,Active" bitfld.long 0x00 17. " ASB561 ,Active Status Bit 561" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB560 ,Active Status Bit 560" "Not active,Active" bitfld.long 0x00 15. " ASB559 ,Active Status Bit 559" "Not active,Active" bitfld.long 0x00 14. " ASB558 ,Active Status Bit 558" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB557 ,Active Status Bit 557" "Not active,Active" bitfld.long 0x00 12. " ASB556 ,Active Status Bit 556" "Not active,Active" bitfld.long 0x00 11. " ASB555 ,Active Status Bit 555" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB554 ,Active Status Bit 554" "Not active,Active" bitfld.long 0x00 9. " ASB553 ,Active Status Bit 553" "Not active,Active" bitfld.long 0x00 8. " ASB552 ,Active Status Bit 552" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB551 ,Active Status Bit 551" "Not active,Active" bitfld.long 0x00 6. " ASB550 ,Active Status Bit 550" "Not active,Active" bitfld.long 0x00 5. " ASB549 ,Active Status Bit 549" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB548 ,Active Status Bit 548" "Not active,Active" bitfld.long 0x00 3. " ASB547 ,Active Status Bit 547" "Not active,Active" bitfld.long 0x00 2. " ASB546 ,Active Status Bit 546" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB545 ,Active Status Bit 545" "Not active,Active" bitfld.long 0x00 0. " ASB544 ,Active Status Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_ICDABR17,Active Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" bitfld.long 0x00 31. " ASB607 ,Active Status Bit 607" "Not active,Active" bitfld.long 0x00 30. " ASB606 ,Active Status Bit 606" "Not active,Active" bitfld.long 0x00 29. " ASB605 ,Active Status Bit 605" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB604 ,Active Status Bit 604" "Not active,Active" bitfld.long 0x00 27. " ASB603 ,Active Status Bit 603" "Not active,Active" bitfld.long 0x00 26. " ASB602 ,Active Status Bit 602" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB601 ,Active Status Bit 601" "Not active,Active" bitfld.long 0x00 24. " ASB600 ,Active Status Bit 600" "Not active,Active" bitfld.long 0x00 23. " ASB599 ,Active Status Bit 599" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB598 ,Active Status Bit 598" "Not active,Active" bitfld.long 0x00 21. " ASB597 ,Active Status Bit 597" "Not active,Active" bitfld.long 0x00 20. " ASB596 ,Active Status Bit 596" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB595 ,Active Status Bit 595" "Not active,Active" bitfld.long 0x00 18. " ASB594 ,Active Status Bit 594" "Not active,Active" bitfld.long 0x00 17. " ASB593 ,Active Status Bit 593" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB592 ,Active Status Bit 592" "Not active,Active" bitfld.long 0x00 15. " ASB591 ,Active Status Bit 591" "Not active,Active" bitfld.long 0x00 14. " ASB590 ,Active Status Bit 590" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB589 ,Active Status Bit 589" "Not active,Active" bitfld.long 0x00 12. " ASB588 ,Active Status Bit 588" "Not active,Active" bitfld.long 0x00 11. " ASB587 ,Active Status Bit 587" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB586 ,Active Status Bit 586" "Not active,Active" bitfld.long 0x00 9. " ASB585 ,Active Status Bit 585" "Not active,Active" bitfld.long 0x00 8. " ASB584 ,Active Status Bit 584" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB583 ,Active Status Bit 583" "Not active,Active" bitfld.long 0x00 6. " ASB582 ,Active Status Bit 582" "Not active,Active" bitfld.long 0x00 5. " ASB581 ,Active Status Bit 581" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB580 ,Active Status Bit 580" "Not active,Active" bitfld.long 0x00 3. " ASB579 ,Active Status Bit 579" "Not active,Active" bitfld.long 0x00 2. " ASB578 ,Active Status Bit 578" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB577 ,Active Status Bit 577" "Not active,Active" bitfld.long 0x00 0. " ASB576 ,Active Status Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_ICDABR18,Active Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" bitfld.long 0x00 31. " ASB639 ,Active Status Bit 639" "Not active,Active" bitfld.long 0x00 30. " ASB638 ,Active Status Bit 638" "Not active,Active" bitfld.long 0x00 29. " ASB637 ,Active Status Bit 637" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB636 ,Active Status Bit 636" "Not active,Active" bitfld.long 0x00 27. " ASB635 ,Active Status Bit 635" "Not active,Active" bitfld.long 0x00 26. " ASB634 ,Active Status Bit 634" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB633 ,Active Status Bit 633" "Not active,Active" bitfld.long 0x00 24. " ASB632 ,Active Status Bit 632" "Not active,Active" bitfld.long 0x00 23. " ASB631 ,Active Status Bit 631" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB630 ,Active Status Bit 630" "Not active,Active" bitfld.long 0x00 21. " ASB629 ,Active Status Bit 629" "Not active,Active" bitfld.long 0x00 20. " ASB628 ,Active Status Bit 628" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB627 ,Active Status Bit 627" "Not active,Active" bitfld.long 0x00 18. " ASB626 ,Active Status Bit 626" "Not active,Active" bitfld.long 0x00 17. " ASB625 ,Active Status Bit 625" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB624 ,Active Status Bit 624" "Not active,Active" bitfld.long 0x00 15. " ASB623 ,Active Status Bit 623" "Not active,Active" bitfld.long 0x00 14. " ASB622 ,Active Status Bit 622" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB621 ,Active Status Bit 621" "Not active,Active" bitfld.long 0x00 12. " ASB620 ,Active Status Bit 620" "Not active,Active" bitfld.long 0x00 11. " ASB619 ,Active Status Bit 619" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB618 ,Active Status Bit 618" "Not active,Active" bitfld.long 0x00 9. " ASB617 ,Active Status Bit 617" "Not active,Active" bitfld.long 0x00 8. " ASB616 ,Active Status Bit 616" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB615 ,Active Status Bit 615" "Not active,Active" bitfld.long 0x00 6. " ASB614 ,Active Status Bit 614" "Not active,Active" bitfld.long 0x00 5. " ASB613 ,Active Status Bit 613" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB612 ,Active Status Bit 612" "Not active,Active" bitfld.long 0x00 3. " ASB611 ,Active Status Bit 611" "Not active,Active" bitfld.long 0x00 2. " ASB610 ,Active Status Bit 610" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB609 ,Active Status Bit 609" "Not active,Active" bitfld.long 0x00 0. " ASB608 ,Active Status Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_ICDABR19,Active Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" bitfld.long 0x00 31. " ASB671 ,Active Status Bit 671" "Not active,Active" bitfld.long 0x00 30. " ASB670 ,Active Status Bit 670" "Not active,Active" bitfld.long 0x00 29. " ASB669 ,Active Status Bit 669" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB668 ,Active Status Bit 668" "Not active,Active" bitfld.long 0x00 27. " ASB667 ,Active Status Bit 667" "Not active,Active" bitfld.long 0x00 26. " ASB666 ,Active Status Bit 666" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB665 ,Active Status Bit 665" "Not active,Active" bitfld.long 0x00 24. " ASB664 ,Active Status Bit 664" "Not active,Active" bitfld.long 0x00 23. " ASB663 ,Active Status Bit 663" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB662 ,Active Status Bit 662" "Not active,Active" bitfld.long 0x00 21. " ASB661 ,Active Status Bit 661" "Not active,Active" bitfld.long 0x00 20. " ASB660 ,Active Status Bit 660" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB659 ,Active Status Bit 659" "Not active,Active" bitfld.long 0x00 18. " ASB658 ,Active Status Bit 658" "Not active,Active" bitfld.long 0x00 17. " ASB657 ,Active Status Bit 657" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB656 ,Active Status Bit 656" "Not active,Active" bitfld.long 0x00 15. " ASB655 ,Active Status Bit 655" "Not active,Active" bitfld.long 0x00 14. " ASB654 ,Active Status Bit 654" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB653 ,Active Status Bit 653" "Not active,Active" bitfld.long 0x00 12. " ASB652 ,Active Status Bit 652" "Not active,Active" bitfld.long 0x00 11. " ASB651 ,Active Status Bit 651" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB650 ,Active Status Bit 650" "Not active,Active" bitfld.long 0x00 9. " ASB649 ,Active Status Bit 649" "Not active,Active" bitfld.long 0x00 8. " ASB648 ,Active Status Bit 648" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB647 ,Active Status Bit 647" "Not active,Active" bitfld.long 0x00 6. " ASB646 ,Active Status Bit 646" "Not active,Active" bitfld.long 0x00 5. " ASB645 ,Active Status Bit 645" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB644 ,Active Status Bit 644" "Not active,Active" bitfld.long 0x00 3. " ASB643 ,Active Status Bit 643" "Not active,Active" bitfld.long 0x00 2. " ASB642 ,Active Status Bit 642" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB641 ,Active Status Bit 641" "Not active,Active" bitfld.long 0x00 0. " ASB640 ,Active Status Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_ICDABR20,Active Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" bitfld.long 0x00 31. " ASB703 ,Active Status Bit 703" "Not active,Active" bitfld.long 0x00 30. " ASB702 ,Active Status Bit 702" "Not active,Active" bitfld.long 0x00 29. " ASB701 ,Active Status Bit 701" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB700 ,Active Status Bit 700" "Not active,Active" bitfld.long 0x00 27. " ASB699 ,Active Status Bit 699" "Not active,Active" bitfld.long 0x00 26. " ASB698 ,Active Status Bit 698" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB697 ,Active Status Bit 697" "Not active,Active" bitfld.long 0x00 24. " ASB696 ,Active Status Bit 696" "Not active,Active" bitfld.long 0x00 23. " ASB695 ,Active Status Bit 695" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB694 ,Active Status Bit 694" "Not active,Active" bitfld.long 0x00 21. " ASB693 ,Active Status Bit 693" "Not active,Active" bitfld.long 0x00 20. " ASB692 ,Active Status Bit 692" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB691 ,Active Status Bit 691" "Not active,Active" bitfld.long 0x00 18. " ASB690 ,Active Status Bit 690" "Not active,Active" bitfld.long 0x00 17. " ASB689 ,Active Status Bit 689" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB688 ,Active Status Bit 688" "Not active,Active" bitfld.long 0x00 15. " ASB687 ,Active Status Bit 687" "Not active,Active" bitfld.long 0x00 14. " ASB686 ,Active Status Bit 686" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB685 ,Active Status Bit 685" "Not active,Active" bitfld.long 0x00 12. " ASB684 ,Active Status Bit 684" "Not active,Active" bitfld.long 0x00 11. " ASB683 ,Active Status Bit 683" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB682 ,Active Status Bit 682" "Not active,Active" bitfld.long 0x00 9. " ASB681 ,Active Status Bit 681" "Not active,Active" bitfld.long 0x00 8. " ASB680 ,Active Status Bit 680" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB679 ,Active Status Bit 679" "Not active,Active" bitfld.long 0x00 6. " ASB678 ,Active Status Bit 678" "Not active,Active" bitfld.long 0x00 5. " ASB677 ,Active Status Bit 677" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB676 ,Active Status Bit 676" "Not active,Active" bitfld.long 0x00 3. " ASB675 ,Active Status Bit 675" "Not active,Active" bitfld.long 0x00 2. " ASB674 ,Active Status Bit 674" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB673 ,Active Status Bit 673" "Not active,Active" bitfld.long 0x00 0. " ASB672 ,Active Status Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_ICDABR21,Active Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" bitfld.long 0x00 31. " ASB735 ,Active Status Bit 735" "Not active,Active" bitfld.long 0x00 30. " ASB734 ,Active Status Bit 734" "Not active,Active" bitfld.long 0x00 29. " ASB733 ,Active Status Bit 733" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB732 ,Active Status Bit 732" "Not active,Active" bitfld.long 0x00 27. " ASB731 ,Active Status Bit 731" "Not active,Active" bitfld.long 0x00 26. " ASB730 ,Active Status Bit 730" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB729 ,Active Status Bit 729" "Not active,Active" bitfld.long 0x00 24. " ASB728 ,Active Status Bit 728" "Not active,Active" bitfld.long 0x00 23. " ASB727 ,Active Status Bit 727" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB726 ,Active Status Bit 726" "Not active,Active" bitfld.long 0x00 21. " ASB725 ,Active Status Bit 725" "Not active,Active" bitfld.long 0x00 20. " ASB724 ,Active Status Bit 724" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB723 ,Active Status Bit 723" "Not active,Active" bitfld.long 0x00 18. " ASB722 ,Active Status Bit 722" "Not active,Active" bitfld.long 0x00 17. " ASB721 ,Active Status Bit 721" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB720 ,Active Status Bit 720" "Not active,Active" bitfld.long 0x00 15. " ASB719 ,Active Status Bit 719" "Not active,Active" bitfld.long 0x00 14. " ASB718 ,Active Status Bit 718" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB717 ,Active Status Bit 717" "Not active,Active" bitfld.long 0x00 12. " ASB716 ,Active Status Bit 716" "Not active,Active" bitfld.long 0x00 11. " ASB715 ,Active Status Bit 715" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB714 ,Active Status Bit 714" "Not active,Active" bitfld.long 0x00 9. " ASB713 ,Active Status Bit 713" "Not active,Active" bitfld.long 0x00 8. " ASB712 ,Active Status Bit 712" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB711 ,Active Status Bit 711" "Not active,Active" bitfld.long 0x00 6. " ASB710 ,Active Status Bit 710" "Not active,Active" bitfld.long 0x00 5. " ASB709 ,Active Status Bit 709" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB708 ,Active Status Bit 708" "Not active,Active" bitfld.long 0x00 3. " ASB707 ,Active Status Bit 707" "Not active,Active" bitfld.long 0x00 2. " ASB706 ,Active Status Bit 706" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB705 ,Active Status Bit 705" "Not active,Active" bitfld.long 0x00 0. " ASB704 ,Active Status Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_ICDABR22,Active Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" bitfld.long 0x00 31. " ASB767 ,Active Status Bit 767" "Not active,Active" bitfld.long 0x00 30. " ASB766 ,Active Status Bit 766" "Not active,Active" bitfld.long 0x00 29. " ASB765 ,Active Status Bit 765" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB764 ,Active Status Bit 764" "Not active,Active" bitfld.long 0x00 27. " ASB763 ,Active Status Bit 763" "Not active,Active" bitfld.long 0x00 26. " ASB762 ,Active Status Bit 762" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB761 ,Active Status Bit 761" "Not active,Active" bitfld.long 0x00 24. " ASB760 ,Active Status Bit 760" "Not active,Active" bitfld.long 0x00 23. " ASB759 ,Active Status Bit 759" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB758 ,Active Status Bit 758" "Not active,Active" bitfld.long 0x00 21. " ASB757 ,Active Status Bit 757" "Not active,Active" bitfld.long 0x00 20. " ASB756 ,Active Status Bit 756" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB755 ,Active Status Bit 755" "Not active,Active" bitfld.long 0x00 18. " ASB754 ,Active Status Bit 754" "Not active,Active" bitfld.long 0x00 17. " ASB753 ,Active Status Bit 753" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB752 ,Active Status Bit 752" "Not active,Active" bitfld.long 0x00 15. " ASB751 ,Active Status Bit 751" "Not active,Active" bitfld.long 0x00 14. " ASB750 ,Active Status Bit 750" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB749 ,Active Status Bit 749" "Not active,Active" bitfld.long 0x00 12. " ASB748 ,Active Status Bit 748" "Not active,Active" bitfld.long 0x00 11. " ASB747 ,Active Status Bit 747" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB746 ,Active Status Bit 746" "Not active,Active" bitfld.long 0x00 9. " ASB745 ,Active Status Bit 745" "Not active,Active" bitfld.long 0x00 8. " ASB744 ,Active Status Bit 744" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB743 ,Active Status Bit 743" "Not active,Active" bitfld.long 0x00 6. " ASB742 ,Active Status Bit 742" "Not active,Active" bitfld.long 0x00 5. " ASB741 ,Active Status Bit 741" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB740 ,Active Status Bit 740" "Not active,Active" bitfld.long 0x00 3. " ASB739 ,Active Status Bit 739" "Not active,Active" bitfld.long 0x00 2. " ASB738 ,Active Status Bit 738" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB737 ,Active Status Bit 737" "Not active,Active" bitfld.long 0x00 0. " ASB736 ,Active Status Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_ICDABR23,Active Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" bitfld.long 0x00 31. " ASB799 ,Active Status Bit 799" "Not active,Active" bitfld.long 0x00 30. " ASB798 ,Active Status Bit 798" "Not active,Active" bitfld.long 0x00 29. " ASB797 ,Active Status Bit 797" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB796 ,Active Status Bit 796" "Not active,Active" bitfld.long 0x00 27. " ASB795 ,Active Status Bit 795" "Not active,Active" bitfld.long 0x00 26. " ASB794 ,Active Status Bit 794" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB793 ,Active Status Bit 793" "Not active,Active" bitfld.long 0x00 24. " ASB792 ,Active Status Bit 792" "Not active,Active" bitfld.long 0x00 23. " ASB791 ,Active Status Bit 791" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB790 ,Active Status Bit 790" "Not active,Active" bitfld.long 0x00 21. " ASB789 ,Active Status Bit 789" "Not active,Active" bitfld.long 0x00 20. " ASB788 ,Active Status Bit 788" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB787 ,Active Status Bit 787" "Not active,Active" bitfld.long 0x00 18. " ASB786 ,Active Status Bit 786" "Not active,Active" bitfld.long 0x00 17. " ASB785 ,Active Status Bit 785" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB784 ,Active Status Bit 784" "Not active,Active" bitfld.long 0x00 15. " ASB783 ,Active Status Bit 783" "Not active,Active" bitfld.long 0x00 14. " ASB782 ,Active Status Bit 782" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB781 ,Active Status Bit 781" "Not active,Active" bitfld.long 0x00 12. " ASB780 ,Active Status Bit 780" "Not active,Active" bitfld.long 0x00 11. " ASB779 ,Active Status Bit 779" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB778 ,Active Status Bit 778" "Not active,Active" bitfld.long 0x00 9. " ASB777 ,Active Status Bit 777" "Not active,Active" bitfld.long 0x00 8. " ASB776 ,Active Status Bit 776" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB775 ,Active Status Bit 775" "Not active,Active" bitfld.long 0x00 6. " ASB774 ,Active Status Bit 774" "Not active,Active" bitfld.long 0x00 5. " ASB773 ,Active Status Bit 773" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB772 ,Active Status Bit 772" "Not active,Active" bitfld.long 0x00 3. " ASB771 ,Active Status Bit 771" "Not active,Active" bitfld.long 0x00 2. " ASB770 ,Active Status Bit 770" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB769 ,Active Status Bit 769" "Not active,Active" bitfld.long 0x00 0. " ASB768 ,Active Status Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_ICDABR24,Active Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" bitfld.long 0x00 31. " ASB831 ,Active Status Bit 831" "Not active,Active" bitfld.long 0x00 30. " ASB830 ,Active Status Bit 830" "Not active,Active" bitfld.long 0x00 29. " ASB829 ,Active Status Bit 829" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB828 ,Active Status Bit 828" "Not active,Active" bitfld.long 0x00 27. " ASB827 ,Active Status Bit 827" "Not active,Active" bitfld.long 0x00 26. " ASB826 ,Active Status Bit 826" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB825 ,Active Status Bit 825" "Not active,Active" bitfld.long 0x00 24. " ASB824 ,Active Status Bit 824" "Not active,Active" bitfld.long 0x00 23. " ASB823 ,Active Status Bit 823" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB822 ,Active Status Bit 822" "Not active,Active" bitfld.long 0x00 21. " ASB821 ,Active Status Bit 821" "Not active,Active" bitfld.long 0x00 20. " ASB820 ,Active Status Bit 820" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB819 ,Active Status Bit 819" "Not active,Active" bitfld.long 0x00 18. " ASB818 ,Active Status Bit 818" "Not active,Active" bitfld.long 0x00 17. " ASB817 ,Active Status Bit 817" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB816 ,Active Status Bit 816" "Not active,Active" bitfld.long 0x00 15. " ASB815 ,Active Status Bit 815" "Not active,Active" bitfld.long 0x00 14. " ASB814 ,Active Status Bit 814" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB813 ,Active Status Bit 813" "Not active,Active" bitfld.long 0x00 12. " ASB812 ,Active Status Bit 812" "Not active,Active" bitfld.long 0x00 11. " ASB811 ,Active Status Bit 811" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB810 ,Active Status Bit 810" "Not active,Active" bitfld.long 0x00 9. " ASB809 ,Active Status Bit 809" "Not active,Active" bitfld.long 0x00 8. " ASB808 ,Active Status Bit 808" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB807 ,Active Status Bit 807" "Not active,Active" bitfld.long 0x00 6. " ASB806 ,Active Status Bit 806" "Not active,Active" bitfld.long 0x00 5. " ASB805 ,Active Status Bit 805" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB804 ,Active Status Bit 804" "Not active,Active" bitfld.long 0x00 3. " ASB803 ,Active Status Bit 803" "Not active,Active" bitfld.long 0x00 2. " ASB802 ,Active Status Bit 802" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB801 ,Active Status Bit 801" "Not active,Active" bitfld.long 0x00 0. " ASB800 ,Active Status Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_ICDABR25,Active Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" bitfld.long 0x00 31. " ASB863 ,Active Status Bit 863" "Not active,Active" bitfld.long 0x00 30. " ASB862 ,Active Status Bit 862" "Not active,Active" bitfld.long 0x00 29. " ASB861 ,Active Status Bit 861" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB860 ,Active Status Bit 860" "Not active,Active" bitfld.long 0x00 27. " ASB859 ,Active Status Bit 859" "Not active,Active" bitfld.long 0x00 26. " ASB858 ,Active Status Bit 858" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB857 ,Active Status Bit 857" "Not active,Active" bitfld.long 0x00 24. " ASB856 ,Active Status Bit 856" "Not active,Active" bitfld.long 0x00 23. " ASB855 ,Active Status Bit 855" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB854 ,Active Status Bit 854" "Not active,Active" bitfld.long 0x00 21. " ASB853 ,Active Status Bit 853" "Not active,Active" bitfld.long 0x00 20. " ASB852 ,Active Status Bit 852" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB851 ,Active Status Bit 851" "Not active,Active" bitfld.long 0x00 18. " ASB850 ,Active Status Bit 850" "Not active,Active" bitfld.long 0x00 17. " ASB849 ,Active Status Bit 849" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB848 ,Active Status Bit 848" "Not active,Active" bitfld.long 0x00 15. " ASB847 ,Active Status Bit 847" "Not active,Active" bitfld.long 0x00 14. " ASB846 ,Active Status Bit 846" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB845 ,Active Status Bit 845" "Not active,Active" bitfld.long 0x00 12. " ASB844 ,Active Status Bit 844" "Not active,Active" bitfld.long 0x00 11. " ASB843 ,Active Status Bit 843" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB842 ,Active Status Bit 842" "Not active,Active" bitfld.long 0x00 9. " ASB841 ,Active Status Bit 841" "Not active,Active" bitfld.long 0x00 8. " ASB840 ,Active Status Bit 840" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB839 ,Active Status Bit 839" "Not active,Active" bitfld.long 0x00 6. " ASB838 ,Active Status Bit 838" "Not active,Active" bitfld.long 0x00 5. " ASB837 ,Active Status Bit 837" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB836 ,Active Status Bit 836" "Not active,Active" bitfld.long 0x00 3. " ASB835 ,Active Status Bit 835" "Not active,Active" bitfld.long 0x00 2. " ASB834 ,Active Status Bit 834" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB833 ,Active Status Bit 833" "Not active,Active" bitfld.long 0x00 0. " ASB832 ,Active Status Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_ICDABR26,Active Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" bitfld.long 0x00 31. " ASB895 ,Active Status Bit 895" "Not active,Active" bitfld.long 0x00 30. " ASB894 ,Active Status Bit 894" "Not active,Active" bitfld.long 0x00 29. " ASB893 ,Active Status Bit 893" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB892 ,Active Status Bit 892" "Not active,Active" bitfld.long 0x00 27. " ASB891 ,Active Status Bit 891" "Not active,Active" bitfld.long 0x00 26. " ASB890 ,Active Status Bit 890" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB889 ,Active Status Bit 889" "Not active,Active" bitfld.long 0x00 24. " ASB888 ,Active Status Bit 888" "Not active,Active" bitfld.long 0x00 23. " ASB887 ,Active Status Bit 887" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB886 ,Active Status Bit 886" "Not active,Active" bitfld.long 0x00 21. " ASB885 ,Active Status Bit 885" "Not active,Active" bitfld.long 0x00 20. " ASB884 ,Active Status Bit 884" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB883 ,Active Status Bit 883" "Not active,Active" bitfld.long 0x00 18. " ASB882 ,Active Status Bit 882" "Not active,Active" bitfld.long 0x00 17. " ASB881 ,Active Status Bit 881" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB880 ,Active Status Bit 880" "Not active,Active" bitfld.long 0x00 15. " ASB879 ,Active Status Bit 879" "Not active,Active" bitfld.long 0x00 14. " ASB878 ,Active Status Bit 878" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB877 ,Active Status Bit 877" "Not active,Active" bitfld.long 0x00 12. " ASB876 ,Active Status Bit 876" "Not active,Active" bitfld.long 0x00 11. " ASB875 ,Active Status Bit 875" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB874 ,Active Status Bit 874" "Not active,Active" bitfld.long 0x00 9. " ASB873 ,Active Status Bit 873" "Not active,Active" bitfld.long 0x00 8. " ASB872 ,Active Status Bit 872" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB871 ,Active Status Bit 871" "Not active,Active" bitfld.long 0x00 6. " ASB870 ,Active Status Bit 870" "Not active,Active" bitfld.long 0x00 5. " ASB869 ,Active Status Bit 869" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB868 ,Active Status Bit 868" "Not active,Active" bitfld.long 0x00 3. " ASB867 ,Active Status Bit 867" "Not active,Active" bitfld.long 0x00 2. " ASB866 ,Active Status Bit 866" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB865 ,Active Status Bit 865" "Not active,Active" bitfld.long 0x00 0. " ASB864 ,Active Status Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_ICDABR27,Active Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" bitfld.long 0x00 31. " ASB927 ,Active Status Bit 927" "Not active,Active" bitfld.long 0x00 30. " ASB926 ,Active Status Bit 926" "Not active,Active" bitfld.long 0x00 29. " ASB925 ,Active Status Bit 925" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB924 ,Active Status Bit 924" "Not active,Active" bitfld.long 0x00 27. " ASB923 ,Active Status Bit 923" "Not active,Active" bitfld.long 0x00 26. " ASB922 ,Active Status Bit 922" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB921 ,Active Status Bit 921" "Not active,Active" bitfld.long 0x00 24. " ASB920 ,Active Status Bit 920" "Not active,Active" bitfld.long 0x00 23. " ASB919 ,Active Status Bit 919" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB918 ,Active Status Bit 918" "Not active,Active" bitfld.long 0x00 21. " ASB917 ,Active Status Bit 917" "Not active,Active" bitfld.long 0x00 20. " ASB916 ,Active Status Bit 916" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB915 ,Active Status Bit 915" "Not active,Active" bitfld.long 0x00 18. " ASB914 ,Active Status Bit 914" "Not active,Active" bitfld.long 0x00 17. " ASB913 ,Active Status Bit 913" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB912 ,Active Status Bit 912" "Not active,Active" bitfld.long 0x00 15. " ASB911 ,Active Status Bit 911" "Not active,Active" bitfld.long 0x00 14. " ASB910 ,Active Status Bit 910" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB909 ,Active Status Bit 909" "Not active,Active" bitfld.long 0x00 12. " ASB908 ,Active Status Bit 908" "Not active,Active" bitfld.long 0x00 11. " ASB907 ,Active Status Bit 907" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB906 ,Active Status Bit 906" "Not active,Active" bitfld.long 0x00 9. " ASB905 ,Active Status Bit 905" "Not active,Active" bitfld.long 0x00 8. " ASB904 ,Active Status Bit 904" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB903 ,Active Status Bit 903" "Not active,Active" bitfld.long 0x00 6. " ASB902 ,Active Status Bit 902" "Not active,Active" bitfld.long 0x00 5. " ASB901 ,Active Status Bit 901" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB900 ,Active Status Bit 900" "Not active,Active" bitfld.long 0x00 3. " ASB899 ,Active Status Bit 899" "Not active,Active" bitfld.long 0x00 2. " ASB898 ,Active Status Bit 898" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB897 ,Active Status Bit 897" "Not active,Active" bitfld.long 0x00 0. " ASB896 ,Active Status Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_ICDABR28,Active Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" bitfld.long 0x00 31. " ASB959 ,Active Status Bit 959" "Not active,Active" bitfld.long 0x00 30. " ASB958 ,Active Status Bit 958" "Not active,Active" bitfld.long 0x00 29. " ASB957 ,Active Status Bit 957" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB956 ,Active Status Bit 956" "Not active,Active" bitfld.long 0x00 27. " ASB955 ,Active Status Bit 955" "Not active,Active" bitfld.long 0x00 26. " ASB954 ,Active Status Bit 954" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB953 ,Active Status Bit 953" "Not active,Active" bitfld.long 0x00 24. " ASB952 ,Active Status Bit 952" "Not active,Active" bitfld.long 0x00 23. " ASB951 ,Active Status Bit 951" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB950 ,Active Status Bit 950" "Not active,Active" bitfld.long 0x00 21. " ASB949 ,Active Status Bit 949" "Not active,Active" bitfld.long 0x00 20. " ASB948 ,Active Status Bit 948" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB947 ,Active Status Bit 947" "Not active,Active" bitfld.long 0x00 18. " ASB946 ,Active Status Bit 946" "Not active,Active" bitfld.long 0x00 17. " ASB945 ,Active Status Bit 945" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB944 ,Active Status Bit 944" "Not active,Active" bitfld.long 0x00 15. " ASB943 ,Active Status Bit 943" "Not active,Active" bitfld.long 0x00 14. " ASB942 ,Active Status Bit 942" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB941 ,Active Status Bit 941" "Not active,Active" bitfld.long 0x00 12. " ASB940 ,Active Status Bit 940" "Not active,Active" bitfld.long 0x00 11. " ASB939 ,Active Status Bit 939" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB938 ,Active Status Bit 938" "Not active,Active" bitfld.long 0x00 9. " ASB937 ,Active Status Bit 937" "Not active,Active" bitfld.long 0x00 8. " ASB936 ,Active Status Bit 936" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB935 ,Active Status Bit 935" "Not active,Active" bitfld.long 0x00 6. " ASB934 ,Active Status Bit 934" "Not active,Active" bitfld.long 0x00 5. " ASB933 ,Active Status Bit 933" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB932 ,Active Status Bit 932" "Not active,Active" bitfld.long 0x00 3. " ASB931 ,Active Status Bit 931" "Not active,Active" bitfld.long 0x00 2. " ASB930 ,Active Status Bit 930" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB929 ,Active Status Bit 929" "Not active,Active" bitfld.long 0x00 0. " ASB928 ,Active Status Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_ICDABR29,Active Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" bitfld.long 0x00 31. " ASB991 ,Active Status Bit 991" "Not active,Active" bitfld.long 0x00 30. " ASB990 ,Active Status Bit 990" "Not active,Active" bitfld.long 0x00 29. " ASB989 ,Active Status Bit 989" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB988 ,Active Status Bit 988" "Not active,Active" bitfld.long 0x00 27. " ASB987 ,Active Status Bit 987" "Not active,Active" bitfld.long 0x00 26. " ASB986 ,Active Status Bit 986" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB985 ,Active Status Bit 985" "Not active,Active" bitfld.long 0x00 24. " ASB984 ,Active Status Bit 984" "Not active,Active" bitfld.long 0x00 23. " ASB983 ,Active Status Bit 983" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB982 ,Active Status Bit 982" "Not active,Active" bitfld.long 0x00 21. " ASB981 ,Active Status Bit 981" "Not active,Active" bitfld.long 0x00 20. " ASB980 ,Active Status Bit 980" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB979 ,Active Status Bit 979" "Not active,Active" bitfld.long 0x00 18. " ASB978 ,Active Status Bit 978" "Not active,Active" bitfld.long 0x00 17. " ASB977 ,Active Status Bit 977" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB976 ,Active Status Bit 976" "Not active,Active" bitfld.long 0x00 15. " ASB975 ,Active Status Bit 975" "Not active,Active" bitfld.long 0x00 14. " ASB974 ,Active Status Bit 974" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB973 ,Active Status Bit 973" "Not active,Active" bitfld.long 0x00 12. " ASB972 ,Active Status Bit 972" "Not active,Active" bitfld.long 0x00 11. " ASB971 ,Active Status Bit 971" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB970 ,Active Status Bit 970" "Not active,Active" bitfld.long 0x00 9. " ASB969 ,Active Status Bit 969" "Not active,Active" bitfld.long 0x00 8. " ASB968 ,Active Status Bit 968" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB967 ,Active Status Bit 967" "Not active,Active" bitfld.long 0x00 6. " ASB966 ,Active Status Bit 966" "Not active,Active" bitfld.long 0x00 5. " ASB965 ,Active Status Bit 965" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB964 ,Active Status Bit 964" "Not active,Active" bitfld.long 0x00 3. " ASB963 ,Active Status Bit 963" "Not active,Active" bitfld.long 0x00 2. " ASB962 ,Active Status Bit 962" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB961 ,Active Status Bit 961" "Not active,Active" bitfld.long 0x00 0. " ASB960 ,Active Status Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_ICDABR30,Active Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)==0x1F) rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active" bitfld.long 0x00 26. " ASB1018 ,Active Status Bit 1018" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active" bitfld.long 0x00 24. " ASB1016 ,Active Status Bit 1016" "Not active,Active" bitfld.long 0x00 23. " ASB1015 ,Active Status Bit 1015" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active" bitfld.long 0x00 21. " ASB1013 ,Active Status Bit 1013" "Not active,Active" bitfld.long 0x00 20. " ASB1012 ,Active Status Bit 1012" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active" bitfld.long 0x00 18. " ASB1010 ,Active Status Bit 1010" "Not active,Active" bitfld.long 0x00 17. " ASB1009 ,Active Status Bit 1009" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active" bitfld.long 0x00 15. " ASB1007 ,Active Status Bit 1007" "Not active,Active" bitfld.long 0x00 14. " ASB1006 ,Active Status Bit 1006" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active" bitfld.long 0x00 12. " ASB1004 ,Active Status Bit 1004" "Not active,Active" bitfld.long 0x00 11. " ASB1003 ,Active Status Bit 1003" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active" bitfld.long 0x00 9. " ASB1001 ,Active Status Bit 1001" "Not active,Active" bitfld.long 0x00 8. " ASB1000 ,Active Status Bit 1000" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB999 ,Active Status Bit 999" "Not active,Active" bitfld.long 0x00 6. " ASB998 ,Active Status Bit 998" "Not active,Active" bitfld.long 0x00 5. " ASB997 ,Active Status Bit 997" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB996 ,Active Status Bit 996" "Not active,Active" bitfld.long 0x00 3. " ASB995 ,Active Status Bit 995" "Not active,Active" bitfld.long 0x00 2. " ASB994 ,Active Status Bit 994" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB993 ,Active Status Bit 993" "Not active,Active" bitfld.long 0x00 0. " ASB992 ,Active Status Bit 992" "Not active,Active" else hgroup.long 0x037C++0x03 hide.long 0x0 "GICD_ICDABR31,Active Status Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 20. tree "Priority Registers" group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1F) group.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 " group.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 " group.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000" group.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004" group.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008" group.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012" group.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016" else hgroup.long 0x7E0++0x03 hide.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hgroup.long 0x7E4++0x03 hide.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hgroup.long 0x7E8++0x03 hide.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hgroup.long 0x7EC++0x03 hide.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hgroup.long 0x7F0++0x03 hide.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hgroup.long 0x7F4++0x03 hide.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hgroup.long 0x7F8++0x03 hide.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" endif tree.end width 19. tree "Processor Targets Registers" if (((d.l(AD:0x48241000+0x04))&0x000000E0)>0x1) rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 " if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1F) group.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 " group.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 " group.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000" group.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004" group.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008" group.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012" group.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016" else hgroup.long 0xBE0++0x03 hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hgroup.long 0xBE4++0x03 hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hgroup.long 0xBE8++0x03 hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hgroup.long 0xBEC++0x03 hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hgroup.long 0xBF0++0x03 hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hgroup.long 0xBF4++0x03 hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hgroup.long 0xBF8++0x03 hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hgroup.long 0xBE0++0x03 hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hgroup.long 0xBE4++0x03 hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hgroup.long 0xBE8++0x03 hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hgroup.long 0xBEC++0x03 hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hgroup.long 0xBF0++0x03 hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hgroup.long 0xBF4++0x03 hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hgroup.long 0xBF8++0x03 hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif tree.end width 14. tree "Configuration Registers" hgroup.long 0xC00++0x03 hide.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" textline " " rgroup.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1F) group.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCF8++0x03 hide.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" hgroup.long 0xCFC++0x03 hide.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" endif tree.end width 12. tree "Peripheral Interrupt Status Registers" rgroup.long 0x0D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI_C[15] ,Returns the status of the ppi_c[15] inputs on the Distributor" "Low,High" bitfld.long 0x00 14. " PPI_C[14] ,Returns the status of the ppi_c[14] inputs on the Distributor" "Low,High" bitfld.long 0x00 13. " PPI_C[13] ,Returns the status of the ppi_c[13] inputs on the Distributor" "Low,High" bitfld.long 0x00 12. " PPI_C[12] ,Returns the status of the ppi_c[12] inputs on the Distributor" "Low,High" textline " " bitfld.long 0x00 11. " PPI_C[11] ,Returns the status of the ppi_c[11] inputs on the Distributor" "Low,High" bitfld.long 0x00 10. " PPI_C[10] ,Returns the status of the ppi_c[10] inputs on the Distributor" "Low,High" bitfld.long 0x00 9. " PPI_C[9] ,Returns the status of the ppi_c[9] inputs on the Distributor" "Low,High" bitfld.long 0x00 8. " PPI_C[8] ,Returns the status of the ppi_c[8] inputs on the Distributor" "Low,High" textline " " bitfld.long 0x00 7. " PPI_C[7] ,Returns the status of the ppi_c[7] inputs on the Distributor" "Low,High" bitfld.long 0x00 6. " PPI_C[6] ,Returns the status of the ppi_c[6] inputs on the Distributor" "Low,High" bitfld.long 0x00 5. " PPI_C[5] ,Returns the status of the ppi_c[5] inputs on the Distributor" "Low,High" bitfld.long 0x00 4. " PPI_C[4] ,Returns the status of the ppi_c[4] inputs on the Distributor" "Low,High" textline " " bitfld.long 0x00 3. " PPI_C[3] ,Returns the status of the ppi_c[3] inputs on the Distributor" "Low,High" bitfld.long 0x00 2. " PPI_C[2] ,Returns the status of the ppi_c[2] inputs on the Distributor" "Low,High" bitfld.long 0x00 1. " PPI_C[1] ,Returns the status of the ppi_c[1] inputs on the Distributor" "Low,High" bitfld.long 0x00 0. " PPI_C[0] ,Returns the status of the ppi_c[0] inputs on the Distributor" "Low,High" textline " " width 22. if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High" bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High" bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High" textline " " bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High" bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High" bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High" textline " " bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High" bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High" bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High" textline " " bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High" bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High" bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High" textline " " bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High" bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High" bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High" textline " " bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High" bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High" bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High" textline " " bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High" bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High" bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High" textline " " bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High" bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High" bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High" textline " " bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High" bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High" bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High" textline " " bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High" bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High" bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High" textline " " bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High" bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High" bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High" bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High" bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High" bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High" bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High" bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High" bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High" bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High" bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High" bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High" bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High" bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High" bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High" bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High" bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High" bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High" bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High" bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High" bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High" bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High" bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High" bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High" bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High" bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High" bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High" bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High" bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High" bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High" bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High" bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High" bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High" bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High" bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High" bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High" bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High" bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High" bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High" bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High" bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High" bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High" bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High" bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High" bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High" bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High" bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High" bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High" bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High" bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High" bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High" bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High" bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High" bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High" bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High" bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High" bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High" bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High" bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High" bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High" bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High" bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High" bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High" bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High" bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High" bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High" bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High" bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High" bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High" bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High" bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High" bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High" bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High" bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High" bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High" bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High" bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High" bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High" bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High" bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High" bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High" bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High" bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High" bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High" bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High" bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High" bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High" bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High" bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High" bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High" bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High" bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High" bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High" bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High" bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High" bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High" bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High" bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High" bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High" bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High" bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High" bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High" bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High" bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High" bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High" bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High" bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High" bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High" bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High" bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High" bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High" bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High" bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High" bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High" bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High" bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High" bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High" bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High" bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High" bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High" bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High" bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High" bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High" bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High" bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High" bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High" bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High" bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High" bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High" bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High" bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High" bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High" bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High" bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High" bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High" bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High" bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High" bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High" bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High" bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High" bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High" bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High" bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High" bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High" bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High" bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High" bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High" bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High" bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High" bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High" bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High" bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High" bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High" bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High" bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High" bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High" bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High" bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High" bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High" bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High" bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High" bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High" bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High" bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High" bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High" bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High" bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High" bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High" bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High" bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High" bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High" bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High" bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High" bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High" bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High" bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High" bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High" bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High" bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High" bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High" bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High" bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High" bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High" bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High" bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High" bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High" bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High" bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High" bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High" bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High" bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High" bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High" bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High" bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High" bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High" bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High" bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High" bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High" bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High" bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High" bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High" bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High" bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High" bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High" bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High" bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High" bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High" bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High" bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High" bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High" bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High" bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High" bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High" bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High" bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High" bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High" bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High" bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High" bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High" bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High" bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High" bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High" bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High" bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High" bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High" bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High" bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High" bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High" bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High" bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High" bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High" bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High" bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High" bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High" bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High" bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High" bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High" bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High" bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High" bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High" bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High" bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High" bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High" bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High" bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High" bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High" bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High" bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High" bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High" bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High" bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High" bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High" bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High" bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High" bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High" bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High" bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High" bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High" bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High" bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High" bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High" bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High" bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High" bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High" bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High" bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High" bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High" bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High" bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High" bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High" bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High" bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High" bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High" bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High" bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High" bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High" bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High" bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High" bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High" bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High" bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High" bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High" bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High" bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High" bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High" bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High" bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High" bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High" bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High" bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High" bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High" bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High" bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High" bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High" bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High" bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High" bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High" bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High" bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High" bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High" bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High" bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High" bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High" bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High" bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High" bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High" bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High" bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High" bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High" bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High" bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High" bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High" bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High" bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High" bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High" bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High" bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High" bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High" bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High" bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High" bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High" bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High" bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High" bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High" bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High" bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High" bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High" bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High" bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High" bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High" bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High" bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High" bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High" bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High" bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High" bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High" bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High" bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High" bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High" bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High" bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High" bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High" bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High" bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High" bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High" bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High" bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High" bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High" bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High" bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High" bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High" bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High" bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High" bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High" bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High" bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High" bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High" bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High" bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High" bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High" bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High" bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High" bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High" bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High" bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High" bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High" bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High" bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High" bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High" bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High" bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High" bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High" bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High" bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High" bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High" bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High" bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High" bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High" bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High" bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High" bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High" bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High" bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High" bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High" bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High" bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High" bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High" bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High" bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High" bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High" bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High" bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High" bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High" bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High" bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High" bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High" bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High" bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High" bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High" bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High" bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High" bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High" bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High" bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High" bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High" bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High" bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High" bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High" bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High" bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High" bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High" bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High" bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High" bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High" bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High" bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High" bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High" bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High" bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High" bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High" bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High" bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High" bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High" bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High" bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High" bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High" bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High" bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High" bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High" bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High" bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High" bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High" bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High" bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High" bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High" bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High" bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High" bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High" bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High" bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High" bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High" bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High" bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High" bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High" bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High" bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High" bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High" bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High" bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High" bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High" bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High" bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High" bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High" bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High" bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High" bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High" bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High" bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High" bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High" bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High" bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High" bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High" bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High" bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) rgroup.long 0x060++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High" bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High" bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High" bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High" bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High" bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High" bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High" bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High" bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High" bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High" bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High" bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High" bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High" bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High" bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High" bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High" bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High" bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High" bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High" bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High" bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High" bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High" bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High" bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High" bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High" bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High" bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High" bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High" bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High" bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High" bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High" bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High" bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High" bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High" bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High" bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High" bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High" bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High" bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High" bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High" bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High" bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High" bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High" bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High" bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High" bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High" bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High" bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High" bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High" bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High" bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High" bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High" bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High" bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High" bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High" bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High" bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High" bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High" bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High" bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High" bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High" bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High" bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High" bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High" bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High" bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High" bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High" bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High" bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High" bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High" bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High" bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High" bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High" bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High" bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High" bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High" bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High" bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High" bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High" bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High" bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High" bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High" bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High" bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High" bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High" bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High" bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High" bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High" bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High" bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High" bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High" bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High" bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High" bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High" bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High" bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High" bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High" bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High" bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High" bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High" bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High" bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High" bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High" bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High" bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High" bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High" bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High" bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High" bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High" bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High" bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High" bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High" bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High" bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High" bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High" bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High" bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High" bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High" bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High" bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High" bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High" bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High" bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High" bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High" bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High" bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High" bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High" bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High" bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High" bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High" bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High" bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High" bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High" bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High" bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High" bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High" bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High" bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High" bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High" bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High" bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High" bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High" bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High" bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High" bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High" bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High" bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High" bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1F) rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High" bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High" bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High" bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High" bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High" bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High" bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High" bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High" bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High" bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High" bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High" bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High" bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High" bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High" bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High" bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High" bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High" bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High" bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High" else hgroup.long 0x0D7C++0x03 hide.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 25. tree "Software Generated Interrupt" if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.byte 0x0FE0++0x00 line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.byte 0x00 0.--7. 1. " PART_NUMBER_0 ,Returns 0x90" rgroup.byte 0x0FE4++0x00 line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.byte 0x00 4.--7. " JEP106_ID_3_0 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PART_NUMBER_1 ,Returns 0x3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FE8++0x00 line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.byte 0x00 4.--7. " ARCHITECTURE ,Identifies the architecture version of the GIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 3. " JEDEC_USED ,This indicates that the GIC uses a manufacturers identity code that was allocated by JEDEC according to JEP106" "Low,High" bitfld.byte 0x00 0.--2. " JEP106_ID_CODE ,JEP106 identity code field" "0,1,2,3,4,5,6,7" rgroup.byte 0x0FEC++0x00 line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.byte 0x00 4.--7. " REVAND ,The top-level RTL provides four AND gates that are tied-off to provide an output value of 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " MOD_NUMBER ,The customer can update this field if they modify the RTL of the GIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD0++0x00 line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.byte 0x00 4.--7. " 4KB_COUNT ,The number of 4KB address blocks you require to access the registers expressed in powers of 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " JEP106_C_CODE ,The JEP106 continuation code value represents how many 0x7F continuation characters occur in the manufacturers identity code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD4++0x00 line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register" bitfld.byte 0x00 5.--7. " PPI_NUMBER_0 ,The LSBs of the number of PPIs that the GIC provides" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--4. " SGI_NUMBER ,The number of SGIs that the GIC provides" "None,INTID0,INTID[1:0],INTID[2:0],INTID[3:0],INTID[4:0],INTID[5:0],INTID[6:0],INTID[7:0],INTID[8:0],INTID[9:0],INTID[10:0],INTID[11:0],INTID[12:0],INTID[13:0],INTID[14:0],INTID[15:0],?..." rgroup.byte 0x0FD8++0x00 line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register" bitfld.byte 0x00 2.--7. " SPI_NUMBER_0 ,The LSBs of the number of SPIs that the GIC provides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.byte 0x00 0.--1. " PPI_NUMBER_1 ,The MSBs of the number of PPIs that the GIC provides" "0,1,2,3" rgroup.byte 0x0FDC++0x00 line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register" bitfld.byte 0x00 7. " TZ ,Identifies the number of security states that the GIC supports" "S,NS&S" bitfld.byte 0x00 4.--6. " PRIORITY ,The number of priority levels that the GIC provides" "16,32,64,128,256,?..." bitfld.byte 0x00 0.--3. " SPI_NUMBER_1 ,The MSBs of the number of SPIs that the GIC provides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FC0++0x00 line.byte 0x00 "GICD_PIDR8,Peripheral ID8 Register" bitfld.byte 0x00 7. " IDENTIFIER ,Identifies the AMBA interface that this register belongs to" "Distributor,CPU Interface" bitfld.byte 0x00 5.--6. " IF_TYPE ,Identifies the AMBA protocol that the GIC supports" "AXI,AHB-Lite,?..." bitfld.byte 0x00 2.--4. " CPU_IF ,Identifies the number of CPU Interfaces that the GIC contains" "1,2,3,4,5,6,7,8" textline " " bitfld.byte 0x00 1. " FIQ_LEGACY ,Identifies if the GIC provides a legacy FIQ input signal for each CPU Interface" "Not supported,Supported" bitfld.byte 0x00 0. " IRQ_LEGACY ,Identifies if the GIC provides a legacy IRQ input signal for each CPU Interface" "Not supported,Supported" tree.end tree.end base AD:0x48240100 width 17. tree "CPU Interface" if (((d.l(AD:0x48241000+0x04))&0x400)==0x0) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 0. " ENABLE ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " textline " " else group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)" bitfld.long 0x00 0. " ENABLE ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " textline " " endif group.long 0x0004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif hgroup.long 0x000C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) group.long 0x001C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else hgroup.long 0x001C++0x03 hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register" endif rgroup.long 0x00FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" tree.end width 0x0B tree.end tree.end tree.open "PRCM" tree "CORE_CM2" base ad:0x4A008700 width 29. group.long 0x0++0x3 line.long 0x00 "CM_L3_1_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 8. " CLKACTIVITY_L3_1_ICLK ,This field indicates the state of the L3_1_ICLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3_1 clock domain. - . - . - . - ." "NO_SLEEP,Reserved,Reserved,HW_AUTO" group.long 0x8++0x3 line.long 0x00 "CM_L3_1_DYNAMICDEP,This register controls the dynamic domain depedencies from L3_1 domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12. " L4CFG_DYNDEP ,Dynamic dependency towards L4CFG clock domain - ." "0,Enabled" bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 4. " MEMIF_DYNDEP ,Dynamic dependency towards MEMIF clock domain - ." "0,Enabled" bitfld.long 0x00 3. " ABE_DYNDEP ,Dynamic dependency towards ABE clock domain - ." "0,Enabled" rgroup.long 0x20++0x3 line.long 0x00 "CM_L3_1_L3_1_CLKCTRL,This register manages the L3_1 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0x100++0x3 line.long 0x00 "CM_L3_2_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 8. " CLKACTIVITY_L3_2_ICLK ,This field indicates the state of the L3_2_ICLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3_2 clock domain. - . - . - . - ." "NO_SLEEP,Reserved,Reserved,HW_AUTO" group.long 0x108++0x3 line.long 0x00 "CM_L3_2_DYNAMICDEP,This register controls the dynamic domain dependencies from L3_2 domain towards 'target' domains. It is relevant only for domain having INTERCONN master port(s)." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14. " L4SEC_DYNDEP ,Dynamic dependency towards L4SEC clock domain - ." "0,Enabled" bitfld.long 0x00 13. " L4PER_DYNDEP ,Dynamic dependency towards L4PER clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 10. " SGX_DYNDEP ,Dynamic dependency towards SGX clock domain - ." "0,Enabled" bitfld.long 0x00 9. " CAM_DYNDEP ,Dynamic dependency towards ISS clock domain - ." "Disabled,1" bitfld.long 0x00 8. " DSS_DYNDEP ,Dynamic dependency towards DSS clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 7. " L3_INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain - ." "0,Enabled" bitfld.long 0x00 5. " L3_1_DYNDEP ,Dynamic dependency towards L3_1 clock domain - ." "0,Enabled" bitfld.long 0x00 2. " IVAHD_DYNDEP ,Dynamic dependency towards IVAHD clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 0. " MPU_M3_DYNDEP ,Dynamic dependency towards CORTEXM3 clock domain - ." "0,Enabled" rgroup.long 0x120++0x3 line.long 0x00 "CM_L3_2_L3_2_CLKCTRL,This register manages the L3_2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0x128++0x3 line.long 0x00 "CM_L3_2_GPMC_CLKCTRL,This register manages the GPMC clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." rgroup.long 0x130++0x3 line.long 0x00 "CM_L3_2_OCMC_RAM_CLKCTRL,This register manages the OCMC_RAM clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0x200++0x3 line.long 0x00 "CM_MPU_M3_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 8. " CLKACTIVITY_MPU_M3_CLK ,This field indicates the state of the MPU_M3_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the MPU_A3 clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x204++0x3 line.long 0x00 "CM_MPU_M3_STATICDEP,This register controls the static domain dependencies from MPU_M3 domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 16. " ALWONCORE_STATDEP ,Static dependency towards ALWONCORE clock domain - ." "Disabled,1" bitfld.long 0x00 15. " L4WKUP_STATDEP ,Static dependency towards L4WKUP clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 11. " SDMA_STATDEP ,Static dependency towards SDMA clock domain - ." "Disabled,1" textline " " bitfld.long 0x00 10. " SGX_STATDEP ,Static dependency towards SGX clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " ISS_STATDEP ,Static dependency towards ISS clock domain - ." "Disabled,1" bitfld.long 0x00 8. " DSS_STATDEP ,Static dependency towards DSS clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 3. " ABE_STATDEP ,Static dependency towards ABE clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DSP_STATDEP ,Static dependency towards DSP clock domain - . - ." "Disabled,Enabled" group.long 0x208++0x3 line.long 0x00 "CM_MPU_M3_DYNAMICDEP,This register controls the dynamic domain depedencies from MPU_A3 domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. " CAM_DYNDEP ,Dynamic dependency towards ISS clock domain - ." "Disabled,1" bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "0,Enabled" group.long 0x220++0x3 line.long 0x00 "CM_MPU_M3_MPU_M3_CLKCTRL,This register manages the MPU_A3 clocks." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disable" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x300++0x3 line.long 0x00 "CM_SDMA_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 8. " CLKACTIVITY_DMA_L3_ICLK ,This field indicates the state of the DMA_L3_ICLK clock in the domain. [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the SDMA clock domain. - . - . - . - ." "NO_SLEEP,Reserved,SW_WKUP,HW_AUTO" group.long 0x304++0x3 line.long 0x00 "CM_SDMA_STATICDEP,This register controls the static domain dependencies from SDMA domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 15. " L4WKUP_STATDEP ,Static dependency towards L4WKUP clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " ISS_STATDEP ,Static dependency towards ISS clock domain - ." "Disabled,1" bitfld.long 0x00 8. " DSS_STATDEP ,Static dependency towards DSS clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - ." "0,Enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 3. " ABE_STATDEP ,Static dependency towards ABE clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MPU_M3_STATDEP ,Static dependency towards MPU_A3 clock domain - . - ." "Disabled,Enabled" rgroup.long 0x308++0x3 line.long 0x00 "CM_SDMA_DYNAMICDEP,This register controls the dynamic domain depedencies from SDMA domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "Disabled,1" rgroup.long 0x320++0x3 line.long 0x00 "CM_SDMA_SDMA_CLKCTRL,This register manages the SDMA clocks." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0x400++0x3 line.long 0x00 "CM_MEMIF_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 10. " CLKACTIVITY_PHY_ROOT_CLK ,This field indicates the state of the PHY_ROOT_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 9. " CLKACTIVITY_DLL_CLK ,This field indicates the state of the DLL_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 8. " CLKACTIVITY_L3_EMIF_ICLK ,This field indicates the state of the L3_EMIF_ICLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the MEMIF clock domain. - . - . - . - ." "NO_SLEEP,Reserved,SW_WKUP,HW_AUTO" rgroup.long 0x420++0x3 line.long 0x00 "CM_MEMIF_DMM_CLKCTRL,This register manages the DMM clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" rgroup.long 0x428++0x3 line.long 0x00 "CM_MEMIF_EMIF_FW_CLKCTRL,This register manages the EMIF_FW clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0x430++0x3 line.long 0x00 "CM_MEMIF_EMIF_1_CLKCTRL,This register manages the EMIF_1 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x438++0x3 line.long 0x00 "CM_MEMIF_EMIF_2_CLKCTRL,This register manages the EMIF_2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x440++0x3 line.long 0x00 "CM_MEMIF_DLL_CLKCTRL,This register manages the DLL clock." bitfld.long 0x00 8. " OPTFCLKEN_DLL_CLK ,Optional functional clock control. - . - ." "Disabled,Enabled" group.long 0x500++0x3 line.long 0x00 "CM_C2C_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 10. " CLKACTIVITY_L3X2_C2C_ICLK ,This field indicates the state of the C2C_L3X2_ICLK clock in the domain. [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 9. " CLKACTIVITY_L4_C2C_ICLK ,This field indicates the state of the L4_C2C_ICLK clock in the domain. [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 8. " CLKACTIVITY_L3_C2C_ICLK ,This field indicates the state of the L3_C2C_ICLK clock in the domain. [warm reset insensitive] - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the C2C clock domain. - . - . - . - ." "0,Reserved,2,3" group.long 0x504++0x3 line.long 0x00 "CM_C2C_STATICDEP,This register controls the static domain depedencies from C2C domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" textline " " bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" textline " " bitfld.long 0x00 3. " ABE_STATDEP ,Static dependency towards ABE clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0x508++0x3 line.long 0x00 "CM_C2C_DYNAMICDEP,This register controls the dynamic domain depedencies from C2C domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 4. " MEMIF_DYNDEP ,Dynamic dependency towards MEMIF clock domain - ." "0,Dependency_is_enabled" rgroup.long 0x520++0x3 line.long 0x00 "CM_C2C_C2C_CLKCTRL,This register manages the C2C clocks." bitfld.long 0x00 18. " STBYST ,C2C module standby status. [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 16.--17. " IDLEST ,C2C interface idle status. [warm reset insensitive] - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,1,2,3" rgroup.long 0x530++0x3 line.long 0x00 "CM_C2C_C2C_FW_CLKCTRL,This register manages the C2C_FW clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,1,2,3" group.long 0x600++0x3 line.long 0x00 "CM_L4CFG_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 8. " CLKACTIVITY_CFG_L4_ICLK ,This field indicates the state of the CFG_L4_ICLK clock in the domain. [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4CFG clock domain. - . - . - . - ." "NO_SLEEP,Reserved,Reserved,HW_AUTO" group.long 0x608++0x3 line.long 0x00 "CM_L4CFG_DYNAMICDEP,This register controls the dynamic domain depedencies from L4_CFG domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18. " C2C_DYNDEP ,Dynamic dependency towards C2C clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 16. " ALWONCORE_DYNDEP ,Dynamic dependency towards ALWONCORE clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 15. " L4WKUP_DYNDEP ,Dynamic dependency towards L4WKUP clock domain - ." "0,Enabled" bitfld.long 0x00 11. " SDMA_DYNDEP ,Dynamic dependency towards SDMA clock domain - ." "0,Enabled" bitfld.long 0x00 9. " CAM_DYNDEP ,Dynamic dependency towards ISS clock domain - ." "Disabled,1" textline " " bitfld.long 0x00 8. " DSS_DYNDEP ,Dynamic dependency towards DSS clock domain - ." "0,Enabled" bitfld.long 0x00 7. " L3_INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 5. " L3_1_DYNDEP ,Dynamic dependency towards L3_1 clock domain - ." "0,Enabled" bitfld.long 0x00 4. " MEMIF_DYNDEP ,Dynamic dependency towards MEMIF clock domain - ." "0,Enabled" bitfld.long 0x00 1. " DSP_DYNDEP ,Dynamic dependency towards DSP clock domain - ." "0,Enabled" rgroup.long 0x620++0x3 line.long 0x00 "CM_L4CFG_L4_CFG_CLKCTRL,This register manages the L4_CFG clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" rgroup.long 0x628++0x3 line.long 0x00 "CM_L4CFG_SPINLOCK_CLKCTRL,This register manages the HW_SEM clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" rgroup.long 0x630++0x3 line.long 0x00 "CM_L4CFG_MAILBOX_CLKCTRL,This register manages the MAILBOX clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" rgroup.long 0x638++0x3 line.long 0x00 "CM_L4CFG_SAR_ROM_CLKCTRL,This register manages the SAR_ROM clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" rgroup.long 0x700++0x3 line.long 0x00 "CM_L3INSTR_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 8. " CLKACTIVITY_L3_INSTR_ICLK ,This field indicates the state of the L3_INSTR_GICLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3INSTR clock domain. - ." "0,1,2,HW_AUTO" group.long 0x720++0x3 line.long 0x00 "CM_L3INSTR_L3_3_CLKCTRL,This register manages the L3_3 clocks. [warm reset insensitive]" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x728++0x3 line.long 0x00 "CM_L3INSTR_L3_INSTR_CLKCTRL,This register manages the L3 INSTRUMENTATION clocks. [warm reset insensitive]" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x740++0x3 line.long 0x00 "CM_L3INSTR_OCP_WP1_CLKCTRL,This register manages the OCP_WP1 clocks. [warm reset insensitive]" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,1,?..." tree.end tree "CAM_PRM" base ad:0x4A307000 width 21. group.long 0x0++0x3 line.long 0x00 "PM_CAM_PWRSTCTRL,This register controls the CAM power state to reach upon a domain sleep transition" bitfld.long 0x00 16.--17. " CAM_MEM_ONSTATE ,CAM_MEM memory state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "Off,Reserved,Inactive,On" rgroup.long 0x4++0x3 line.long 0x00 "PM_CAM_PWRSTST,This register provides a status on the current CAM power domain state. [warm reset insensitive]" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 4.--5. " CAM_MEM_STATEST ,CAM_MEM memory state status - . - . - . - ." "Off,Reserved,Reserved,On" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" textline " " bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Off,Retention,On-Inactive,On-Active" group.long 0x24++0x3 line.long 0x00 "RM_CAM_ISS_CONTEXT,This register contains dedicated ISS context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_CAM_MEM ,Specify if memory-based context in CAM_MEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CAM_RST signal) - . - ." "Maintained,Lost" group.long 0x2C++0x3 line.long 0x00 "RM_CAM_FDIF_CONTEXT,This register contains dedicated FDIF context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_CAM_MEM ,Specify if memory-based context in CAM_MEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CAM_RST signal) - . - ." "Maintained,Lost" tree.end tree "INSTR_PRM" base ad:0x4A307F00 width 21. rgroup.long 0x0++0x3 line.long 0x00 "PMI_IDENTICATION,PM profiling identification register" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "PMI_SYS_CONFIG,PM profiling system configuartion register" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local tartget state management mode" "0,1,2,3" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "0,1" rgroup.long 0x14++0x3 line.long 0x00 "PMI_STATUS,PM profiling status register" bitfld.long 0x00 8. " FIFOEMPTY ,PM Profiling buffer empty" "0,1" group.long 0x24++0x3 line.long 0x00 "PMI_CONFIGURATION,PM profiling configuration register" bitfld.long 0x00 30.--31. " CLAIM_3 ,Ownership" "0,1,2,3" bitfld.long 0x00 29. " CLAIM_2 ,Debugger override qualifier" "0,1" bitfld.long 0x00 28. " CLAIM_1 ,Current owner" "0,1" textline " " bitfld.long 0x00 7. " EVT_CAPT_EN ,When HIGH the PM events capture is enabled" "0,1" group.long 0x28++0x3 line.long 0x00 "PMI_CLASS_FILTERING,PM profiling class filtering register" bitfld.long 0x00 3. " SNAP_CAPT_EN_03 ,Snapshot capture enable - Class-ID = 0x03" "0,1" bitfld.long 0x00 2. " SNAP_CAPT_EN_02 ,Snapshot capture enable - Class-ID = 0x02" "0,1" bitfld.long 0x00 1. " SNAP_CAPT_EN_01 ,Snapshot capture enable - Class-ID = 0x01" "0,1" textline " " bitfld.long 0x00 0. " SNAP_CAPT_EN_00 ,Snapshot capture enable - Class-ID = 0x00" "0,1" group.long 0x2C++0x3 line.long 0x00 "PMI_TRIGGERING,PM profiling triggering control register" bitfld.long 0x00 1. " TRIG_STOP_EN ,Enable stop capturing PM events from external trigger detection" "0,1" bitfld.long 0x00 0. " TRIG_START_EN ,Enable start capturing PM events from external trigger detection" "0,1" group.long 0x30++0x3 line.long 0x00 "PMI_SAMPLING,PM profiling sampling window register" bitfld.long 0x00 16.--19. " FCLK_DIV_FACOR ,FunClk divide factor ranging from 1 to 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SAMP_WIND_SIZE ,PM events sampling window size" tree.end tree "DSP_CM1" base ad:0x4A004400 width 20. group.long 0x0++0x3 line.long 0x00 "CM_DSP_CLKSTCTRL,This register enables the DSP domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 8. " CLKACTIVITY_DSP_ROOT_CLK ,This field indicates the state of the DSP_ROOT_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSP clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x4++0x3 line.long 0x00 "CM_DSP_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 16. " ALWONCORE_STATDEP ,Static dependency towards ALWONCORE clock domain - ." "Disabled,1" bitfld.long 0x00 15. " L4WKUP_STATDEP ,Static dependency towards L4WKUP clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " ISS_STATDEP ,Static dependency towards ISS clock domain - ." "Disabled,1" bitfld.long 0x00 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ABE_STATDEP ,Static dependency towards ABE clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Disabled,Enabled" group.long 0x8++0x3 line.long 0x00 "CM_DSP_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " L3_1_DYNDEP ,Dynamic dependency towards L3_1 clock domain - ." "0,Enabled" bitfld.long 0x00 3. " ABE_DYNDEP ,Dynamic dependency towards ABE clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 2. " IVAHD_DYNDEP ,Dynamic dependency towards IVAHD clock domain - ." "0,Enabled" group.long 0x20++0x3 line.long 0x00 "CM_DSP_DSP_CLKCTRL,This register manages the DSP clocks." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." tree.end tree "ABE_CM1" base ad:0x4A004500 width 26. group.long 0x0++0x3 line.long 0x00 "CM1_ABE_CLKSTCTRL,This register enables the ABE domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 13. " CLKACTIVITY_ABE_24M_FCLK ,This field indicates the state of the ABE_24M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 12. " CLKACTIVITY_ABE_ALWON_32K_CLK ,This field indicates the state of the ABE_ALWON_32K_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 11. " CLKACTIVITY_ABE_SYSCLK ,This field indicates the state of the ABE_SYSCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 10. " CLKACTIVITY_24M_FCLK ,This field indicates the state of the 24M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 9. " CLKACTIVITY_ABE_ICLK2 ,This field indicates the state of the ABE_ICLK2 interface clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 8. " CLKACTIVITY_DPLL_ABE_X2_CLK ,This field indicates the state of the DPLL_ABE_X2_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the ABE clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" rgroup.long 0x20++0x3 line.long 0x00 "CM1_ABE_L4ABE_CLKCTRL,This register manages the L4ABE clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0x28++0x3 line.long 0x00 "CM1_ABE_AESS_CLKCTRL,This register manages the AESS clocks." bitfld.long 0x00 24. " CLKSEL_AESS_FCLK ,Selects the ratio of AESS_FCLK to ABE_CLK - . - ." "/1,/2" bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x30++0x3 line.long 0x00 "CM1_ABE_PDM_CLKCTRL,This register manages the PDM clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x38++0x3 line.long 0x00 "CM1_ABE_DMIC_CLKCTRL,This register manages the DMIC clocks." bitfld.long 0x00 26.--27. " CLKSEL_INTERNAL_SOURCE ,Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source. - . - . - . - ." "ABE_24MHz,ABE_SYSCLK,PER_24MHz,?..." bitfld.long 0x00 24.--25. " CLKSEL_SOURCE ,Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless. - . - . - . - ." "Internal,CLKS,Audio_SLIMBUS,?..." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x40++0x3 line.long 0x00 "CM1_ABE_MCASP_CLKCTRL,This register manages the MCASP clocks." bitfld.long 0x00 26.--27. " CLKSEL_INTERNAL_SOURCE ,Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source. - . - . - . - ." "ABE_24MHz,ABE_SYSCLK,PER_24MHz,?..." bitfld.long 0x00 24.--25. " CLKSEL_SOURCE ,Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless. - . - . - . - ." "Internal,CLKS,Audio_SLIMBUS,?..." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x48++0x3 line.long 0x00 "CM1_ABE_MCBSP1_CLKCTRL,This register manages the MCBSP1 clocks." bitfld.long 0x00 26.--27. " CLKSEL_INTERNAL_SOURCE ,Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source. - . - . - . - ." "ABE_24MHz,ABE_SYSCLK,PER_24MHz,?..." bitfld.long 0x00 24.--25. " CLKSEL_SOURCE ,Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless. - . - . - . - ." "Internal,CLKS,Audio_SLIMBUS,?..." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x50++0x3 line.long 0x00 "CM1_ABE_MCBSP2_CLKCTRL,This register manages the MCBSP2 clocks." bitfld.long 0x00 26.--27. " CLKSEL_INTERNAL_SOURCE ,Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source. - . - . - . - ." "ABE_24MHz,ABE_SYSCLK,PER_24MHz,?..." bitfld.long 0x00 24.--25. " CLKSEL_SOURCE ,Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless. - . - . - . - ." "Internal,CLKS,Audio_SLIMBUS,?..." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x58++0x3 line.long 0x00 "CM1_ABE_MCBSP3_CLKCTRL,This register manages the MCBSP3 clocks." bitfld.long 0x00 26.--27. " CLKSEL_INTERNAL_SOURCE ,Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source. - . - . - . - ." "ABE_24MHz,ABE_SYSCLK,PER_24MHz,?..." bitfld.long 0x00 24.--25. " CLKSEL_SOURCE ,Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless. - . - . - . - ." "Internal,CLKS,Audio_SLIMBUS,?..." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x60++0x3 line.long 0x00 "CM1_ABE_SLIMBUS_CLKCTRL,This register manages the SLIMBUS clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 11. " OPTFCLKEN_SLIMBUS_CLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 10. " OPTFCLKEN_FCLK2 ,Optional functional clock control. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 9. " OPTFCLKEN_FCLK1 ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " OPTFCLKEN_FCLK0 ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x68++0x3 line.long 0x00 "CM1_ABE_GPTIMER5_CLKCTRL,This register manages the TIMER5 clocks." bitfld.long 0x00 24. " CLKSEL ,Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock - . - ." "0,1" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,Reserved,2,?..." group.long 0x70++0x3 line.long 0x00 "CM1_ABE_GPTIMER6_CLKCTRL,This register manages the TIMER6 clocks." bitfld.long 0x00 24. " CLKSEL ,Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock - . - ." "0,1" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,Reserved,2,?..." group.long 0x78++0x3 line.long 0x00 "CM1_ABE_GPTIMER7_CLKCTRL,This register manages the TIMER7 clocks." bitfld.long 0x00 24. " CLKSEL ,Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock - . - ." "0,1" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,Reserved,2,?..." group.long 0x80++0x3 line.long 0x00 "CM1_ABE_GPTIMER8_CLKCTRL,This register manages the TIMER8 clocks." bitfld.long 0x00 24. " CLKSEL ,Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock - . - ." "0,1" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,Reserved,2,?..." group.long 0x88++0x3 line.long 0x00 "CM1_ABE_WDTIMER3_CLKCTRL,This register manages the WDT3 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." tree.end tree "EMU_CM" base ad:0x4A307A00 width 24. group.long 0x0++0x3 line.long 0x00 "CM_EMU_CLKSTCTRL,This register enables the EMU domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain. [warm re.." bitfld.long 0x00 9. " CLKACTIVITY_CORE_DPLL_EMU_CLK ,This field indicates the state of the CORE_DPLL_EMU_CLK clock in the domain. - . - ." "Inactive,Active" bitfld.long 0x00 8. " CLKACTIVITY_EMU_SYS_CLK ,This field indicates the state of the EMU_SYS_CLK clock in the domain. - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the EMU clock domain. - . - . - . - ." "Reserved,Reserved,SW_WKUP,HW_AUTO" group.long 0x8++0x3 line.long 0x00 "CM_EMU_DYNAMICDEP,This register controls the dynamic domain depedencies from EMU domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "0,Enabled" group.long 0x20++0x3 line.long 0x00 "CM_EMU_DEBUGSS_CLKCTRL,This register manages the DEBUGSS clocks. [warm reset insensitive]" bitfld.long 0x00 27.--29. " CLKSEL_PMD_STM_CLK ,Selection of STM clock division - . - . - . - . - . - . - . - ." "Reserved,/1,/2,Reserved,/4,?..." bitfld.long 0x00 24.--26. " CLKSEL_PMD_TRACE_CLK ,Selection of TRACE clock division - . - . - . - . - . - . - . - ." "Reserved,/1,/2,Reserved,/4,?..." bitfld.long 0x00 22.--23. " PMD_TRACE_MUX_CTRL ,Selection of TRACE source clock - . - . - . - ." "SYS_CLK,CORE_DPLL_EMU_CLK,PER_DPLL_EMU_CLK,?..." textline " " bitfld.long 0x00 20.--21. " PMD_STM_MUX_CTRL ,Selection of STM source clock - . - . - . - ." "SYS_CLK,CORE_DPLL_EMU_CLK,PER_DPLL_EMU_CLK,?..." bitfld.long 0x00 18. " STBYST ,Module standby status - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" tree.end tree "CAM_CM2" base ad:0x4A009000 width 21. group.long 0x0++0x3 line.long 0x00 "CM_CAM_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 10. " CLKACTIVITY_FDIF_FCLK ,This field indicates the state of the FDIF_FCLK clock input of the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 9. " CLKACTIVITY_CAM_PHY_CTRL_CLK ,This field indicates the state of the CAM_PHY_CTRL_CLK clock input of the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 8. " CLKACTIVITY_ISS_CLK ,This field indicates the state of the ISS_CLK clock input of the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the CAM clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x4++0x3 line.long 0x00 "CM_CAM_STATICDEP,This register controls the static domain depedencies from CAM domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - ." "0,Enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Disabled,Enabled" rgroup.long 0x8++0x3 line.long 0x00 "CM_CAM_DYNAMICDEP,This register controls the dynamic domain depedencies from CAM domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "Disabled,1" group.long 0x20++0x3 line.long 0x00 "CM_CAM_ISS_CLKCTRL,This register manages the ISS clocks." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_CTRLCLK ,Optional functional clock control for CAM_PHY_CTRL_GCLK 96Mhz clock. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x28++0x3 line.long 0x00 "CM_CAM_FDIF_CLKCTRL,This register manages the FDIF clocks." bitfld.long 0x00 24.--25. " CLKSEL_FCLK ,Select the ration of FDIF_FCLK to FUNC_128M_CLK - . - . - . - ." "/1,/2,/4,?..." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." tree.end tree "MPU_CM1" base ad:0x4A004300 width 20. group.long 0x0++0x3 line.long 0x00 "CM_MPU_CLKSTCTRL,This register enables the MPU domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 8. " CLKACTIVITY_MPU_DPLL_CLK ,This field indicates the state of the MPU_DPLL_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the MPU clock domain. - . - . - . - ." "NO_SLEEP,Reserved,SW_WKUP,HW_AUTO" group.long 0x4++0x3 line.long 0x00 "CM_MPU_STATICDEP,This register controls the static domain dependencies from MPU domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 18. " C2C_STATDEP ,Static dependency towards C2C clock domain - ." "Dependency_is_disabled,1" bitfld.long 0x00 16. " ALWONCORE_STATDEP ,Static dependency towards ALWONCORE clock domain - ." "Disabled,1" bitfld.long 0x00 15. " L4WKUP_STATDEP ,Static dependency towards L4WKUP clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SDMA_STATDEP ,Static dependency towards SDMA clock domain - ." "Disabled,1" bitfld.long 0x00 10. " SGX_STATDEP ,Static dependency towards SGX clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " ISS_STATDEP ,Static dependency towards ISS clock domain - ." "Disabled,1" textline " " bitfld.long 0x00 8. " DSS_STATDEP ,Static dependency towards DSS clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 3. " ABE_STATDEP ,Static dependency towards ABE clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " DSP_STATDEP ,Static dependency towards DSP clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " MPU_M3_STATDEP ,Static dependency towards MPU_A3 clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0x8++0x3 line.long 0x00 "CM_MPU_DYNAMICDEP,This register controls the dynamic domain depedencies from MPU domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " L3_1_DYNDEP ,Dynamic dependency towards L3_1 clock domain - ." "0,Enabled" bitfld.long 0x00 4. " MEMIF_DYNDEP ,Dynamic dependency towards MEMIF clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 3. " ABE_DYNDEP ,Dynamic dependency towards ABE clock domain - ." "0,Enabled" rgroup.long 0x20++0x3 line.long 0x00 "CM_MPU_MPU_CLKCTRL,This register manages the MPU clocks." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" tree.end tree "INSTR_CM2" base ad:0x4A009F00 width 22. rgroup.long 0x0++0x3 line.long 0x00 "CMI2_IDENTIFICATION,CM profiling identification register" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "CMI2_SYS_CONFIG,CM profiling system configuartion register" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local tartget state management mode" "0,1,2,3" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "0,1" rgroup.long 0x14++0x3 line.long 0x00 "CMI2_STATUS,CM profiling status register" bitfld.long 0x00 8. " FIFOEMPTY ,PM Profiling buffer empty" "0,1" group.long 0x24++0x3 line.long 0x00 "CMI2_CONFIGURATION,CM profiling configuration register" bitfld.long 0x00 30.--31. " CLAIM_3 ,Ownership" "0,1,2,3" bitfld.long 0x00 29. " CLAIM_2 ,Debugger override qualifier" "0,1" bitfld.long 0x00 28. " CLAIM_1 ,Current owner" "0,1" textline " " bitfld.long 0x00 7. " EVT_CAPT_EN ,When HIGH the PM events capture is enabled" "0,1" group.long 0x28++0x3 line.long 0x00 "CMI2_CLASS_FILTERING,CM profiling class filtering register" bitfld.long 0x00 3. " SNAP_CAPT_EN_03 ,Snapshot capture enable - Class-ID = 0x03" "0,1" bitfld.long 0x00 2. " SNAP_CAPT_EN_02 ,Snapshot capture enable - Class-ID = 0x02" "0,1" bitfld.long 0x00 1. " SNAP_CAPT_EN_01 ,Snapshot capture enable - Class-ID = 0x01" "0,1" textline " " bitfld.long 0x00 0. " SNAP_CAPT_EN_00 ,Snapshot capture enable - Class-ID = 0x00" "0,1" group.long 0x2C++0x3 line.long 0x00 "CMI2_TRIGGERING,CM profiling triggering control register" bitfld.long 0x00 1. " TRIG_STOP_EN ,Enable stop capturing PM events from external trigger detection" "0,1" bitfld.long 0x00 0. " TRIG_START_EN ,Enable start capturing PM events from external trigger detection" "0,1" group.long 0x30++0x3 line.long 0x00 "CMI2_SAMPLING,CM profiling sampling window register" bitfld.long 0x00 16.--19. " FCLK_DIV_FACOR ,FunClk divide factor ranging from 1 to 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SAMP_WIND_SIZE ,PM events sampling window size" tree.end tree "INSTR_CM1" base ad:0x4A004F00 width 22. rgroup.long 0x0++0x3 line.long 0x00 "CMI1_IDENTIFICATION,CM profiling identification register" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "CMI1_SYS_CONFIG,CM profiling system configuartion register" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local tartget state management mode" "0,1,2,3" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "0,1" rgroup.long 0x14++0x3 line.long 0x00 "CMI1_STATUS,CM profiling status register" bitfld.long 0x00 8. " FIFOEMPTY ,PM Profiling buffer empty" "0,1" group.long 0x24++0x3 line.long 0x00 "CMI1_CONFIGURATION,CM profiling configuration register" bitfld.long 0x00 30.--31. " CLAIM_3 ,Ownership" "0,1,2,3" bitfld.long 0x00 29. " CLAIM_2 ,Debugger override qualifier" "0,1" bitfld.long 0x00 28. " CLAIM_1 ,Current owner" "0,1" textline " " bitfld.long 0x00 7. " EVT_CAPT_EN ,When HIGH the PM events capture is enabled" "0,1" group.long 0x28++0x3 line.long 0x00 "CMI1_CLASS_FILTERING,CM profiling class filtering register" bitfld.long 0x00 3. " SNAP_CAPT_EN_03 ,Snapshot capture enable - Class-ID = 0x03" "0,1" bitfld.long 0x00 2. " SNAP_CAPT_EN_02 ,Snapshot capture enable - Class-ID = 0x02" "0,1" bitfld.long 0x00 1. " SNAP_CAPT_EN_01 ,Snapshot capture enable - Class-ID = 0x01" "0,1" textline " " bitfld.long 0x00 0. " SNAP_CAPT_EN_00 ,Snapshot capture enable - Class-ID = 0x00" "0,1" group.long 0x2C++0x3 line.long 0x00 "CMI1_TRIGGERING,CM profiling triggering control register" bitfld.long 0x00 1. " TRIG_STOP_EN ,Enable stop capturing PM events from external trigger detection" "0,1" bitfld.long 0x00 0. " TRIG_START_EN ,Enable start capturing PM events from external trigger detection" "0,1" group.long 0x30++0x3 line.long 0x00 "CMI1_SAMPLING,CM profiling sampling window register" bitfld.long 0x00 16.--19. " FCLK_DIV_FACOR ,FunClk divide factor ranging from 1 to 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SAMP_WIND_SIZE ,PM events sampling window size" tree.end tree "DEVICE_PRM" base ad:0x4A307B00 width 30. group.long 0x0++0x3 line.long 0x00 "PRM_RSTCTRL,Global software cold and warm reset control. This register is auto-cleared. Only write 1 is possible. A read returns 0 only." bitfld.long 0x00 1. " RST_GLOBAL_COLD_software ,Global COLD software reset control. This bit is reset only upon a global cold source of reset. - . - ." "0,1" bitfld.long 0x00 0. " RST_GLOBAL_WARM_software ,Global WARM software reset control. This bit is reset upon any global source of reset (warm and cold). - . - ." "0,1" group.long 0x4++0x3 line.long 0x00 "PRM_RSTST,This register logs the global reset sources. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" eventfld.long 0x00 10. " C2C_RST ,C2C warm reset event. This is a source of global warm reset. - . - ." "0,1" eventfld.long 0x00 9. " ICEPICK_RST ,IcePick reset event. This is a source of global warm reset initiated by the emulation. - . - ." "No_reset,Reset" eventfld.long 0x00 8. " VDD_CORE_VOLT_MGR_RST ,VDD_CORE voltage manager reset event This is a source of global WARM reset. - . - ." "No_reset,Reset" textline " " eventfld.long 0x00 7. " VDD_IVA_VOLT_MGR_RST ,VDD_IVA voltage manager reset event This is a source of global WARM reset. - . - ." "No_reset,Reset" eventfld.long 0x00 6. " VDD_MPU_VOLT_MGR_RST ,VDD_MPU voltage manager reset event This is a source of global WARM reset. - . - ." "No_reset,Reset" eventfld.long 0x00 5. " EXTERNAL_WARM_RST ,External warm reset event - . - ." "No_reset,Reset" textline " " eventfld.long 0x00 3. " MPU_WDT_RST ,MPU Watchdog timer reset event. This is a source of global WARM reset. - . - ." "No_reset,Reset" eventfld.long 0x00 1. " GLOBAL_WARM_SW_RST ,Global warm software reset event - . - ." "No_reset,Reset" eventfld.long 0x00 0. " GLOBAL_COLD_RST ,Power-on (cold) reset event - . - ." "No_reset,Reset" group.long 0x8++0x3 line.long 0x00 "PRM_RSTTIME,Reset duration control. [warm reset insensitive]" bitfld.long 0x00 10.--14. " RSTTIME2 ,(Power domain) reset duration 2 (number of RM.SYSCLK clock cycles) - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. " RSTTIME1 ,(Global) reset duration 1 (number of Func_32k.clk clock cycles) - ." group.long 0xC++0x3 line.long 0x00 "PRM_CLKREQCTRL,This register allows controlling the CLKREQ signal towards SCRM." bitfld.long 0x00 0.--2. " CLKREQ_COND ,Control upon which condition CLKREQ signal is deasserted. - . - . - . - . - . - . - . - ." "Never,OFF,RET/OFF,SLEEP/RET/OFF,Device,?..." group.long 0x10++0x3 line.long 0x00 "PRM_VOLTCTRL,This register provides voltage domain management controls." bitfld.long 0x00 14. " VDD_IVA_I2C_DISABLE ,This bit allows disabling I2C interface with powerIC for IVA voltage (for debug purpose only). [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 13. " VDD_MPU_I2C_DISABLE ,This bit allows disabling I2C interface with powerIC for MPU voltage (for debug purpose only). [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 12. " VDD_CORE_I2C_DISABLE ,This bit allows disabling I2C interface with powerIC for CORE voltage (for debug purpose only). [warm reset insensitive] - . - ." "0,1" textline " " bitfld.long 0x00 9. " VDD_IVA_PRESENCE ,This bit control the presence of IVA voltage in device. [warm reset insensitive] - . - ." "Absent,Present" bitfld.long 0x00 8. " VDD_MPU_PRESENCE ,This bit control the presence of MPU voltage in device. [warm reset insensitive] - . - ." "Absent,Present" bitfld.long 0x00 4.--5. " AUTO_CTRL_VDD_IVA_L ,This bit field specifies the state to which the hardware can automatically transition the VDD_IVA_L voltage domain. - . - . - . - ." "Disabled,SLEEP,RET,?..." textline " " bitfld.long 0x00 2.--3. " AUTO_CTRL_VDD_MPU_L ,This bit field specifies the state to which the hardware can automatically transition the VDD_MPU_L voltage domain. - . - . - . - ." "Disabled,SLEEP,RET,?..." bitfld.long 0x00 0.--1. " AUTO_CTRL_VDD_CORE_L ,This bit field specifies the state to which the hardware can automatically transition the VDD_CORE_L voltage domain. - . - . - . - ." "Disabled,SLEEP,RET,?..." group.long 0x14++0x3 line.long 0x00 "PRM_PWRREQCTRL,This register allows controlling the signal towards power IC." bitfld.long 0x00 0.--1. " PWRREQ_COND ,Control upon which condition from MPU, IVA and CORE voltage domainsPWRREQ is deasserted. - . - . - . - ." "Never,SLEEP/RET/OFF,RET/OFF,OFF" group.long 0x18++0x3 line.long 0x00 "PRM_PSCON_COUNT,This register allows controlling 2 parameters for power state controller. [warm reset insensitive]" hexmask.long.byte 0x00 8.--15. 1. " PONOUT_2_PGOODIN_TIME ,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS. The duration is computed as 8 x NbCycles of system clock cycles." hexmask.long.byte 0x00 0.--7. 1. " PCHARGE_TIME ,Number of system clock cycles for the SRAM precharge duration." group.long 0x1C++0x3 line.long 0x00 "PRM_IO_COUNT,This register allows controlling LPDDR2 I/O isolation removal setup. [warm reset insensitive]" hexmask.long.byte 0x00 0.--7. 1. " ISO_2_ON_TIME ,Determines the setup time of the LPDDR2 IOs going out of isolation. Counting on the system clock. Target is 1.5us." group.long 0x20++0x3 line.long 0x00 "PRM_IO_PMCTRL,This register allows overriding ISOCLK signal towards I/O pad ring." bitfld.long 0x00 16. " GLOBAL_WUEN ,Global I/O wakeup enable. This is a gating condition to all individual I/O WUEN coming from control module. Gating is done in the Spinner logic. - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " WUCLK_STATUS ,Gives value of WUCLKOUT signal coming back from I/O pad ring." "0,1" bitfld.long 0x00 8. " WUCLK_CTRL ,Direct control on WUCLKIN signal to I/O pad ring. - . - ." "Low,High" textline " " bitfld.long 0x00 5. " IOON_STATUS ,Gives the functional status of the I/O ring. - . - ." "0,1" bitfld.long 0x00 4. " ISOOVR_EXTEND ,Control non-EMIF I/O isolation extension upon a device wakeup from OFF mode. - . - ." "0,1" bitfld.long 0x00 1. " ISOCLK_STATUS ,Gives value of ISOCLKOUT signal coming back from I/O pad ring." "0,1" textline " " bitfld.long 0x00 0. " ISOCLK_OVERRIDE ,Override control on ISOCLKIN signal to I/O pad ring. Override should be used at boot time only when it is needed to change the mode of an I/O from 1.8-V default mode to 1.2-V mode. When not overriden, this signal is controlle.." "Not_overriden,Overriden" group.long 0x24++0x3 line.long 0x00 "PRM_VOLTSETUP_WARMRESET,This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_CORE_L domain transitions with OFF state. [warm reset insensitive]" bitfld.long 0x00 8.--9. " STABLE_PRESCAL ,Determines prescaler for stabilization duration counting. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--5. " STABLE_COUNT ,Determines the stabilization duration of all VDD_xxx_L regulators upon a global warm reset assertion. The duration is computed according to Stable_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x28++0x3 line.long 0x00 "PRM_VOLTSETUP_CORE_OFF,This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_CORE_L domain transitions with OFF state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " RAMP_DOWN_PRESCAL ,Determines prescaler for ramp-down duration counting. - . - . - . - ." "64,256,512,2048" bitfld.long 0x00 16.--21. " RAMP_DOWN_COUNT ,Determines the ramp-down duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Down_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " RAMP_UP_PRESCAL ,Determines prescaler for ramp-up duration counting. - . - . - . - ." "64,256,512,2048" textline " " bitfld.long 0x00 0.--5. " RAMP_UP_COUNT ,Determines the ramp-up duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Up_Prescal. At cold reset, PRCM assumes that VDD_CORE_L will be at a valid ON voltage before SYS_NRESPWRON is deasserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2C++0x3 line.long 0x00 "PRM_VOLTSETUP_MPU_OFF,This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_MPU_L domain transitions to or from OFF state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " RAMP_DOWN_PRESCAL ,Determines prescaler for ramp-down duration counting. - . - . - . - ." "64,256,512,2048" bitfld.long 0x00 16.--21. " RAMP_DOWN_COUNT ,Determines the ramp-down duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Down_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " RAMP_UP_PRESCAL ,Determines prescaler for ramp-up duration counting. - . - . - . - ." "64,256,512,2048" textline " " bitfld.long 0x00 0.--5. " RAMP_UP_COUNT ,Determines the ramp-up duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Up_Prescal. At cold reset, PRCM assumes that VDD_CORE_L will be at a valid ON voltage before SYS_NRESPWRON is deasserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30++0x3 line.long 0x00 "PRM_VOLTSETUP_IVA_OFF,This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_IVA_L domain transitions to or from OFF state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " RAMP_DOWN_PRESCAL ,Determines prescaler for ramp-down duration counting. - . - . - . - ." "64,256,512,2048" bitfld.long 0x00 16.--21. " RAMP_DOWN_COUNT ,Determines the ramp-down duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Down_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " RAMP_UP_PRESCAL ,Determines prescaler for ramp-up duration counting. - . - . - . - ." "64,256,512,2048" textline " " bitfld.long 0x00 0.--5. " RAMP_UP_COUNT ,Determines the ramp-up duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Up_Prescal. At cold reset, PRCM assumes that VDD_CORE_L will be at a valid ON voltage before SYS_NRESPWRON is deasserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x34++0x3 line.long 0x00 "PRM_VOLTSETUP_CORE_RET_SLEEP,This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_CORE_L domain transitions between ON and RET or SLEEP state. [warm rese.." bitfld.long 0x00 24.--25. " RAMP_DOWN_PRESCAL ,Determines prescaler for ramp-down duration counting. - . - . - . - ." "16,64,128,512" bitfld.long 0x00 16.--21. " RAMP_DOWN_COUNT ,Determines the ramp-down duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Down_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " RAMP_UP_PRESCAL ,Determines prescaler for ramp-up duration counting. - . - . - . - ." "16,64,128,512" textline " " bitfld.long 0x00 0.--5. " RAMP_UP_COUNT ,Determines the ramp-up duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Up_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x38++0x3 line.long 0x00 "PRM_VOLTSETUP_MPU_RET_SLEEP,This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_MPU_L domain transitions between ON and RET or SLEEP state. [warm reset .." bitfld.long 0x00 24.--25. " RAMP_DOWN_PRESCAL ,Determines prescaler for ramp-down duration counting. - . - . - . - ." "16,64,128,512" bitfld.long 0x00 16.--21. " RAMP_DOWN_COUNT ,Determines the ramp-down duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Down_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " RAMP_UP_PRESCAL ,Determines prescaler for ramp-up duration counting. - . - . - . - ." "16,64,128,512" textline " " bitfld.long 0x00 0.--5. " RAMP_UP_COUNT ,Determines the ramp-up duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Up_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x3C++0x3 line.long 0x00 "PRM_VOLTSETUP_IVA_RET_SLEEP,This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_IVA_L domain transitions between ON and RET or SLEEP state. [warm reset .." bitfld.long 0x00 24.--25. " RAMP_DOWN_PRESCAL ,Determines prescaler for ramp-down duration counting. - . - . - . - ." "16,64,128,512" bitfld.long 0x00 16.--21. " RAMP_DOWN_COUNT ,Determines the ramp-down duration of VDD_IVA_L regulators. The duration is computed according to Ramp_Down_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " RAMP_UP_PRESCAL ,Determines prescaler for ramp-up duration counting. - . - . - . - ." "16,64,128,512" textline " " bitfld.long 0x00 0.--5. " RAMP_UP_COUNT ,Determines the ramp-up duration of VDD_IVA_L regulators. The duration is computed according to Ramp_Up_Prescal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x40++0x3 line.long 0x00 "PRM_VP_CORE_CONFIG,This register allows the configuration of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L)." hexmask.long.byte 0x00 24.--31. 1. " ERROROFFSET ,Offset value in the Error to Voltage converter (two's complement number)." hexmask.long.byte 0x00 16.--23. 1. " ERRORGAIN ,Gain value in the Error to Voltage converter (two's complement number)." hexmask.long.byte 0x00 8.--15. 1. " INITVOLTAGE ,Set the initial voltage level of the SMPS. It must be reconfigured before enable the SmartReflex around a new OPP." textline " " bitfld.long 0x00 3. " TIMEOUTEN ,Enable or disable the timeout capability of the Voltage Controller State Machine. - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " INITVDD ,Initializes the voltage in the Voltage Processor. - . - ." "Reset,Positive_edge" bitfld.long 0x00 1. " FORCEUPDATE ,Forces an update of the SMPS. - . - ." "Reset,Positive_edge" textline " " bitfld.long 0x00 0. " VPENABLE ,Enables or disables the Voltage Processor updates on SR_SInterruptz. - . - ." "Disabled,Enabled" rgroup.long 0x44++0x3 line.long 0x00 "PRM_VP_CORE_STATUS,This register reflects the idle state of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L. This register is read only and automatically updated." bitfld.long 0x00 0. " VPINIDLE ,CORE Voltage Processor idle status. - . - ." "Normal,Idle" group.long 0x48++0x3 line.long 0x00 "PRM_VP_CORE_VLIMITTO,This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)." hexmask.long.byte 0x00 24.--31. 1. " VDDMAX ,Defines the maximum voltage supply level." hexmask.long.byte 0x00 16.--23. 1. " VDDMIN ,Defines the minimum voltage supply level." hexmask.long.word 0x00 0.--15. 1. " TIMEOUT ,Defines Voltage Controller maximum wait time for responses, measured in sysclk cycles." group.long 0x4C++0x3 line.long 0x00 "PRM_VP_CORE_VOLTAGE,This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)." hexmask.long.tbyte 0x00 8.--31. 1. " FORCEUPDATEWAIT ,The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge. This wait only be used during force_update operation." hexmask.long.byte 0x00 0.--7. 1. " VPVOLTAGE ,Indicates the current SMPS programmed voltage." group.long 0x50++0x3 line.long 0x00 "PRM_VP_CORE_VSTEPMAX,This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L)." hexmask.long.word 0x00 8.--23. 1. " SMPsoftwareAITTIMEMAX ,Slew rate for positive voltage step (in number of cycles per step)." hexmask.long.byte 0x00 0.--7. 1. " VSTEPMAX ,Maximum voltage step" group.long 0x54++0x3 line.long 0x00 "PRM_VP_CORE_VSTEPMIN,This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)." hexmask.long.word 0x00 8.--23. 1. " SMPsoftwareAITTIMEMIN ,Slew rate for negative voltage step (in number of cycles per step)." hexmask.long.byte 0x00 0.--7. 1. " VSTEPMIN ,Minimum voltage step" group.long 0x58++0x3 line.long 0x00 "PRM_VP_MPU_CONFIG,This register allows the configuration of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L)." hexmask.long.byte 0x00 24.--31. 1. " ERROROFFSET ,Offset value in the Error to Voltage converter (two's complement number)." hexmask.long.byte 0x00 16.--23. 1. " ERRORGAIN ,Gain value in the Error to Voltage converter (two's complement number)." hexmask.long.byte 0x00 8.--15. 1. " INITVOLTAGE ,Set the initial voltage level of the SMPS. It must be reconfigured before enable the SmartReflex around a new OPP." textline " " bitfld.long 0x00 3. " TIMEOUTEN ,Enable or disable the timeout capability of the Voltage Controller State Machine. - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " INITVDD ,Initializes the voltage in the Voltage Processor. - . - ." "Reset,Positive_edge" bitfld.long 0x00 1. " FORCEUPDATE ,Forces an update of the SMPS. - . - ." "Reset,Positive_edge" textline " " bitfld.long 0x00 0. " VPENABLE ,Enables or disables the Voltage Processor updates on SR_SInterruptz. - . - ." "Disabled,Enabled" rgroup.long 0x5C++0x3 line.long 0x00 "PRM_VP_MPU_STATUS,This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L. This register is read only and automatically updated." bitfld.long 0x00 0. " VPINIDLE ,Voltage Processor 1 idle status. - . - ." "Normal,Idle" group.long 0x60++0x3 line.long 0x00 "PRM_VP_MPU_VLIMITTO,This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)." hexmask.long.byte 0x00 24.--31. 1. " VDDMAX ,Defines the maximum voltage supply level." hexmask.long.byte 0x00 16.--23. 1. " VDDMIN ,Defines the minimum voltage supply level." hexmask.long.word 0x00 0.--15. 1. " TIMEOUT ,Defines Voltage Controller maximum wait time for responses, measured in sysclk cycles." group.long 0x64++0x3 line.long 0x00 "PRM_VP_MPU_VOLTAGE,This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)." hexmask.long.tbyte 0x00 8.--31. 1. " FORCEUPDATEWAIT ,The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge. This wait only be used during force_update operation." hexmask.long.byte 0x00 0.--7. 1. " VPVOLTAGE ,Indicates the current SMPS programmed voltage." group.long 0x68++0x3 line.long 0x00 "PRM_VP_MPU_VSTEPMAX,This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L)." hexmask.long.word 0x00 8.--23. 1. " SMPsoftwareAITTIMEMAX ,Slew rate for positive voltage step (in number of cycles per step)." hexmask.long.byte 0x00 0.--7. 1. " VSTEPMAX ,Maximum voltage step" group.long 0x6C++0x3 line.long 0x00 "PRM_VP_MPU_VSTEPMIN,This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)." hexmask.long.word 0x00 8.--23. 1. " SMPsoftwareAITTIMEMIN ,Slew rate for negative voltage step (in number of cycles per step)." hexmask.long.byte 0x00 0.--7. 1. " VSTEPMIN ,Minimum voltage step" group.long 0x70++0x3 line.long 0x00 "PRM_VP_IVA_CONFIG,This register allows the configuration of the Voltage Processor dedicated to IVAVoltage Domain (VDD_IVA_L)." hexmask.long.byte 0x00 24.--31. 1. " ERROROFFSET ,Offset value in the Error to Voltage converter (two's complement number)." hexmask.long.byte 0x00 16.--23. 1. " ERRORGAIN ,Gain value in the Error to Voltage converter (two's complement number)." hexmask.long.byte 0x00 8.--15. 1. " INITVOLTAGE ,Set the initial voltage level of the SMPS. It must be reconfigured before enable the SmartReflex around a new OPP." textline " " bitfld.long 0x00 3. " TIMEOUTEN ,Enable or disable the timeout capability of the Voltage Controller State Machine. - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " INITVDD ,Initializes the voltage in the Voltage Processor. - . - ." "Reset,Positive_edge" bitfld.long 0x00 1. " FORCEUPDATE ,Forces an update of the SMPS. - . - ." "Reset,Positive_edge" textline " " bitfld.long 0x00 0. " VPENABLE ,Enables or disables the Voltage Processor updates on SR_SInterruptz. - . - ." "Disabled,Enabled" rgroup.long 0x74++0x3 line.long 0x00 "PRM_VP_IVA_STATUS,This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_IVA_L. This register is read only and automatically updated." bitfld.long 0x00 0. " VPINIDLE ,Voltage Processor 1 idle status. - . - ." "Normal,Idle" group.long 0x78++0x3 line.long 0x00 "PRM_VP_IVA_VLIMITTO,This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the IVA Voltage Domain (VDD_IVA_L)." hexmask.long.byte 0x00 24.--31. 1. " VDDMAX ,Defines the maximum voltage supply level." hexmask.long.byte 0x00 16.--23. 1. " VDDMIN ,Defines the minimum voltage supply level." hexmask.long.word 0x00 0.--15. 1. " TIMEOUT ,Defines Voltage Controller maximum wait time for responses, measured in sysclk cycles." group.long 0x7C++0x3 line.long 0x00 "PRM_VP_IVA_VOLTAGE,This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the IVA Voltage Domain (VDD_IVA_L)." hexmask.long.tbyte 0x00 8.--31. 1. " FORCEUPDATEWAIT ,The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge. This wait only be used during force_update operation." hexmask.long.byte 0x00 0.--7. 1. " VPVOLTAGE ,Indicates the current SMPS programmed voltage." group.long 0x80++0x3 line.long 0x00 "PRM_VP_IVA_VSTEPMAX,This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to IVA Voltage Domain (VDD_IVA_L)." hexmask.long.word 0x00 8.--23. 1. " SMPsoftwareAITTIMEMAX ,Slew rate for positive voltage step (in number of cycles per step)." hexmask.long.byte 0x00 0.--7. 1. " VSTEPMAX ,Maximum voltage step" group.long 0x84++0x3 line.long 0x00 "PRM_VP_IVA_VSTEPMIN,This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the IVA Voltage Domain (VDD_IVA_L)." hexmask.long.word 0x00 8.--23. 1. " SMPsoftwareAITTIMEMIN ,Slew rate for negative voltage step (in number of cycles per step)." hexmask.long.byte 0x00 0.--7. 1. " VSTEPMIN ,Minimum voltage step" group.long 0x88++0x3 line.long 0x00 "PRM_VC_SMPS_SA,This register allows the setting of the I2C slave address of the Power IC device. [warm reset insensitive]" hexmask.long.byte 0x00 16.--22. 1. " SA_VDD_MPU_L ,Set the I2C slave address value for the third (if any) Power IC device." hexmask.long.byte 0x00 8.--14. 1. " SA_VDD_IVA_L ,Set the I2C slave address value for the second (if any) Power IC device." hexmask.long.byte 0x00 0.--6. 1. " SA_VDD_CORE_L ,Set the I2C slave address value for the first Power IC device." group.long 0x8C++0x3 line.long 0x00 "PRM_VC_VAL_SMPS_RA_VOL,This register allows the setting of the voltage configuration register address for the VDD channels. [warm reset insensitive]" hexmask.long.byte 0x00 16.--23. 1. " VOLRA_VDD_MPU_L ,Voltage configuration register address value for VDD_MPU_L channel" hexmask.long.byte 0x00 8.--15. 1. " VOLRA_VDD_IVA_L ,Voltage configuration register address value for VDD_IVA_L channel (if VDD_IVA_L source is placed in same chip as VDD_CORE_L source and have different voltage configuration register)" hexmask.long.byte 0x00 0.--7. 1. " VOLRA_VDD_CORE_L ,Voltage configuration register address value for the VDD_CORE_L channel (if the VDD_CORE_L source is placed in the same chip as the VDD_MPU_L source and has a different voltage configuration register)" group.long 0x90++0x3 line.long 0x00 "PRM_VC_VAL_SMPS_RA_CMD,Command (ON/ON-Low-Power/Retention/OFF) configuration register address values for the VDD channels (if used SMPS chips have different command configuration register than voltage configuration register) [warm reset insensitive]" hexmask.long.byte 0x00 16.--23. 1. " CMDRA_VDD_MPU_L ,Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_MPU_L channel" hexmask.long.byte 0x00 8.--15. 1. " CMDRA_VDD_IVA_L ,Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_IVA_L channel (if VDD_IVA_L source has different command configuration register than voltage VDD_CORE_L)" hexmask.long.byte 0x00 0.--7. 1. " CMDRA_VDD_CORE_L ,Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_CORE_L channel (if the VDD_CORE_L source has a different command configuration register than the voltage VDD_MPU_L)" group.long 0x94++0x3 line.long 0x00 "PRM_VC_VAL_CMD_VDD_CORE_L,This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_CORE_L channel. [warm reset insensitive]" hexmask.long.byte 0x00 24.--31. 1. " ON ,Set the ON command value." hexmask.long.byte 0x00 16.--23. 1. " ONLP ,Set the ON-Low-Power command value." hexmask.long.byte 0x00 8.--15. 1. " RET ,Set the RET command value." textline " " hexmask.long.byte 0x00 0.--7. 1. " OFF ,Set the OFF command value." group.long 0x98++0x3 line.long 0x00 "PRM_VC_VAL_CMD_VDD_MPU_L,This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_MPU_L channel. [warm reset insensitive]" hexmask.long.byte 0x00 24.--31. 1. " ON ,Set the ON command value." hexmask.long.byte 0x00 16.--23. 1. " ONLP ,Set the ON-Low-Power command value." hexmask.long.byte 0x00 8.--15. 1. " RET ,Set the RET command value." textline " " hexmask.long.byte 0x00 0.--7. 1. " OFF ,Set the OFF command value." group.long 0x9C++0x3 line.long 0x00 "PRM_VC_VAL_CMD_VDD_IVA_L,This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_IVA_L channel. [warm reset insensitive]" hexmask.long.byte 0x00 24.--31. 1. " ON ,Set the ON command value." hexmask.long.byte 0x00 16.--23. 1. " ONLP ,Set the ON-Low-Power command value." hexmask.long.byte 0x00 8.--15. 1. " RET ,Set the RET command value." textline " " hexmask.long.byte 0x00 0.--7. 1. " OFF ,Set the OFF command value." group.long 0xA0++0x3 line.long 0x00 "PRM_VC_VAL_BYPASS,Bypass data values register used for bypass command channel to send other configuration information (other then voltage configuration parameters) for SMPS chips which have no other configuration interface then this I2C interface. [war.." bitfld.long 0x00 24. " VALID ,This bit validates the bypass command. It is automatically cleared by hardware either after getting the acknowledge back from the SMPS or if an error occured. - . - ." "Acknowledged,Pending" hexmask.long.byte 0x00 16.--23. 1. " DATA ,Data to send to the Power IC device." hexmask.long.byte 0x00 8.--15. 1. " REGADDR ,Set the address of Power IC device register to configure." textline " " hexmask.long.byte 0x00 0.--6. 1. " SLAVEADDR ,Set the I2C slave address value." group.long 0xA4++0x3 line.long 0x00 "PRM_VC_CFG_CHANNEL,This register allows the configuration pointers for both VDD channels. [warm reset insensitive]" bitfld.long 0x00 20. " RACEN_VDD_MPU_L ,Enable bit for usage of RAC_VDD_MPU_L - . - ." "VOLRA,CMDRA" bitfld.long 0x00 19. " RAC_VDD_MPU_L ,Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_MPU_L channel - . - ." "CORE,MPU" bitfld.long 0x00 18. " RAV_VDD_MPU_L ,Voltage configuration register address pointer for VDD_MPU_L channel. - . - ." "CORE,MPU" textline " " bitfld.long 0x00 17. " CMD_VDD_MPU_L ,Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_MPU_L channel - . - ." "CORE,MPU" bitfld.long 0x00 16. " SA_VDD_MPU_L ,Slave address pointer for VDD_MPU_L channel. - . - ." "CORE,MPU" bitfld.long 0x00 12. " CMD_VDD_IVA_L ,Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_IVA_L channel - . - ." "CORE,IVA" textline " " bitfld.long 0x00 11. " RACEN_VDD_IVA_L ,Enable bit for usage of RAC_VDD_IVA_L - . - ." "VOLRA,CMDRA" bitfld.long 0x00 10. " RAC_VDD_IVA_L ,Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_IVA_L channel - . - ." "CORE,IVA" bitfld.long 0x00 9. " RAV_VDD_IVA_L ,Voltage configuration register address pointer for VDD_IVA_L channel. - . - ." "CORE,IVA" textline " " bitfld.long 0x00 8. " SA_VDD_IVA_L ,Slave address pointer for VDD_IVA_L channel. - . - ." "CORE,IVA" bitfld.long 0x00 4. " CMD_VDD_CORE_L ,Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_CORE_L channel (This bit has no influence on VDD_CORE_L channel)" "Low,High" bitfld.long 0x00 3. " RACEN_VDD_CORE_L ,Enable bit for usage of RAC_VDD_CORE_L. - . - ." "VOLRA,CMDRA" textline " " bitfld.long 0x00 2. " RAC_VDD_CORE_L ,Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_CORE_L channel. - . - ." "Low,High" bitfld.long 0x00 1. " RAV_VDD_CORE_L ,Voltage configuration register address pointer for VDD_CORE_L channel. 0x0: Select VOLRA_VDD_MPU_L for the VDD_CORE_L channel. 0x1: Select VOLRA_VDD_CORE_L for the VDD_CORE_L channel." "Low,High" bitfld.long 0x00 0. " SA_VDD_CORE_L ,Slave address pointer for VDD_CORE_L channel. 0x0: Select SA_VDD_MPU_L for the VDD_CORE_L channel. 0x1: Select SA_VDD_CORE_L for the VDD_CORE_L channel." "Low,High" group.long 0xA8++0x3 line.long 0x00 "PRM_VC_CFG_I2C_MODE,I2C configuration register. [warm reset insensitive]" bitfld.long 0x00 6. " DFILTEREN ,This field enables double filter procedure for IC input lines - . - ." "<1,<2" bitfld.long 0x00 4. " SRMODEEN ,Enables the IC repeated start operation mode. - (Effect of holding the SCL and SDA lines low, in effect blocking the I2C bus from losing arbitration between repeated start points). . - . - Use of this feature .." "Disabled,Enabled" bitfld.long 0x00 3. " HSMODEEN ,Enables IC bus high-speed mode. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " HSMCODE ,Master code value forIC high-speed preamble transmission." "0,1,2,3,4,5,6,7" group.long 0xAC++0x3 line.long 0x00 "PRM_VC_CFG_I2C_CLK,I2C Interface clock configuration parameters. [warm reset insensitive]" hexmask.long.byte 0x00 24.--31. 1. " HSSCLL ,Number of the system clock cycles, necessary to count the low period of the I2C clock signal, when the I2C interface runs in high-speed mode of operation. The value of the bit field is automatically increased by 7." hexmask.long.byte 0x00 16.--23. 1. " HSSCLH ,Number of the system clock cycles, necessary to count the high period of the I2C clock signal, when the I2C interface runs in high-speed mode of operation. The value of the bit field is automatically increased.." hexmask.long.byte 0x00 8.--15. 1. " SCLL ,Number of the system clock cycles, necessary to count the low period of the I2C clock signal, when the I2C interface runs in fast mode of operation. The value of the bit field is automatically increased by 7." textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLH ,Number of the system clock cycles, necessary to count the high period of the I2C clock signal, when the I2C interface runs in fast mode of operation. The value of the bit field is automatically increased by 5." group.long 0xB0++0x3 line.long 0x00 "PRM_SRAM_COUNT,Common setup for SRAM LDO transition counters. Applies to all voltage domains. [warm reset insensitive]" hexmask.long.byte 0x00 24.--31. 1. " STARTUP_COUNT ,Determines the start-up duration of SRAM and ABB LDO. The duration is computed as 16 x NbCycles of system clock cycles. Target is 50us." hexmask.long.byte 0x00 16.--23. 1. " SLPCNT_VALUE ,Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high. Counting on system clock. Target is 2us." hexmask.long.byte 0x00 8.--15. 1. " VSETUPCNT_VALUE ,SRAM LDO rampup time from retention to active mode. The duration is computed as 8 x NbCycles of system clock cycles. Target is 30us." textline " " bitfld.long 0x00 0.--5. " PCHARGECNT_VALUE ,Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good. Counting on system clock. Target is 600ns." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB4++0x3 line.long 0x00 "PRM_SRAM_WKUP_SETUP,Setup of memory in WKUP voltage domain. [warm reset insensitive]" bitfld.long 0x00 0. " DISABLE_RTA_EXPORT ,Control for HD memory RTA feature. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" group.long 0xB8++0x3 line.long 0x00 "PRM_LDO_SRAM_CORE_SETUP,Setup of the SRAM LDO for CORE voltage domain. [warm reset insensitive]" bitfld.long 0x00 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO. - . - ." "Not_overriden,Overriden" bitfld.long 0x00 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO. - . - ." "One,Two" bitfld.long 0x00 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO. - . - ." "External_cap,No_External_cap" textline " " bitfld.long 0x00 5. " ENFUNC3_EXPORT ,ENFUNC3 input of SRAM LDO. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" bitfld.long 0x00 4. " ENFUNC2_EXPORT ,ENFUNC2 input of SRAM LDO. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "External_cap,No_External_cap" bitfld.long 0x00 3. " ENFUNC1_EXPORT ,ENFUNC1 input of SRAM LDO. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" textline " " bitfld.long 0x00 2. " ABBOFF_SLEEP_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable afte.." "VDDS,VDDAR" bitfld.long 0x00 1. " ABBOFF_ACT_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains.." "VDDS,VDDAR" bitfld.long 0x00 0. " DISABLE_RTA_EXPORT ,Control for HD memory RTA feature. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" group.long 0xBC++0x3 line.long 0x00 "PRM_LDO_SRAM_CORE_CTRL,Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive]" bitfld.long 0x00 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state. - . - ." "0,1" bitfld.long 0x00 8. " SRAMLDO_STATUS ,SRAMLDO status - . - ." "0,1" bitfld.long 0x00 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not. - . - ." "0,1" group.long 0xC0++0x3 line.long 0x00 "PRM_LDO_SRAM_MPU_SETUP,Setup of the SRAM LDO for MPU voltage domain. [warm reset insensitive]" bitfld.long 0x00 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO. - . - ." "Not_overriden,Overriden" bitfld.long 0x00 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO. - . - ." "One,Two" bitfld.long 0x00 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO. - . - ." "External_cap,No_External_cap" textline " " bitfld.long 0x00 5. " ENFUNC3_EXPORT ,ENFUNC3 input of SRAM LDO. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" bitfld.long 0x00 4. " ENFUNC2_EXPORT ,ENFUNC2 input of SRAM LDO. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "External_cap,No_External_cap" bitfld.long 0x00 3. " ENFUNC1_EXPORT ,ENFUNC1 input of SRAM LDO. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" textline " " bitfld.long 0x00 2. " ABBOFF_SLEEP_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable afte.." "VDDS,VDDAR" bitfld.long 0x00 1. " ABBOFF_ACT_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains.." "VDDS,VDDAR" bitfld.long 0x00 0. " DISABLE_RTA_EXPORT ,Control for HD memory RTA feature. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" group.long 0xC4++0x3 line.long 0x00 "PRM_LDO_SRAM_MPU_CTRL,Control and status of the SRAM LDO for MPU voltage domain. [warm reset insensitive]" bitfld.long 0x00 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state. - . - ." "0,1" bitfld.long 0x00 8. " SRAMLDO_STATUS ,SRAMLDO status - . - ." "0,1" bitfld.long 0x00 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not. - . - ." "0,1" group.long 0xC8++0x3 line.long 0x00 "PRM_LDO_SRAM_IVA_SETUP,Setup of the SRAM LDO for IVA voltage domain. [warm reset insensitive]" bitfld.long 0x00 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO. - . - ." "Not_overriden,Overriden" bitfld.long 0x00 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO. - . - ." "One,Two" bitfld.long 0x00 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO. - . - ." "External_cap,No_External_cap" textline " " bitfld.long 0x00 5. " ENFUNC3_EXPORT ,ENFUNC3 input of SRAM LDO. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" bitfld.long 0x00 4. " ENFUNC2_EXPORT ,ENFUNC2 input of SRAM LDO. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "External_cap,No_External_cap" bitfld.long 0x00 3. " ENFUNC1_EXPORT ,ENFUNC1 input of SRAM LDO. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" textline " " bitfld.long 0x00 2. " ABBOFF_SLEEP_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable afte.." "VDDS,VDDAR" bitfld.long 0x00 1. " ABBOFF_ACT_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains.." "VDDS,VDDAR" bitfld.long 0x00 0. " DISABLE_RTA_EXPORT ,Control for HD memory RTA feature. After PowerOn reset and eFuse sensing, this bit field is automatically loaded with an eFuse value from control module. Bit field remains writable after this. - . - ." "0,1" group.long 0xCC++0x3 line.long 0x00 "PRM_LDO_SRAM_IVA_CTRL,Control and status of the SRAM LDO for IVA voltage domain. [warm reset insensitive]" bitfld.long 0x00 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state. - . - ." "0,1" bitfld.long 0x00 8. " SRAMLDO_STATUS ,SRAMLDO status - . - ." "0,1" bitfld.long 0x00 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not. - . - ." "0,1" group.long 0xD0++0x3 line.long 0x00 "PRM_LDO_ABB_MPU_SETUP,Selects the MPU_ABB LDO mode." hexmask.long.byte 0x00 8.--15. 1. " SR2_WTCNT_VALUE ,LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive]" bitfld.long 0x00 2. " ACTIVE_FBB_SEL ,Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive] - . - ." "Bypass,FBB" bitfld.long 0x00 0. " SR2EN ,Enable ABB power management - . - ." "Bypass,Functional" group.long 0xD4++0x3 line.long 0x00 "PRM_LDO_ABB_MPU_CTRL,Control and Status of ABB on MPU voltage domain. [warm reset insensitive]" bitfld.long 0x00 6. " SR2_IN_TRANSITION ,Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion. - . - ." "UNKN_MNEMO,1" bitfld.long 0x00 3.--4. " SR2_STATUS ,Indicate ABB LDO current operation status - . - . - . - ." "0,Reserved,2,?..." bitfld.long 0x00 2. " OPP_CHANGE ,When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL and ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_.." "0,1" textline " " bitfld.long 0x00 0.--1. " OPP_SEL ,Selects the OPP at which the MPU voltage domain is operating - . - . - . - ." "default_:_Nominal,Fast_OPP,Nominal,Slow_OPP" group.long 0xD8++0x3 line.long 0x00 "PRM_LDO_ABB_IVA_SETUP,Selects the IVA_ABB LDO mode." hexmask.long.byte 0x00 8.--15. 1. " SR2_WTCNT_VALUE ,LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive]" bitfld.long 0x00 2. " ACTIVE_FBB_SEL ,Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive] - . - ." "Bypass,FBB" bitfld.long 0x00 0. " SR2EN ,Enable ABB power management - . - ." "Bypass,Functional" group.long 0xDC++0x3 line.long 0x00 "PRM_LDO_ABB_IVA_CTRL,Control and Status of ABB on IVA voltage domain. [warm reset insensitive]" bitfld.long 0x00 6. " SR2_IN_TRANSITION ,Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion. - . - ." "UNKN_MNEMO,1" bitfld.long 0x00 3.--4. " SR2_STATUS ,Indicate ABB LDO current operation status - . - . - . - ." "0,Reserved,2,?..." bitfld.long 0x00 2. " OPP_CHANGE ,When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL and ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_.." "0,1" textline " " bitfld.long 0x00 0.--1. " OPP_SEL ,Selects the OPP at which the IVA voltage domain is operating (Fast OPP, Nominal OPP or Slow OPP) - . - . - . - ." "default_:_Nominal,Fast_OPP,Nominal,Slow_OPP" group.long 0xE0++0x3 line.long 0x00 "PRM_LDO_BANDGAP_SETUP,Control of the bandgap. [warm reset insensitive]" hexmask.long.byte 0x00 0.--7. 1. " STARTUP_COUNT ,Determines the start-up duration of BANDGAP. The duration is computed as 32 x NbCycles of system clock cycles. Target is 100us." group.long 0xE4++0x3 line.long 0x00 "PRM_DEVICE_OFF_CTRL,This register is used to control device OFF transition." bitfld.long 0x00 0. " DEVICE_OFF_ENABLE ,Controls transition to device OFF mode. - . - ." "Disabled,Enabled" rgroup.long 0xE8++0x3 line.long 0x00 "PRM_PHASE1_CNDP,This register stores the start descriptor address of automatic restore phase1. [warm reset insensitive]" hexmask.long 0x00 0.--31. 1. " PHASE1_CNDP ,Start descriptor address of automatic restore phase1. Hard-coded to SAR_ROM base address." rgroup.long 0xEC++0x3 line.long 0x00 "PRM_PHASE2A_CNDP,This register stores the start descriptor address of automatic restore phase2A. [warm reset insensitive]" hexmask.long 0x00 0.--31. 1. " PHASE2A_CNDP ,Start descriptor address of automatic restore phase2A. Hard-coded to SAR_ROM base address + 0x30." rgroup.long 0xF0++0x3 line.long 0x00 "PRM_PHASE2B_CNDP,This register stores the start descriptor address of automatic restore phase2B. [warm reset insensitive]" hexmask.long 0x00 0.--31. 1. " PHASE2B_CNDP ,Start descriptor address of automatic restore phase2B. Hard-coded to SAR_ROM base address + 0x60." group.long 0xF8++0x3 line.long 0x00 "PRM_VC_ERRST,This debug register logs the error status coming from Voltage Controller. Must be cleared by software." eventfld.long 0x00 26. " BYPS_TIMEOUT_ERR ,Bypass command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. - . - ." "No_error,1" eventfld.long 0x00 25. " BYPS_RA_ERR ,Wrong register address error for bypass command - . - ." "No_error,1" eventfld.long 0x00 24. " BYPS_SA_ERR ,Wrong slave address error for bypass command - . - ." "No_error,1" textline " " eventfld.long 0x00 21. " VFSM_TIMEOUT_ERR_MPU ,MPU voltage FSM command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. - . - ." "No_error,1" eventfld.long 0x00 20. " VFSM_RA_ERR_MPU ,Wrong register address error for MPU voltage FSM - . - ." "No_error,1" eventfld.long 0x00 19. " VFSM_SA_ERR_MPU ,Wrong slave address error for MPU voltage FSM - . - ." "No_error,1" textline " " eventfld.long 0x00 18. " SMPS_TIMEOUT_ERR_MPU ,MPU voltage processor command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. - . - ." "No_error,1" eventfld.long 0x00 17. " SMPS_RA_ERR_MPU ,Wrong register address error for MPU voltage processor - . - ." "No_error,1" eventfld.long 0x00 16. " SMPS_SA_ERR_MPU ,Wrong slave address error for MPU voltage processor - . - ." "No_error,1" textline " " eventfld.long 0x00 13. " VFSM_TIMEOUT_ERR_IVA ,IVA voltage FSM command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. - . - ." "No_error,1" eventfld.long 0x00 12. " VFSM_RA_ERR_IVA ,Wrong register address error for IVA voltage FSM - . - ." "No_error,1" eventfld.long 0x00 11. " VFSM_SA_ERR_IVA ,Wrong slave address error for IVA voltage FSM - . - ." "No_error,1" textline " " eventfld.long 0x00 10. " SMPS_TIMEOUT_ERR_IVA ,IVA voltage processor command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. - . - ." "No_error,1" eventfld.long 0x00 9. " SMPS_RA_ERR_IVA ,Wrong register address error for IVA voltage processor - . - ." "No_error,1" eventfld.long 0x00 8. " SMPS_SA_ERR_IVA ,Wrong slave address error for IVA voltage processor - . - ." "No_error,1" textline " " eventfld.long 0x00 5. " VFSM_TIMEOUT_ERR_CORE ,CORE voltage FSM command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. - . - ." "No_error,1" eventfld.long 0x00 4. " VFSM_RA_ERR_CORE ,Wrong register address error for CORE voltage FSM - . - ." "No_error,1" eventfld.long 0x00 3. " VFSM_SA_ERR_CORE ,Wrong slave address error for CORE voltage FSM - . - ." "No_error,1" textline " " eventfld.long 0x00 2. " SMPS_TIMEOUT_ERR_CORE ,CORE voltage processor command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost. - . - ." "No_error,1" eventfld.long 0x00 1. " SMPS_RA_ERR_CORE ,Wrong register address error for CORE voltage processor - . - ." "No_error,1" eventfld.long 0x00 0. " SMPS_SA_ERR_CORE ,Wrong slave address error for CORE voltage processor - . - ." "No_error,1" tree.end tree "CKGEN_PRM" base ad:0x4A306100 width 23. group.long 0x0++0x3 line.long 0x00 "CM_ABE_DSS_SYS_CLKSEL,Select the SYS CLK for ABE and DSS subsystems. [warm reset insensitive]" bitfld.long 0x00 0. " CLKSEL ,Selects the divider value - . - ." "/1,/2" group.long 0x8++0x3 line.long 0x00 "CM_L4_WKUP_CLKSEL,Control the functional clock source of L4_WKUP, PRM and Smart Reflex functional clock." bitfld.long 0x00 0. " CLKSEL ,Select the clock source for L4WKUP_ICLK and for ABE_DPLL_BYPASS_CLK clocks. - . - ." "SYS_CLK,ABE_X1_LP_CLK" group.long 0xC++0x3 line.long 0x00 "CM_ABE_PLL_REF_CLKSEL,Control the source of the reference clock for DPLL_ABE" bitfld.long 0x00 0. " CLKSEL ,Select the source for the DPLL_ABE reference clock. - . - ." "DPLL_SYS_REF_CLK,SYS_32K" group.long 0x10++0x3 line.long 0x00 "CM_SYS_CLKSEL,Software sets the SYS_CLK configuration corresponding to the frequency of SYS_CLK. [warm reset insensitive]" bitfld.long 0x00 0.--2. " SYS_CLKSEL ,System clock input selection. - . - . - . - . - . - . - . - ." "Reserved,12_MHz,13_MHz,19.2_MHz,26_MHz,27_MHz,38.4_MHz,?..." tree.end tree "L3INIT_PRM" base ad:0x4A307300 width 29. group.long 0x0++0x3 line.long 0x00 "PM_L3INIT_PWRSTCTRL,This register controls the L3INIT power state to reach upon a domain sleep transition" bitfld.long 0x00 16.--17. " L3INIT_BANK1_ONSTATE ,L3INIT BANK state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 8. " L3INIT_BANK1_RETSTATE ,L3INIT BANK1 state when domain is RETENTION. - ." "Off,1" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" textline " " bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION - . - ." "Off,Retained" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "Off,RETENTION,Inactive,On" group.long 0x4++0x3 line.long 0x00 "PM_L3INIT_PWRSTST,This register provides a status on the current L3INIT power domain state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 4.--5. " L3INIT_BANK1_STATEST ,L3INIT BANK1 state status - . - . - . - ." "Off,Reserved,Reserved,On" textline " " bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Off,Retention,On-Inactive,On-Active" group.long 0x28++0x3 line.long 0x00 "PM_L3INIT_MMC1_WKDEP,This register controls wakeup dependency based on MMC1 service requests." bitfld.long 0x00 3. " WKUPDEP_MMC1_SDMA ,Wakeup dependency from MMC1 module (softwareakeup signal) towards SDMA + L3_2 + L4PER domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_MMC1_DSP ,Wakeup dependency from MMC1 module (softwareakeup signal) towards DSP + L3_1 + L3_2 + L4_PER domains - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " WKUPDEP_MMC1_MPU_M3 ,Wakeup dependency from MMC1 module (softwareakeup signal) towards MPU_A3 + L3_2 + L4_PER domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_MMC1_MPU ,Wakeup dependency from MMC1 module (softwareakeup signal) towards MPU + L3_1 + L3_2 + L4_PER domains - . - ." "Disabled,Enabled" group.long 0x2C++0x3 line.long 0x00 "RM_L3INIT_MMC1_CONTEXT,This register contains dedicated MMC1 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x30++0x3 line.long 0x00 "PM_L3INIT_MMC2_WKDEP,This register controls wakeup dependency based on MMC2 service requests." bitfld.long 0x00 3. " WKUPDEP_MMC2_SDMA ,Wakeup dependency from MMC2 module (softwareakeup signal) towards SDMA + L3_2 + L4PER domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_MMC2_DSP ,Wakeup dependency from MMC2 module (softwareakeup signal) towards DSP + L3_1 + L3_2 + L4_PER domains - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " WKUPDEP_MMC2_MPU_M3 ,Wakeup dependency from MMC2 module (softwareakeup signal) towards MPU_A3 + L3_2 + L4_PER domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_MMC2_MPU ,Wakeup dependency from MMC2 module (softwareakeup signal) towards MPU + L3_1 + L3_2 + L4_PER domains - . - ." "Disabled,Enabled" group.long 0x34++0x3 line.long 0x00 "RM_L3INIT_MMC2_CONTEXT,This register contains dedicated MMC2 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x38++0x3 line.long 0x00 "PM_L3INIT_HSI_WKDEP,This register controls wakeup dependency based on HSI service requests." bitfld.long 0x00 8. " WKUPDEP_WGM_HSI_WAKE_MPU ,Wakeup dependency from modem HSI_WAKE signal towards MPU + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " WKUPDEP_HSI_DSP_DSP ,Wakeup dependency from HSI module (softwareakeup_DSP signal) towards DSP + L3_1 + L4_CFG domains - ." "0,Enabled" bitfld.long 0x00 1. " WKUPDEP_HSI_MCU_MPU_M3 ,Wakeup dependency from HSI module (softwareakeup_MPU signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_HSI_MCU_MPU ,Wakeup dependency from HSI module (softwareakeup_MPU signal) towards MPU + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" group.long 0x3C++0x3 line.long 0x00 "RM_L3INIT_HSI_CONTEXT,This register contains dedicated HSI context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x58++0x3 line.long 0x00 "PM_L3INIT_HSUSBHOST_WKDEP,This register controls wakeup dependency based on USB_HOST_HS service requests." bitfld.long 0x00 1. " WKUPDEP_HSUSBHOST_MPU_M3 ,Wakeup dependency from USB_HOST_HS module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 0. " WKUPDEP_HSUSBHOST_MPU ,Wakeup dependency from USB_HOST_HS module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0x5C++0x3 line.long 0x00 "RM_L3INIT_HSUSBHOST_CONTEXT,This register contains dedicated USB_HOST context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x60++0x3 line.long 0x00 "PM_L3INIT_HSUSBOTG_WKDEP,This register controls wakeup dependency based on USB_OTG_HS service requests." bitfld.long 0x00 1. " WKUPDEP_HSUSBOTG_MPU_M3 ,Wakeup dependency from USB_OTG_HS module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_HSUSBOTG_MPU ,Wakeup dependency from USB_OTG_HS module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" group.long 0x64++0x3 line.long 0x00 "RM_L3INIT_HSUSBOTG_CONTEXT,This register contains dedicated USB_OTG_HS context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x68++0x3 line.long 0x00 "PM_L3INIT_HSUSBTLL_WKDEP,This register controls wakeup dependency based on USB_TLL service requests." bitfld.long 0x00 1. " WKUPDEP_HSUSBTLL_MPU_M3 ,Wakeup dependency from USB_TLL module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 0. " WKUPDEP_HSUSBTLL_MPU ,Wakeup dependency from USB_TLL module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0x6C++0x3 line.long 0x00 "RM_L3INIT_HSUSBTLL_CONTEXT,This register contains dedicated USB_TLL context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal) - . - ." "Maintained,Lost" group.long 0xD0++0x3 line.long 0x00 "PM_L3INIT_FSUSB_WKDEP,This register controls wakeup dependency based on USB_HOST_FS service requests." bitfld.long 0x00 1. " WKUPDEP_FSUSB_MPU_M3 ,Wakeup dependency from USB_HOST_FS module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 0. " WKUPDEP_FSUSB_MPU ,Wakeup dependency from USB_HOST_FS module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0xD4++0x3 line.long 0x00 "RM_L3INIT_FSUSB_CONTEXT,This register contains dedicated USB_HOST_FS context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal) - . - ." "Maintained,Lost" group.long 0xE4++0x3 line.long 0x00 "RM_L3INIT_USBPHY_CONTEXT,This register contains dedicated USBPHY context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RST signal) - . - ." "Maintained,Lost" tree.end tree "ABE_PRM" base ad:0x4A306500 width 25. group.long 0x0++0x3 line.long 0x00 "PM_ABE_PWRSTCTRL,This register controls the ABE domain power state to reach upon a domain sleep transition" bitfld.long 0x00 20.--21. " PERIPHMEM_ONSTATE ,PERIPHMEM memory state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 16.--17. " AESSMEM_ONSTATE ,AESSMEM memory state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 10. " PERIPHMEM_RETSTATE ,PERIPHMEM memory state when domain is RETENTION. - ." "Off,1" textline " " bitfld.long 0x00 8. " AESSMEM_RETSTATE ,AESSMEM memory state when domain is RETENTION. - ." "0,Retained" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION - ." "Off,1" textline " " bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "Off,Retention,Inactive,On" group.long 0x4++0x3 line.long 0x00 "PM_ABE_PWRSTST,This register provides a status on the ABE domain current power domain state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 8.--9. " PERIPHMEM_STATEST ,PERIPHMEM memory state status - . - . - . - ." "Off,Reserved,Reserved,On" textline " " bitfld.long 0x00 4.--5. " AESSMEM_STATEST ,AESSMEM memory state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Off,Retention,On-Inactive,On-Active" group.long 0x2C++0x3 line.long 0x00 "RM_ABE_AESS_CONTEXT,This register contains dedicated AESS context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_AESSMEM ,Specify if memory-based context in AESSMEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "Maintained,Lost" group.long 0x30++0x3 line.long 0x00 "PM_ABE_PDM_WKDEP,This register controls wakeup dependency based on PDM service requests." bitfld.long 0x00 7. " WKUPDEP_PDM_DMA_SDMA ,Wakeup dependency from PDM module (softwareakeup_dma signal) towards SDMA + L3_2 + L3_1 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " WKUPDEP_PDM_DMA_DSP ,Wakeup dependency from PDM module (softwareakeup_dma signal) towards DSP domain - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_PDM_IRQ_DSP ,Wakeup dependency from PDM module (softwareakeup_irq signal) towards DSP domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_PDM_IRQ_MPU ,Wakeup dependency from PDM module (softwareakeup_irq signal) towards MPU domain - . - ." "Disabled,Enabled" group.long 0x34++0x3 line.long 0x00 "RM_ABE_PDM_CONTEXT,This register contains dedicated PDM context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_PERIHPMEM ,Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "Maintained,Lost" group.long 0x38++0x3 line.long 0x00 "PM_ABE_DMIC_WKDEP,This register controls wakeup dependency based on DMIC service requests." bitfld.long 0x00 7. " WKUPDEP_DMIC_DMA_SDMA ,Wakeup dependency from DMIC module (softwareakeup_dma signal) towards SDMA + L3_2 + L3_1 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " WKUPDEP_DMIC_DMA_DSP ,Wakeup dependency from DMIC module (softwareakeup_dma signal) towards DSP domain - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_DMIC_IRQ_DSP ,Wakeup dependency from DMIC module (softwareakeup_irq signal) towards DSP domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_DMIC_IRQ_MPU ,Wakeup dependency from DMIC module (softwareakeup_irq signal) towards MPU domain - . - ." "Disabled,Enabled" group.long 0x3C++0x3 line.long 0x00 "RM_ABE_DMIC_CONTEXT,This register contains dedicated DMIC context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_PERIHPMEM ,Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "Maintained,Lost" group.long 0x40++0x3 line.long 0x00 "PM_ABE_MCASP_WKDEP,This register controls wakeup dependency based on MCASP service requests." bitfld.long 0x00 7. " WKUPDEP_MCASP1_DMA_SDMA ,Wakeup dependency from MCASP1 module (softwareakeup_dma signal) towards SDMA + L3_2 + L3_1 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " WKUPDEP_MCASP1_DMA_DSP ,Wakeup dependency from MCASP1 module (softwareakeup_dma signal) towards DSP domain - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_MCASP1_IRQ_DSP ,Wakeup dependency from MCASP1 module (softwareakeup_irq signal) towards DSP domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_MCASP1_IRQ_MPU ,Wakeup dependency from MCASP1 module (softwareakeup_irq signal) towards MPU domain - . - ." "Disabled,Enabled" group.long 0x44++0x3 line.long 0x00 "RM_ABE_MCASP_CONTEXT,This register contains dedicated MCASP context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "Maintained,Lost" group.long 0x48++0x3 line.long 0x00 "PM_ABE_MCBSP1_WKDEP,This register controls wakeup dependency based on MCBSP1 service requests." bitfld.long 0x00 3. " WKUPDEP_MCBSP1_SDMA ,Wakeup dependency from MCBSP1 module (softwareakeup signal) towards SDMA + L3_2 + L3_1 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_MCBSP1_DSP ,Wakeup dependency from MCBSP1 module (softwareakeup signal) towards DSP domain - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MCBSP1_MPU ,Wakeup dependency from MCBSP1 module (softwareakeup signal) towards MPU domain - . - ." "Disabled,Enabled" group.long 0x4C++0x3 line.long 0x00 "RM_ABE_MCBSP1_CONTEXT,This register contains dedicated MCBSP1 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_PERIHPMEM ,Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "Maintained,Lost" group.long 0x50++0x3 line.long 0x00 "PM_ABE_MCBSP2_WKDEP,This register controls wakeup dependency based on MCBSP2 service requests." bitfld.long 0x00 3. " WKUPDEP_MCBSP2_SDMA ,Wakeup dependency from MCBSP2 module (softwareakeup signal) towards SDMA + L3_2 + L3_1 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_MCBSP2_DSP ,Wakeup dependency from MCBSP2 module (softwareakeup signal) towards DSP domain - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MCBSP2_MPU ,Wakeup dependency from MCBSP2 module (softwareakeup signal) towards MPU domain - . - ." "Disabled,Enabled" group.long 0x54++0x3 line.long 0x00 "RM_ABE_MCBSP2_CONTEXT,This register contains dedicated MCBSP2 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_PERIHPMEM ,Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "Maintained,Lost" group.long 0x58++0x3 line.long 0x00 "PM_ABE_MCBSP3_WKDEP,This register controls wakeup dependency based on MCBSP3 service requests." bitfld.long 0x00 3. " WKUPDEP_MCBSP3_SDMA ,Wakeup dependency from MCBSP3 module (softwareakeup signal) towards SDMA + L3_2 + L3_1 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_MCBSP3_DSP ,Wakeup dependency from MCBSP3 module (softwareakeup signal) towards DSP domain - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MCBSP3_MPU ,Wakeup dependency from MCBSP3 module (softwareakeup signal) towards MPU domain - . - ." "Disabled,Enabled" group.long 0x5C++0x3 line.long 0x00 "RM_ABE_MCBSP3_CONTEXT,This register contains dedicated MCBSP3 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_PERIHPMEM ,Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "Maintained,Lost" group.long 0x60++0x3 line.long 0x00 "PM_ABE_SLIMBUS_WKDEP,This register controls wakeup dependency based on SLIMBUS service requests." bitfld.long 0x00 7. " WKUPDEP_SLIMBUS1_DMA_SDMA ,Wakeup dependency from SLIMBUS1 module (softwareakeup_dma signal) towards SDMA + L3_2 + L3_1 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " WKUPDEP_SLIMBUS1_DMA_DSP ,Wakeup dependency from SLIMBUS1 module (softwareakeup_dma signal) towards DSP domain - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_SLIMBUS1_IRQ_DSP ,Wakeup dependency from SLIMBUS1 module (softwareakeup_irq signal) towards DSP domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_SLIMBUS1_IRQ_MPU ,Wakeup dependency from SLIMBUS1 module (softwareakeup_irq signal) towards MPU domain - . - ." "Disabled,Enabled" group.long 0x64++0x3 line.long 0x00 "RM_ABE_SLIMBUS_CONTEXT,This register contains dedicated SLIMBUS context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_PERIHPMEM ,Specify if memory-based context in PERIHPMEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "Maintained,Lost" group.long 0x68++0x3 line.long 0x00 "PM_ABE_GPTIMER5_WKDEP,This register controls wakeup dependency based on TIMER5 service requests." bitfld.long 0x00 2. " WKUPDEP_TIMER5_DSP ,Wakeup dependency from TIMER5 module (softwareakeup signal) towards DSP domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 0. " WKUPDEP_TIMER5_MPU ,Wakeup dependency from TIMER5 module (softwareakeup signal) towards MPU domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0x6C++0x3 line.long 0x00 "RM_ABE_GPTIMER5_CONTEXT,This register contains dedicated TIMER5 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "0,1" group.long 0x70++0x3 line.long 0x00 "PM_ABE_GPTIMER6_WKDEP,This register controls wakeup dependency based on TIMER6 service requests." bitfld.long 0x00 2. " WKUPDEP_TIMER6_DSP ,Wakeup dependency from TIMER6 module (softwareakeup signal) towards DSP domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 0. " WKUPDEP_TIMER6_MPU ,Wakeup dependency from TIMER6 module (softwareakeup signal) towards MPU domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0x74++0x3 line.long 0x00 "RM_ABE_GPTIMER6_CONTEXT,This register contains dedicated TIMER6 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "0,1" group.long 0x78++0x3 line.long 0x00 "PM_ABE_GPTIMER7_WKDEP,This register controls wakeup dependency based on TIMER7 service requests." bitfld.long 0x00 2. " WKUPDEP_TIMER7_DSP ,Wakeup dependency from TIMER7 module (softwareakeup signal) towards DSP domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 0. " WKUPDEP_TIMER7_MPU ,Wakeup dependency from TIMER7 module (softwareakeup signal) towards MPU domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0x7C++0x3 line.long 0x00 "RM_ABE_GPTIMER7_CONTEXT,This register contains dedicated TIMER7 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "0,1" group.long 0x80++0x3 line.long 0x00 "PM_ABE_GPTIMER8_WKDEP,This register controls wakeup dependency based on TIMER8 service requests." bitfld.long 0x00 2. " WKUPDEP_TIMER8_DSP ,Wakeup dependency from TIMER8 module (softwareakeup signal) towards DSP domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 0. " WKUPDEP_TIMER8_MPU ,Wakeup dependency from TIMER8 module (softwareakeup signal) towards MPU domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0x84++0x3 line.long 0x00 "RM_ABE_GPTIMER8_CONTEXT,This register contains dedicated TIMER8 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "0,1" rgroup.long 0x88++0x3 line.long 0x00 "PM_ABE_WDTIMER3_WKDEP,This register controls wakeup dependency based on WDT3 service requests." bitfld.long 0x00 0. " WKUPDEP_WDT3_MPU ,Wakeup dependency from WDT3 module (softwareakeup signal) towards MPU domain - ." "0,Dependency_is_enabled" group.long 0x8C++0x3 line.long 0x00 "RM_ABE_WDTIMER3_CONTEXT,This register contains dedicated WDT3 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of AUDIO_RST signal) - . - ." "0,1" tree.end tree "ALWAYS_ON_PRM" base ad:0x4A306600 width 26. rgroup.long 0x28++0x3 line.long 0x00 "PM_ALWON_SR_MPU_WKDEP,This register controls wakeup dependency based on SR_MPU service requests." bitfld.long 0x00 0. " WKUPDEP_SR_MPU_MPU ,Wakeup dependency from SR_MPU module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - ." "0,Enabled" group.long 0x2C++0x3 line.long 0x00 "RM_ALWON_SR_MPU_CONTEXT,This register contains dedicated SR_MPU context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of Always_on_CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x30++0x3 line.long 0x00 "PM_ALWON_SR_IVA_WKDEP,This register controls wakeup dependency based on SR_IVA service requests." bitfld.long 0x00 1. " WKUPDEP_SR_IVA_MPU_M3 ,Wakeup dependency from SR_IVA module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_SR_IVA_MPU ,Wakeup dependency from SR_IVA module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" group.long 0x34++0x3 line.long 0x00 "RM_ALWON_SR_IVA_CONTEXT,This register contains dedicated SR_IVA context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of Always_on_CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x38++0x3 line.long 0x00 "PM_ALWON_SR_CORE_WKDEP,This register controls wakeup dependency based on SR_CORE service requests." bitfld.long 0x00 1. " WKUPDEP_SR_CORE_MPU_M3 ,Wakeup dependency from SR_CORE module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_SR_CORE_MPU ,Wakeup dependency from SR_CORE module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" group.long 0x3C++0x3 line.long 0x00 "RM_ALWON_SR_CORE_CONTEXT,This register contains dedicated SR_CORE context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of Always_on_CORE_RST signal) - . - ." "Maintained,Lost" tree.end tree "DSS_PRM" base ad:0x4A307100 width 20. group.long 0x0++0x3 line.long 0x00 "PM_DSS_PWRSTCTRL,This register controls the DSS power state to reach upon a domain sleep transition" bitfld.long 0x00 16.--17. " DSS_MEM_ONSTATE ,DSS_MEM state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 8. " DSS_MEM_RETSTATE ,DSS_MEM state when domain is RETENTION. - ." "Off,1" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" textline " " bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION - ." "Off,1" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "Off,Retention,Inactive,On" rgroup.long 0x4++0x3 line.long 0x00 "PM_DSS_PWRSTST,This register provides a status on the current DSS power domain state. [warm reset insensitive]" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 4.--5. " DSS_MEM_STATEST ,DSS_MEM state status - . - . - . - ." "Off,Reserved,Reserved,On" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" textline " " bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Off,Retention,On-Inactive,On-Active" group.long 0x20++0x3 line.long 0x00 "PM_DSS_DSS_WKDEP,This register controls wakeup dependency based on DSS service requests." bitfld.long 0x00 19. " WKUPDEP_HDMIDMA_SDMA ,Wakeup dependency from HDMI module (softwareakeup_HDMI_dma signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 14. " WKUPDEP_HDMIIRQ_DSP ,Wakeup dependency from HDMI module (softwareakeup_HDMI_irq signal) towards DSP + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 13. " WKUPDEP_HDMIIRQ_MPU_M3 ,Wakeup dependency from HDMI module (softwareakeup_HDMI_irq signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 12. " WKUPDEP_HDMIIRQ_MPU ,Wakeup dependency from HDMI module (softwareakeup_HDMI_irq signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 11. " WKUPDEP_DSI2_SDMA ,Wakeup dependency from DSI2 module (softwareakeup_DSI2 signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 10. " WKUPDEP_DSI2_DSP ,Wakeup dependency from DSI2 module (softwareakeup_DSI2 signal) towards DSP + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 9. " WKUPDEP_DSI2_MPU_M3 ,Wakeup dependency from DSI2 module (softwareakeup_DSI2 signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " WKUPDEP_DSI2_MPU ,Wakeup dependency from DSI2 module (softwareakeup_DSI2 signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " WKUPDEP_DSI1_SDMA ,Wakeup dependency from DSI1 module (softwareakeup_DSI1 signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 6. " WKUPDEP_DSI1_DSP ,Wakeup dependency from DSI1 module (softwareakeup_DSI1 signal) towards DSP + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " WKUPDEP_DSI1_MPU_M3 ,Wakeup dependency from DSI1 module (softwareakeup_DSI1 signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 4. " WKUPDEP_DSI1_MPU ,Wakeup dependency from DSI1 module (softwareakeup_DSI1 signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 3. " WKUPDEP_DISPC_SDMA ,Wakeup dependency from DISPC module (softwareakeup_DISPC signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_DISPC_DSP ,Wakeup dependency from DISPC module (softwareakeup_DISPC signal) towards DSP + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " WKUPDEP_DISPC_MPU_M3 ,Wakeup dependency from DISPC module (softwareakeup_DISPC signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_DISPC_MPU ,Wakeup dependency from DISPC module (softwareakeup_DISPC signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x24++0x3 line.long 0x00 "RM_DSS_DSS_CONTEXT,This register contains dedicated DSS context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_DSS_MEM ,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSS_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSS_RST signal) - . - ." "Maintained,Lost" tree.end tree "CKGEN_CM1" base ad:0x4A004100 width 29. group.long 0x0++0x3 line.long 0x00 "CM_CLKSEL_CORE,CORE module clock selection." bitfld.long 0x00 8. " CLKSEL_L4 ,Selects L4 interconnect clock (L4_clk) - . - ." "/1,/2" bitfld.long 0x00 4. " CLKSEL_L3 ,Selects L3 interconnect clock (L3_clk) - . - ." "/1,/2" bitfld.long 0x00 0. " CLKSEL_CORE ,Selects CORE_CLK configuration - . - ." "/1,/2" group.long 0x8++0x3 line.long 0x00 "CM_CLKSEL_ABE,ABE module clock selection." bitfld.long 0x00 10. " SLIMBUS_CLK_GATE ,Gating control for SLIMBUS_CLK clock tree in ABE. SLIMbus module always gets the ungated version. - . - ." "Gated,Enabled" bitfld.long 0x00 8. " PAD_CLKS_GATE ,Gating control for PAD_CLKS clock tree in ABE - . - ." "Gated,Enabled" bitfld.long 0x00 0.--1. " CLKSEL_OPP ,Selects the OPP divider ABE domain - . - . - . - ." "/1,/2,/4,?..." group.long 0x10++0x3 line.long 0x00 "CM_DLL_CTRL,Special register for DLL control" bitfld.long 0x00 0. " DLL_OVERRIDE ,Control if DLL lock and code outputs are overriden or not - . - ." "Not_overriden,Overriden" group.long 0x20++0x3 line.long 0x00 "CM_CLKMODE_DPLL_CORE,This register allows controlling the DPLL modes." bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required - . - ." "Both,Lower" bitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - . - ." "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled. - ." "Disabled,1" bitfld.long 0x00 10. " DPLL_LPMODE_EN ,Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled. - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set. - .." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode. - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,Reserved,MN_Bypass,Idle_Bypass_Low_Power,Idle_Bypass_Fast_Relock,Lock" rgroup.long 0x24++0x3 line.long 0x00 "CM_IDLEST_DPLL_CORE,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status - . - ." "0,1" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL lock status - . - ." "0,DPLL_is_LOCKED" group.long 0x28++0x3 line.long 0x00 "CM_AUTOIDLE_DPLL_CORE,This register provides automatic control over the DPLL activity." bitfld.long 0x00 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control. - . - . - . - . - . - . - . - ." "Disabled,Low_Power_Stop,Fast_Relock_Stop,Reserved,Reserved,Idle_Bypass_Low,Idle_Bypass_Fast,?..." group.long 0x2C++0x3 line.long 0x00 "CM_CLKSEL_DPLL_CORE,This register provides controls over the DPLL." bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL locked mode, 0 - No impact 1 - No impact In DPLL bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLK.." "CLKINP,CLKINPULOW" bitfld.long 0x00 20. " DPLL_CLKOUTHIF_CLKSEL ,Selects the source of the DPLL CLKOUTHIF clock. Same as CLKINPHIFSEL pin on the DPLL - . - ." "DCO,CLKINPHIF" hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 =.." textline " " hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)." group.long 0x30++0x3 line.long 0x00 "CM_DIV_M2_DPLL_CORE,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT - . - ." "Gated,Enabled" bitfld.long 0x00 5. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" textline " " bitfld.long 0x00 0.--4. " DPLL_CLKOUT_DIV ,DPLL post-divider factor, M2, for internal clock generation (1 to 31); Divide value from 1 to 31. - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x34++0x3 line.long 0x00 "CM_DIV_M3_DPLL_CORE,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x00 9. " ST_DPLL_CLKOUTHIF ,DPLL CLKOUTHIF status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUTHIF_GATE_CTRL ,Control gating of DPLL CLKOUTHIF - . - ." "Gated,Enabled" bitfld.long 0x00 5. " DPLL_CLKOUTHIF_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUTHIF_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" textline " " bitfld.long 0x00 0.--4. " DPLL_CLKOUTHIF_DIV ,DPLL post-divider factor, M3, for internal clock generation (1 to 31);Divide value from 1 to 31. - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x38++0x3 line.long 0x00 "CM_DIV_M4_DPLL_CORE,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT1_PWDN ,Automatic power down for HSDIVIDER M4 divider and hence CLKOUT1 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT1 ,HSDIVIDER CLKOUT1 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT1_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT1 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT1_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT1_DIV ,DPLL M4 post-divider factor (1 to 31). - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3C++0x3 line.long 0x00 "CM_DIV_M5_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT2_PWDN ,Automatic power down for HSDIVIDER M5 divider and hence CLKOUT2 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT2 ,HSDIVIDER CLKOUT2 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT2_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT2 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT2_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT2_DIV ,DPLL M5 post-divider factor (1 to 31). - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "CM_DIV_M6_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT3_PWDN ,Automatic power down for HSDIVIDER M6 divider and hence CLKOUT3 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT3 ,HSDIVIDER CLKOUT3 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT3_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT3 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT3_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT3_DIV ,DPLL M6 post-divider factor (1 to 31). - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x44++0x3 line.long 0x00 "CM_DIV_M7_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT4_PWDN ,Automatic power down for HSDIVIDER M7 divider and hence CLKOUT4 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT4 ,HSDIVIDER CLKOUT4 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT4_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT4 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT4_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT4_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT4_DIV ,DPLL M7 post-divider factor (1 to 31). - . - . - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x48++0x3 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_CORE,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part.." group.long 0x4C++0x3 line.long 0x00 "CM_SSC_MODFREQDIV_DPLL_CORE,Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x50++0x3 line.long 0x00 "CM_EMU_OVERRIDE_DPLL_CORE,This register provides emulation override controls over the CORE DPLL." bitfld.long 0x00 19. " OVERRIDE_ENABLE ,This bit allows to enable or disable the emulation override controls - . - ." "Disabled,Enabled" hexmask.long.word 0x00 8.--18. 1. " CORE_DPLL_EMU_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M) - . - ." hexmask.long.byte 0x00 0.--6. 1. " CORE_DPLL_EMU_DIV ,CORE DPLL override divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)." group.long 0x60++0x3 line.long 0x00 "CM_CLKMODE_DPLL_MPU,This register allows controlling the DPLL modes." bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required - . - ." "Both,Lower" bitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - . - ." "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled. - ." "Disabled,1" bitfld.long 0x00 10. " DPLL_LPMODE_EN ,Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled. - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set. - .." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode. - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,Reserved,MN_Bypass,Idle_Bypass_Low_Power,Idle_Bypass_Fast_Relock,Lock" rgroup.long 0x64++0x3 line.long 0x00 "CM_IDLEST_DPLL_MPU,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status - . - ." "0,1" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL lock status - . - ." "Bypass/Stop,Locked" group.long 0x68++0x3 line.long 0x00 "CM_AUTOIDLE_DPLL_MPU,This register provides automatic control over the DPLL activity." bitfld.long 0x00 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control; - . - . - . - . - . - . - . - ." "Disabled,Low_Power_Stop,Fast_Relock_Stop,Reserved,Reserved,Idle_Bypass_Low,Idle_Bypass_Fast,?..." group.long 0x6C++0x3 line.long 0x00 "CM_CLKSEL_DPLL_MPU,This register provides controls over the DPLL." bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Only CLKINPULOW bypass clock supported for this PLL" "Not_supported,Supported" hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL m.." hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)." group.long 0x70++0x3 line.long 0x00 "CM_DIV_M2_DPLL_MPU,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT - . - ." "Gated,Enabled" bitfld.long 0x00 5. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" textline " " bitfld.long 0x00 0.--4. " DPLL_CLKOUT_DIV ,DPLL post-divider factor, M2, for internal clock generation (1 to 31);Divide value from 1 to 31. - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x88++0x3 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_MPU,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part.." group.long 0x8C++0x3 line.long 0x00 "CM_SSC_MODFREQDIV_DPLL_MPU,Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x9C++0x3 line.long 0x00 "CM_BYPCLK_DPLL_MPU,Control MPU PLL BYPASS clock. [warm reset insensitive]" bitfld.long 0x00 0.--1. " CLKSEL ,Select the DPLL MPU bypass clock - . - . - . - ." "/1,/2,/4,/8" group.long 0xA0++0x3 line.long 0x00 "CM_CLKMODE_DPLL_IVA,This register allows controlling the DPLL modes." bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required - . - ." "Both,Lower" bitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - . - ." "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled. - ." "Disabled,1" bitfld.long 0x00 10. " DPLL_LPMODE_EN ,Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled. - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set. - .." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode. - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,Reserved,MN_Bypass,Idle_Bypass_Low_Power,Idle_Bypass_Fast_Relock,Lock" rgroup.long 0xA4++0x3 line.long 0x00 "CM_IDLEST_DPLL_IVA,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status - . - ." "0,1" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL lock status - . - ." "Bypass/Stop,Locked" group.long 0xA8++0x3 line.long 0x00 "CM_AUTOIDLE_DPLL_IVA,This register provides automatic control over the DPLL activity." bitfld.long 0x00 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control; - . - . - . - . - . - . - . - ." "Disabled,Low_Power_Stop,Fast_Relock_Stop,Reserved,Reserved,Idle_Bypass_Low,Idle_Bypass_Fast,?..." group.long 0xAC++0x3 line.long 0x00 "CM_CLKSEL_DPLL_IVA,This register provides controls over the DPLL." bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL locked mode, 0 - No impact 1 - No impact In DPLL bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLK.." "Not_supported,Supported" hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL m.." hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)." group.long 0xB8++0x3 line.long 0x00 "CM_DIV_M4_DPLL_IVA,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT1_PWDN ,Automatic power down for HSDIVIDER M4 divider and hence CLKOUT1 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT1 ,HSDIVIDER CLKOUT1 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT1_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT1 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT1_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT1_DIV ,DPLL M4 post-divider factor (1 to 31). - . - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xBC++0x3 line.long 0x00 "CM_DIV_M5_DPLL_IVA,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT2_PWDN ,Automatic power down for HSDIVIDER M5 divider and hence CLKOUT2 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT2 ,HSDIVIDER CLKOUT2 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT2_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT2 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT2_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT2_DIV ,DPLL M5 post-divider factor (1 to 31). - . - . - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC8++0x3 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_IVA,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part.." group.long 0xCC++0x3 line.long 0x00 "CM_SSC_MODFREQDIV_DPLL_IVA,Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0xDC++0x3 line.long 0x00 "CM_BYPCLK_DPLL_IVA,Control IVA PLL BYPASS clock. [warm reset insensitive]" bitfld.long 0x00 0.--1. " CLKSEL ,Select the DPLL IVA bypass clock - . - . - . - ." "/1,/2,/4,/8" group.long 0xE0++0x3 line.long 0x00 "CM_CLKMODE_DPLL_ABE,This register allows controlling the DPLL modes." bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required - . - ." "Both,Lower" bitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - . - ." "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled. - ." "Disabled,1" bitfld.long 0x00 10. " DPLL_LPMODE_EN ,Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled. - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set. - .." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode. - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,Reserved,MN_Bypass,Idle_Bypass_Low_Power,Idle_Bypass_Fast_Relock,Lock" rgroup.long 0xE4++0x3 line.long 0x00 "CM_IDLEST_DPLL_ABE,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status - . - ." "0,1" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL lock status - . - ." "Bypass/Stop,Locked" group.long 0xE8++0x3 line.long 0x00 "CM_AUTOIDLE_DPLL_ABE,This register provides automatic control over the DPLL activity." bitfld.long 0x00 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control; - . - . - . - . - . - . - . - ." "Disabled,Low_Power_Stop,Fast_Relock_Stop,Reserved,Reserved,Idle_Bypass_Low,Idle_Bypass_Fast,?..." group.long 0xEC++0x3 line.long 0x00 "CM_CLKSEL_DPLL_ABE,This register provides controls over the DPLL." bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Only CLKINPULOW bypass clock supported for this PLL" "Not_supported,Supported" hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL m.." hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)." group.long 0xF0++0x3 line.long 0x00 "CM_DIV_M2_DPLL_ABE,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x00 11. " ST_DPLL_CLKOUTX2 ,DPLL CLKOUTX2 status - . - ." "Gated,Enabled" bitfld.long 0x00 10. " DPLL_CLKOUTX2_GATE_CTRL ,Control gating of DPLL CLKOUTX2 - . - ." "Gated,Enabled" bitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT - . - ." "Gated,Enabled" bitfld.long 0x00 5. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " DPLL_CLKOUT_DIV ,DPLL post-divider factor, M2, for internal clock generation (1 to 31).Divide value from 1 to 31 - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF4++0x3 line.long 0x00 "CM_DIV_M3_DPLL_ABE,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x00 9. " ST_DPLL_CLKOUTHIF ,DPLL CLKOUTHIF status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUTHIF_GATE_CTRL ,Control gating of DPLL CLKOUTHIF - . - ." "Gated,Enabled" bitfld.long 0x00 5. " DPLL_CLKOUTHIF_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUTHIF_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" textline " " bitfld.long 0x00 0.--4. " DPLL_CLKOUTHIF_DIV ,DPLL post-divider factor, M3, for internal clock generation (1 to 31).Divide value from 1 to 31. - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x108++0x3 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_ABE,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part.." group.long 0x10C++0x3 line.long 0x00 "CM_SSC_MODFREQDIV_DPLL_ABE,Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x160++0x3 line.long 0x00 "CM_SHADOW_FREQ_CONFIG1,Shadow register to program new DPLL configuration affecting EMIF and GPMC (L3 clock) functional frequency during DVFS. The PRCM h/w automatically applies the new configuration after EMIF/GPMC have been put in idle state." bitfld.long 0x00 11.--15. " DPLL_CORE_M2_DIV ,Shadow register forCM_DIV_M2_DPLL_CORE.DPLL_CLKOUT_DIV. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1. Divide value from 1 to 31. - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " DPLL_CORE_DPLL_EN ,Shadow register forCM_CLKMODE_DPLL_CORE.DPLL_EN. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1. - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,Reserved,MN_Bypass,Idle_Bypass_Low_Power,Idle_Bypass_Fast_Relock,Lock" bitfld.long 0x00 3. " DLL_RESET ,Specify if DLL should be reset or not during the frequency change hardware sequence. - . - ." "No_reset,Reset" textline " " bitfld.long 0x00 2. " DLL_OVERRIDE ,Shadow register forCM_DLL_CTRL.DLL_OVERRIDE.The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1. - . - ." "Not_overriden,Overriden" bitfld.long 0x00 0. " FREQ_UPDATE ,Writing 1 indicates that a new configuration is available. It is automatically cleared by h/w after the configuration has been applied." "Not_updated,Updated" group.long 0x164++0x3 line.long 0x00 "CM_SHADOW_FREQ_CONFIG2,Shadow register to program new DPLL configuration affecting GPMC (L3 clock) functional frequency during DVFS. The PRCM h/w automatically applies the new configuration after EMIF/GPMC have been put in idle state." bitfld.long 0x00 3.--7. " DPLL_CORE_M5_DIV ,Shadow register forCM_DIV_M5_DPLL_CORE.HSDIVIDER_CLKOUT2_DIV. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FRE.." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " CLKSEL_L3 ,Shadow register forCM_CLKSEL_CORE.CLKSEL_L3. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FREQ_U.." "/1,/2" bitfld.long 0x00 1. " CLKSEL_CORE ,Shadow register forCM_CLKSEL_CORE.CLKSEL_CORE. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and .." "/1,/2" textline " " bitfld.long 0x00 0. " GPMC_FREQ_UPDATE ,Controls whether or not GPMC has to be put automatically into idle during the frequency change operation. - . - ." "Disabled,Enabled" group.long 0x170++0x3 line.long 0x00 "CM_DYN_DEP_PRESCAL,Control the time unit of the sliding window for dynamic dependencies (auto-sleep feature)." bitfld.long 0x00 0.--5. " PRESCAL ,Time unit is equal to (PRESCAL + 1) L4 clock cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x180++0x3 line.long 0x00 "CM_RESTORE_ST,Automatic restore status. This register is used by the system DMA to write a predefined value at the end of end automatic restore phase. [warm reset insensitive]" bitfld.long 0x00 2. " PHASE2B_COMPLETED ,Indicates if restore phase 2b is completed. Must be cleared by software before going to device OFF mode." "0,1" bitfld.long 0x00 1. " PHASE2A_COMPLETED ,Indicates if restore phase 2a is completed. Must be cleared by software before going to device OFF mode." "0,1" bitfld.long 0x00 0. " PHASE1_COMPLETED ,Indicates if restore phase 1 is completed. Must be cleared by software before going to device OFF mode." "0,1" tree.end tree "CKGEN_CM2" base ad:0x4A008100 width 28. group.long 0x0++0x3 line.long 0x00 "CM_CLKSEL_MPU_M3_ISS_ROOT,MPU_A3/ISS root clock selection (MPU_A3_ISS_CLK)." bitfld.long 0x00 0. " CLKSEL ,Select the source for the root clock of MPU_A3/ISS - . - ." "CORE_CLK,DPLL_PER" group.long 0x4++0x3 line.long 0x00 "CM_CLKSEL_USB_60MHZ,Selects the configuration of the divider generating 60MHz clock for USB from the DPLL_USB o/p." bitfld.long 0x00 0. " CLKSEL ,Select the configuration of the divider - . - ." "/1,/8" group.long 0x8++0x3 line.long 0x00 "CM_SCALE_FCLK,This register can be used to scale PER_ABE_NC_FCLK, 96M_FCLK, 48M_FCLK, and 64M_FCLK to half their respective typical frequencies." bitfld.long 0x00 0. " SCALE_FCLK ,Enable or disable the functional clock scaling. - . - ." "Default_freq.,Half_freq." group.long 0x10++0x3 line.long 0x00 "CM_CORE_DVFS_PERF1,This register allows to system master #1 to specify which level of performance is required from CORE domain (mainly external memory throughput?)" hexmask.long.byte 0x00 0.--7. 1. " PERF_REQ ,Current performance request. Unit to be defined by user." group.long 0x14++0x3 line.long 0x00 "CM_CORE_DVFS_PERF2,This register allows to system master #2 to specify which level of performance is require from CORE domain (mainly external memory throughput?)" hexmask.long.byte 0x00 0.--7. 1. " PERF_REQ ,Current performance request. Unit to be defined by user." group.long 0x18++0x3 line.long 0x00 "CM_CORE_DVFS_PERF3,This register allows to system master #3 to specify which level of performance is require from CORE domain (mainly external memory throughput?)" hexmask.long.byte 0x00 0.--7. 1. " PERF_REQ ,Current performance request. Unit to be defined by user." group.long 0x1C++0x3 line.long 0x00 "CM_CORE_DVFS_PERF4,This register allows to system master #4 to specify which level of performance is require from CORE domain (mainly external memory throughput?)" hexmask.long.byte 0x00 0.--7. 1. " PERF_REQ ,Current performance request. Unit to be defined by user." group.long 0x24++0x3 line.long 0x00 "CM_CORE_DVFS_CURRENT,This register hold the current level of performance achievable by the CORE domain, according to the current OPP setting" hexmask.long.byte 0x00 0.--7. 1. " PERF_CURRENT ,Current achievable performance level. Unit to be defined by user." group.long 0x28++0x3 line.long 0x00 "CM_IVA_DVFS_PERF_DSP,This register allows to specify which level of performance is required from IVA domain for DSP to operate." hexmask.long.byte 0x00 0.--7. 1. " PERF_REQ ,Current performance request. Unit to be defined by user." group.long 0x2C++0x3 line.long 0x00 "CM_IVA_DVFS_PERF_IVAHD,This register allows to specify which level of performance is required from IVA domain for IVAHD to operate." hexmask.long.byte 0x00 0.--7. 1. " PERF_REQ ,Current performance request. Unit to be defined by user." group.long 0x30++0x3 line.long 0x00 "CM_IVA_DVFS_PERF_ABE,This register allows to specify which level of performance is required from IVA domain for ABE to operate." hexmask.long.byte 0x00 0.--7. 1. " PERF_REQ ,Current performance request. Unit to be defined by user." group.long 0x38++0x3 line.long 0x00 "CM_IVA_DVFS_CURRENT,This register hold the current level of performance achievable by the IVA domain, according to the current OPP setting" hexmask.long.byte 0x00 0.--7. 1. " PERF_CURRENT ,Current achievable performance level. Unit to be defined by user." group.long 0x40++0x3 line.long 0x00 "CM_CLKMODE_DPLL_PER,This register allows controlling the DPLL modes." bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required - . - ." "Both,Lower" bitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - . - ." "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled. - ." "Disabled,1" bitfld.long 0x00 10. " DPLL_LPMODE_EN ,Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled. - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode. - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,Reserved,MN_Bypass,Bypass_Low_Power,Bypass_Fast_Relock,Lock" rgroup.long 0x44++0x3 line.long 0x00 "CM_IDLEST_DPLL_PER,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status - . - ." "0,1" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL lock status - . - ." "Bypass/Stop,Locked" group.long 0x48++0x3 line.long 0x00 "CM_AUTOIDLE_DPLL_PER,This register provides automatic control over the DPLL activity." bitfld.long 0x00 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control; - . - . - . - . - . - . - . - ." "Disabled,Low_Power_Stop,Fast_Relock_Stop,Reserved,Reserved,Idle_Bypass_Low,Idle_Bypass_Fast,?..." group.long 0x4C++0x3 line.long 0x00 "CM_CLKSEL_DPLL_PER,This register provides controls over the DPLL." bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLK.." "CLKINP,CLKINPULOW" hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL .." hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)." group.long 0x50++0x3 line.long 0x00 "CM_DIV_M2_DPLL_PER,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x00 11. " ST_DPLL_CLKOUTX2 ,DPLL CLKOUTX2 status - . - ." "Gated,Enabled" bitfld.long 0x00 10. " DPLL_CLKOUTX2_GATE_CTRL ,Control gating of DPLL CLKOUTX2 - . - ." "Gated,Enabled" bitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT - . - ." "Gated,Enabled" bitfld.long 0x00 5. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " DPLL_CLKOUT_DIV ,DPLL post-divider factor, M2, for internal clock generation (1 to 31) - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x3 line.long 0x00 "CM_DIV_M3_DPLL_PER,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x00 9. " ST_DPLL_CLKOUTHIF ,DPLL CLKOUTHIF status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUTHIF_GATE_CTRL ,Control gating of DPLL CLKOUTHIF - . - ." "Gated,Enabled" bitfld.long 0x00 5. " DPLL_CLKOUTHIF_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUTHIF_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" textline " " bitfld.long 0x00 0.--4. " DPLL_CLKOUTHIF_DIV ,DPLL post-divider factor, M3, for internal clock generation (1 to 31). The values listed below (3, 4, 6 and 8) are used for maximum supported frequency at each OPP. Higher dividers (max 31), thus lower frequencies, are also.." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58++0x3 line.long 0x00 "CM_DIV_M4_DPLL_PER,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT1_PWDN ,Automatic power down for HSDIVIDER M4 divider and hence CLKOUT1 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT1 ,HSDIVIDER CLKOUT1 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT1_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT1 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT1_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT1_DIV ,DPLL M4 post-divider factor (1 to 31). - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x3 line.long 0x00 "CM_DIV_M5_DPLL_PER,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT2_PWDN ,Automatic power down for HSDIVIDER M5 divider and hence CLKOUT2 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT2 ,HSDIVIDER CLKOUT2 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT2_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT2 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT2_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT2_DIV ,DPLL M5 post-divider factor (1 to 31). - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x60++0x3 line.long 0x00 "CM_DIV_M6_DPLL_PER,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT3_PWDN ,Automatic power down for HSDIVIDER M6 divider and hence CLKOUT3 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT3 ,HSDIVIDER CLKOUT3 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT3_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT3 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT3_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT3_DIV ,DPLL M6 post-divider factor (1 to 31). - . - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x64++0x3 line.long 0x00 "CM_DIV_M7_DPLL_PER,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT4_PWDN ,Automatic power down for HSDIVIDER M7 divider and hence CLKOUT4 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT4 ,HSDIVIDER CLKOUT4 status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT4_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT4 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT4_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT4_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT4_DIV ,DPLL M7 post-divider factor (1 to 31). - . - . - . - . - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x68++0x3 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_PER,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part.." group.long 0x6C++0x3 line.long 0x00 "CM_SSC_MODFREQDIV_DPLL_PER,Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x80++0x3 line.long 0x00 "CM_CLKMODE_DPLL_USB,This register allows controlling the DPLL modes." bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required - . - ." "Both,Lower" bitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - . - ." "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect DPLL low-power stop mode. - . - . - . - . - . - . - . - ." "Reserved,Low_Power_Stop,Reserved,Reserved,MN_Bypass,Idle_Bypass_Low_Power,Reserved,Lock" rgroup.long 0x84++0x3 line.long 0x00 "CM_IDLEST_DPLL_USB,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status - . - ." "0,1" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL lock status - . - ." "Bypass/Stop,Locked" group.long 0x88++0x3 line.long 0x00 "CM_AUTOIDLE_DPLL_USB,This register provides automatic control over the DPLL activity." bitfld.long 0x00 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control; - . - . - . - . - . - . - . - ." "Disabled,Low_Power_Stop,Reserved,Reserved,Reserved,Idle_Bypass_Low,?..." group.long 0x8C++0x3 line.long 0x00 "CM_CLKSEL_DPLL_USB,This register provides controls over the DPLL." hexmask.long.byte 0x00 24.--31. 1. " DPLL_SD_DIV ,Sigma-Delta divider select (2-255). This factor must be set by s/w to ensure optimum jitter performance. DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP / 250), where CLKINP is the input clock of the DPLL in MHz). .." bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL locked mode, 0 - No impact 1 - No impact In DPLL bypass mode, 0 - CLKINP is selected as the BY.." "CLKINP,CLKINPULOW" hexmask.long.word 0x00 8.--19. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 4095). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 4095 = DPLL mu.." textline " " hexmask.long.byte 0x00 0.--7. 1. " DPLL_DIV ,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)." group.long 0x90++0x3 line.long 0x00 "CM_DIV_M2_DPLL_USB,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT - . - ." "Gated,Enabled" bitfld.long 0x00 7. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" textline " " hexmask.long.byte 0x00 0.--6. 1. " DPLL_CLKOUT_DIV ,DPLL post-divider factor, M2, for internal clock generation (1 to 127) - . - ." group.long 0xA8++0x3 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_USB,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part.." group.long 0xAC++0x3 line.long 0x00 "CM_SSC_MODFREQDIV_DPLL_USB,Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0xB4++0x3 line.long 0x00 "CM_CLKDCOLDO_DPLL_USB,This register provides controls over the CLKDCOLDO output of the DPLL." bitfld.long 0x00 9. " ST_DPLL_CLKDCOLDO ,DPLL CLKDCOLDO status - . - ." "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKDCOLDO_GATE_CTRL ,Control gating of DPLL CLKDCOLDO - . - ." "Gated,Enabled" tree.end tree "IVAHD_CM2" base ad:0x4A008F00 width 24. group.long 0x0++0x3 line.long 0x00 "CM_IVAHD_CLKSTCTRL,This register enables the IVAHD domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 8. " CLKACTIVITY_IVAHD_CLK ,This field indicates the state of the IVAHD_CLK clock input of the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the IVAHD clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x4++0x3 line.long 0x00 "CM_IVAHD_STATICDEP,This register controls the static domain depedencies from IVAHD domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - ." "0,Enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" rgroup.long 0x8++0x3 line.long 0x00 "CM_IVAHD_DYNAMICDEP,This register controls the dynamic domain depedencies from IVAHD domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "Disabled,1" group.long 0x20++0x3 line.long 0x00 "CM_IVAHD_IVAHD_CLKCTRL,This register manages the IVAHD clocks." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x28++0x3 line.long 0x00 "CM_IVAHD_SL2_CLKCTRL,This register manages the SL2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." tree.end tree "DSS_CM2" base ad:0x4A009100 width 20. group.long 0x0++0x3 line.long 0x00 "CM_DSS_CLKSTCTRL,This register enables the DSS domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 11. " CLKACTIVITY_HDMI_PHY_48M_FCLK ,This field indicates the state of the HDMI_PHY_48MHz_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 10. " CLKACTIVITY_DSS_ALWON_SYS_CLK ,This field indicates the state of the DSS_ALWON_SYS_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 9. " CLKACTIVITY_DSS_FCLK ,This field indicates the state of the DSS_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 8. " CLKACTIVITY_DSS_L3_ICLK ,This field indicates the state of the DSS_L3_ICLK (and DSS_L4_ICLK) clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSS clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x4++0x3 line.long 0x00 "CM_DSS_STATICDEP,This register controls the static domain depedencies from DSS domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - ." "0,Enabled" bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Disabled,Enabled" rgroup.long 0x8++0x3 line.long 0x00 "CM_DSS_DYNAMICDEP,This register controls the dynamic domain depedencies from DSS domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 5. " L3_1_DYNDEP ,Dynamic dependency towards L3_1 domain - ." "Disabled,1" group.long 0x20++0x3 line.long 0x00 "CM_DSS_DSS_CLKCTRL,This register manages the DSS clocks." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 11. " OPTFCLKEN_TV_FCLK ,Optional functional clock control. - . - ." "0,1" textline " " bitfld.long 0x00 10. " OPTFCLKEN_SYS_CLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " OPTFCLKEN_48MHZ_CLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " OPTFCLKEN_DSSCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." tree.end tree "INTRCONN_SOCKET_CM1" base ad:0x4A004000 width 26. rgroup.long 0x0++0x3 line.long 0x00 "REVISION_CM1,This register contains the IP revision code for the CM1 part of the PRCM" hexmask.long 0x00 0.--31. 1. " REVISION ,Revision Number" group.long 0x40++0x3 line.long 0x00 "CM_CM1_PROFILING_CLKCTRL,This register manages the CM1_PROFILING clock. [warm reset insensitive]" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0xF0++0x3 line.long 0x00 "CM1_DEBUG_CFG,This register is used to configure the CM1's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. [warm reset insensitive]" hexmask.long.byte 0x00 24.--30. 1. " SEL3 ,Internal signal block select for debug word byte-3" hexmask.long.byte 0x00 16.--22. 1. " SEL2 ,Internal signal block select for debug word byte-2" hexmask.long.byte 0x00 8.--14. 1. " SEL1 ,Internal signal block select for debug word byte-1" textline " " hexmask.long.byte 0x00 0.--6. 1. " SEL0 ,Internal signal block select for debug word byte-0" tree.end tree "INTRCONN_SOCKET_CM2" base ad:0x4A008000 width 26. rgroup.long 0x0++0x3 line.long 0x00 "REVISION_CM2,This register contains the IP revision code for the CM2 part of the PRCM" hexmask.long 0x00 0.--31. 1. " REVISION ,Revision Number" group.long 0x40++0x3 line.long 0x00 "CM_CM2_PROFILING_CLKCTRL,This register manages the CM2_PROFILING clocks. [warm reset insensitive]" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0xF0++0x3 line.long 0x00 "CM2_DEBUG_CFG,This register is used to configure the CM2's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. [warm reset insensitive]" hexmask.long.byte 0x00 24.--31. 1. " SEL3 ,Internal signal block select for debug word byte-3" hexmask.long.byte 0x00 16.--23. 1. " SEL2 ,Internal signal block select for debug word byte-2" hexmask.long.byte 0x00 8.--15. 1. " SEL1 ,Internal signal block select for debug word byte-1" textline " " hexmask.long.byte 0x00 0.--7. 1. " SEL0 ,Internal signal block select for debug word byte-0" tree.end tree "WKUP_PRM" base ad:0x4A307700 width 26. group.long 0x24++0x3 line.long 0x00 "RM_WKUP_L4WKUP_CONTEXT,This register contains dedicated L4WKUP context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUP_RST signal) - . - ." "Maintained,Lost" group.long 0x30++0x3 line.long 0x00 "PM_WKUP_WDTIMER2_WKDEP,This register controls wakeup dependency based on WDT2 service requests." bitfld.long 0x00 1. " WKUPDEP_WDT2_MPU_M3 ,Wakeup dependency from WDT2 module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_WDT2_MPU ,Wakeup dependency from WDT2 module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" group.long 0x34++0x3 line.long 0x00 "RM_WKUP_WDTIMER2_CONTEXT,This register contains dedicated WDT2 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUP_RST signal) - . - ." "Maintained,Lost" group.long 0x38++0x3 line.long 0x00 "PM_WKUP_GPIO1_WKDEP,This register controls wakeup dependency based on GPIO1 service requests." bitfld.long 0x00 6. " WKUPDEP_GPIO1_IRQ2_DSP ,Wakeup dependency from GPIO1 module (POINTRsoftwareAKEUP2 signal) towards DSP + L3_1 + L4_CFG domains - ." "0,Enabled" bitfld.long 0x00 1. " WKUPDEP_GPIO1_IRQ1_MPU_M3 ,Wakeup dependency from GPIO1 module (POINTRsoftwareAKEUP1 signal) module towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_GPIO1_IRQ1_MPU ,Wakeup dependency from GPIO1 module (POINTRsoftwareAKEUP1 signal) towards MPU + L3_1 + L4_CFG domains - . - ." "Disabled,Enabled" group.long 0x3C++0x3 line.long 0x00 "RM_WKUP_GPIO1_CONTEXT,This register contains dedicated GPIO1 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUP_RST signal) - . - ." "Maintained,Lost" rgroup.long 0x40++0x3 line.long 0x00 "PM_WKUP_GPTIMER1_WKDEP,This register controls wakeup dependency based on TIMER1 service requests." bitfld.long 0x00 0. " WKUPDEP_TIMER1_MPU ,Wakeup dependency from TIMER1 module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - ." "0,Enabled" group.long 0x44++0x3 line.long 0x00 "RM_WKUP_GPTIMER1_CONTEXT,This register contains dedicated TIMER1 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUP_RST signal) - . - ." "Maintained,Lost" group.long 0x54++0x3 line.long 0x00 "RM_WKUP_32KTIMER_CONTEXT,This register contains dedicated SYNCTIMER context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUP_SYS_PWRON_RST signal) - . - ." "Maintained,Lost" group.long 0x64++0x3 line.long 0x00 "RM_WKUP_SARRAM_CONTEXT,This register contains dedicated SARRAM context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_WKUP_BANK ,Specify if memory-based context in WKUP_BANK memory bank has been lost due to a previous global cold reset. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUP_RST signal) - . - ." "Maintained,Lost" rgroup.long 0x78++0x3 line.long 0x00 "PM_WKUP_KEYBOARD_WKDEP,This register controls wakeup dependency based on KEYBOARD service requests." bitfld.long 0x00 0. " WKUPDEP_KEYBOARD_MPU ,Wakeup dependency from KEYBOARD module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains - ." "0,Enabled" group.long 0x7C++0x3 line.long 0x00 "RM_WKUP_KEYBOARD_CONTEXT,This register contains dedicated KEYBOARD context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUP_RST signal) - . - ." "Maintained,Lost" tree.end tree "INTRCONN_SOCKET_PRM" base ad:0x4A306000 width 26. rgroup.long 0x0++0x3 line.long 0x00 "REVISION_PRM,This register contains the IP revision code for the PRM part of the PRCM" hexmask.long 0x00 0.--31. 1. " REV ,Revision Number" group.long 0x10++0x3 line.long 0x00 "PRM_IRQSTATUS_MPU_A9,This register provides status on MPU interrupt events. Any event is logged independently of the corresponding IRQENABLE value. Software is required to clear a set bit by writing a 1 into the bit-position to be cleared." eventfld.long 0x00 31. " ABB_IVA_DONE_ST ,IVA ABB mode change done. This status is set when OPP_CHANGE bit is cleared by hardware in PRM_LDO_ABB_IVA_CRTL register. It is cleared by software. - . - ." "No_interrupt,Interrupt_is_pending" eventfld.long 0x00 30. " VC_IVA_VPACK_ST ,Voltage Controller IVA voltage processor command acknowledge status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 29. " VP_IVA_TRANXDONE_ST ,Voltage Processor IVA transaction completion status. This status is set when a transaction is completed in the voltage processor, including ABB mode change done if applicable (OPP_CHANGE bit cleared in PRM_LDO_ABB_IV.." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 28. " VP_IVA_EQVALUE_ST ,Voltage Processor IVA voltage value change event. This status is set when an update has been requested but the new voltage value is the same as the current SMPS voltage value. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 27. " VP_IVA_NOSMPSACK_ST ,Voltage Processor IVA timeout event status. This status is set when the timeout occured before the SMPS acknowledge. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 26. " VP_IVA_MAXVDD_ST ,Voltage Processor IVA voltage higher limit event status. This status is set when the voltage higher limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 25. " VP_IVA_MINVDD_ST ,Voltage Processor IVA voltage lower limit event status. This status is set when the voltage lower limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 24. " VP_IVA_OPPCHANGEDONE_ST ,Voltage Processor IVA OPP change done status, including ABB mode change done if applicable (OPP_CHANGE bit cleared in PRM_LDO_ABB_IVA_CRTL). It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 22. " VC_CORE_VPACK_ST ,Voltage Controller CORE voltage processor command acknowledge status - . - ." "No_interrupt,Interrupt_is_pending" textline " " eventfld.long 0x00 21. " VP_CORE_TRANXDONE_ST ,Voltage Processor CORE transaction completion status. This status is set when a transaction is completed in the voltage processor. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 20. " VP_CORE_EQVALUE_ST ,Voltage Processor CORE voltage value change event. This status is set when an update has been requested but the new voltage value is the same as the current SMPS voltage value. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 19. " VP_CORE_NOSMPSACK_ST ,Voltage Processor CORE timeout event status. This status is set when the timeout occured before the SMPS acknowledge. It is cleared by software. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 18. " VP_CORE_MAXVDD_ST ,Voltage Processor CORE voltage higher limit event status. This status is set when the voltage higher limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 17. " VP_CORE_MINVDD_ST ,Voltage Processor CORE voltage lower limit event status. This status is set when the voltage lower limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 16. " VP_CORE_OPPCHANGEDONE_ST ,Voltage Processor CORE OPP change done status. It is cleared by software. - . - ." "No_interrupt,Interrupt" textline " " bitfld.long 0x00 15. " Reserved ," "0,1" eventfld.long 0x00 14. " VC_BYPASSACK_ST ,Voltage Controller bypass command acknowledge status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 13. " VC_TOERR_ST ,Voltage Controller timeout error event status. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 12. " VC_RAERR_ST ,Voltage Controller register address acknowledge error event status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 11. " VC_SAERR_ST ,Voltage Controller slave address acknowledge error event status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 9. " IO_ST ,I/O pad event interrupt status. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TRANSITION_ST ,Software supervised transition completed event interrupt status (any domain). Asserted upon completion of any clock domain force wakeup transition or upon completion of any power domain sleep transition with at least one enclosed.." "No_interrupt,Interrupt" eventfld.long 0x00 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" group.long 0x14++0x3 line.long 0x00 "PRM_IRQSTATUS_MPU_A9_2,This register provides status on MPU interrupt events. Any event is logged independently of the corresponding IRQENABLE value. Software is required to clear a set bit by writing a 1 into the bit-position to be cleared." eventfld.long 0x00 7. " ABB_MPU_DONE_ST ,MPU ABB mode change done. This status is set when OPP_CHANGE bit is cleared by hardware in PRM_LDO_ABB_MPU_CRTL register. It is cleared by software. - . - ." "No_interrupt,Interrupt_is_pending" eventfld.long 0x00 6. " VC_MPU_VPACK_ST ,Voltage Controller MPU voltage processor command acknowledge status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 5. " VP_MPU_TRANXDONE_ST ,Voltage Processor MPU transaction completion status. This status is set when a transaction is completed in the voltage processor, including ABB mode change done if applicable (OPP_CHANGE bit cleared in PRM_LDO_ABB_MP.." "No_interrupt,Interrupt_is_pending" textline " " eventfld.long 0x00 4. " VP_MPU_EQVALUE_ST ,Voltage Processor MPU voltage value change event. This status is set when an update has been requested but the new voltage value is the same as the current SMPS voltage value. It is cleared by software. - . - ." "No_interrupt,Interrupt_is_pending" eventfld.long 0x00 3. " VP_MPU_NOSMPSACK_ST ,Voltage Processor MPU timeout event status. This status is set when the timeout occured before the SMPS acknowledge. It is cleared by software. - . - ." "No_interrupt,Interrupt_is_pending" eventfld.long 0x00 2. " VP_MPU_MAXVDD_ST ,Voltage Processor MPU voltage higher limit event status. This status is set when the voltage higher limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt_is_pending" textline " " eventfld.long 0x00 1. " VP_MPU_MINVDD_ST ,Voltage Processor MPU voltage lower limit event status. This status is set when the voltage lower limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt_is_pending" eventfld.long 0x00 0. " VP_MPU_OPPCHANGEDONE_ST ,Voltage Processor MPU OPP change done status, including ABB mode change done if applicable (OPP_CHANGE bit cleared in PRM_LDO_ABB_MPU_CRTL). It is cleared by software. - . - ." "No_interrupt,Interrupt_is_pending" group.long 0x18++0x3 line.long 0x00 "PRM_IRQENABLE_MPU_A9,This register is used to enable or disable MPU interrupt activation upon presence of corresponding bit." bitfld.long 0x00 31. " ABB_IVA_DONE_EN ,IIVA ABB mode change done enable. - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 30. " VC_IVA_VPACK_EN ,Voltage Controller IVA voltage processor command acknowledge enable. - . - ." "Masked,Enabled" bitfld.long 0x00 29. " VP_IVA_TRANXDONE_EN ,Voltage Processor IVA transaction completion enable. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 28. " VP_IVA_EQVALUE_EN ,Voltage Processor IVA voltage value change event enable. - . - ." "Masked,Enabled" bitfld.long 0x00 27. " VP_IVA_NOSMPSACK_EN ,Voltage Processor IVA timeout event enable. - . - ." "Masked,Enabled" bitfld.long 0x00 26. " VP_IVA_MAXVDD_EN ,Voltage Processor IVA voltage higher limit event enable. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 25. " VP_IVA_MINVDD_EN ,Voltage Processor IVA voltage lower limit event enable. - . - ." "Masked,Enabled" bitfld.long 0x00 24. " VP_IVA_OPPCHANGEDONE_EN ,Voltage Processor IVA OPP change done enable. - . - ." "Masked,Enabled" bitfld.long 0x00 22. " VC_CORE_VPACK_EN ,Voltage Controller CORE voltage processor command acknowledge enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" textline " " bitfld.long 0x00 21. " VP_CORE_TRANXDONE_EN ,Voltage Processor CORE transaction completion enable. - . - ." "Masked,Enabled" bitfld.long 0x00 20. " VP_CORE_EQVALUE_EN ,Voltage Processor CORE voltage value change event enable. - . - ." "Masked,Enabled" bitfld.long 0x00 19. " VP_CORE_NOSMPSACK_EN ,Voltage Processor CORE timeout event enable. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " VP_CORE_MAXVDD_EN ,Voltage Processor CORE voltage higher limit event enable. - . - ." "Masked,Enabled" bitfld.long 0x00 17. " VP_CORE_MINVDD_EN ,Voltage Processor CORE voltage lower limit event enable. - . - ." "Masked,Enabled" bitfld.long 0x00 16. " VP_CORE_OPPCHANGEDONE_EN ,Voltage Processor CORE OPP change done enable. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 14. " VC_BYPASSACK_EN ,Voltage Controller bypass command acknowledge enable. - . - ." "Masked,Enabled" bitfld.long 0x00 13. " VC_TOERR_EN ,Voltage Controller timeout error event enable. - . - ." "Masked,Enabled" bitfld.long 0x00 12. " VC_RAERR_EN ,Voltage Controller register address acknowledge error event enable. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 11. " VC_SAERR_EN ,Voltage Controller slave address acknowledge error event enable. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " IO_EN ,I/O pad event interrupt enable. - . - ." "Masked,Enabled" bitfld.long 0x00 8. " TRANSITION_EN ,Software supervised transition completed event interrupt enable (any domain). - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 4. " DPLL_ABE_RECAL_EN ,ABE DPLL recalibration interrupt enable. - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable. - . - ." "Masked,Enabled" bitfld.long 0x00 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable. - . - ." "Masked,Enabled" bitfld.long 0x00 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable. - . - ." "Masked,Enabled" group.long 0x1C++0x3 line.long 0x00 "PRM_IRQENABLE_MPU_A9_2,This register is used to enable or disable MPU interrupt activation upon presence of corresponding bit." bitfld.long 0x00 7. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable. - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 6. " VC_MPU_VPACK_EB ,Voltage Controller MPU voltage processor command acknowledge enable. - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 5. " VP_MPU_TRANXDONE_EN ,Voltage Processor MPU transaction completion enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 4. " VP_MPU_EQVALUE_EN ,Voltage Processor MPU voltage value change event enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " VP_MPU_NOSMPSACK_EN ,Voltage Processor MPU timeout event enable - . - ." "Masked,Enabled" bitfld.long 0x00 2. " VP_MPU_MAXVDD_EN ,Voltage Processor MPU voltage higher limit event enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 1. " VP_MPU_MINVDD_EN ,Voltage Processor MPU voltage lower limit event enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " VP_MPU_OPPCHANGEDONE_EN ,Voltage Processor MPU OPP change done enable - . - ." "Masked,Enabled" group.long 0x20++0x3 line.long 0x00 "PRM_IRQSTATUS_MPU_M3,This register provides status on MPU_A3 interrupt events. Any event is logged independently of the corresponding IRQENABLE value. Software is required to clear a set bit by writing a 1 into the bit-position to be cleared." eventfld.long 0x00 31. " ABB_IVA_DONE_ST ,IVA ABB mode change done. This status is set when OPP_CHANGE bit is cleared by hardware in PRM_LDO_ABB_IVA_CRTL register. It is cleared by software. - . - ." "No_interrupt,Interrupt_is_pending" eventfld.long 0x00 30. " VC_IVA_VPACK_ST ,Voltage Controller IVA voltage processor command acknowledge status - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 29. " VP_IVA_TRANXDONE_ST ,Voltage Processor IVA transaction completion status. This status is set when a transaction is completed in the voltage processor, including ABB mode change done if applicable (OPP_CHANGE bit cleared in PRM_LDO_ABB_IV.." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 28. " VP_IVA_EQVALUE_ST ,Voltage Processor IVA voltage value change event. This status is set when an update has been requested but the new voltage value is the same as the current SMPS voltage value. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 27. " VP_IVA_NOSMPSACK_ST ,Voltage Processor IVA timeout event status. This status is set when the timeout occured before the SMPS acknowledge. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 26. " VP_IVA_MAXVDD_ST ,Voltage Processor IVA voltage higher limit event status. This status is set when the voltage higher limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 25. " VP_IVA_MINVDD_ST ,Voltage Processor IVA voltage lower limit event status. This status is set when the voltage lower limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 24. " VP_IVA_OPPCHANGEDONE_ST ,Voltage Processor IVA OPP change done status, including ABB mode change done if applicable (OPP_CHANGE bit cleared in PRM_LDO_ABB_IVA_CRTL). It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 22. " VC_CORE_VPACK_ST ,Voltage Controller CORE voltage processor command acknowledge status - . - ." "No_interrupt,Interrupt_is_pending" textline " " eventfld.long 0x00 21. " VP_CORE_TRANXDONE_ST ,Voltage Processor CORE transaction completion status. This status is set when a transaction is completed in the voltage processor. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 20. " VP_CORE_EQVALUE_ST ,Voltage Processor CORE voltage value change event. This status is set when an update has been requested but the new voltage value is the same as the current SMPS voltage value. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 19. " VP_CORE_NOSMPSACK_ST ,Voltage Processor CORE timeout event status. This status is set when the timeout occured before the SMPS acknowledge. It is cleared by software. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 18. " VP_CORE_MAXVDD_ST ,Voltage Processor CORE voltage higher limit event status. This status is set when the voltage higher limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 17. " VP_CORE_MINVDD_ST ,Voltage Processor CORE voltage lower limit event status. This status is set when the voltage lower limit is reached. It is cleared by software. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 16. " VP_CORE_OPPCHANGEDONE_ST ,Voltage Processor CORE OPP change done status. It is cleared by software. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 14. " VC_BYPASSACK_ST ,Voltage Controller bypass command acknowledge status - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 13. " VC_TOERR_ST ,Voltage Controller timeout error event status - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 12. " VC_RAERR_ST ,Voltage Controller register address acknowledge error event status - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 11. " VC_SAERR_ST ,Voltage Controller slave address acknowledge error event status - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 10. " FORCEWKUP_ST ,CORTEXM3 domain software supervised wakeup transition completed event interrupt status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 9. " IO_ST ,I/O pad event interrupt status. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TRANSITION_ST ,Software supervised transition completed event interrupt status (any domain). Asserted upon completion of any clock domain force wakeup transition or upon completion of any power domain sleep transition with at least one enclosed.." "No_interrupt,Interrupt" eventfld.long 0x00 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt_is_pending" eventfld.long 0x00 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" textline " " eventfld.long 0x00 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" group.long 0x28++0x3 line.long 0x00 "PRM_IRQENABLE_MPU_M3,This register is used to enable or disable MPU_A3 interrupt activation upon presence of corresponding bit." bitfld.long 0x00 31. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 30. " VC_IVA_VPACK_EN ,Voltage Controller IVA voltage processor command acknowledge enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 29. " VP_IVA_TRANXDONE_EN ,Voltage Processor IVA transaction completion enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" textline " " bitfld.long 0x00 28. " VP_IVA_EQVALUE_EN ,Voltage Processor IVA voltage value change event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 27. " VP_IVA_NOSMPSACK_EN ,Voltage Processor IVA timeout event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 26. " VP_IVA_MAXVDD_EN ,Voltage Processor IVA voltage higher limit event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" textline " " bitfld.long 0x00 25. " VP_IVA_MINVDD_EN ,Voltage Processor IVA voltage lower limit event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 24. " VP_IVA_OPPCHANGEDONE_EN ,Voltage Processor IVA OPP change done enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 22. " VC_CORE_VPACK_EN ,Voltage Controller CORE voltage processor command acknowledge enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" textline " " bitfld.long 0x00 21. " VP_CORE_TRANXDONE_EN ,Voltage Processor CORE transaction completion enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 20. " VP_CORE_EQVALUE_EN ,Voltage Processor CORE voltage value change event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 19. " VP_CORE_NOSMPSACK_EN ,Voltage Processor CORE timeout event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" textline " " bitfld.long 0x00 18. " VP_CORE_MAXVDD_EN ,Voltage Processor CORE voltage higher limit event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 17. " VP_CORE_MINVDD_EN ,Voltage Processor CORE voltage lower limit event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 16. " VP_CORE_OPPCHANGEDONE_EN ,Voltage Processor CORE OPP change done enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" textline " " bitfld.long 0x00 14. " VC_BYPASSACK_EN ,Voltage Controller bypass command acknowledge enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 13. " VC_TOERR_EN ,Voltage Controller timeout error event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 12. " VC_RAERR_EN ,Voltage Controller register address acknowledge error event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" textline " " bitfld.long 0x00 11. " VC_SAERR_EN ,Voltage Controller slave address acknowledge error event enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 10. " FORCEWKUP_EN ,CORTEXM3 domain software supervised wakeup transition completed event interrupt enable. - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 9. " IO_EN ,I/O pad event interrupt enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" textline " " bitfld.long 0x00 8. " TRANSITION_EN ,Software supervised transition completed event interrupt enable (any domain) - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" textline " " bitfld.long 0x00 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" bitfld.long 0x00 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable - . - ." "Interrupt_is_masked,Interrupt_is_enabled" group.long 0x30++0x3 line.long 0x00 "PRM_IRQSTATUS_DSP,This register provides status on DSP interrupt events. Any event is logged independently of the corresponding IRQENABLE value. Software is required to clear a set bit by writing a 1 into the bit-position to be cleared." eventfld.long 0x00 10. " FORCEWKUP_ST ,DSP domain software supervised wakeup transition completed event interrupt status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" eventfld.long 0x00 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status. - . - ." "No_interrupt,Interrupt" group.long 0x38++0x3 line.long 0x00 "PRM_IRQENABLE_DSP,This register is used to enable or disable DSP interrupt activation upon presence of corresponding bit." bitfld.long 0x00 10. " FORCEWKUP_EN ,DSP domain software supervised wakeup transition completed event interrupt enable. - . - ." "Masked,Enabled" bitfld.long 0x00 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable - . - ." "Masked,Enabled" bitfld.long 0x00 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable - . - ." "Masked,Enabled" group.long 0x40++0x3 line.long 0x00 "CM_PRM_PROFILING_CLKCTRL,This register manages the PRM_PROFILING clock. [warm reset insensitive]" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status - . - . - . - ." "0,1,2,Module_is_disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,1,?..." group.long 0xF0++0x3 line.long 0x00 "PRM_DEBUG_CFG,This register is used to configure the PRM's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. [warm reset insensitive]" hexmask.long.byte 0x00 24.--30. 1. " SEL3 ,Internal signal block select for debug word byte-3" hexmask.long.byte 0x00 16.--22. 1. " SEL2 ,Internal signal block select for debug word byte-2" hexmask.long.byte 0x00 8.--14. 1. " SEL1 ,Internal signal block select for debug word byte-1" textline " " hexmask.long.byte 0x00 0.--6. 1. " SEL0 ,Internal signal block select for debug word byte-0" tree.end tree "L4PER_CM2" base ad:0x4A009400 width 28. group.long 0x0++0x3 line.long 0x00 "CM_L4PER_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 25. " CLKACTIVITY_PER_ABE_24M_FCLK ,This field indicates the state of the PER_ABE_24M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 22. " CLKACTIVITY_PER_MCBSP4_FCLK ,This field indicates the state of the PER_MCBSP4_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 19. " CLKACTIVITY_PER_96M_FCLK ,This field indicates the state of the PER_96M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 18. " CLKACTIVITY_PER_48M_FCLK ,This field indicates the state of the PER_48M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 17. " CLKACTIVITY_PER_32K_FCLK ,This field indicates the state of the PER_32K_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 16. " CLKACTIVITY_PER_24MC_FCLK ,This field indicates the state of the PER_24MC_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 15. " CLKACTIVITY_12M_FCLK ,This field indicates the state of the FUNC_12M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 14. " CLKACTIVITY_GPT9_FCLK ,This field indicates the state of the DMT9_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 13. " CLKACTIVITY_GPT4_FCLK ,This field indicates the state of the DMT4_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 12. " CLKACTIVITY_GPT3_FCLK ,This field indicates the state of the DMT3_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 11. " CLKACTIVITY_GPT2_FCLK ,This field indicates the state of the DMT2_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 10. " CLKACTIVITY_GPT11_FCLK ,This field indicates the state of the DMT11_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 9. " CLKACTIVITY_GPT10_FCLK ,This field indicates the state of the DMT10_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 8. " CLKACTIVITY_L4_PER_ICLK ,This field indicates the state of the L4_PER_GICLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4PER clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x8++0x3 line.long 0x00 "CM_L4PER_DYNAMICDEP,This register controls the dynamic domain dependencies from L4PER domain towards 'target' domains. It is relevant only for domain having INTERCONN master port(s)." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor INTERCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14. " L4SEC_DYNDEP ,Dynamic dependency towards L4SEC clock domain - ." "0,Enabled" bitfld.long 0x00 8. " DSS_DYNDEP ,Dynamic dependency towards DSS clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 7. " L3_INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain - ." "0,Enabled" group.long 0x28++0x3 line.long 0x00 "CM_L4PER_GPTIMER10_CLKCTRL,This register manages the DMTIMER10 clocks." bitfld.long 0x00 24. " CLKSEL ,Select the source of the functional clock - . - ." "SYS_CLK,32_KHz" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x30++0x3 line.long 0x00 "CM_L4PER_GPTIMER11_CLKCTRL,This register manages the DMTIMER11 clocks." bitfld.long 0x00 24. " CLKSEL ,Select the source of the functional clock - . - ." "SYS_CLK,32_KHz" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x38++0x3 line.long 0x00 "CM_L4PER_GPTIMER2_CLKCTRL,This register manages the DMTIMER2 clocks." bitfld.long 0x00 24. " CLKSEL ,Select the source of the functional clock - . - ." "SYS_CLK,32_KHz" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x40++0x3 line.long 0x00 "CM_L4PER_GPTIMER3_CLKCTRL,This register manages the DMTIMER3 clocks." bitfld.long 0x00 24. " CLKSEL ,Select the source of the functional clock - . - ." "SYS_CLK,32_KHz" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x48++0x3 line.long 0x00 "CM_L4PER_GPTIMER4_CLKCTRL,This register manages the DMTIMER4 clocks." bitfld.long 0x00 24. " CLKSEL ,Select the source of the functional clock - . - ." "SYS_CLK,32_KHz" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x50++0x3 line.long 0x00 "CM_L4PER_GPTIMER9_CLKCTRL,This register manages the DMTIMER9 clocks." bitfld.long 0x00 24. " CLKSEL ,Select the source of the functional clock - . - ." "SYS_CLK,32_KHz" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." rgroup.long 0x58++0x3 line.long 0x00 "CM_L4PER_ELM_CLKCTRL,This register manages the ELM clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0x60++0x3 line.long 0x00 "CM_L4PER_GPIO2_CLKCTRL,This register manages the GPIO2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x68++0x3 line.long 0x00 "CM_L4PER_GPIO3_CLKCTRL,This register manages the GPIO3 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x70++0x3 line.long 0x00 "CM_L4PER_GPIO4_CLKCTRL,This register manages the GPIO4 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x78++0x3 line.long 0x00 "CM_L4PER_GPIO5_CLKCTRL,This register manages the GPIO5 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x80++0x3 line.long 0x00 "CM_L4PER_GPIO6_CLKCTRL,This register manages the GPIO6 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x88++0x3 line.long 0x00 "CM_L4PER_HDQ1W_CLKCTRL,This register manages the HDQ1W clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0xA0++0x3 line.long 0x00 "CM_L4PER_I2C1_CLKCTRL,This register manages the I2C1 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0xA8++0x3 line.long 0x00 "CM_L4PER_I2C2_CLKCTRL,This register manages the I2C2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0xB0++0x3 line.long 0x00 "CM_L4PER_I2C3_CLKCTRL,This register manages the I2C3 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0xB8++0x3 line.long 0x00 "CM_L4PER_I2C4_CLKCTRL,This register manages the I2C4 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." rgroup.long 0xC0++0x3 line.long 0x00 "CM_L4PER_L4PER_CLKCTRL,This register manages the L4PER clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0xE0++0x3 line.long 0x00 "CM_L4PER_MCBSP4_CLKCTRL,This register manages the MCBSP4 clocks." bitfld.long 0x00 25. " CLKSEL_INTERNAL_SOURCE ,Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source. - . - ." "96_MHz,98_MHz" bitfld.long 0x00 24. " CLKSEL_SOURCE ,Selects the source of the functional clock between, internal source and CLKS pad. The switching between the clocks is not guaranteed to be glitchless. - . - ." "Internal,CLKS" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0xF0++0x3 line.long 0x00 "CM_L4PER_MCSPI1_CLKCTRL,This register manages the MCSPI1 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0xF8++0x3 line.long 0x00 "CM_L4PER_MCSPI2_CLKCTRL,This register manages the MCSPI2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x100++0x3 line.long 0x00 "CM_L4PER_MCSPI3_CLKCTRL,This register manages the MCSPI3 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x108++0x3 line.long 0x00 "CM_L4PER_MCSPI4_CLKCTRL,This register manages the MCSPI4 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x120++0x3 line.long 0x00 "CM_L4PER_MMCSD3_CLKCTRL,This register manages the MMCSD3 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x128++0x3 line.long 0x00 "CM_L4PER_MMCSD4_CLKCTRL,This register manages the MMCSD4 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x138++0x3 line.long 0x00 "CM_L4PER_SLIMBUS2_CLKCTRL,This register manages the SLIMBUS2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 10. " OPTFCLKEN_SLIMBUS_CLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " OPTFCLKEN_PERABE24M_FCLK ,Optional functional clock control for PER_ABE_24M_FCLK clock. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 8. " OPTFCLKEN_PER24MC_FCLK ,Optional functional clock control for PER_24MC_FCLK clock. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x140++0x3 line.long 0x00 "CM_L4PER_UART1_CLKCTRL,This register manages the UART1 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x148++0x3 line.long 0x00 "CM_L4PER_UART2_CLKCTRL,This register manages the UART2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x150++0x3 line.long 0x00 "CM_L4PER_UART3_CLKCTRL,This register manages the UART3 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x158++0x3 line.long 0x00 "CM_L4PER_UART4_CLKCTRL,This register manages the UART4 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x160++0x3 line.long 0x00 "CM_L4PER_MMCSD5_CLKCTRL,This register manages the MMCSD5 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x180++0x3 line.long 0x00 "CM_L4SEC_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware-supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds one status bit per clock input of the domain." bitfld.long 0x00 9. " CLKACTIVITY_L4_SECURE_GICLK ,This field indicates the state of the L4_SECURE_GICLK clock in the domain. - . - ." "0,1" bitfld.long 0x00 8. " CLKACTIVITY_L3_SECURE_GICLK ,This field indicates the state of the L3_SECURE_GICLK clock in the domain. - . - ." "0,1" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4SEC clock domain. - . - . - . - ." "0,1,2,3" group.long 0x184++0x3 line.long 0x00 "CM_L4SEC_STATICDEP,This register controls the static domain dependencies from L4SEC domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" textline " " bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" rgroup.long 0x188++0x3 line.long 0x00 "CM_L4SEC_DYNAMICDEP,This register controls the dynamic domain dependencies from L4SEC domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "Dependency_is_disabled,1" group.long 0x1A0++0x3 line.long 0x00 "CM_L4SEC_AES1_CLKCTRL,This register manages the AES1 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,Reserved,2,?..." group.long 0x1A8++0x3 line.long 0x00 "CM_L4SEC_AES2_CLKCTRL,This register manages the AES2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,Reserved,2,?..." group.long 0x1B0++0x3 line.long 0x00 "CM_L4SEC_DES3DES_CLKCTRL,This register manages the DES3DES clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,Reserved,2,?..." group.long 0x1B8++0x3 line.long 0x00 "CM_L4SEC_PKA_CLKCTRL,This register manages the PKA clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,Reserved,2,?..." group.long 0x1C0++0x3 line.long 0x00 "CM_L4SEC_RNG_CLKCTRL,This register manages the RNG clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,1,?..." group.long 0x1C8++0x3 line.long 0x00 "CM_L4SEC_SHA2MD5_CLKCTRL,This register manages the SHA2MD5 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,Reserved,2,?..." tree.end tree "L3INIT_CM2" base ad:0x4A009300 width 29. group.long 0x0++0x3 line.long 0x00 "CM_L3INIT_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 29. " CLKACTIVITY_INIT_60M_P2_FCLK ,This field indicates the state of the INIT_60M_P2_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 28. " CLKACTIVITY_INIT_60M_P1_FCLK ,This field indicates the state of the INIT_60M_P1_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 27. " CLKACTIVITY_HSIC_P2_FCLK ,This field indicates the state of the HSIC_P2_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 26. " CLKACTIVITY_HSIC_P1_FCLK ,This field indicates the state of the HSIC_P1_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 25. " CLKACTIVITY_UTMI_ROOT_FCLK ,This field indicates the state of the UTMI_ROOT_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 23. " CLKACTIVITY_TLL_CH1_FCLK ,This field indicates the state of the TLL_CH1_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 22. " CLKACTIVITY_TLL_CH0_FCLK ,This field indicates the state of the TLL_CH0_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 21. " CLKACTIVITY_HSIC_P2_480M_FCLK ,This field indicates the state of the HSIC_P2_480M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 20. " CLKACTIVITY_HSIC_P1_480M_FCLK ,This field indicates the state of the HSIC_P1_480M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 18. " CLKACTIVITY_INIT_HSMMC2_FCLK ,This field indicates the state of the INIT_HSMMC2_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 17. " CLKACTIVITY_INIT_HSMMC1_FCLK ,This field indicates the state of the INIT_HSMMC1_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 16. " CLKACTIVITY_INIT_HSI_FCLK ,This field indicates the state of the INIT_HSI_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 15. " CLKACTIVITY_USB_DPLL_HS_CLK ,This field indicates the state of the USB_DPLL_HS_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 14. " CLKACTIVITY_USB_DPLL_CLK ,This field indicates the state of the USB_DPLL_CLK clock in the domain. [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 13. " CLKACTIVITY_INIT_48MC_FCLK ,This field indicates the state of the INIT_48MC_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 12. " CLKACTIVITY_INIT_48M_FCLK ,This field indicates the state of the INIT_48M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 9. " CLKACTIVITY_INIT_L4_ICLK ,This field indicates the state of the L4_INIT_ICLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 8. " CLKACTIVITY_INIT_L3_ICLK ,This field indicates the state of the L3_INIT_ICLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3INIT clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x4++0x3 line.long 0x00 "CM_L3INIT_STATICDEP,This register controls the static domain dependencies from L3INIT domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 15. " L4WKUP_STATDEP ,Static dependency towards L4WKUP clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - ." "0,Enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - ." "0,Enabled" textline " " bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 3. " ABE_STATDEP ,Static dependency towards ABE clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Disabled,Enabled" rgroup.long 0x8++0x3 line.long 0x00 "CM_L3INIT_DYNAMICDEP,This register controls the dynamic domain depedencies from L3INIT domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "Disabled,1" bitfld.long 0x00 5. " L3_1_DYNDEP ,Dynamic dependency towards L3_1 clock domain - ." "Disabled,1" group.long 0x28++0x3 line.long 0x00 "CM_L3INIT_HSMMC1_CLKCTRL,This register manages the MMC1 clocks." bitfld.long 0x00 24. " CLKSEL ,Selects the source of the functional clock. - . - ." "64_MHz,96_MHz" bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x30++0x3 line.long 0x00 "CM_L3INIT_HSMMC2_CLKCTRL,This register manages the MMC2 clocks." bitfld.long 0x00 24. " CLKSEL ,Selects the source of the functional clock. - . - ." "64_MHz,96_MHz" bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x38++0x3 line.long 0x00 "CM_L3INIT_HSI_CLKCTRL,This register manages the HSI clocks." bitfld.long 0x00 24.--25. " CLKSEL ,Selects the functional clock source. - . - . - . - ." "/1,/2,/4,?..." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . Read 0x: Reserved. - . - ." "Disabled,Reserved,2,?..." group.long 0x58++0x3 line.long 0x00 "CM_L3INIT_HSUSBHOST_CLKCTRL,This register manages the USB_HOST_HS clocks." bitfld.long 0x00 25. " CLKSEL_UTMI_P2 ,Selects the source of the functional clock for UTMI Port2 on USB Host - . - ." "Internal,External" bitfld.long 0x00 24. " CLKSEL_UTMI_P1 ,Selects the source of the functional clock for UTMI Por1 on USB Host - . - ." "Internal,External" bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" textline " " bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 15. " OPTFCLKEN_FUNC48MCLK ,USB-HOST optional clock control: FUNC48MCLK - . - ." "Disabled,Enabled" bitfld.long 0x00 14. " OPTFCLKEN_HSIC480M_P2_CLK ,USB-HOST optional clock control: HSIC480M_P2_CLK - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 13. " OPTFCLKEN_HSIC480M_P1_CLK ,USB-HOST optional clock control: HSIC480M_P1_CLK - . - ." "Disabled,Enabled" bitfld.long 0x00 12. " OPTFCLKEN_HSIC60M_P2_CLK ,USB-HOST optional clock control: HSIC60M_P2_CLK - . - ." "Disabled,Enabled" bitfld.long 0x00 11. " OPTFCLKEN_HSIC60M_P1_CLK ,USB-HOST optional clock control: HSIC60M_P1_CLK - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OPTFCLKEN_UTMI_P3_CLK ,USB-HOST optional clock control: UTMI_P3_CLK - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " OPTFCLKEN_UTMI_P2_CLK ,USB-HOST optional clock control: UTMI_P2_CLK when CLKSEL_UTMI_P2 is 0 - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " OPTFCLKEN_UTMI_P1_CLK ,USB-HOST optional clock control: UTMI_P1_CLK when CLKSEL_UTMI_P1 is 0 - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SAR_MODE ,SAR mode control for the module. Shall not be modify except if module is disabled. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x60++0x3 line.long 0x00 "CM_L3INIT_HSUSBOTG_CLKCTRL,This register manages the USB_OTG_HS clocks." bitfld.long 0x00 24. " CLKSEL_60M ,Selects the source of the 60MHz functional clock. - . - ." "0,1" bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 8. " OPTFCLKEN_XCLK ,USB_OTG optional clock control: XCLK (60MHz clock) - . - ." "0,1" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,1,?..." group.long 0x68++0x3 line.long 0x00 "CM_L3INIT_HSUSBTLL_CLKCTRL,This register manages the USB_TLL clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 9. " OPTFCLKEN_USB_CH1_CLK ,USB-HOST optional clock control: USB_CH1_CLK - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " OPTFCLKEN_USB_CH0_CLK ,USB-HOST optional clock control: USB_CH0_CLK - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SAR_MODE ,SAR mode control for the module. Shall not be modify except if module is disabled. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0xD0++0x3 line.long 0x00 "CM_L3INIT_FSUSB_CLKCTRL,This register manages the USB_HOST_FS clocks." bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0xE0++0x3 line.long 0x00 "CM_L3INIT_USBPHY_CLKCTRL,This register manages the USBPHY clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_PHY_48M ,USBPHY optional clock control: PHY_48M - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." tree.end tree "ALWAYS_ON_CM2" base ad:0x4A008600 width 26. group.long 0x0++0x3 line.long 0x00 "CM_ALWON_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 12. " CLKACTIVITY_CORE_ALWON_32K_GFCLK ,This field indicates the state of the CORE_ALWON_32K_GFCLK clock in the domain. [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 11. " CLKACTIVITY_SR_CORE_SYSCLK ,This field indicates the state of the SR_CORE_SYSCLK clock input of the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 10. " CLKACTIVITY_SR_IVA_SYSCLK ,This field indicates the state of the SR_IVA_SYSCLK clock input of the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 9. " CLKACTIVITY_SR_MPU_SYSCLK ,This field indicates the state of the SR_MPU_SYSCLK clock input of the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 8. " CLKACTIVITY_L4_AO_ICLK ,This field indicates the state of the L4_AO_ICLK clock of the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the ALWONCORE clock domain. - . - . - . - ." "NO_SLEEP,Reserved,SW_WKUP,HW_AUTO" group.long 0x28++0x3 line.long 0x00 "CM_ALWON_SR_MPU_CLKCTRL,This register manages the SR_MPU clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x30++0x3 line.long 0x00 "CM_ALWON_SR_IVA_CLKCTRL,This register manages the SR_IVA clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x38++0x3 line.long 0x00 "CM_ALWON_SR_CORE_CLKCTRL,This register manages the SR_CORE clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x40++0x3 line.long 0x00 "CM_ALWON_USBPHY_CLKCTRL,This register manages the USB PHY 32KHz clock." bitfld.long 0x00 8. " OPTFCLKEN_CLK32K ,Optional functional clock control. - . - ." "0,1" tree.end tree "EMU_PRM" base ad:0x4A307900 width 24. rgroup.long 0x0++0x3 line.long 0x00 "PM_EMU_PWRSTCTRL,This register controls the EMU power state to reach upon a domain sleep transition" bitfld.long 0x00 16.--17. " EMU_BANK_ONSTATE ,EMU memory state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - ." "Off,1,2,3" rgroup.long 0x4++0x3 line.long 0x00 "PM_EMU_PWRSTST,This register provides a status on the EMU domain current power state. [warm reset insensitive]" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 4.--5. " EMU_BANK_STATEST ,EMU memory bank state status - . - . - . - ." "Off,Reserved,Reserved,On" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" textline " " bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - ." "Off,1,2,On-Active" group.long 0x24++0x3 line.long 0x00 "RM_EMU_DEBUGSS_CONTEXT,This register contains dedicated DEBUGSS context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_EMU_BANK ,Specify if memory-based context in EMU_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of EMU_RST signal) - . - ." "Maintained,Lost" tree.end tree "DSP_PRM" base ad:0x4A306400 width 20. group.long 0x0++0x3 line.long 0x00 "PM_DSP_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" bitfld.long 0x00 20.--21. " DSP_EDMA_ONSTATE ,DSP_EDMA state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 18.--19. " DSP_L2_ONSTATE ,DSP_L2 state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 16.--17. " DSP_L1_ONSTATE ,DSP_L1 state when domain is ON. - ." "0,1,2,On" textline " " bitfld.long 0x00 10. " DSP_EDMA_RETSTATE ,DSP_EDMA state when domain is RETENTION. - ." "0,Retained" bitfld.long 0x00 9. " DSP_L2_RETSTATE ,DSP_L2 state when domain is RETENTION. - . - ." "Off,Retained" bitfld.long 0x00 8. " DSP_L1_RETSTATE ,DSP_L2 state when domain is RETENTION. - . - ." "Off,Retained" textline " " bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION - . - ." "Off,Retained" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "Off,Retention,Inactive,On" group.long 0x4++0x3 line.long 0x00 "PM_DSP_PWRSTST,This register provides a status on the DSP domain current power state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 8.--9. " DSP_EDMA_STATEST ,DSP_EDMA memory state status - . - . - . - ." "Off,Retention,Reserved,On" textline " " bitfld.long 0x00 6.--7. " DSP_L2_STATEST ,DSP_L2 memory state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 4.--5. " DSP_L1_STATEST ,DSP_L1 memory state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" textline " " bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Off,Retention,On-Inactive,On-Active" group.long 0x10++0x3 line.long 0x00 "RM_DSP_RSTCTRL,This register controls the release of the DSP sub-system resets." bitfld.long 0x00 1. " RST2 ,DSP - MMU, cache and slave interface reset control - . - ." "Cleared,Reset" bitfld.long 0x00 0. " RST1 ,DSP - DSP reset control - . - ." "Cleared,Reset" group.long 0x14++0x3 line.long 0x00 "RM_DSP_RSTST,This register logs the different reset sources of the DSP domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" eventfld.long 0x00 3. " DSP_DSP_EMU_REQ_RSTST ,DSP DSP processor has been reset due to DSP emulation reset request driven from DSPSS - . - ." "No_reset,Reset" eventfld.long 0x00 2. " DSPSS_EMU_RSTST ,DSP domain has been reset due to emulation reset source, that is, assert reset command initiated by the icepick module - . - ." "No_reset,Reset" eventfld.long 0x00 1. " RST2ST ,DSP MMU, cache and slave interface software reset status - . - ." "No_reset,Reset" textline " " eventfld.long 0x00 0. " RST1ST ,DSP DSP software reset - . - ." "No_reset,Reset" group.long 0x24++0x3 line.long 0x00 "RM_DSP_DSP_CONTEXT,This register contains dedicated DSP context statuses. [warm reset insensitive]" eventfld.long 0x00 10. " LOSTMEM_DSP_EDMA ,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 9. " LOSTMEM_DSP_L2 ,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 8. " LOSTMEM_DSP_L1 ,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" textline " " eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSP_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSP_SYS_RST signal) - . - ." "Maintained,Lost" tree.end tree "L4PER_PRM" base ad:0x4A307400 width 28. group.long 0x0++0x3 line.long 0x00 "PM_L4PER_PWRSTCTRL,This register controls the L4PER power state to reach upon a domain sleep transition" bitfld.long 0x00 18.--19. " NONRETAINED_BANK_ONSTATE ,NONRETAINED_BANK state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 16.--17. " RETAINED_BANK_ONSTATE ,RETAINED_BANK state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 9. " NONRETAINED_BANK_RETSTATE ,NONRETAINED_BANK state when domain is RETENTION. - ." "Off,1" textline " " bitfld.long 0x00 8. " RETAINED_BANK_RETSTATE ,RETAINED_BANK state when domain is RETENTION. - ." "0,Retained" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION - . - ." "Off,Retained" textline " " bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "Off,Retention,Inactive,On" group.long 0x4++0x3 line.long 0x00 "PM_L4PER_PWRSTST,This register provides a status on the current L4PER power domain state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 6.--7. " NONRETAINED_BANK_STATEST ,NONRETAINED_BANK state status - . - . - . - ." "Off,Reserved,Reserved,On" textline " " bitfld.long 0x00 4.--5. " RETAINED_BANK_STATEST ,RETAINED_BANK state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Off,Retention,On-Inactive,On-Active" rgroup.long 0x28++0x3 line.long 0x00 "PM_L4PER_GPTIMER10_WKDEP,This register controls wakeup dependency based on DMTIMER10 service requests." bitfld.long 0x00 0. " WKUPDEP_DMTIMER10_MPU ,Wakeup dependency from DMTIMER10 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - ." "0,Enabled" group.long 0x2C++0x3 line.long 0x00 "RM_L4PER_GPTIMER10_CONTEXT,This register contains dedicated DMTIMER10 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x30++0x3 line.long 0x00 "PM_L4PER_GPTIMER11_WKDEP,This register controls wakeup dependency based on DMTIMER11 service requests." bitfld.long 0x00 1. " WKUPDEP_DMTIMER11_MPU_M3 ,Wakeup dependency from DMTIMER11 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_DMTIMER11_MPU ,Wakeup dependency from DMTIMER11 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x34++0x3 line.long 0x00 "RM_L4PER_GPTIMER11_CONTEXT,This register contains dedicated DMTIMER11 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" rgroup.long 0x38++0x3 line.long 0x00 "PM_L4PER_GPTIMER2_WKDEP,This register controls wakeup dependency based on DMTIMER2 service requests." bitfld.long 0x00 0. " WKUPDEP_DMTIMER2_MPU ,Wakeup dependency from DMTIMER2 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - ." "0,Enabled" group.long 0x3C++0x3 line.long 0x00 "RM_L4PER_GPTIMER2_CONTEXT,This register contains dedicated DMTIMER2 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x40++0x3 line.long 0x00 "PM_L4PER_GPTIMER3_WKDEP,This register controls wakeup dependency based on DMTIMER3 service requests." bitfld.long 0x00 1. " WKUPDEP_DMTIMER3_MPU_M3 ,Wakeup dependency from DMTIMER3 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_DMTIMER3_MPU ,Wakeup dependency from DMTIMER3 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x44++0x3 line.long 0x00 "RM_L4PER_GPTIMER3_CONTEXT,This register contains dedicated DMTIMER3 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x48++0x3 line.long 0x00 "PM_L4PER_GPTIMER4_WKDEP,This register controls wakeup dependency based on DMTIMER4 service requests." bitfld.long 0x00 1. " WKUPDEP_DMTIMER4_MPU_M3 ,Wakeup dependency from DMTIMER4 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_DMTIMER4_MPU ,Wakeup dependency from DMTIMER4 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x4C++0x3 line.long 0x00 "RM_L4PER_GPTIMER4_CONTEXT,This register contains dedicated DMTIMER4 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x50++0x3 line.long 0x00 "PM_L4PER_GPTIMER9_WKDEP,This register controls wakeup dependency based on DMTIMER9 service requests." bitfld.long 0x00 1. " WKUPDEP_DMTIMER9_MPU_M3 ,Wakeup dependency from DMTIMER9 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_DMTIMER9_MPU ,Wakeup dependency from DMTIMER9 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x54++0x3 line.long 0x00 "RM_L4PER_GPTIMER9_CONTEXT,This register contains dedicated DMTIMER9 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x5C++0x3 line.long 0x00 "RM_L4PER_ELM_CONTEXT,This register contains dedicated ELM context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x60++0x3 line.long 0x00 "PM_L4PER_GPIO2_WKDEP,This register controls wakeup dependency based on GPIO2 service requests." bitfld.long 0x00 6. " WKUPDEP_GPIO2_IRQ2_DSP ,Wakeup dependency from GPIO2 module (POINTRsoftwareAKEUP2 signal) towards DSP + L3_1 + L3_2 domains - ." "0,Enabled" bitfld.long 0x00 1. " WKUPDEP_GPIO2_IRQ1_MPU_M3 ,Wakeup dependency from GPIO2 module (POINTRsoftwareAKEUP1 signal) module towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_GPIO2_IRQ1_MPU ,Wakeup dependency from GPIO2 module (POINTRsoftwareAKEUP1 signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x64++0x3 line.long 0x00 "RM_L4PER_GPIO2_CONTEXT,This register contains dedicated GPIO2 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x68++0x3 line.long 0x00 "PM_L4PER_GPIO3_WKDEP,This register controls wakeup dependency based on GPIO3 service requests." bitfld.long 0x00 6. " WKUPDEP_GPIO3_IRQ2_DSP ,Wakeup dependency from GPIO3 module (POINTRsoftwareAKEUP2 signal) towards DSP + L3_1 + L3_2 domains - ." "0,Enabled" bitfld.long 0x00 0. " WKUPDEP_GPIO3_IRQ1_MPU ,Wakeup dependency from GPIO3 module (POINTRsoftwareAKEUP1 signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x6C++0x3 line.long 0x00 "RM_L4PER_GPIO3_CONTEXT,This register contains dedicated GPIO3 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x70++0x3 line.long 0x00 "PM_L4PER_GPIO4_WKDEP,This register controls wakeup dependency based on GPIO4 service requests." bitfld.long 0x00 6. " WKUPDEP_GPIO4_IRQ2_DSP ,Wakeup dependency from GPIO4 module (POINTRsoftwareAKEUP2 signal) towards DSP + L3_1 + L3_2 domains - ." "0,Enabled" bitfld.long 0x00 0. " WKUPDEP_GPIO4_IRQ1_MPU ,Wakeup dependency from GPIO4 module (POINTRsoftwareAKEUP1 signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x74++0x3 line.long 0x00 "RM_L4PER_GPIO4_CONTEXT,This register contains dedicated GPIO4 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" rgroup.long 0x78++0x3 line.long 0x00 "PM_L4PER_GPIO5_WKDEP,This register controls wakeup dependency based on GPIO5 service requests." bitfld.long 0x00 6. " WKUPDEP_GPIO5_IRQ2_DSP ,Wakeup dependency from GPIO5 module (POINTRsoftwareAKEUP2 signal) towards DSP + L3_1 + L3_2 domains - ." "0,Enabled" bitfld.long 0x00 0. " WKUPDEP_GPIO5_IRQ1_MPU ,Wakeup dependency from GPIO5 module (POINTRsoftwareAKEUP1 signal) towards MPU + L3_1 + L3_2 domains - ." "0,Enabled" group.long 0x7C++0x3 line.long 0x00 "RM_L4PER_GPIO5_CONTEXT,This register contains dedicated GPIO5 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" rgroup.long 0x80++0x3 line.long 0x00 "PM_L4PER_GPIO6_WKDEP,This register controls wakeup dependency based on GPIO6 service requests." bitfld.long 0x00 6. " WKUPDEP_GPIO6_IRQ2_DSP ,Wakeup dependency from GPIO6 module (POINTRsoftwareAKEUP2 signal) towards DSP + L3_1 + L3_2 domains - ." "0,Enabled" bitfld.long 0x00 0. " WKUPDEP_GPIO6_IRQ1_MPU ,Wakeup dependency from GPIO6 module (POINTRsoftwareAKEUP1 signal) towards MPU + L3_1 + L3_2 domains - ." "0,Enabled" group.long 0x84++0x3 line.long 0x00 "RM_L4PER_GPIO6_CONTEXT,This register contains dedicated GPIO6 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x8C++0x3 line.long 0x00 "RM_L4PER_HDQ1W_CONTEXT,This register contains dedicated HDQ1W context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0xA0++0x3 line.long 0x00 "PM_L4PER_I2C1_WKDEP,This register controls wakeup dependency based on I2C1 service requests." bitfld.long 0x00 7. " WKUPDEP_I2C1_DMA_SDMA ,Wakeup dependency from I2C1 module (softwareakeup_dma signal) towards SDMA + L3_2 domains - ." "0,Enabled" bitfld.long 0x00 1. " WKUPDEP_I2C1_IRQ_MPU_M3 ,Wakeup dependency from I2C1 module (softwareakeup_irq signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_I2C1_IRQ_MPU ,Wakeup dependency from I2C1 module (softwareakeup_irq signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0xA4++0x3 line.long 0x00 "RM_L4PER_I2C1_CONTEXT,This register contains dedicated I2C1 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" group.long 0xA8++0x3 line.long 0x00 "PM_L4PER_I2C2_WKDEP,This register controls wakeup dependency based on I2C2 service requests." bitfld.long 0x00 7. " WKUPDEP_I2C2_DMA_SDMA ,Wakeup dependency from I2C2 module (softwareakeup_dma signal) towards SDMA + L3_2 domains - ." "0,Enabled" bitfld.long 0x00 1. " WKUPDEP_I2C2_IRQ_MPU_M3 ,Wakeup dependency from I2C2 module (softwareakeup_irq signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_I2C2_IRQ_MPU ,Wakeup dependency from I2C2 module (softwareakeup_irq signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0xAC++0x3 line.long 0x00 "RM_L4PER_I2C2_CONTEXT,This register contains dedicated I2C2 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0xB0++0x3 line.long 0x00 "PM_L4PER_I2C3_WKDEP,This register controls wakeup dependency based on I2C3 service requests." bitfld.long 0x00 7. " WKUPDEP_I2C3_DMA_SDMA ,Wakeup dependency from I2C3 module (softwareakeup_dma signal) towards SDMA + L3_2 domains - ." "0,Enabled" bitfld.long 0x00 1. " WKUPDEP_I2C3_IRQ_MPU_M3 ,Wakeup dependency from I2C3 module (softwareakeup_irq signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_I2C3_IRQ_MPU ,Wakeup dependency from I2C3 module (softwareakeup_irq signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0xB4++0x3 line.long 0x00 "RM_L4PER_I2C3_CONTEXT,This register contains dedicated I2C3 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0xB8++0x3 line.long 0x00 "PM_L4PER_I2C4_WKDEP,This register controls wakeup dependency based on I2C4 service requests." bitfld.long 0x00 7. " WKUPDEP_I2C4_DMA_SDMA ,Wakeup dependency from I2C4 module (softwareakeup_dma signal) towards SDMA + L3_2 domains - ." "0,Enabled" bitfld.long 0x00 1. " WKUPDEP_I2C4_IRQ_MPU_M3 ,Wakeup dependency from I2C4 module (softwareakeup_irq signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_I2C4_IRQ_MPU ,Wakeup dependency from I2C4 module (softwareakeup_irq signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0xBC++0x3 line.long 0x00 "RM_L4PER_I2C4_CONTEXT,This register contains dedicated I2C4 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0xC0++0x3 line.long 0x00 "RM_L4PER_L4_PER_CONTEXT,This register contains dedicated L4_PER context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_PWRON_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0xE0++0x3 line.long 0x00 "PM_L4PER_MCBSP4_WKDEP,This register controls wakeup dependency based on MCBSP4 service requests." bitfld.long 0x00 3. " WKUPDEP_MCBSP4_SDMA ,Wakeup dependency from MCBSP4 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_MCBSP4_DSP ,Wakeup dependency from MCBSP4 module (softwareakeup signal) towards DSP + L3_1 + L3_2 domain - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MCBSP4_MPU ,Wakeup dependency from MCBSP4 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domain - . - ." "Disabled,Enabled" group.long 0xE4++0x3 line.long 0x00 "RM_L4PER_MCBSP4_CONTEXT,This register contains dedicated MCBSP4 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_NONRETAINED_BANK ,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0xF0++0x3 line.long 0x00 "PM_L4PER_MCSPI1_WKDEP,This register controls wakeup dependency based on MCSPI1 service requests." bitfld.long 0x00 3. " WKUPDEP_MCSPI1_SDMA ,Wakeup dependency from MCSPI1 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_MCSPI1_DSP ,Wakeup dependency from MCSPI1 module (softwareakeup signal) towards DSP + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " WKUPDEP_MCSPI1_MPU_M3 ,Wakeup dependency from MCSPI1 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_MCSPI1_MPU ,Wakeup dependency from MCSPI1 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0xF4++0x3 line.long 0x00 "RM_L4PER_MCSPI1_CONTEXT,This register contains dedicated MCSPI1 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0xF8++0x3 line.long 0x00 "PM_L4PER_MCSPI2_WKDEP,This register controls wakeup dependency based on MCSPI2 service requests." bitfld.long 0x00 3. " WKUPDEP_MCSPI2_SDMA ,Wakeup dependency from MCSPI2 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " WKUPDEP_MCSPI2_MPU_M3 ,Wakeup dependency from MCSPI2 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MCSPI2_MPU ,Wakeup dependency from MCSPI2 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0xFC++0x3 line.long 0x00 "RM_L4PER_MCSPI2_CONTEXT,This register contains dedicated MCSPI2 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x100++0x3 line.long 0x00 "PM_L4PER_MCSPI3_WKDEP,This register controls wakeup dependency based on MCSPI3 service requests." bitfld.long 0x00 3. " WKUPDEP_MCSPI3_SDMA ,Wakeup dependency from MCSPI3 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MCSPI3_MPU ,Wakeup dependency from MCSPI3 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x104++0x3 line.long 0x00 "RM_L4PER_MCSPI3_CONTEXT,This register contains dedicated MCSPI3 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x108++0x3 line.long 0x00 "PM_L4PER_MCSPI4_WKDEP,This register controls wakeup dependency based on MCSPI4 service requests." bitfld.long 0x00 3. " WKUPDEP_MCSPI4_SDMA ,Wakeup dependency from MCSPI4 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MCSPI4_MPU ,Wakeup dependency from MCSPI4 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x10C++0x3 line.long 0x00 "RM_L4PER_MCSPI4_CONTEXT,This register contains dedicated MCSPI4 context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x120++0x3 line.long 0x00 "PM_L4PER_MMCSD3_WKDEP,This register controls wakeup dependency based on MMCSD3 service requests." bitfld.long 0x00 3. " WKUPDEP_MMCSD3_SDMA ,Wakeup dependency from MMCSD3 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " WKUPDEP_MMCSD3_MPU_M3 ,Wakeup dependency from MMCSD3 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MMCSD3_MPU ,Wakeup dependency from MMCSD3 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x124++0x3 line.long 0x00 "RM_L4PER_MMCSD3_CONTEXT,This register contains dedicated MMCSD3 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_NONRETAINED_BANK ,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x128++0x3 line.long 0x00 "PM_L4PER_MMCSD4_WKDEP,This register controls wakeup dependency based on MMCSD4 service requests." bitfld.long 0x00 3. " WKUPDEP_MMCSD4_SDMA ,Wakeup dependency from MMCSD4 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " WKUPDEP_MMCSD4_MPU_M3 ,Wakeup dependency from MMCSD4 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MMCSD4_MPU ,Wakeup dependency from MMCSD4 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x12C++0x3 line.long 0x00 "RM_L4PER_MMCSD4_CONTEXT,This register contains dedicated MMCSD4 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_NONRETAINED_BANK ,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x138++0x3 line.long 0x00 "PM_L4PER_SLIMBUS2_WKDEP,This register controls wakeup dependency based on SLIMBUS2 service requests." bitfld.long 0x00 7. " WKUPDEP_SLIMBUS2_DMA_SDMA ,Wakeup dependency from SLIMBUS2 module (softwareakeup_dma signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " WKUPDEP_SLIMBUS2_DMA_DSP ,Wakeup dependency from SLIMBUS2 module (softwareakeup_dma signal) towards DSP + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_SLIMBUS2_IRQ_DSP ,Wakeup dependency from SLIMBUS2 module (softwareakeup_irq signal) towards DSP + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_SLIMBUS2_IRQ_MPU ,Wakeup dependency from SLIMBUS2 module (softwareakeup_irq signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x13C++0x3 line.long 0x00 "RM_L4PER_SLIMBUS2_CONTEXT,This register contains dedicated SLIMBUS2 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_NONRETAINED_BANK ,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x140++0x3 line.long 0x00 "PM_L4PER_UART1_WKDEP,This register controls wakeup dependency based on UART1 service requests." bitfld.long 0x00 3. " WKUPDEP_UART1_SDMA ,Wakeup dependency from UART1 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_UART1_MPU ,Wakeup dependency from UART1 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x144++0x3 line.long 0x00 "RM_L4PER_UART1_CONTEXT,This register contains dedicated UART1 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x148++0x3 line.long 0x00 "PM_L4PER_UART2_WKDEP,This register controls wakeup dependency based on UART2 service requests." bitfld.long 0x00 3. " WKUPDEP_UART2_SDMA ,Wakeup dependency from UART2 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_UART2_MPU ,Wakeup dependency from UART2 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x14C++0x3 line.long 0x00 "RM_L4PER_UART2_CONTEXT,This register contains dedicated UART2 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x150++0x3 line.long 0x00 "PM_L4PER_UART3_WKDEP,This register controls wakeup dependency based on UART3 service requests." bitfld.long 0x00 3. " WKUPDEP_UART3_SDMA ,Wakeup dependency from UART3 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " WKUPDEP_UART3_DSP ,Wakeup dependency from UART3 module (softwareakeup signal) towards DSP + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " WKUPDEP_UART3_MPU_M3 ,Wakeup dependency from UART3 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " WKUPDEP_UART3_MPU ,Wakeup dependency from UART3 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x154++0x3 line.long 0x00 "RM_L4PER_UART3_CONTEXT,This register contains dedicated UART3 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x158++0x3 line.long 0x00 "PM_L4PER_UART4_WKDEP,This register controls wakeup dependency based on UART4 service requests." bitfld.long 0x00 3. " WKUPDEP_UART4_SDMA ,Wakeup dependency from UART4 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_UART4_MPU ,Wakeup dependency from UART4 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x15C++0x3 line.long 0x00 "RM_L4PER_UART4_CONTEXT,This register contains dedicated UART4 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x160++0x3 line.long 0x00 "PM_L4PER_MMCSD5_WKDEP,This register controls wakeup dependency based on MMCSD5 service requests." bitfld.long 0x00 3. " WKUPDEP_MMCSD5_SDMA ,Wakeup dependency from MMCSD5 module (softwareakeup signal) towards SDMA + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " WKUPDEP_MMCSD5_MPU_M3 ,Wakeup dependency from MMCSD5 module (softwareakeup signal) towards MPU_A3 + L3_2 domains - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " WKUPDEP_MMCSD5_MPU ,Wakeup dependency from MMCSD5 module (softwareakeup signal) towards MPU + L3_1 + L3_2 domains - . - ." "Disabled,Enabled" group.long 0x164++0x3 line.long 0x00 "RM_L4PER_MMCSD5_CONTEXT,This register contains dedicated MMCSD5 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_NONRETAINED_BANK ,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RST signal) - . - ." "Maintained,Lost" group.long 0x1A4++0x3 line.long 0x00 "RM_L4SEC_AES1_CONTEXT,This register contains dedicated AES1 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "0,1" group.long 0x1AC++0x3 line.long 0x00 "RM_L4SEC_AES2_CONTEXT,This register contains dedicated AES2 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "0,1" group.long 0x1B4++0x3 line.long 0x00 "RM_L4SEC_DES3DES_CONTEXT,This register contains dedicated DES3DES context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4_PER_RET_RST signal) - . - ." "0,1" group.long 0x1BC++0x3 line.long 0x00 "RM_L4SEC_PKA_CONTEXT,This register contains dedicated PKA context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_NONRETAINED_BANK ,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "0,1" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source (set upon assertion of L4_PER_RST signal). - . - ." "0,1" group.long 0x1C4++0x3 line.long 0x00 "RM_L4SEC_RNG_CONTEXT,This register contains dedicated RNG context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source (set upon assertion of L4_PER_RET_RST signal). - . - ." "0,1" group.long 0x1CC++0x3 line.long 0x00 "RM_L4SEC_SHA2MD5_CONTEXT,This register contains dedicated SHA2MD5 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source (set upon assertion of L4_PER_RET_RST signal). - . - ." "0,1" group.long 0x1DC++0x3 line.long 0x00 "RM_L4SEC_CRYPTODMA_CONTEXT,This register contains dedicated CRYPTODMA context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "0,1" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source (set upon assertion of L4_PER_RST signal). - . - ." "0,1" tree.end tree "IVAHD_PRM" base ad:0x4A306F00 width 24. group.long 0x0++0x3 line.long 0x00 "PM_IVAHD_PWRSTCTRL,This register controls the IVAHD power state to reach upon a domain sleep transition" bitfld.long 0x00 22.--23. " TCM2_MEM_ONSTATE ,TCM2 memory state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 20.--21. " TCM1_MEM_ONSTATE ,TCM1 memory state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 18.--19. " SL2_MEM_ONSTATE ,SL2 memory state when domain is ON. - ." "0,1,2,On" textline " " bitfld.long 0x00 16.--17. " HWA_MEM_ONSTATE ,HWA memory state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 11. " TCM2_MEM_RETSTATE ,TCM2 memory state when domain is RETENTION. - . - ." "Off,Retained" bitfld.long 0x00 10. " TCM1_MEM_RETSTATE ,TCM1 memory state when domain is RETENTION. - . - ." "Off,Retained" textline " " bitfld.long 0x00 9. " SL2_MEM_RETSTATE ,SL2 memory state when domain is RETENTION. - . - ." "Off,Retained" bitfld.long 0x00 8. " HWA_MEM_RETSTATE ,HWA memory state when domain is RETENTION. - ." "Off,1" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" textline " " bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION - ." "Off,1" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "Off,Retention,Inactive,On" group.long 0x4++0x3 line.long 0x00 "PM_IVAHD_PWRSTST,This register provides a status on the current IVAHD power domain state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 10.--11. " TCM2_MEM_STATEST ,TCM2 memory state status - . - . - . - ." "Off,Retention,Reserved,On" textline " " bitfld.long 0x00 8.--9. " TCM1_MEM_STATEST ,TCM1 memory state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 6.--7. " SL2_MEM_STATEST ,SL2 memory state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 4.--5. " HWA_MEM_STATEST ,HWA memory state status - . - . - . - ." "Off,Retention,Reserved,On" textline " " bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Off,Retention,On-Inactive,On-Active" group.long 0x10++0x3 line.long 0x00 "RM_IVAHD_RSTCTRL,This register controls the release of the IVAHD sub-system resets." bitfld.long 0x00 2. " RST3 ,IVAHD logic and SL2 reset control - . - ." "Cleared,Reset" bitfld.long 0x00 1. " RST2 ,IVAHD Sequencer2 reset control - . - ." "Cleared,Reset" bitfld.long 0x00 0. " RST1 ,IVAHD sequencer1 reset control - . - ." "Cleared,Reset" group.long 0x14++0x3 line.long 0x00 "RM_IVAHD_RSTST,This register logs the different reset sources of the IVAHD domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" eventfld.long 0x00 6. " ICECRUSHER_SEQ2_RST2ST ,Sequencer2 CPU has been reset due to IVAHD ICECRUSHER2 reset event - . - ." "No_reset,Reset" eventfld.long 0x00 5. " ICECRUSHER_SEQ1_RST1ST ,Sequencer1 CPU has been reset due to IVAHD ICECRUSHER1 reset event - . - ." "No_reset,Reset" eventfld.long 0x00 4. " EMULATION_SEQ2_RST2ST ,- . - ." "No_reset,Reset" textline " " eventfld.long 0x00 3. " EMULATION_SEQ1_RST1ST ,Sequencer1 CPU has been reset due to emulation reset source, that is, assert reset command initiated by the icepick module - . - ." "No_reset,Reset" eventfld.long 0x00 2. " RST3ST ,IVAHD logic and SL2 software reset - . - ." "No_reset,Reset" eventfld.long 0x00 1. " RST2ST ,IVAHD Sequencer2 CPU software reset - . - ." "No_reset,Reset" textline " " eventfld.long 0x00 0. " RST1ST ,IVAHD Sequencer1 CPU software reset - . - ." "No_reset,Reset" group.long 0x24++0x3 line.long 0x00 "RM_IVAHD_IVAHD_CONTEXT,This register contains dedicated IVAHD context statuses. [warm reset insensitive]" eventfld.long 0x00 10. " LOSTMEM_HWA_MEM ,Specify if memory-based context in HWA_MEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 9. " LOSTMEM_TCM2_MEM ,Specify if memory-based context in TCM2_MEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 8. " LOSTMEM_TCM1_MEM ,Specify if memory-based context in TCM1_MEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" textline " " eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IVAHD_RST signal) - . - ." "Maintained,Lost" group.long 0x2C++0x3 line.long 0x00 "RM_IVAHD_SL2_CONTEXT,This register contains dedicated SL2 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_SL2_MEM ,Specify if memory-based context in SL2_MEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IVAHD_RST signal) - . - ." "Maintained,Lost" tree.end tree "SGX_PRM" base ad:0x4A307200 width 20. group.long 0x0++0x3 line.long 0x00 "PM_SGX_PWRSTCTRL,This register controls the SGX power state to reach upon a domain sleep transition" bitfld.long 0x00 16.--17. " SGX_MEM_ONSTATE ,SGX_MEM memory bank state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "Off,Reserved,Inactive,On" rgroup.long 0x4++0x3 line.long 0x00 "PM_SGX_PWRSTST,This register provides a status on the current SGX power domain state. [warm reset insensitive]" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 4.--5. " SGX_MEM_STATEST ,SGX_MEM memory bank state status - . - . - . - ." "Off,Reserved,Reserved,On" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" textline " " bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Off,Retention,On-Inactive,On-Active" group.long 0x24++0x3 line.long 0x00 "RM_SGX_SGX_CONTEXT,This register contains dedicated SGX context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_SGX_MEM ,Specify if memory-based context in SGX_MEM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of SGX_RST signal) - . - ." "Maintained,Lost" tree.end tree "MPU_PRM" base ad:0x4A306300 width 20. group.long 0x0++0x3 line.long 0x00 "PM_MPU_PWRSTCTRL,This register controls the MPU domain power state to reach upon a domain sleep transition" bitfld.long 0x00 20.--21. " MPU_RAM_ONSTATE ,MPU_RAM memory state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 18.--19. " MPU_L2_ONSTATE ,MPU_L2 memory state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 16.--17. " MPU_L1_ONSTATE ,MPU_L1 memory state when domain is ON. - ." "0,1,2,On" textline " " bitfld.long 0x00 10. " MPU_RAM_RETSTATE ,MPU_RAM memory state when domain is RETENTION. - ." "0,Retained" bitfld.long 0x00 9. " MPU_L2_RETSTATE ,MPU_L2 memory state when domain is RETENTION. - . - ." "Off,Retained" bitfld.long 0x00 8. " MPU_L1_RETSTATE ,MPU_L1 memory state when domain is RETENTION. Should always be same as LogicRETState bit field. - . - ." "Off,Retained" textline " " bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION - . - ." "Off,Retained" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control. - . - . - . - ." "Off,Retention,Inactive,On" group.long 0x4++0x3 line.long 0x00 "PM_MPU_PWRSTST,This register provides a status on the MPU domain current power state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 8.--9. " MPU_RAM_STATEST ,MPU_RAM memory state status - . - . - . - ." "Off,Retention,Reserved,On" textline " " bitfld.long 0x00 6.--7. " MPU_L2_STATEST ,MPU_L2 memory state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 4.--5. " MPU_L1_STATEST ,MPU_L1 memory state status - . - . - . - ." "Off,Reserved,Reserved,On" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" textline " " bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Off,Retention,On-Inactive,On-Active" group.long 0x14++0x3 line.long 0x00 "RM_MPU_RSTST,This register logs the different reset sources of the MPU domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" eventfld.long 0x00 0. " EMULATION_RST ,MPU domain has been reset due to emulation reset source, that is, assert reset command initiated by the icepick module - . - ." "No_reset,Reset" group.long 0x24++0x3 line.long 0x00 "RM_MPU_MPU_CONTEXT,This register contains dedicated MPU context statuses. [warm reset insensitive]" eventfld.long 0x00 10. " LOSTMEM_MPU_RAM ,Specify if memory-based context in MPU_RAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset). - . - ." "Maintained,Lost" eventfld.long 0x00 9. " LOSTMEM_MPU_L2 ,Specify if memory-based context in MPU_L2 memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 8. " LOSTMEM_MPU_L1 ,Specify if memory-based context in MPU_L1 memory bank has been lost due to a previous power transition or other reset source. Not applicable to Cortex-A9 SMP. - . - ." "Maintained,Lost" textline " " eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of MPU_RST signal) - . - ." "Maintained,Lost" tree.end tree "SGX_CM2" base ad:0x4A009200 width 20. group.long 0x0++0x3 line.long 0x00 "CM_SGX_CLKSTCTRL,This register enables the SGX domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 9. " CLKACTIVITY_SGX_FCLK ,This field indicates the state of the SGX_FCLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 8. " CLKACTIVITY_SGX_L3_ICLK ,This field indicates the state of the SGX_L3_ICLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the SGX clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x4++0x3 line.long 0x00 "CM_SGX_STATICDEP,This register controls the static domain depedencies from SGX domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - ." "0,Enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Disabled,Enabled" rgroup.long 0x8++0x3 line.long 0x00 "CM_SGX_DYNAMICDEP,This register controls the dynamic domain depedencies from SGX domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "Disabled,1" group.long 0x20++0x3 line.long 0x00 "CM_SGX_SGX_CLKCTRL,This register manages the SGX clocks." bitfld.long 0x00 24. " CLKSEL_SGX_FCLK ,Select the source of SGX_FCLK - . - ." "SEL_DPLL_CORE,SEL_PER_192M" bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." tree.end tree "WKUP_CM" base ad:0x4A307800 width 26. group.long 0x0++0x3 line.long 0x00 "CM_WKUP_CLKSTCTRL,This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 12. " CLKACTIVITY_L4_WKUP_ICLK ,This field indicates the state of the clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 11. " CLKACTIVITY_WKUP_32K_FCLK ,This field indicates the state of the clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 9. " CLKACTIVITY_ABE_LP_CLK ,This field indicates the state of the clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" textline " " bitfld.long 0x00 8. " CLKACTIVITY_SYS_CLK ,This field indicates the state of the SYS_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the WKUP clock domain. - . - . - . - ." "NO_SLEEP,Reserved,Reserved,HW_AUTO" rgroup.long 0x20++0x3 line.long 0x00 "CM_WKUP_L4WKUP_CLKCTRL,This register manages the L4WKUP clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0x30++0x3 line.long 0x00 "CM_WKUP_WDTIMER2_CLKCTRL,This register manages the WDT2 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x38++0x3 line.long 0x00 "CM_WKUP_GPIO1_CLKCTRL,This register manages the GPIO1 clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x40++0x3 line.long 0x00 "CM_WKUP_GPTIMER1_CLKCTRL,This register manages the TIMER1 clocks." bitfld.long 0x00 24. " CLKSEL ,Select the source of the functional clock - . - ." "SYS_CLK,32KHz" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." rgroup.long 0x50++0x3 line.long 0x00 "CM_WKUP_32KTIMER_CLKCTRL,This register manages the SYNCTIMER clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" rgroup.long 0x60++0x3 line.long 0x00 "CM_WKUP_SARRAM_CLKCTRL,This register manages the SARRAM clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - ." "0,AUTO,2,3" group.long 0x78++0x3 line.long 0x00 "CM_WKUP_KEYBOARD_CLKCTRL,This register manages the KEYBOARD clocks." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x88++0x3 line.long 0x00 "CM_WKUP_BANDGAP_CLKCTRL,This register manages the bandgap clock." bitfld.long 0x00 8. " OPTFCLKEN_BGAP_32K ,Optional functional clock control. - . - ." "Disabled,Enabled" tree.end tree "CORE_PRM" base ad:0x4A306700 width 29. group.long 0x0++0x3 line.long 0x00 "PM_CORE_PWRSTCTRL,This register controls the CORE power state to reach upon a domain sleep transition" bitfld.long 0x00 24.--25. " INTRCONN_NRET_BANK_ONSTATE ,INTRCONN_WP bank and DMM bank2 state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 22.--23. " MPU_M3_UNICACHE_ONSTATE ,MPU_A3 UNICACHE bank state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 20.--21. " MPU_M3_L2RAM_ONSTATE ,MPU_A3 L2 bank state when domain is ON. - ." "0,1,2,On" textline " " bitfld.long 0x00 18.--19. " CORE_OCMRAM_ONSTATE ,OCMRAM bank state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 16.--17. " CORE_OTHER_BANK_ONSTATE ,DMA/ICR bank and DMM bank1 state when domain is ON. - ." "0,1,2,On" bitfld.long 0x00 12. " INTRCONN_NRET_BANK_RETSTATE ,INTRCONN_WP bank and DMM bank2 state when domain is RETENTION. - ." "Off,1" textline " " bitfld.long 0x00 11. " MPU_M3_UNICACHE_RETSTATE ,MPU_A3 UNICACHE bank state when domain is RETENTION. - . - ." "Off,Retained" bitfld.long 0x00 10. " MPU_M3_L2RAM_RETSTATE ,MPU_A3 L2 bank state when domain is RETENTION. - . - ." "Off,Retained" bitfld.long 0x00 9. " CORE_OCMRAM_RETSTATE ,OCMRAM bank state when domain is RETENTION. - ." "0,Retained" textline " " bitfld.long 0x00 8. " CORE_OTHER_BANK_RETSTATE ,DMA/ICR bank and DMM bank1 state when domain is RETENTION. - ." "0,Retained" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain. - . - ." "Not_requested,Requested" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION - . - ." "Off,Retained" textline " " bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "Reserved,Retention,Inactive,On" group.long 0x4++0x3 line.long 0x00 "PM_CORE_PWRSTST,This register provides a status on the current CORE power domain state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "No,In_progress" bitfld.long 0x00 12.--13. " INTRCONN_NRET_BANK_STATEST ,INTRCONN_WP bank and DMM bank2 state status - . - . - . - ." "Off,Reserved,Reserved,On" textline " " bitfld.long 0x00 10.--11. " MPU_M3_UNICACHE_STATEST ,MPU_A3 UNICACHE bank state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 8.--9. " MPU_M3_L2RAM_STATEST ,MPU_A3 L2 bank state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 6.--7. " CORE_OCMRAM_STATEST ,OCMRAM bank state status - . - . - . - ." "Off,Retention,Reserved,On" textline " " bitfld.long 0x00 4.--5. " CORE_OTHER_BANK_STATEST ,DMA/ICR bank and DMM bank1 state status - . - . - . - ." "Off,Retention,Reserved,On" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "Off,On" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "Reserved,Retention,On-Inactive,On-Active" group.long 0x24++0x3 line.long 0x00 "RM_L3_1_L3_1_CONTEXT,This register contains dedicated L3_1 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x124++0x3 line.long 0x00 "RM_L3_2_L3_2_CONTEXT,This register contains dedicated L3_2 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x12C++0x3 line.long 0x00 "RM_L3_2_GPMC_CONTEXT,This register contains dedicated GPMC context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x134++0x3 line.long 0x00 "RM_L3_2_OCMC_RAM_CONTEXT,This register contains dedicated OCMC_RAM context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_CORE_OCMRAM ,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset). - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x210++0x3 line.long 0x00 "RM_MPU_M3_RSTCTRL,This register controls the release of the MPU_A3 sub-system resets." bitfld.long 0x00 2. " RST3 ,MPU_A3 MMU and CACHE interface reset control. - . - ." "Cleared,Reset" bitfld.long 0x00 1. " RST2 ,MPU_A3 Cortex M3 CPU2 reset control. - . - ." "Cleared,Reset" bitfld.long 0x00 0. " RST1 ,MPU_A3 Cortex M3 CPU1 reset control. - . - ." "Cleared,Reset" group.long 0x214++0x3 line.long 0x00 "RM_MPU_M3_RSTST,This register logs the different reset sources of the MPU_A3 SS. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" eventfld.long 0x00 6. " ICECRUSHER_RST2ST ,Cortex M3 CPU2 has been reset due to MPU_A3 ICECRUSHER2 reset source - . - ." "No_reset,Reset" eventfld.long 0x00 5. " ICECRUSHER_RST1ST ,Cortex M3 CPU1 has been reset due to MPU_A3 ICECRUSHER1 reset source - . - ." "No_reset,Reset" eventfld.long 0x00 4. " EMULATION_RST2ST ,Cortex M3 CPU2 has been reset due to emulation reset source, that is, assert reset command initiated by the icepick module - . - ." "No_reset,Reset" textline " " eventfld.long 0x00 3. " EMULATION_RST1ST ,Cortex M3 CPU1 has been reset due to emulation reset source, that is, assert reset command initiated by the icepick module - . - ." "No_reset,Reset" eventfld.long 0x00 2. " RST3ST ,MPU_A3 MMU and CACHE interface software reset status - . - ." "No_reset,Reset" eventfld.long 0x00 1. " RST2ST ,MPU_A3 Cortex-M3 CPU2 software reset status - . - ." "No_reset,Reset" textline " " eventfld.long 0x00 0. " RST1ST ,MPU_A3 Cortex-M3 CPU1 software reset status - . - ." "No_reset,Reset" group.long 0x224++0x3 line.long 0x00 "RM_MPU_M3_MPU_M3_CONTEXT,This register contains dedicated MPU_A3 context statuses. [warm reset insensitive]" eventfld.long 0x00 9. " LOSTMEM_MPU_M3_L2RAM ,Specify if memory-based context in MPU_A3_L2RAM memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 8. " LOSTMEM_MPU_M3_UNICACHE ,Specify if memory-based context in MPU_A3_UNICACHE memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of MPU_A3_RET_RST signal) - . - ." "Maintained,Lost" textline " " eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of MPU_A3_RST3 signal) - . - ." "Maintained,Lost" group.long 0x324++0x3 line.long 0x00 "RM_SDMA_SDMA_CONTEXT,This register contains dedicated SDMA context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_CORE_OTHER_BANK ,Specify if memory-based context in CORE_OTHER_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of SDMA_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x424++0x3 line.long 0x00 "RM_MEMIF_DMM_CONTEXT,This register contains dedicated DMM context statuses. [warm reset insensitive]" eventfld.long 0x00 9. " LOSTMEM_CORE_NRET_BANK ,Specify if memory-based context in CORE_NRET_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 8. " LOSTMEM_CORE_OTHER_BANK ,Specify if memory-based context in CORE_OTHER_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "Maintained,Lost" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RET_RST signal) - . - ." "Maintained,Lost" textline " " eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x42C++0x3 line.long 0x00 "RM_MEMIF_EMIF_FW_CONTEXT,This register contains dedicated EMIF_FW context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x434++0x3 line.long 0x00 "RM_MEMIF_EMIF_1_CONTEXT,This register contains dedicated EMIF_1 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RST signal) - . - ." "0,1" group.long 0x43C++0x3 line.long 0x00 "RM_MEMIF_EMIF_2_CONTEXT,This register contains dedicated EMIF_2 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RST signal) - . - ." "0,1" group.long 0x444++0x3 line.long 0x00 "RM_MEMIF_DLL_CONTEXT,This register contains dedicated DLL context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DLL_RST signal) - . - ." "Maintained,Lost" group.long 0x524++0x3 line.long 0x00 "RM_C2C_C2C_CONTEXT,This register contains dedicated C2C context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "0,1" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "0,1" group.long 0x534++0x3 line.long 0x00 "RM_C2C_C2C_FW_CONTEXT,This register contains dedicated C2C_FW context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RET_RST signal) - . - ." "0,1" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "0,1" group.long 0x624++0x3 line.long 0x00 "RM_L4CFG_L4_CFG_CONTEXT,This register contains dedicated L4_CFG context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x62C++0x3 line.long 0x00 "RM_L4CFG_SPINLOCK_CONTEXT,This register contains dedicated HW_SEM context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RET_RST signal) - . - ." "0,1" group.long 0x634++0x3 line.long 0x00 "RM_L4CFG_MAILBOX_CONTEXT,This register contains dedicated MAILBOX context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RET_RST signal) - . - ." "Maintained,Lost" group.long 0x63C++0x3 line.long 0x00 "RM_L4CFG_SAR_ROM_CONTEXT,This register contains dedicated SAR_ROM context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x724++0x3 line.long 0x00 "RM_L3INSTR_L3_3_CONTEXT,This register contains dedicated L3_3 context statuses. [warm reset insensitive]" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RET_RST signal) - . - ." "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x72C++0x3 line.long 0x00 "RM_L3INSTR_L3_INSTR_CONTEXT,This register contains dedicated L3_INSTR context statuses. [warm reset insensitive]" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "Maintained,Lost" group.long 0x744++0x3 line.long 0x00 "RM_L3INSTR_OCP_WP1_CONTEXT,This register contains dedicated OCP_WP1 context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_CORE_NRET_BANK ,Specify if memory-based context in CORE_NRET_BANK memory bank has been lost due to a previous power transition or other reset source. - . - ." "0,1" eventfld.long 0x00 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_PWRON_RET_RST signal) - . - ." "0,1" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CORE_RST signal) - . - ." "0,1" tree.end tree "RESTORE_CM1" base ad:0x4A004E00 width 37. group.long 0x0++0x3 line.long 0x00 "CM_CLKSEL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 8. " CLKSEL_L4 ,Selects L4 interconnect clock (L4_clk) - . - ." "/1,/2" bitfld.long 0x00 4. " CLKSEL_L3 ,Selects L3 interconnect clock (L3_clk) - . - ." "/1,/2" bitfld.long 0x00 0. " CLKSEL_CORE ,Selects CORE_CLK configuration - . - ." "/1,/2" group.long 0x4++0x3 line.long 0x00 "CM_DIV_M2_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status - . - ." "Enabled,Gated" bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT - . - ." "Gated,Enabled" bitfld.long 0x00 5. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" textline " " bitfld.long 0x00 0.--4. " DPLL_CLKOUT_DIV ,DPLL post-divider factor, M2, for internal clock generation (1 to 31); Divide value from 1 to 31. - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8++0x3 line.long 0x00 "CM_DIV_M3_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 9. " ST_DPLL_CLKOUTHIF ,DPLL CLKOUTHIF status - . - ." "Enabled,Gated" bitfld.long 0x00 8. " DPLL_CLKOUTHIF_GATE_CTRL ,Control gating of DPLL CLKOUTHIF - . - ." "Gated,Enabled" bitfld.long 0x00 5. " DPLL_CLKOUTHIF_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUTHIF_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" textline " " bitfld.long 0x00 0.--4. " DPLL_CLKOUTHIF_DIV ,DPLL post-divider factor, M3, for internal clock generation (1 to 31);Divide value from 1 to 31. - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC++0x3 line.long 0x00 "CM_DIV_M4_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT1_PWDN ,Automatic power down for HSDIVIDER M4 divider and hence CLKOUT1 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT1 ,HSDIVIDER CLKOUT1 status - . - ." "Enabled,Gated" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT1_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT1 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT1_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT1_DIV ,DPLL M4 post-divider factor (1 to 31). - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10++0x3 line.long 0x00 "CM_DIV_M5_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT2_PWDN ,Automatic power down for HSDIVIDER M5 divider and hence CLKOUT2 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT2 ,HSDIVIDER CLKOUT2 status - . - ." "Enabled,Gated" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT2_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT2 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT2_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT2_DIV ,DPLL M5 post-divider factor (1 to 31). - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14++0x3 line.long 0x00 "CM_DIV_M6_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT3_PWDN ,Automatic power down for HSDIVIDER M6 divider and hence CLKOUT3 output when the o/p clock is gated. - ." "Always_active,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT3 ,HSDIVIDER CLKOUT3 status - . - ." "Enabled,Gated" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT3_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT3 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT3_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT3_DIV ,DPLL M6 post-divider factor (1 to 31). - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x18++0x3 line.long 0x00 "CM_DIV_M7_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 12. " HSDIVIDER_CLKOUT4_PWDN ,Automatic power down for HSDIVIDER M7 divider and hence CLKOUT4 output when the o/p clock is gated. - ." "ALWAYS_ACTIVE,1" bitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT4 ,HSDIVIDER CLKOUT4 status - . - ." "Enabled,Gated" bitfld.long 0x00 8. " HSDIVIDER_CLKOUT4_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT4 - . - ." "Gated,Enabled" textline " " bitfld.long 0x00 5. " HSDIVIDER_CLKOUT4_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT4_DIV indicates that the change in divider value has taken effect" "Not_acknowledged,Acknowledged" bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT4_DIV ,DPLL M7 post-divider factor (1 to 31). - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C++0x3 line.long 0x00 "CM_CLKSEL_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLK.." "CLKINP,CLKINPULOW" bitfld.long 0x00 20. " DPLL_CLKOUTHIF_CLKSEL ,Selects the source of the DPLL CLKOUTHIF clock. Same as CLKINPHIFSEL pin on the DPLL - . - ." "DCO,CLKINPHIF" hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 =.." textline " " hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)." group.long 0x20++0x3 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part.." group.long 0x24++0x3 line.long 0x00 "CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x28++0x3 line.long 0x00 "CM_CLKMODE_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required - . - ." "Both,Lower" bitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - . - ." "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled. - ." "Disabled,1" bitfld.long 0x00 10. " DPLL_LPMODE_EN ,Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled. - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set. - .." "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode. - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,Reserved,MN_Bypass,Idle_Bypass_Low_Power,Idle_Bypass_Fast_Relock,Lock" group.long 0x2C++0x3 line.long 0x00 "CM_SHADOW_FREQ_CONFIG2_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 3.--7. " DPLL_CORE_M5_DIV ,Shadow register forCM_DIV_M5_DPLL_CORE.HSDIVIDER_CLKOUT2_DIV. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FRE.." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " CLKSEL_L3 ,Shadow register forCM_CLKSEL_CORE.CLKSEL_L3. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FREQ_U.." "0,1" bitfld.long 0x00 1. " CLKSEL_CORE ,Shadow register forCM_CLKSEL_CORE.CLKSEL_CORE. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and.." "0,1" textline " " bitfld.long 0x00 0. " GPMC_FREQ_UPDATE ,Controls whether or not GPMC has to be put automatically into idle during the frequency change operation. - . - ." "0,1" group.long 0x30++0x3 line.long 0x00 "CM_SHADOW_FREQ_CONFIG1_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 11.--15. " DPLL_CORE_M2_DIV ,Shadow register forCM_DIV_M2_DPLL_CORE.DPLL_CLKOUT_DIV. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1. Divide value from 1 to 31. - ." "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " DPLL_CORE_DPLL_EN ,Shadow register forCM_CLKMODE_DPLL_CORE.DPLL_EN. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1. - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,Reserved,MN_Bypass,Idle_Bypass_Low_Power,Idle_Bypass_Fast_Relock,Lock" bitfld.long 0x00 3. " DLL_RESET ,Specify if DLL should be reset or not during the frequency change hardware sequence. - . - ." "No_reset,Reset" textline " " bitfld.long 0x00 2. " DLL_OVERRIDE ,Shadow register forCM_DLL_CTRL.DLL_OVERRIDE.The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1. - . - ." "Not_overriden,Overriden" bitfld.long 0x00 0. " FREQ_UPDATE ,Writing 1 indicates that a new configuration is available. It is automatically cleared by h/w after the configuration has been applied." "Not_updated,Updated" group.long 0x34++0x3 line.long 0x00 "CM_AUTOIDLE_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 4. " DPLL_DCOCLKLDO_PWDN ,Allows powering down the DCOCLKLDO o/p of DPLL if all dividers in HSDIVIDER are powered down. PRCM takes care of reenabling this path for either restarting HSDIVIDER o/p or entering bypass mode. - . - ." "Always_active,Power_down" bitfld.long 0x00 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control. - . - . - . - . - . - . - . - ." "Disabled,Low_Power_Stop,Fast_Relock_Stop,Reserved,Reserved,Idle_Bypass_Low,Idle_Bypass_Fast,Reserved2" group.long 0x38++0x3 line.long 0x00 "CM_MPU_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 8. " CLKACTIVITY_MPU_DPLL_CLK ,This field indicates the state of the MPU_DPLL_CLK clock in the domain. [warm reset insensitive] - . - ." "Inactive,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the MPU clock domain. - . - . - . - ." "NO_SLEEP,Reserved,SW_WKUP,HW_AUTO" group.long 0x3C++0x3 line.long 0x00 "CM_CM1_PROFILING_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status - . - . - . - ." "0,1,2,Module_is_disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,1,?..." group.long 0x40++0x3 line.long 0x00 "CM_DYN_DEP_PRESCAL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 0.--5. " PRESCAL ,Time unit is equal to (PRESCAL + 1) L4 clock cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "RESTORE_CM2" base ad:0x4A009E00 width 37. group.long 0x0++0x3 line.long 0x00 "CM_L3_1_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 8. " CLKACTIVITY_L3_1_ICLK ,This field indicates the state of the L3_1_GICLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3_1 clock domain. - . - . - . - ." "NO_SLEEP,Reserved,Reserved,HW_AUTO" group.long 0x4++0x3 line.long 0x00 "CM_L3_2_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 8. " CLKACTIVITY_L3_2_ICLK ,This field indicates the state of the L3_2_GICLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3_2 clock domain. - . - . - . - ." "NO_SLEEP,Reserved,Reserved,HW_AUTO" group.long 0x8++0x3 line.long 0x00 "CM_L4CFG_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 8. " CLKACTIVITY_CFG_L4_ICLK ,This field indicates the state of the L4_CFG_GICLK clock in the domain. [warm reset insensitive] - . - ." "0,1" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4CFG clock domain. - . - . - . - ." "NO_SLEEP,Reserved,Reserved,HW_AUTO" group.long 0xC++0x3 line.long 0x00 "CM_MEMIF_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 13. " CLKACTIVITY_ASYNC_PHY2_CLK ,This field indicates the state of the ASYNC_PHY2_CLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 12. " CLKACTIVITY_ASYNC_PHY1_CLK ,This field indicates the state of the ASYNC_PHY1_CLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 11. " CLKACTIVITY_ASYNC_DLL_CLK ,This field indicates the state of the ASYNC_DLL_CLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 10. " CLKACTIVITY_PHY_ROOT_CLK ,This field indicates the state of the PHY_ROOT_CLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 9. " CLKACTIVITY_DLL_CLK ,This field indicates the state of the DLL_CLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 8. " CLKACTIVITY_L3_EMIF_ICLK ,This field indicates the state of the L3_EMIF_GICLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the MEMIF clock domain. - . - . - . - ." "NO_SLEEP,Reserved,SW_WKUP,HW_AUTO" group.long 0x10++0x3 line.long 0x00 "CM_L4PER_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 25. " CLKACTIVITY_PER_ABE_24M_FCLK ,This field indicates the state of the PER_ABE_24M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 22. " CLKACTIVITY_PER_MCBSP4_FCLK ,This field indicates the state of the PER_MCBSP4_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 19. " CLKACTIVITY_PER_96M_FCLK ,This field indicates the state of the PER_96M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 18. " CLKACTIVITY_PER_48M_FCLK ,This field indicates the state of the PER_48M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 17. " CLKACTIVITY_PER_32K_FCLK ,This field indicates the state of the PER_32K_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 16. " CLKACTIVITY_PER_24MC_FCLK ,This field indicates the state of the PER_24MC_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 15. " CLKACTIVITY_12M_FCLK_FCLK ,This field indicates the state of the FUNC_12M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 14. " CLKACTIVITY_GPT9_FCLK ,This field indicates the state of the DMT9_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 13. " CLKACTIVITY_GPT4_FCLK ,This field indicates the state of the DMT4_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 12. " CLKACTIVITY_GPT3_FCLK ,This field indicates the state of the DMT3_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 11. " CLKACTIVITY_GPT2_FCLK ,This field indicates the state of the DMT2_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 10. " CLKACTIVITY_GPT11_FCLK ,This field indicates the state of the DMT11_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 9. " CLKACTIVITY_GPT10_FCLK ,This field indicates the state of the DMT10_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 8. " CLKACTIVITY_L4_PER_ICLK ,This field indicates the state of the L4_PER_GICLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4PER clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x14++0x3 line.long 0x00 "CM_L3INIT_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 29. " CLKACTIVITY_INIT_60M_P2_FCLK ,This field indicates the state of the INIT_60M_P2_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 28. " CLKACTIVITY_INIT_60M_P1_FCLK ,This field indicates the state of the INIT_60M_P1_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 27. " CLKACTIVITY_HSIC_P2_FCLK ,This field indicates the state of the HSIC_P2_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 26. " CLKACTIVITY_HSIC_P1_FCLK ,This field indicates the state of the HSIC_P1_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 25. " CLKACTIVITY_UTMI_ROOT_FCLK ,This field indicates the state of the UTMI_ROOT_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 23. " CLKACTIVITY_TLL_CH1_FCLK ,This field indicates the state of the TLL_CH1_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 22. " CLKACTIVITY_TLL_CH0_FCLK ,This field indicates the state of the TLL_CH0_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 21. " CLKACTIVITY_HSIC_P2_480M_FCLK ,This field indicates the state of the HSIC_P2_480M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 20. " CLKACTIVITY_HSIC_P1_480M_FCLK ,This field indicates the state of the HSIC_P1_480M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 19. " CLKACTIVITY_INIT_HSMMC6_FCLK ,This field indicates the state of the INIT_HSMMC6_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 18. " CLKACTIVITY_INIT_HSMMC2_FCLK ,This field indicates the state of the INIT_HSMMC2_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 17. " CLKACTIVITY_INIT_HSMMC1_FCLK ,This field indicates the state of the INIT_HSMMC1_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 16. " CLKACTIVITY_INIT_HSI_FCLK ,This field indicates the state of the INIT_HSI_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 15. " CLKACTIVITY_USB_DPLL_HS_CLK ,This field indicates the state of the USB_DPLL_HS_CLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 14. " CLKACTIVITY_USB_DPLL_CLK ,This field indicates the state of the USB_DPLL_CLK clock in the domain. [warm reset insensitive] - . - ." "0,1" textline " " bitfld.long 0x00 13. " CLKACTIVITY_INIT_48MC_FCLK ,This field indicates the state of the INIT_48MC_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 12. " CLKACTIVITY_INIT_48M_FCLK ,This field indicates the state of the INIT_48M_FCLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 9. " CLKACTIVITY_INIT_L4_ICLK ,This field indicates the state of the L4_INIT_GICLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" textline " " bitfld.long 0x00 8. " CLKACTIVITY_INIT_L3_ICLK ,This field indicates the state of the L3_INIT_GICLK clock in the domain. [warm reset insensitive] - . - ." "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3INIT clock domain. - . - . - . - ." "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x18++0x3 line.long 0x00 "CM_L3INSTR_L3_3_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x1C++0x3 line.long 0x00 "CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,AUTO,?..." group.long 0x20++0x3 line.long 0x00 "CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,1,?..." group.long 0x24++0x3 line.long 0x00 "CM_CM2_PROFILING_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status - . - . - . - ." "0,1,2,Module_is_disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,1,?..." group.long 0x28++0x3 line.long 0x00 "CM_C2C_STATICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" textline " " bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" textline " " bitfld.long 0x00 3. " ABE_STATDEP ,Static dependency towards ABE clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Dependency_is_disabled,Dependency_is_enabled" group.long 0x2C++0x3 line.long 0x00 "CM_L3_1_DYNAMICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12. " L4CFG_DYNDEP ,Dynamic dependency towards L4CFG clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "0,Dependency_is_enabled" textline " " bitfld.long 0x00 4. " MEMIF_DYNDEP ,Dynamic dependency towards MEMIF clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 3. " ABE_DYNDEP ,Dynamic dependency towards ABE clock domain - ." "0,Dependency_is_enabled" group.long 0x30++0x3 line.long 0x00 "CM_L3_2_DYNAMICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18. " C2C_DYNDEP ,Dynamic dependency towards D2D clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 14. " L4SEC_DYNDEP ,Dynamic dependency towards L4SEC clock domain - ." "0,Dependency_is_enabled" textline " " bitfld.long 0x00 13. " L4PER_DYNDEP ,Dynamic dependency towards L4PER clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 10. " GFX_DYNDEP ,Dynamic dependency towards GFX clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 9. " ISS_DYNDEP ,Dynamic dependency towards ISS clock domain - ." "Dependency_is_disabled,1" textline " " bitfld.long 0x00 8. " DSS_DYNDEP ,Dynamic dependency towards DSS clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 7. " L3INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 5. " L3_1_DYNDEP ,Dynamic dependency towards L3_1 clock domain - ." "0,Dependency_is_enabled" textline " " bitfld.long 0x00 2. " IVAHD_DYNDEP ,Dynamic dependency towards IVAHD clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 0. " MPU_M3_DYNDEP ,Dynamic dependency towards CORTEXM3 clock domain - ." "0,Dependency_is_enabled" group.long 0x34++0x3 line.long 0x00 "CM_C2C_DYNAMICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 4. " MEMIF_DYNDEP ,Dynamic dependency towards MEMIF clock domain - ." "0,Dependency_is_enabled" group.long 0x38++0x3 line.long 0x00 "CM_L4CFG_DYNAMICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18. " C2C_DYNDEP ,Dynamic dependency towards D2D clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 16. " ALWONCORE_DYNDEP ,Dynamic dependency towards ALWONCORE clock domain - ." "0,Dependency_is_enabled" textline " " bitfld.long 0x00 15. " L4WKUP_DYNDEP ,Dynamic dependency towards L4WKUP clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 11. " SDMA_DYNDEP ,Dynamic dependency towards SDMA clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 9. " ISS_DYNDEP ,Dynamic dependency towards ISS clock domain - ." "Dependency_is_disabled,1" textline " " bitfld.long 0x00 8. " DSS_DYNDEP ,Dynamic dependency towards DSS clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 7. " L3INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 6. " L3_2_DYNDEP ,Dynamic dependency towards L3_2 clock domain - ." "0,Dependency_is_enabled" textline " " bitfld.long 0x00 5. " L3_1_DYNDEP ,Dynamic dependency towards L3_1 clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 4. " MEMIF_DYNDEP ,Dynamic dependency towards MEMIF clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 1. " DSP_DYNDEP ,Dynamic dependency towards DSP clock domain - ." "0,Dependency_is_enabled" group.long 0x3C++0x3 line.long 0x00 "CM_L4PER_DYNAMICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14. " L4SEC_DYNDEP ,Dynamic dependency towards L4SEC clock domain - ." "0,Dependency_is_enabled" bitfld.long 0x00 8. " DSS_DYNDEP ,Dynamic dependency towards DSS clock domain - ." "0,Dependency_is_enabled" textline " " bitfld.long 0x00 7. " L3INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain - ." "0,Dependency_is_enabled" group.long 0x40++0x3 line.long 0x00 "CM_L4PER_GPIO2_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x44++0x3 line.long 0x00 "CM_L4PER_GPIO3_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x48++0x3 line.long 0x00 "CM_L4PER_GPIO4_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x4C++0x3 line.long 0x00 "CM_L4PER_GPIO5_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x50++0x3 line.long 0x00 "CM_L4PER_GPIO6_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x54++0x3 line.long 0x00 "CM_L3INIT_HSUSBHOST_CLKCTRL_RESTORE,Second address map for register CM_L3INIT_USB_HOST_CLKCTRL. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 25. " CLKSEL_UTMI_P2 ,Selects the source of the functional clock for UTMI Port2 on USB Host - . - ." "Internal,External" bitfld.long 0x00 24. " CLKSEL_UTMI_P1 ,Selects the source of the functional clock for UTMI Por1 on USB Host - . - ." "Internal,External" bitfld.long 0x00 18. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "Functional,Standby" textline " " bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "Functional,Transition,Idle,Disabled" bitfld.long 0x00 15. " OPTFCLKEN_FUNC48MCLK ,USB-HOST optional clock control: FUNC48MCLK - . - ." "Disabled,Enabled" bitfld.long 0x00 14. " OPTFCLKEN_HSIC480M_P2_CLK ,USB-HOST optional clock control: HSIC480M_P2_CLK - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 13. " OPTFCLKEN_HSIC480M_P1_CLK ,USB-HOST optional clock control: HSIC480M_P1_CLK - . - ." "Disabled,Enabled" bitfld.long 0x00 12. " OPTFCLKEN_HSIC60M_P2_CLK ,USB-HOST optional clock control: HSIC60M_P2_CLK - . - ." "Disabled,Enabled" bitfld.long 0x00 11. " OPTFCLKEN_HSIC60M_P1_CLK ,USB-HOST optional clock control: HSIC60M_P1_CLK - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OPTFCLKEN_UTMI_P3_CLK ,USB-HOST optional clock control: UTMI_P3_CLK - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " OPTFCLKEN_UTMI_P2_CLK ,USB-HOST optional clock control: UTMI_P2_CLK when CLKSEL_UTMI_P2 is 0 - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " OPTFCLKEN_UTMI_P1_CLK ,USB-HOST optional clock control: UTMI_P1_CLK when CLKSEL_UTMI_P1 is 0 - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SAR_MODE ,SAR mode control for the module. Shall not be modify except if module is disabled. - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "Disabled,Reserved,Enabled,?..." group.long 0x58++0x3 line.long 0x00 "CM_L3INIT_HSUSBTLL_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 16.--17. " IDLEST ,Module idle status. [warm reset insensitive] - . - . - . - ." "0,1,2,3" bitfld.long 0x00 9. " OPTFCLKEN_USB_CH1_CLK ,USB-HOST optional clock control: USB_CH1_CLK - . - ." "0,1" bitfld.long 0x00 8. " OPTFCLKEN_USB_CH0_CLK ,USB-HOST optional clock control: USB_CH0_CLK - . - ." "0,1" textline " " bitfld.long 0x00 4. " SAR_MODE ,SAR mode control for the module. Shall not be modify except if module is disabled. - . - ." "0,1" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. - . - . - . - ." "0,1,?..." group.long 0x5C++0x3 line.long 0x00 "CM_SDMA_STATICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." bitfld.long 0x00 15. " L4WKUP_STATDEP ,Static dependency towards L4WKUP clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " ISS_STATDEP ,Static dependency towards ISS clock domain - ." "Disabled,1" bitfld.long 0x00 8. " DSS_STATDEP ,Static dependency towards DSS clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " L3_2_STATDEP ,Static dependency towards L3_2 clock domain - ." "0,Enabled" bitfld.long 0x00 5. " L3_1_STATDEP ,Static dependency towards L3_1 clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MEMIF_STATDEP ,Static dependency towards MEMIF clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 3. " ABE_STATDEP ,Static dependency towards ABE clock domain - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " IVAHD_STATDEP ,Static dependency towards IVAHD clock domain - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MPU_M3_STATDEP ,Static dependency towards MPU_A3 clock domain - . - ." "Disabled,Enabled" tree.end tree "SCRM" base ad:0x4A30A000 width 18. rgroup.long 0x0++0x3 line.long 0x00 "REVISION_SCRM,This register contains the IP revision code for the SCRM." hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision Number" group.long 0x100++0x3 line.long 0x00 "CLKSETUPTIME,This register holds the clock setup time counters of the system clock source supplier." bitfld.long 0x00 16.--21. " DOWNTIME ,Holds the number of 32 kHz clock cycles it takes to gate the clock source supplier." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--11. 1. " SETUPTIME ,Holds the number of 32 kHz clock cycles it takes to stabilize the clock source supplier." group.long 0x104++0x3 line.long 0x00 "PMICSETUPTIME,This register holds the setup time counters for the sleep mode of the PMIC." bitfld.long 0x00 16.--21. " WAKEUPTIME ,Holds the number of 32 kHz clock cycles it takes to exit the PMIC from sleep mode." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " SLEEPTIME ,Holds the number of 32 kHz clock cycles it takes to enter the PMIC in sleep mode." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x110++0x3 line.long 0x00 "ALTCLKSRC,This register controls the alternate system clock source supplier." bitfld.long 0x00 3. " ENABLE_EXT ,This bit allows to enable and disable the output alternate system clock version. This bit is intended to be used in order to gate this clock path while the source is stabilizing. - . - ." "0,1" bitfld.long 0x00 2. " ENABLE_INT ,This bit allows to enable and disable the alternate system clock version used to generate the auxiliary clocks. This bit is intended to be used in order to gate this clock path while the source is stabilizing and also to gate th.." "0,1" bitfld.long 0x00 0.--1. " MODE ,This bit field defines the functional mode of the alternate system clock supplier. - . - . - . - ." "0,1,2,?..." group.long 0x11C++0x3 line.long 0x00 "C2CCLKM,This register controls the clocks of the external C2C interface." bitfld.long 0x00 1. " SYSCLK ,This bit allows to enable and disable the system clock version of the external C2C interface. - . - ." "0,1" bitfld.long 0x00 0. " CLK_32KHZ ,This bit allows to enable and disable the 32 kHz clock version of the external C2C interface. - . - ." "0,1" group.long 0x200++0x3 line.long 0x00 "EXTCLKREQ,This register holds qualifiers for the external clock request." bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the external clock request. - . - ." "Active_low,Active_high" group.long 0x204++0x3 line.long 0x00 "ACCCLKREQ,This register holds qualifiers for the accurate clock request." bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the accurate clock request. - . - ." "0,1" group.long 0x208++0x3 line.long 0x00 "PWRREQ,This register holds qualifiers for the external power request." bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the external power request. - . - ." "Active_low,Active_high" group.long 0x210++0x3 line.long 0x00 "AUXCLKREQ0,This register holds qualifiers for the auxiliary clock request #0." bitfld.long 0x00 2.--4. " MAPPING ,This field allows re-mapping the auxiliary clock request #0 on another auxiliary clock output than auxiliary clock #0. - . - . - . - . - . - . - . - ." "Aux._0,Aux._1,Aux._2,Aux._3,Aux._4,Aux._5,?..." bitfld.long 0x00 1. " ACCURACY ,This bit qualifies the auxiliary clock request #0 as an accurate clock request. - . - ." "Not_generated,Generated" bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the auxiliary clock request #0. - . - ." "Active_low,Active_high" group.long 0x214++0x3 line.long 0x00 "AUXCLKREQ1,This register holds qualifiers for the auxiliary clock request #1." bitfld.long 0x00 2.--4. " MAPPING ,This field allows re-mapping the auxiliary clock request #1 on another auxiliary clock output than auxiliary clock #1. - . - . - . - . - . - . - . - ." "Aux._0,Aux._1,Aux._2,Aux._3,Aux._4,Aux._5,?..." bitfld.long 0x00 1. " ACCURACY ,This bit qualifies the auxiliary clock request #1 as an accurate clock request. - . - ." "Not_generated,Generated" bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the auxiliary clock request #1. - . - ." "Active_low,Active_high" group.long 0x218++0x3 line.long 0x00 "AUXCLKREQ2,This register holds qualifiers for the auxiliary clock request #2." bitfld.long 0x00 2.--4. " MAPPING ,This field allows re-mapping the auxiliary clock request #2 on another auxiliary clock output than auxiliary clock #2. - . - . - . - . - . - . - . - ." "Aux._0,Aux._1,Aux._2,Aux._3,Aux._4,Aux._5,?..." bitfld.long 0x00 1. " ACCURACY ,This bit qualifies the auxiliary clock request #2 as an accurate clock request. - . - ." "Not_generated,Generated" bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the auxiliary clock request #2. - . - ." "Active_low,Active_high" group.long 0x21C++0x3 line.long 0x00 "AUXCLKREQ3,This register holds qualifiers for the auxiliary clock request #3." bitfld.long 0x00 2.--4. " MAPPING ,This field allows re-mapping the auxiliary clock request #3 on another auxiliary clock output than auxiliary clock #3. - . - . - . - . - . - . - . - ." "Aux._0,Aux._1,Aux._2,Aux._3,Aux._4,Aux._5,?..." bitfld.long 0x00 1. " ACCURACY ,This bit qualifies the auxiliary clock request #3 as an accurate clock request. - . - ." "Not_generated,Generated" bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the auxiliary clock request #3. - . - ." "Active_low,Active_high" group.long 0x220++0x3 line.long 0x00 "AUXCLKREQ4,This register holds qualifiers for the auxiliary clock request #4." bitfld.long 0x00 2.--4. " MAPPING ,This field allows re-mapping the auxiliary clock request #4 on another auxiliary clock output than auxiliary clock #4. - . - . - . - . - . - . - . - ." "Aux._0,Aux._1,Aux._2,Aux._3,Aux._4,Aux._5,?..." bitfld.long 0x00 1. " ACCURACY ,This bit qualifies the auxiliary clock request #4 as an accurate clock request. - . - ." "Not_generated,Generated" bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the auxiliary clock request #4. - . - ." "Active_low,Active_high" group.long 0x224++0x3 line.long 0x00 "AUXCLKREQ5,This register holds qualifiers for the auxiliary clock request #5." bitfld.long 0x00 2.--4. " MAPPING ,This field allows re-mapping the auxiliary clock request #5 on another auxiliary clock output than auxiliary clock #5. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,?..." bitfld.long 0x00 1. " ACCURACY ,This bit qualifies the auxiliary clock request #5 as an accurate clock request. - . - ." "0,1" bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the auxiliary clock request #5. - . - ." "0,1" group.long 0x234++0x3 line.long 0x00 "C2CCLKREQ,This register holds qualifiers for the external C2C interface clock request." bitfld.long 0x00 1. " ACCURACY ,This bit qualifies the external C2C interface clock request as an accurate clock request. - . - ." "0,1" bitfld.long 0x00 0. " POLARITY ,This bit defines the active level of the external C2C interface clock request. - . - ." "0,1" group.long 0x310++0x3 line.long 0x00 "AUXCLK0,This register holds qualifiers for the auxiliary clock #0." bitfld.long 0x00 16.--19. " CLKDIV ,This field holds the divider value for the auxiliary clock #0. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 9. " DISABLECLK ,This bit allows to gate the auxiliary clock #0 without condition. This is bit is intended to be used only when the SOC is not clock provider. - . - ." "Enabled,Disabled" bitfld.long 0x00 8. " ENABLE ,This bit allows to request the auxiliary clock #0 by software. - . - ." "Not_requested,Requested" textline " " bitfld.long 0x00 1.--2. " SRCSELECT ,This field allows selecting the clock source of the auxiliary clock #0. - . - . - . - ." "System,CORE_DPLL,PER_DPLL,?..." bitfld.long 0x00 0. " POLARITY ,This bit defines the output level when the auxiliary clock #0 is gated. - . - ." "Gated_low,Gated_high" group.long 0x314++0x3 line.long 0x00 "AUXCLK1,This register holds qualifiers for the auxiliary clock #1." bitfld.long 0x00 16.--19. " CLKDIV ,This field holds the divider value for the auxiliary clock #1. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8. " ENABLE ,This bit allows to request the auxiliary clock #1 by software. - . - ." "Not_requested,Requested" bitfld.long 0x00 1.--2. " SRCSELECT ,This field allows selecting the clock source of the auxiliary clock #1. - . - . - . - ." "System,CORE_DPLL,PER_DPLL,?..." textline " " bitfld.long 0x00 0. " POLARITY ,This bit defines the output level when the auxiliary clock #1 is gated. - . - ." "Gated_low,Gated_high" group.long 0x318++0x3 line.long 0x00 "AUXCLK2,This register holds qualifiers for the auxiliary clock #2." bitfld.long 0x00 16.--19. " CLKDIV ,This field holds the divider value for the auxiliary clock #2. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8. " ENABLE ,This bit allows to request the auxiliary clock #2 by software. - . - ." "Not_requested,Requested" bitfld.long 0x00 1.--2. " SRCSELECT ,This field allows selecting the clock source of the auxiliary clock #2. - . - . - . - ." "System,CORE_DPLL,PER_DPLL,?..." textline " " bitfld.long 0x00 0. " POLARITY ,This bit defines the output level when the auxiliary clock #2 is gated. - . - ." "Gated_low,Gated_high" group.long 0x31C++0x3 line.long 0x00 "AUXCLK3,This register holds qualifiers for the auxiliary clock #3." bitfld.long 0x00 16.--19. " CLKDIV ,This field holds the divider value for the auxiliary clock #3. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8. " ENABLE ,This bit allows to request the auxiliary clock #3 by software. - . - ." "Not_requested,Requested" bitfld.long 0x00 1.--2. " SRCSELECT ,This field allows selecting the clock source of the auxiliary clock #3. - . - . - . - ." "System,CORE_DPLL,PER_DPLL,?..." textline " " bitfld.long 0x00 0. " POLARITY ,This bit defines the output level when the auxiliary clock #3 is gated. - . - ." "Gated_low,Gated_high" group.long 0x320++0x3 line.long 0x00 "AUXCLK4,This register holds qualifiers for the auxiliary clock #4." bitfld.long 0x00 16.--19. " CLKDIV ,This field holds the divider value for the auxiliary clock #4. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8. " ENABLE ,This bit allows to request the auxiliary clock #4 by software. - . - ." "Not_requested,Requested" bitfld.long 0x00 1.--2. " SRCSELECT ,This field allows selecting the clock source of the auxiliary clock #4. - . - . - . - ." "System,CORE_DPLL,PER_DPLL,?..." textline " " bitfld.long 0x00 0. " POLARITY ,This bit defines the output level when the auxiliary clock #4 is gated. - . - ." "Gated_low,Gated_high" group.long 0x324++0x3 line.long 0x00 "AUXCLK5,This register holds qualifiers for the auxiliary clock #5." bitfld.long 0x00 16.--19. " CLKDIV ,This field holds the divider value for the auxiliary clock #5. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8. " ENABLE ,This bit allows to request the auxiliary clock #5 by software. - . - ." "Not_requested,Requested" bitfld.long 0x00 1.--2. " SRCSELECT ,This field allows selecting the clock source of the auxiliary clock #5. - . - . - . - ." "System,CORE_DPLL,PER_DPLL,?..." textline " " bitfld.long 0x00 0. " POLARITY ,This bit defines the output level when the auxiliary clock #5 is gated. - . - ." "Gated_low,Gated_high" group.long 0x400++0x3 line.long 0x00 "RSTTIME_REG,This register holds the reset time counter which is used to extend the reset lines beyond the release of the pad reset." bitfld.long 0x00 0.--3. " RSTTIME ,Holds the number of 32 kHz clock cycles for which the reset duration is extended. Values 0,1 and 2 are not allowed. 0x0: Reserved. 0x1: Reserved. 0x2: Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x41C++0x3 line.long 0x00 "C2CRSTCTRL,This register controls the release of the external C2C interface reset lines." bitfld.long 0x00 1. " WARMRST ,This bit allows to release the warm reset line of the external C2C interface. [warm reset sensitive] - . - ." "0,1" bitfld.long 0x00 0. " COLDRST ,This bit allows to release the cold reset line of the external C2C interface. - . - ." "0,1" group.long 0x420++0x3 line.long 0x00 "EXTPWRONRSTCTRL,This register allows the software to perform an external power-on reset." bitfld.long 0x00 1. " PWRONRST ,This bit controls the assertion and the de-assertion of the external power-on reset. - . - ." "Deasserted,Asserted" bitfld.long 0x00 0. " ENABLE ,This bit must be set to 1 to allow the software to assert the external power-on reset. - . - ." "Disabled,Enabled" group.long 0x510++0x3 line.long 0x00 "EXTWARMRSTST_REG,This register logs the source of warm reset output. Each bit is set upon release of the warm reset output and must be cleared by software." eventfld.long 0x00 0. " EXTWARMRSTST ,This bit logs the external warm reset source. - . - ." "0,1" group.long 0x514++0x3 line.long 0x00 "APEWARMRSTST_REG,This register logs the source of warm reset on the APE. Each bit is set upon release of the APE warm reset and must be cleared by software." eventfld.long 0x00 1. " APEWARMRSTST ,This bit logs the APE warm reset source. - . - ." "0,1" group.long 0x51C++0x3 line.long 0x00 "C2CWARMRSTST_REG,This register logs the source of warm reset on the external C2C interface. Each bit is set upon release of the external C2C interface warm reset and must be cleared by software." eventfld.long 0x00 3. " C2CWARMRSTST ,This bit logs the C2C warm reset source. - . - ." "0,1" tree.end tree.open "SR_MPU" tree "SR_MPU" base ad:0x4A0D9000 width 18. group.long 0x0++0x3 line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing." hexmask.long.word 0x00 22.--31. 1. " ACCUMDATA ,Number of Values to Accumulate" hexmask.long.word 0x00 12.--21. 1. " SRCLKLENGTH ,Determines frequency of SRClk" bitfld.long 0x00 11. " SRENABLE ,0: Asynchronously resets MinMaxAvgAccumValid, MinMaxAvgValid, ErrorGeneratorValid, AccumData sensor, SRClk counter, and MinMaxAvg registers. Also gates the clock for power savings and disables all the digital logic. , 1: Enables .." "0,1" textline " " bitfld.long 0x00 10. " SENENABLE ,0: All sensors disabled, 1: Sensors enabled per SenNEnable and SenPEnable" "0,1" bitfld.long 0x00 9. " ERRORGENERATORENABLE ,0: Error Generator Module disabled, 1: Error Generator Module enabled" "0,1" bitfld.long 0x00 8. " MINMAXAVGENABLE ,0: MinMaxAvg Detector Module disabled, 1: MinMaxAvg Detector Module enabled" "0,1" textline " " bitfld.long 0x00 1. " SENNENABLE ,0: Disable SenN sensor, 1: Enable SenN sensor" "0,1" bitfld.long 0x00 0. " SENPENABLE ,0: Disable SenP sensor, 1: Enable SenP sensor" "0,1" rgroup.long 0x4++0x3 line.long 0x00 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred." bitfld.long 0x00 3. " AVGERRVALID ,0: AvgError registers are not valid, 1: AvgError registers are valid." "0,1" bitfld.long 0x00 2. " MINMAXAVGVALID ,0: SenVal, SenMin, SenMax, SenAvg registers are not valid, 1: SenVal, SenMin, SenMax, SenAvg registers are valid, but not necessarily fully accumulated" "0,1" bitfld.long 0x00 1. " ERRORGENERATORVALID ,0: SenError register do not have valid data, 1: SenError registers have valid data." "0,1" textline " " bitfld.long 0x00 0. " MINMAXAVGACCUMVALID ,0: SenVal, SenMin, SenMax, SenAvg registers are not valid, 1: SenVal, SenMin, SenMax, SenAvg registers have valid, final data" "0,1" rgroup.long 0x8++0x3 line.long 0x00 "SENVAL,The current sensor values from the Sensor Core." hexmask.long.word 0x00 16.--31. 1. " SENPVAL ,The latest value of the SenPVal from the sensor core." hexmask.long.word 0x00 0.--15. 1. " SENNVAL ,The latest value of the SenNVal from the sensor core." rgroup.long 0xC++0x3 line.long 0x00 "SENMIN,The minimum sensor values." hexmask.long.word 0x00 16.--31. 1. " SENPMIN ,The minimum value of the SenPVal from the sensor core since the last restat operation." hexmask.long.word 0x00 0.--15. 1. " SENNMIN ,The minimum value of the SenNVal from the sensor core since the last restat operation." rgroup.long 0x10++0x3 line.long 0x00 "SENMAX,The maximum sensor values." hexmask.long.word 0x00 16.--31. 1. " SENPMAX ,The maximum value of the SenPVal from the sensor core since the last restat operation." hexmask.long.word 0x00 0.--15. 1. " SENNMAX ,The maximum value of the SenNVal from the sensor core since the last restat operation." rgroup.long 0x14++0x3 line.long 0x00 "SENAVG,The average sensor values." hexmask.long.word 0x00 16.--31. 1. " SENPAVG ,The running average of the SenPVal from the sensor core since the last restat operation." hexmask.long.word 0x00 0.--15. 1. " SENNAVG ,The running average of the SenNVal from the sensor core since the last restat operation." group.long 0x18++0x3 line.long 0x00 "AVGWEIGHT,The weighting factor in the average computation." bitfld.long 0x00 2.--3. " SENPAVGWEIGHT ,The weighting factor for the SenP averager." "0,1,2,3" bitfld.long 0x00 0.--1. " SENNAVGWEIGHT ,The weighting factor for the SenN averager." "0,1,2,3" group.long 0x1C++0x3 line.long 0x00 "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation." bitfld.long 0x00 20.--23. " SENPGAIN ,The gain value for the SenP reciprocal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SENNGAIN ,The gain value for the SenN reciprocal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SENPRN ,The scale value for the SenP reciprocal." textline " " hexmask.long.byte 0x00 0.--7. 1. " SENNRN ,The scale value for the SenN reciprocal." group.long 0x24++0x3 line.long 0x00 "IRQSTATUS_RAW,MCU raw interrup status and set." bitfld.long 0x00 3. " MCUACCUMINTSTATRAW ,0: Accum interrupt status is unchanged 1: Accum interrupt status is set" "0,1" bitfld.long 0x00 2. " MCUVALIDINTSTATRAW ,0: Valid interrupt status is unchanged 1: Valid interrupt status is set" "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTSTATRAW ,0: Bounds interrupt status is unchanged 1: Bounds interrupt status is set" "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACKINTSTATRAW ,0: MCUDisable acknowledge status is unchanged 1: MCUDisable acknowledge status is set" "0,1" group.long 0x28++0x3 line.long 0x00 "IRQSTATUS,MCU masked interrupt status and clear." bitfld.long 0x00 3. " MCUACCUMINTSTATENA ,Read 0: Accum interrupt status is unchanged. - . - . - ." "0,1" bitfld.long 0x00 2. " MCUVALIDINTSTATENA ,Read 0: Valid interrupt status is unchanged. - . - . - ." "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTSTATENA ,Read 0: Bounds interrupt status is unchanged. - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACKINTSTATENA ,Read 0: MCUDisable acknowledge status is unchanged. - . - . - ." "0,1" group.long 0x2C++0x3 line.long 0x00 "IRQENABLE_SET,MCU interrupt enable flag and set." bitfld.long 0x00 3. " MCUACCUMINTENASET ,Read mode: 0: Accum interrupt generation is disabled/masked, 1: Accum interrupt generation is enabled; Write mode: 0: No change to Accum interrupt enable, 1: Enable Accum interrupt generation." "0,1" bitfld.long 0x00 2. " MCUVALIDINTENASET ,Read mode: 0: Valid interrupt generation is disabled/masked, 1: Valid interrupt generation is enabled; Write mode: 0: No change to Valid interrupt enable, 1: Enable Valid interrupt generation." "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTENASET ,Read mode: 0: Bounds interrupt generation is disabled/masked, 1: Bounds interrupt generation is enabled; Write mode: 0: No change to Bounds interrupt enable, 1: Enable Bounds interrupt generation." "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACTINTENASET ,Read mode: 0: MCUDisableAck interrupt generation is disabled/masked, 1: MCUDisableAck interrupt generation is enabled; Write mode: 0: No change to MCUDisAck interrupt enable, 1: Enable MCUDisableAck interrupt generation." "0,1" group.long 0x30++0x3 line.long 0x00 "IRQENABLE_CLR,MCU interrup enable flag and clear." bitfld.long 0x00 3. " MCUACCUMINTENACLR ,Read mode: 0: Accum interrupt generation is disabled/masked, 1: Accum interrupt generation is enabled; Write mode: 0: No change to Accum interrupt enable, 1: Enable Accum interrupt generation." "0,1" bitfld.long 0x00 2. " MCUVALIDINTENACLR ,Read mode: 0: Valid interrupt generation is disabled/masked, 1: Valid interrupt generation is enabled; Write mode: 0: No change to Valid interrupt enable, 1: Enable Valid interrupt generation." "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTENACLR ,Read mode: 0: Bounds interrupt generation is disabled/masked, 1: Bounds interrupt generation is enabled; Write mode: 0: No change to Bounds interrupt enable, 1: Enable Bounds interrupt generation." "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACKINTENACLR ,Read mode: 0: MCUDisableAck interrupt generation is disabled/masked, 1: MCUDisableAck interrupt generation is enabled; Write mode: 0: No change to MCUDisAck interrupt enable, 1: Enable MCUDisableAck interrupt generation." "0,1" rgroup.long 0x34++0x3 line.long 0x00 "SENERROR,The sensor error from the error generator." hexmask.long.byte 0x00 8.--15. 1. " AVGERROR ,The average sensor error." hexmask.long.byte 0x00 0.--7. 1. " SENERROR ,The percentage of sensor error." group.long 0x38++0x3 line.long 0x00 "ERRCONFIG,The sensor error configuration." bitfld.long 0x00 26. " WAKEUPENABLE ,Wakeup from MCU Interrupts enable." "0,1" bitfld.long 0x00 24.--25. " IDLEMODE ,0b00: Force-Idle Mode, 0b01: No Idle Mode, 0b10: Smart-Idle Mode #2, 0b11: Smart-Idle-Wkup mode" "0,1,2,3" bitfld.long 0x00 23. " VPBOUNDSINTSTATENA ,0: Bounds interrupt status is unchanged, 1: Bounds interrupt status is cleared." "0,1" textline " " bitfld.long 0x00 22. " VPBOUNDSINTENABLE ,0: Bounds interrupt disabled, 1: Bounds interrupt enabled." "0,1" bitfld.long 0x00 16.--18. " ERRWEIGHT ,The AvgSenError weight." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 8.--15. 1. " ERRMAXLIMIT ,The upper limit of SenError for interrupt generation." textline " " hexmask.long.byte 0x00 0.--7. 1. " ERRMINLIMIT ,The lower limit of SenError for interrupt generation." tree.end tree "SR_IVA" base ad:0x4A0DB000 width 18. group.long 0x0++0x3 line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing." hexmask.long.word 0x00 22.--31. 1. " ACCUMDATA ,Number of Values to Accumulate" hexmask.long.word 0x00 12.--21. 1. " SRCLKLENGTH ,Determines frequency of SRClk" bitfld.long 0x00 11. " SRENABLE ,0: Asynchronously resets MinMaxAvgAccumValid, MinMaxAvgValid, ErrorGeneratorValid, AccumData sensor, SRClk counter, and MinMaxAvg registers. Also gates the clock for power savings and disables all the digital logic. , 1: Enables .." "0,1" textline " " bitfld.long 0x00 10. " SENENABLE ,0: All sensors disabled, 1: Sensors enabled per SenNEnable and SenPEnable" "0,1" bitfld.long 0x00 9. " ERRORGENERATORENABLE ,0: Error Generator Module disabled, 1: Error Generator Module enabled" "0,1" bitfld.long 0x00 8. " MINMAXAVGENABLE ,0: MinMaxAvg Detector Module disabled, 1: MinMaxAvg Detector Module enabled" "0,1" textline " " bitfld.long 0x00 1. " SENNENABLE ,0: Disable SenN sensor, 1: Enable SenN sensor" "0,1" bitfld.long 0x00 0. " SENPENABLE ,0: Disable SenP sensor, 1: Enable SenP sensor" "0,1" rgroup.long 0x4++0x3 line.long 0x00 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred." bitfld.long 0x00 3. " AVGERRVALID ,0: AvgError registers are not valid, 1: AvgError registers are valid." "0,1" bitfld.long 0x00 2. " MINMAXAVGVALID ,0: SenVal, SenMin, SenMax, SenAvg registers are not valid, 1: SenVal, SenMin, SenMax, SenAvg registers are valid, but not necessarily fully accumulated" "0,1" bitfld.long 0x00 1. " ERRORGENERATORVALID ,0: SenError register do not have valid data, 1: SenError registers have valid data." "0,1" textline " " bitfld.long 0x00 0. " MINMAXAVGACCUMVALID ,0: SenVal, SenMin, SenMax, SenAvg registers are not valid, 1: SenVal, SenMin, SenMax, SenAvg registers have valid, final data" "0,1" rgroup.long 0x8++0x3 line.long 0x00 "SENVAL,The current sensor values from the Sensor Core." hexmask.long.word 0x00 16.--31. 1. " SENPVAL ,The latest value of the SenPVal from the sensor core." hexmask.long.word 0x00 0.--15. 1. " SENNVAL ,The latest value of the SenNVal from the sensor core." rgroup.long 0xC++0x3 line.long 0x00 "SENMIN,The minimum sensor values." hexmask.long.word 0x00 16.--31. 1. " SENPMIN ,The minimum value of the SenPVal from the sensor core since the last restat operation." hexmask.long.word 0x00 0.--15. 1. " SENNMIN ,The minimum value of the SenNVal from the sensor core since the last restat operation." rgroup.long 0x10++0x3 line.long 0x00 "SENMAX,The maximum sensor values." hexmask.long.word 0x00 16.--31. 1. " SENPMAX ,The maximum value of the SenPVal from the sensor core since the last restat operation." hexmask.long.word 0x00 0.--15. 1. " SENNMAX ,The maximum value of the SenNVal from the sensor core since the last restat operation." rgroup.long 0x14++0x3 line.long 0x00 "SENAVG,The average sensor values." hexmask.long.word 0x00 16.--31. 1. " SENPAVG ,The running average of the SenPVal from the sensor core since the last restat operation." hexmask.long.word 0x00 0.--15. 1. " SENNAVG ,The running average of the SenNVal from the sensor core since the last restat operation." group.long 0x18++0x3 line.long 0x00 "AVGWEIGHT,The weighting factor in the average computation." bitfld.long 0x00 2.--3. " SENPAVGWEIGHT ,The weighting factor for the SenP averager." "0,1,2,3" bitfld.long 0x00 0.--1. " SENNAVGWEIGHT ,The weighting factor for the SenN averager." "0,1,2,3" group.long 0x1C++0x3 line.long 0x00 "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation." bitfld.long 0x00 20.--23. " SENPGAIN ,The gain value for the SenP reciprocal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SENNGAIN ,The gain value for the SenN reciprocal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SENPRN ,The scale value for the SenP reciprocal." textline " " hexmask.long.byte 0x00 0.--7. 1. " SENNRN ,The scale value for the SenN reciprocal." group.long 0x24++0x3 line.long 0x00 "IRQSTATUS_RAW,MCU raw interrup status and set." bitfld.long 0x00 3. " MCUACCUMINTSTATRAW ,0: Accum interrupt status is unchanged 1: Accum interrupt status is set" "0,1" bitfld.long 0x00 2. " MCUVALIDINTSTATRAW ,0: Valid interrupt status is unchanged 1: Valid interrupt status is set" "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTSTATRAW ,0: Bounds interrupt status is unchanged 1: Bounds interrupt status is set" "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACKINTSTATRAW ,0: MCUDisable acknowledge status is unchanged 1: MCUDisable acknowledge status is set" "0,1" group.long 0x28++0x3 line.long 0x00 "IRQSTATUS,MCU masked interrupt status and clear." bitfld.long 0x00 3. " MCUACCUMINTSTATENA ,Read 0: Accum interrupt status is unchanged. - . - . - ." "0,1" bitfld.long 0x00 2. " MCUVALIDINTSTATENA ,Read 0: Valid interrupt status is unchanged. - . - . - ." "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTSTATENA ,Read 0: Bounds interrupt status is unchanged. - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACKINTSTATENA ,Read 0: MCUDisable acknowledge status is unchanged. - . - . - ." "0,1" group.long 0x2C++0x3 line.long 0x00 "IRQENABLE_SET,MCU interrupt enable flag and set." bitfld.long 0x00 3. " MCUACCUMINTENASET ,Read mode: 0: Accum interrupt generation is disabled/masked, 1: Accum interrupt generation is enabled; Write mode: 0: No change to Accum interrupt enable, 1: Enable Accum interrupt generation." "0,1" bitfld.long 0x00 2. " MCUVALIDINTENASET ,Read mode: 0: Valid interrupt generation is disabled/masked, 1: Valid interrupt generation is enabled; Write mode: 0: No change to Valid interrupt enable, 1: Enable Valid interrupt generation." "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTENASET ,Read mode: 0: Bounds interrupt generation is disabled/masked, 1: Bounds interrupt generation is enabled; Write mode: 0: No change to Bounds interrupt enable, 1: Enable Bounds interrupt generation." "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACTINTENASET ,Read mode: 0: MCUDisableAck interrupt generation is disabled/masked, 1: MCUDisableAck interrupt generation is enabled; Write mode: 0: No change to MCUDisAck interrupt enable, 1: Enable MCUDisableAck interrupt generation." "0,1" group.long 0x30++0x3 line.long 0x00 "IRQENABLE_CLR,MCU interrup enable flag and clear." bitfld.long 0x00 3. " MCUACCUMINTENACLR ,Read mode: 0: Accum interrupt generation is disabled/masked, 1: Accum interrupt generation is enabled; Write mode: 0: No change to Accum interrupt enable, 1: Enable Accum interrupt generation." "0,1" bitfld.long 0x00 2. " MCUVALIDINTENACLR ,Read mode: 0: Valid interrupt generation is disabled/masked, 1: Valid interrupt generation is enabled; Write mode: 0: No change to Valid interrupt enable, 1: Enable Valid interrupt generation." "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTENACLR ,Read mode: 0: Bounds interrupt generation is disabled/masked, 1: Bounds interrupt generation is enabled; Write mode: 0: No change to Bounds interrupt enable, 1: Enable Bounds interrupt generation." "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACKINTENACLR ,Read mode: 0: MCUDisableAck interrupt generation is disabled/masked, 1: MCUDisableAck interrupt generation is enabled; Write mode: 0: No change to MCUDisAck interrupt enable, 1: Enable MCUDisableAck interrupt generation." "0,1" rgroup.long 0x34++0x3 line.long 0x00 "SENERROR,The sensor error from the error generator." hexmask.long.byte 0x00 8.--15. 1. " AVGERROR ,The average sensor error." hexmask.long.byte 0x00 0.--7. 1. " SENERROR ,The percentage of sensor error." group.long 0x38++0x3 line.long 0x00 "ERRCONFIG,The sensor error configuration." bitfld.long 0x00 26. " WAKEUPENABLE ,Wakeup from MCU Interrupts enable." "0,1" bitfld.long 0x00 24.--25. " IDLEMODE ,0b00: Force-Idle Mode, 0b01: No Idle Mode, 0b10: Smart-Idle Mode #2, 0b11: Smart-Idle-Wkup mode" "0,1,2,3" bitfld.long 0x00 23. " VPBOUNDSINTSTATENA ,0: Bounds interrupt status is unchanged, 1: Bounds interrupt status is cleared." "0,1" textline " " bitfld.long 0x00 22. " VPBOUNDSINTENABLE ,0: Bounds interrupt disabled, 1: Bounds interrupt enabled." "0,1" bitfld.long 0x00 16.--18. " ERRWEIGHT ,The AvgSenError weight." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 8.--15. 1. " ERRMAXLIMIT ,The upper limit of SenError for interrupt generation." textline " " hexmask.long.byte 0x00 0.--7. 1. " ERRMINLIMIT ,The lower limit of SenError for interrupt generation." tree.end tree "SR_CORE" base ad:0x4A0DD000 width 18. group.long 0x0++0x3 line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing." hexmask.long.word 0x00 22.--31. 1. " ACCUMDATA ,Number of Values to Accumulate" hexmask.long.word 0x00 12.--21. 1. " SRCLKLENGTH ,Determines frequency of SRClk" bitfld.long 0x00 11. " SRENABLE ,0: Asynchronously resets MinMaxAvgAccumValid, MinMaxAvgValid, ErrorGeneratorValid, AccumData sensor, SRClk counter, and MinMaxAvg registers. Also gates the clock for power savings and disables all the digital logic. , 1: Enables .." "0,1" textline " " bitfld.long 0x00 10. " SENENABLE ,0: All sensors disabled, 1: Sensors enabled per SenNEnable and SenPEnable" "0,1" bitfld.long 0x00 9. " ERRORGENERATORENABLE ,0: Error Generator Module disabled, 1: Error Generator Module enabled" "0,1" bitfld.long 0x00 8. " MINMAXAVGENABLE ,0: MinMaxAvg Detector Module disabled, 1: MinMaxAvg Detector Module enabled" "0,1" textline " " bitfld.long 0x00 1. " SENNENABLE ,0: Disable SenN sensor, 1: Enable SenN sensor" "0,1" bitfld.long 0x00 0. " SENPENABLE ,0: Disable SenP sensor, 1: Enable SenP sensor" "0,1" rgroup.long 0x4++0x3 line.long 0x00 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred." bitfld.long 0x00 3. " AVGERRVALID ,0: AvgError registers are not valid, 1: AvgError registers are valid." "0,1" bitfld.long 0x00 2. " MINMAXAVGVALID ,0: SenVal, SenMin, SenMax, SenAvg registers are not valid, 1: SenVal, SenMin, SenMax, SenAvg registers are valid, but not necessarily fully accumulated" "0,1" bitfld.long 0x00 1. " ERRORGENERATORVALID ,0: SenError register do not have valid data, 1: SenError registers have valid data." "0,1" textline " " bitfld.long 0x00 0. " MINMAXAVGACCUMVALID ,0: SenVal, SenMin, SenMax, SenAvg registers are not valid, 1: SenVal, SenMin, SenMax, SenAvg registers have valid, final data" "0,1" rgroup.long 0x8++0x3 line.long 0x00 "SENVAL,The current sensor values from the Sensor Core." hexmask.long.word 0x00 16.--31. 1. " SENPVAL ,The latest value of the SenPVal from the sensor core." hexmask.long.word 0x00 0.--15. 1. " SENNVAL ,The latest value of the SenNVal from the sensor core." rgroup.long 0xC++0x3 line.long 0x00 "SENMIN,The minimum sensor values." hexmask.long.word 0x00 16.--31. 1. " SENPMIN ,The minimum value of the SenPVal from the sensor core since the last restat operation." hexmask.long.word 0x00 0.--15. 1. " SENNMIN ,The minimum value of the SenNVal from the sensor core since the last restat operation." rgroup.long 0x10++0x3 line.long 0x00 "SENMAX,The maximum sensor values." hexmask.long.word 0x00 16.--31. 1. " SENPMAX ,The maximum value of the SenPVal from the sensor core since the last restat operation." hexmask.long.word 0x00 0.--15. 1. " SENNMAX ,The maximum value of the SenNVal from the sensor core since the last restat operation." rgroup.long 0x14++0x3 line.long 0x00 "SENAVG,The average sensor values." hexmask.long.word 0x00 16.--31. 1. " SENPAVG ,The running average of the SenPVal from the sensor core since the last restat operation." hexmask.long.word 0x00 0.--15. 1. " SENNAVG ,The running average of the SenNVal from the sensor core since the last restat operation." group.long 0x18++0x3 line.long 0x00 "AVGWEIGHT,The weighting factor in the average computation." bitfld.long 0x00 2.--3. " SENPAVGWEIGHT ,The weighting factor for the SenP averager." "0,1,2,3" bitfld.long 0x00 0.--1. " SENNAVGWEIGHT ,The weighting factor for the SenN averager." "0,1,2,3" group.long 0x1C++0x3 line.long 0x00 "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation." bitfld.long 0x00 20.--23. " SENPGAIN ,The gain value for the SenP reciprocal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SENNGAIN ,The gain value for the SenN reciprocal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SENPRN ,The scale value for the SenP reciprocal." textline " " hexmask.long.byte 0x00 0.--7. 1. " SENNRN ,The scale value for the SenN reciprocal." group.long 0x24++0x3 line.long 0x00 "IRQSTATUS_RAW,MCU raw interrup status and set." bitfld.long 0x00 3. " MCUACCUMINTSTATRAW ,0: Accum interrupt status is unchanged 1: Accum interrupt status is set" "0,1" bitfld.long 0x00 2. " MCUVALIDINTSTATRAW ,0: Valid interrupt status is unchanged 1: Valid interrupt status is set" "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTSTATRAW ,0: Bounds interrupt status is unchanged 1: Bounds interrupt status is set" "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACKINTSTATRAW ,0: MCUDisable acknowledge status is unchanged 1: MCUDisable acknowledge status is set" "0,1" group.long 0x28++0x3 line.long 0x00 "IRQSTATUS,MCU masked interrupt status and clear." bitfld.long 0x00 3. " MCUACCUMINTSTATENA ,Read 0: Accum interrupt status is unchanged. - . - . - ." "0,1" bitfld.long 0x00 2. " MCUVALIDINTSTATENA ,Read 0: Valid interrupt status is unchanged. - . - . - ." "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTSTATENA ,Read 0: Bounds interrupt status is unchanged. - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACKINTSTATENA ,Read 0: MCUDisable acknowledge status is unchanged. - . - . - ." "0,1" group.long 0x2C++0x3 line.long 0x00 "IRQENABLE_SET,MCU interrupt enable flag and set." bitfld.long 0x00 3. " MCUACCUMINTENASET ,Read mode: 0: Accum interrupt generation is disabled/masked, 1: Accum interrupt generation is enabled; Write mode: 0: No change to Accum interrupt enable, 1: Enable Accum interrupt generation." "0,1" bitfld.long 0x00 2. " MCUVALIDINTENASET ,Read mode: 0: Valid interrupt generation is disabled/masked, 1: Valid interrupt generation is enabled; Write mode: 0: No change to Valid interrupt enable, 1: Enable Valid interrupt generation." "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTENASET ,Read mode: 0: Bounds interrupt generation is disabled/masked, 1: Bounds interrupt generation is enabled; Write mode: 0: No change to Bounds interrupt enable, 1: Enable Bounds interrupt generation." "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACTINTENASET ,Read mode: 0: MCUDisableAck interrupt generation is disabled/masked, 1: MCUDisableAck interrupt generation is enabled; Write mode: 0: No change to MCUDisAck interrupt enable, 1: Enable MCUDisableAck interrupt generation." "0,1" group.long 0x30++0x3 line.long 0x00 "IRQENABLE_CLR,MCU interrup enable flag and clear." bitfld.long 0x00 3. " MCUACCUMINTENACLR ,Read mode: 0: Accum interrupt generation is disabled/masked, 1: Accum interrupt generation is enabled; Write mode: 0: No change to Accum interrupt enable, 1: Enable Accum interrupt generation." "0,1" bitfld.long 0x00 2. " MCUVALIDINTENACLR ,Read mode: 0: Valid interrupt generation is disabled/masked, 1: Valid interrupt generation is enabled; Write mode: 0: No change to Valid interrupt enable, 1: Enable Valid interrupt generation." "0,1" bitfld.long 0x00 1. " MCUBOUNDSINTENACLR ,Read mode: 0: Bounds interrupt generation is disabled/masked, 1: Bounds interrupt generation is enabled; Write mode: 0: No change to Bounds interrupt enable, 1: Enable Bounds interrupt generation." "0,1" textline " " bitfld.long 0x00 0. " MCUDISABLEACKINTENACLR ,Read mode: 0: MCUDisableAck interrupt generation is disabled/masked, 1: MCUDisableAck interrupt generation is enabled; Write mode: 0: No change to MCUDisAck interrupt enable, 1: Enable MCUDisableAck interrupt generation." "0,1" rgroup.long 0x34++0x3 line.long 0x00 "SENERROR,The sensor error from the error generator." hexmask.long.byte 0x00 8.--15. 1. " AVGERROR ,The average sensor error." hexmask.long.byte 0x00 0.--7. 1. " SENERROR ,The percentage of sensor error." group.long 0x38++0x3 line.long 0x00 "ERRCONFIG,The sensor error configuration." bitfld.long 0x00 26. " WAKEUPENABLE ,Wakeup from MCU Interrupts enable." "0,1" bitfld.long 0x00 24.--25. " IDLEMODE ,0b00: Force-Idle Mode, 0b01: No Idle Mode, 0b10: Smart-Idle Mode #2, 0b11: Smart-Idle-Wkup mode" "0,1,2,3" bitfld.long 0x00 23. " VPBOUNDSINTSTATENA ,0: Bounds interrupt status is unchanged, 1: Bounds interrupt status is cleared." "0,1" textline " " bitfld.long 0x00 22. " VPBOUNDSINTENABLE ,0: Bounds interrupt disabled, 1: Bounds interrupt enabled." "0,1" bitfld.long 0x00 16.--18. " ERRWEIGHT ,The AvgSenError weight." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 8.--15. 1. " ERRMAXLIMIT ,The upper limit of SenError for interrupt generation." textline " " hexmask.long.byte 0x00 0.--7. 1. " ERRMINLIMIT ,The lower limit of SenError for interrupt generation." tree.end tree.end tree.end tree.open "Dual_Cortex_A9_MPU_Subsystem" tree "CORTEXA9_SOCKET_PRCM" base ad:0x48243000 width 24. rgroup.long 0x0++0x3 line.long 0x00 "CORTEXA9_PRCM_REVISION,IP Revision register" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" tree.end tree.open "CORTEXA9_CPU0" tree "CORTEXA9_CPU0" base ad:0x48243400 width 23. group.long 0x0++0x3 line.long 0x00 "PM_PDA_CPUi_PWRSTCTRL,This register controls the CPU domain power state to reach upon a domain sleep transition" bitfld.long 0x00 16.--17. " L1_BANK_ONSTATE ,CPU_L1 memory state when domain is ON. - ." "0,1,2,3" bitfld.long 0x00 8. " L1_BANK_RETSTATE ,CPU L1 memory state when domain is RETENTION state. - ." "0,1" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state control when power domain is RETENTION - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "OFF_state,RETENTION_state,INACTIVE_state,ON_State" group.long 0x4++0x3 line.long 0x00 "PM_PDA_CPUi_PWRSTST,This register provides a status on the CPU domain current power state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. The software has to write 0x3 in this field to update this register. 0x0: Power domain was previously in OFF 0x1: Power domain was previously in RETENTION 0x2: Power domain was previously INACTIVE 0.." "0,1,2,3" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "0,1" bitfld.long 0x00 4.--5. " L1_BANK_STATEST ,CPU_L1 memory state status - . - . - . - ." "Memory_is_OFF,Memory_is_RET,Reserved,Memory_is_ON" textline " " bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "0,1" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "0,1,2,3" group.long 0x8++0x3 line.long 0x00 "RM_PDA_CPUi_CONTEXT,This register contains dedicated CPU context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_CPU_L1 ,Specify if memory-based context in CPU_L1 memory bank has been lost due to a previous power transition or other reset source. - . - ." "0,1" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. - . - ." "0,1" group.long 0xC++0x3 line.long 0x00 "RM_PDA_CPUi_RSTCTRL,This register controls the assertion/release of the CPU CORE reset. This is basically a software warm reset (that asserts CPUx_RST) per CPU. One CPU can set this bit to reset the other CPU. Actually the CPU can set this bit to reset.." bitfld.long 0x00 0. " RST ,CPU warm local reset control - . - ." "Reset_is_cleared,Reset_is_asserted" rgroup.long 0x14++0x3 line.long 0x00 "CM_PDA_CPUi_CLKCTRL,This register manages the CPU clocks." bitfld.long 0x00 0. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "0,1" group.long 0x18++0x3 line.long 0x00 "CM_PDA_CPUi_CLKSTCTRL,This register enables the CPU domain power state transition. It controls the hardware-supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the full domain transition of the CPU domain. - . - . - . - ." "0,Reserved,2,3" tree.end tree "CORTEXA9_CPU1" base ad:0x48243800 width 23. group.long 0x0++0x3 line.long 0x00 "PM_PDA_CPUi_PWRSTCTRL,This register controls the CPU domain power state to reach upon a domain sleep transition" bitfld.long 0x00 16.--17. " L1_BANK_ONSTATE ,CPU_L1 memory state when domain is ON. - ." "0,1,2,3" bitfld.long 0x00 8. " L1_BANK_RETSTATE ,CPU L1 memory state when domain is RETENTION state. - ." "0,1" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state control when power domain is RETENTION - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control - . - . - . - ." "OFF_state,RETENTION_state,INACTIVE_state,ON_State" group.long 0x4++0x3 line.long 0x00 "PM_PDA_CPUi_PWRSTST,This register provides a status on the CPU domain current power state. [warm reset insensitive]" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. The software has to write 0x3 in this field to update this register. 0x0: Power domain was previously in OFF 0x1: Power domain was previously in RETENTION 0x2: Power domain was previously INACTIVE 0.." "0,1,2,3" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status - . - ." "0,1" bitfld.long 0x00 4.--5. " L1_BANK_STATEST ,CPU_L1 memory state status - . - . - . - ." "Memory_is_OFF,Memory_is_RET,Reserved,Memory_is_ON" textline " " bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status - . - ." "0,1" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status - . - . - . - ." "0,1,2,3" group.long 0x8++0x3 line.long 0x00 "RM_PDA_CPUi_CONTEXT,This register contains dedicated CPU context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_CPU_L1 ,Specify if memory-based context in CPU_L1 memory bank has been lost due to a previous power transition or other reset source. - . - ." "0,1" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. - . - ." "0,1" group.long 0xC++0x3 line.long 0x00 "RM_PDA_CPUi_RSTCTRL,This register controls the assertion/release of the CPU CORE reset. This is basically a software warm reset (that asserts CPUx_RST) per CPU. One CPU can set this bit to reset the other CPU. Actually the CPU can set this bit to reset.." bitfld.long 0x00 0. " RST ,CPU warm local reset control - . - ." "Reset_is_cleared,Reset_is_asserted" rgroup.long 0x14++0x3 line.long 0x00 "CM_PDA_CPUi_CLKCTRL,This register manages the CPU clocks." bitfld.long 0x00 0. " STBYST ,Module standby status. [warm reset insensitive] - . - ." "0,1" group.long 0x18++0x3 line.long 0x00 "CM_PDA_CPUi_CLKSTCTRL,This register enables the CPU domain power state transition. It controls the hardware-supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the full domain transition of the CPU domain. - . - . - . - ." "0,Reserved,2,3" tree.end tree.end tree "CORTEXA9_WUGEN" base ad:0x48281000 width 17. rgroup.long 0x0++0x3 line.long 0x00 "WKG_CONTROL_0,Wake-up generator status register for CPU0" bitfld.long 0x00 15. " DOMAIN_RST ,MPU always-on power domain (PD_ALWON_MPU) reset status bit. It shows if the the reset occurred previously. 0x0: no reset occur 0x1: reset occur" "0,1" bitfld.long 0x00 14. " CORTEXA9_WARM_RST ,This bit is set when the CORTEXA9_RSTN signal is asserted. 0x0: CORTEXA9_RSTN reset signal has not been asserted 0x1: CORTEXA9_RSTN reset request has been asserted" "0,1" bitfld.long 0x00 13. " CORTEXA9_COLD_RST ,This bit is set when the CORTEXA9_PWRON_RSTN signal is asserted. 0x0: CORTEXA9_PWRON_RSTN reset signal has not been asserted 0x1: CORTEXA9_PWRON_RSTN reset request has been asserted" "0,1" textline " " bitfld.long 0x00 12. " WDT_RST ,This bit is set when the WD timer Reset Request signal from the SCU is asserted. 0x0: WDT reset request has not been asserted 0x1: WDT reset request has been asserted" "0,1" bitfld.long 0x00 10. " EVENTO ,EVENTO status bit. The event output signal is active, when one SEV instruction is executed. This bit is set when a rising edge of EVENTO from CPU is detected. 0x0: Rising edge of EVENTO is not detected 0x1: Rising edge of .." "0,1" bitfld.long 0x00 9. " STANDBYWFE ,This bit gives software the visibility to track whether WFE mode have been entered. 0x0: WFE mode has not been entered 0x1: WFE mode has been entered" "0,1" textline " " bitfld.long 0x00 8. " STANDBYWFI ,This bit gives software the visibility to track whether WFI mode have been entered. 0x0: WFI mode has not been entered 0x1: WFI mode has been entered" "0,1" group.long 0x10++0x3 line.long 0x00 "WKG_ENB_A_0,This register enables the interrupts (for CPU0) from MA_IRQ_0 to MA_IRQ_31 write 0x0: disable interrupt write 0x1: enable interrupt" bitfld.long 0x00 31. " WKG_ENB_FOR_INTR31 ," "0,1" bitfld.long 0x00 30. " WKG_ENB_FOR_INTR30 ," "0,1" bitfld.long 0x00 29. " WKG_ENB_FOR_INTR29 ," "0,1" textline " " bitfld.long 0x00 28. " WKG_ENB_FOR_INTR28 ," "0,1" bitfld.long 0x00 27. " WKG_ENB_FOR_INTR27 ," "0,1" bitfld.long 0x00 26. " WKG_ENB_FOR_INTR26 ," "0,1" textline " " bitfld.long 0x00 25. " WKG_ENB_FOR_INTR25 ," "0,1" bitfld.long 0x00 24. " WKG_ENB_FOR_INTR24 ," "0,1" bitfld.long 0x00 23. " WKG_ENB_FOR_INTR23 ," "0,1" textline " " bitfld.long 0x00 22. " WKG_ENB_FOR_INTR22 ," "0,1" bitfld.long 0x00 21. " WKG_ENB_FOR_INTR21 ," "0,1" bitfld.long 0x00 20. " WKG_ENB_FOR_INTR20 ," "0,1" textline " " bitfld.long 0x00 19. " WKG_ENB_FOR_INTR19 ," "0,1" bitfld.long 0x00 18. " WKG_ENB_FOR_INTR18 ," "0,1" bitfld.long 0x00 17. " WKG_ENB_FOR_INTR17 ," "0,1" textline " " bitfld.long 0x00 16. " WKG_ENB_FOR_INTR16 ," "0,1" bitfld.long 0x00 15. " WKG_ENB_FOR_INTR15 ," "0,1" bitfld.long 0x00 14. " WKG_ENB_FOR_INTR14 ," "0,1" textline " " bitfld.long 0x00 13. " WKG_ENB_FOR_INTR13 ," "0,1" bitfld.long 0x00 12. " WKG_ENB_FOR_INTR12 ," "0,1" bitfld.long 0x00 11. " WKG_ENB_FOR_INTR11 ," "0,1" textline " " bitfld.long 0x00 10. " WKG_ENB_FOR_INTR10 ," "0,1" bitfld.long 0x00 9. " WKG_ENB_FOR_INTR9 ," "0,1" bitfld.long 0x00 7. " WKG_ENB_FOR_INTR7 ," "0,1" textline " " bitfld.long 0x00 4. " WKG_ENB_FOR_INTR4 ," "0,1" bitfld.long 0x00 2. " WKG_ENB_FOR_INTR2 ," "0,1" bitfld.long 0x00 1. " WKG_ENB_FOR_INTR1 ," "0,1" textline " " bitfld.long 0x00 0. " WKG_ENB_FOR_INTR0 ," "0,1" group.long 0x14++0x3 line.long 0x00 "WKG_ENB_B_0,This register enables the interrupts (for CPU0) from MA_IRQ_32 to MA_IRQ_63 write 0x0: disable interrupt write 0x1: enable interrupt" bitfld.long 0x00 30. " WKG_ENB_FOR_INTR62 ," "0,1" bitfld.long 0x00 29. " WKG_ENB_FOR_INTR61 ," "0,1" bitfld.long 0x00 27. " WKG_ENB_FOR_INTR59 ," "0,1" textline " " bitfld.long 0x00 26. " WKG_ENB_FOR_INTR58 ," "0,1" bitfld.long 0x00 25. " WKG_ENB_FOR_INTR57 ," "0,1" bitfld.long 0x00 24. " WKG_ENB_FOR_INTR56 ," "0,1" textline " " bitfld.long 0x00 21. " WKG_ENB_FOR_INTR53 ," "0,1" bitfld.long 0x00 16. " WKG_ENB_FOR_INTR48 ," "0,1" bitfld.long 0x00 15. " WKG_ENB_FOR_INTR47 ," "0,1" textline " " bitfld.long 0x00 14. " WKG_ENB_FOR_INTR46 ," "0,1" bitfld.long 0x00 13. " WKG_ENB_FOR_INTR45 ," "0,1" bitfld.long 0x00 12. " WKG_ENB_FOR_INTR44 ," "0,1" textline " " bitfld.long 0x00 11. " WKG_ENB_FOR_INTR43 ," "0,1" bitfld.long 0x00 10. " WKG_ENB_FOR_INTR42 ," "0,1" bitfld.long 0x00 9. " WKG_ENB_FOR_INTR41 ," "0,1" textline " " bitfld.long 0x00 8. " WKG_ENB_FOR_INTR40 ," "0,1" bitfld.long 0x00 7. " WKG_ENB_FOR_INTR39 ," "0,1" bitfld.long 0x00 6. " WKG_ENB_FOR_INTR38 ," "0,1" textline " " bitfld.long 0x00 5. " WKG_ENB_FOR_INTR37 ," "0,1" bitfld.long 0x00 4. " WKG_ENB_FOR_INTR36 ," "0,1" bitfld.long 0x00 2. " WKG_ENB_FOR_INTR34 ," "0,1" textline " " bitfld.long 0x00 1. " WKG_ENB_FOR_INTR33 ," "0,1" bitfld.long 0x00 0. " WKG_ENB_FOR_INTR32 ," "0,1" group.long 0x18++0x3 line.long 0x00 "WKG_ENB_C_0,This register enables the interrupts (for CPU0) from MA_IRQ_64 to MA_IRQ_95 write 0x0: disable interrupt write 0x1: enable interrupt" bitfld.long 0x00 30. " WKG_ENB_FOR_INTR94 ," "0,1" bitfld.long 0x00 29. " WKG_ENB_FOR_INTR93 ," "0,1" bitfld.long 0x00 28. " WKG_ENB_FOR_INTR92 ," "0,1" textline " " bitfld.long 0x00 27. " WKG_ENB_FOR_INTR91 ," "0,1" bitfld.long 0x00 26. " WKG_ENB_FOR_INTR90 ," "0,1" bitfld.long 0x00 25. " WKG_ENB_FOR_INTR89 ," "0,1" textline " " bitfld.long 0x00 24. " WKG_ENB_FOR_INTR88 ," "0,1" bitfld.long 0x00 23. " WKG_ENB_FOR_INTR87 ," "0,1" bitfld.long 0x00 22. " WKG_ENB_FOR_INTR86 ," "0,1" textline " " bitfld.long 0x00 20. " WKG_ENB_FOR_INTR84 ," "0,1" bitfld.long 0x00 19. " WKG_ENB_FOR_INTR83 ," "0,1" bitfld.long 0x00 16. " WKG_ENB_FOR_INTR80 ," "0,1" textline " " bitfld.long 0x00 14. " WKG_ENB_FOR_INTR78 ," "0,1" bitfld.long 0x00 13. " WKG_ENB_FOR_INTR77 ," "0,1" bitfld.long 0x00 12. " WKG_ENB_FOR_INTR76 ," "0,1" textline " " bitfld.long 0x00 11. " WKG_ENB_FOR_INTR75 ," "0,1" bitfld.long 0x00 10. " WKG_ENB_FOR_INTR74 ," "0,1" bitfld.long 0x00 9. " WKG_ENB_FOR_INTR73 ," "0,1" textline " " bitfld.long 0x00 8. " WKG_ENB_FOR_INTR72 ," "0,1" bitfld.long 0x00 7. " WKG_ENB_FOR_INTR71 ," "0,1" bitfld.long 0x00 6. " WKG_ENB_FOR_INTR70 ," "0,1" textline " " bitfld.long 0x00 5. " WKG_ENB_FOR_INTR69 ," "0,1" bitfld.long 0x00 4. " WKG_ENB_FOR_INTR68 ," "0,1" bitfld.long 0x00 3. " WKG_ENB_FOR_INTR67 ," "0,1" textline " " bitfld.long 0x00 2. " WKG_ENB_FOR_INTR66 ," "0,1" bitfld.long 0x00 1. " WKG_ENB_FOR_INTR65 ," "0,1" group.long 0x1C++0x3 line.long 0x00 "WKG_ENB_D_0,This register enables the interrupts (for CPU0) from MA_IRQ_96 to MA_IRQ_127 write 0x0: disable interrupt write 0x1: enable interrupt" bitfld.long 0x00 24. " WKG_ENB_FOR_INTR120 ," "0,1" bitfld.long 0x00 23. " WKG_ENB_FOR_INTR119 ," "0,1" bitfld.long 0x00 18. " WKG_ENB_FOR_INTR114 ," "0,1" textline " " bitfld.long 0x00 17. " WKG_ENB_FOR_INTR113 ," "0,1" bitfld.long 0x00 16. " WKG_ENB_FOR_INTR112 ," "0,1" bitfld.long 0x00 15. " WKG_ENB_FOR_INTR111 ," "0,1" textline " " bitfld.long 0x00 14. " WKG_ENB_FOR_INTR110 ," "0,1" bitfld.long 0x00 13. " WKG_ENB_FOR_INTR109 ," "0,1" bitfld.long 0x00 11. " WKG_ENB_FOR_INTR107 ," "0,1" textline " " bitfld.long 0x00 8. " WKG_ENB_FOR_INTR104 ," "0,1" bitfld.long 0x00 7. " WKG_ENB_FOR_INTR103 ," "0,1" bitfld.long 0x00 6. " WKG_ENB_FOR_INTR102 ," "0,1" textline " " bitfld.long 0x00 5. " WKG_ENB_FOR_INTR101 ," "0,1" bitfld.long 0x00 4. " WKG_ENB_FOR_INTR100 ," "0,1" bitfld.long 0x00 3. " WKG_ENB_FOR_INTR99 ," "0,1" textline " " bitfld.long 0x00 2. " WKG_ENB_FOR_INTR98 ," "0,1" bitfld.long 0x00 1. " WKG_ENB_FOR_INTR97 ," "0,1" bitfld.long 0x00 0. " WKG_ENB_FOR_INTR96 ," "0,1" rgroup.long 0x400++0x3 line.long 0x00 "WKG_CONTROL_1,Wake-up generator status register for CPU1" bitfld.long 0x00 15. " DOMAIN_RST ,MPU always-on power domain (PD_ALWON_MPU) reset status bit. It shows if the the reset occurred previously. 0x0: no reset occur 0x1: reset occur" "0,1" bitfld.long 0x00 14. " CORTEXA9_WARM_RST ,This bit is set when the CORTEXA9_RSTN signal is asserted. 0x0: CORTEXA9_RSTN reset signal has not been asserted 0x1: CORTEXA9_RSTN reset request has been asserted" "0,1" bitfld.long 0x00 13. " CORTEXA9_COLD_RST ,This bit is set when the CORTEXA9_PWRON_RSTN signal is asserted. 0x0: CORTEXA9_PWRON_RSTN reset signal has not been asserted 0x1: CORTEXA9_PWRON_RSTN reset request has been asserted" "0,1" textline " " bitfld.long 0x00 12. " WDT_RST ,This bit is set when the WD timer Reset Request signal from the SCU is asserted. 0x0: WDT reset request has not been asserted 0x1: WDT reset request has been asserted" "0,1" bitfld.long 0x00 10. " EVENTO ,EVENTO status bit. The event output signal is active, when one SEV instruction is executed. This bit is set when a rising edge of EVENTO from CPU is detected. 0x0: Rising edge of EVENTO is not detected 0x1: Rising edge of .." "0,1" bitfld.long 0x00 9. " STANDBYWFE ,This bit gives software the visibility to track whether WFE mode have been entered. 0x0: WFE mode has not been entered 0x1: WFE mode has been entered" "0,1" textline " " bitfld.long 0x00 8. " STANDBYWFI ,This bit gives software the visibility to track whether WFI mode have been entered. 0x0: WFI mode has not been entered 0x1: WFI mode has been entered" "0,1" group.long 0x410++0x3 line.long 0x00 "WKG_ENB_A_1,This register enables the interrupts (for CPU1) from MA_IRQ_0 to MA_IRQ_31 write 0x0: disable interrupt write 0x1: enable interrupt" bitfld.long 0x00 31. " WKG_ENB_FOR_INTR31 ," "0,1" bitfld.long 0x00 30. " WKG_ENB_FOR_INTR30 ," "0,1" bitfld.long 0x00 29. " WKG_ENB_FOR_INTR29 ," "0,1" textline " " bitfld.long 0x00 28. " WKG_ENB_FOR_INTR28 ," "0,1" bitfld.long 0x00 27. " WKG_ENB_FOR_INTR27 ," "0,1" bitfld.long 0x00 26. " WKG_ENB_FOR_INTR26 ," "0,1" textline " " bitfld.long 0x00 25. " WKG_ENB_FOR_INTR25 ," "0,1" bitfld.long 0x00 24. " WKG_ENB_FOR_INTR24 ," "0,1" bitfld.long 0x00 23. " WKG_ENB_FOR_INTR23 ," "0,1" textline " " bitfld.long 0x00 22. " WKG_ENB_FOR_INTR22 ," "0,1" bitfld.long 0x00 21. " WKG_ENB_FOR_INTR21 ," "0,1" bitfld.long 0x00 20. " WKG_ENB_FOR_INTR20 ," "0,1" textline " " bitfld.long 0x00 19. " WKG_ENB_FOR_INTR19 ," "0,1" bitfld.long 0x00 18. " WKG_ENB_FOR_INTR18 ," "0,1" bitfld.long 0x00 17. " WKG_ENB_FOR_INTR17 ," "0,1" textline " " bitfld.long 0x00 16. " WKG_ENB_FOR_INTR16 ," "0,1" bitfld.long 0x00 15. " WKG_ENB_FOR_INTR15 ," "0,1" bitfld.long 0x00 14. " WKG_ENB_FOR_INTR14 ," "0,1" textline " " bitfld.long 0x00 13. " WKG_ENB_FOR_INTR13 ," "0,1" bitfld.long 0x00 12. " WKG_ENB_FOR_INTR12 ," "0,1" bitfld.long 0x00 11. " WKG_ENB_FOR_INTR11 ," "0,1" textline " " bitfld.long 0x00 10. " WKG_ENB_FOR_INTR10 ," "0,1" bitfld.long 0x00 9. " WKG_ENB_FOR_INTR9 ," "0,1" bitfld.long 0x00 7. " WKG_ENB_FOR_INTR7 ," "0,1" textline " " bitfld.long 0x00 4. " WKG_ENB_FOR_INTR4 ," "0,1" bitfld.long 0x00 2. " WKG_ENB_FOR_INTR2 ," "0,1" bitfld.long 0x00 1. " WKG_ENB_FOR_INTR1 ," "0,1" textline " " bitfld.long 0x00 0. " WKG_ENB_FOR_INTR0 ," "0,1" group.long 0x414++0x3 line.long 0x00 "WKG_ENB_B_1,This register enables the interrupts (for CPU1) from MA_IRQ_32 to MA_IRQ_63 write 0x0: disable interrupt write 0x1: enable interrupt" bitfld.long 0x00 30. " WKG_ENB_FOR_INTR62 ," "0,1" bitfld.long 0x00 29. " WKG_ENB_FOR_INTR61 ," "0,1" bitfld.long 0x00 27. " WKG_ENB_FOR_INTR59 ," "0,1" textline " " bitfld.long 0x00 26. " WKG_ENB_FOR_INTR58 ," "0,1" bitfld.long 0x00 25. " WKG_ENB_FOR_INTR57 ," "0,1" bitfld.long 0x00 24. " WKG_ENB_FOR_INTR56 ," "0,1" textline " " bitfld.long 0x00 21. " WKG_ENB_FOR_INTR53 ," "0,1" bitfld.long 0x00 16. " WKG_ENB_FOR_INTR48 ," "0,1" bitfld.long 0x00 15. " WKG_ENB_FOR_INTR47 ," "0,1" textline " " bitfld.long 0x00 14. " WKG_ENB_FOR_INTR46 ," "0,1" bitfld.long 0x00 13. " WKG_ENB_FOR_INTR45 ," "0,1" bitfld.long 0x00 12. " WKG_ENB_FOR_INTR44 ," "0,1" textline " " bitfld.long 0x00 11. " WKG_ENB_FOR_INTR43 ," "0,1" bitfld.long 0x00 10. " WKG_ENB_FOR_INTR42 ," "0,1" bitfld.long 0x00 9. " WKG_ENB_FOR_INTR41 ," "0,1" textline " " bitfld.long 0x00 8. " WKG_ENB_FOR_INTR40 ," "0,1" bitfld.long 0x00 7. " WKG_ENB_FOR_INTR39 ," "0,1" bitfld.long 0x00 6. " WKG_ENB_FOR_INTR38 ," "0,1" textline " " bitfld.long 0x00 5. " WKG_ENB_FOR_INTR37 ," "0,1" bitfld.long 0x00 4. " WKG_ENB_FOR_INTR36 ," "0,1" bitfld.long 0x00 2. " WKG_ENB_FOR_INTR34 ," "0,1" textline " " bitfld.long 0x00 1. " WKG_ENB_FOR_INTR33 ," "0,1" bitfld.long 0x00 0. " WKG_ENB_FOR_INTR32 ," "0,1" group.long 0x418++0x3 line.long 0x00 "WKG_ENB_C_1,This register enables the interrupts (for CPU1) from MA_IRQ_64 to MA_IRQ_95 write 0x0: disable interrupt write 0x1: enable interrupt" bitfld.long 0x00 30. " WKG_ENB_FOR_INTR94 ," "0,1" bitfld.long 0x00 29. " WKG_ENB_FOR_INTR93 ," "0,1" bitfld.long 0x00 28. " WKG_ENB_FOR_INTR92 ," "0,1" textline " " bitfld.long 0x00 27. " WKG_ENB_FOR_INTR91 ," "0,1" bitfld.long 0x00 26. " WKG_ENB_FOR_INTR90 ," "0,1" bitfld.long 0x00 25. " WKG_ENB_FOR_INTR89 ," "0,1" textline " " bitfld.long 0x00 24. " WKG_ENB_FOR_INTR88 ," "0,1" bitfld.long 0x00 23. " WKG_ENB_FOR_INTR87 ," "0,1" bitfld.long 0x00 22. " WKG_ENB_FOR_INTR86 ," "0,1" textline " " bitfld.long 0x00 20. " WKG_ENB_FOR_INTR84 ," "0,1" bitfld.long 0x00 19. " WKG_ENB_FOR_INTR83 ," "0,1" bitfld.long 0x00 16. " WKG_ENB_FOR_INTR80 ," "0,1" textline " " bitfld.long 0x00 14. " WKG_ENB_FOR_INTR78 ," "0,1" bitfld.long 0x00 13. " WKG_ENB_FOR_INTR77 ," "0,1" bitfld.long 0x00 12. " WKG_ENB_FOR_INTR76 ," "0,1" textline " " bitfld.long 0x00 11. " WKG_ENB_FOR_INTR75 ," "0,1" bitfld.long 0x00 10. " WKG_ENB_FOR_INTR74 ," "0,1" bitfld.long 0x00 9. " WKG_ENB_FOR_INTR73 ," "0,1" textline " " bitfld.long 0x00 8. " WKG_ENB_FOR_INTR72 ," "0,1" bitfld.long 0x00 7. " WKG_ENB_FOR_INTR71 ," "0,1" bitfld.long 0x00 6. " WKG_ENB_FOR_INTR70 ," "0,1" textline " " bitfld.long 0x00 5. " WKG_ENB_FOR_INTR69 ," "0,1" bitfld.long 0x00 4. " WKG_ENB_FOR_INTR68 ," "0,1" bitfld.long 0x00 3. " WKG_ENB_FOR_INTR67 ," "0,1" textline " " bitfld.long 0x00 2. " WKG_ENB_FOR_INTR66 ," "0,1" bitfld.long 0x00 1. " WKG_ENB_FOR_INTR65 ," "0,1" group.long 0x41C++0x3 line.long 0x00 "WKG_ENB_D_1,This register enables the interrupts (for CPU1) from MA_IRQ_96 to MA_IRQ_127 write 0x0: disable interrupt write 0x1: enable interrupt" bitfld.long 0x00 24. " WKG_ENB_FOR_INTR120 ," "0,1" bitfld.long 0x00 23. " WKG_ENB_FOR_INTR119 ," "0,1" bitfld.long 0x00 18. " WKG_ENB_FOR_INTR114 ," "0,1" textline " " bitfld.long 0x00 17. " WKG_ENB_FOR_INTR113 ," "0,1" bitfld.long 0x00 16. " WKG_ENB_FOR_INTR112 ," "0,1" bitfld.long 0x00 15. " WKG_ENB_FOR_INTR111 ," "0,1" textline " " bitfld.long 0x00 14. " WKG_ENB_FOR_INTR110 ," "0,1" bitfld.long 0x00 13. " WKG_ENB_FOR_INTR109 ," "0,1" bitfld.long 0x00 11. " WKG_ENB_FOR_INTR107 ," "0,1" textline " " bitfld.long 0x00 8. " WKG_ENB_FOR_INTR104 ," "0,1" bitfld.long 0x00 7. " WKG_ENB_FOR_INTR103 ," "0,1" bitfld.long 0x00 6. " WKG_ENB_FOR_INTR102 ," "0,1" textline " " bitfld.long 0x00 5. " WKG_ENB_FOR_INTR101 ," "0,1" bitfld.long 0x00 4. " WKG_ENB_FOR_INTR100 ," "0,1" bitfld.long 0x00 3. " WKG_ENB_FOR_INTR99 ," "0,1" textline " " bitfld.long 0x00 2. " WKG_ENB_FOR_INTR98 ," "0,1" bitfld.long 0x00 1. " WKG_ENB_FOR_INTR97 ," "0,1" bitfld.long 0x00 0. " WKG_ENB_FOR_INTR96 ," "0,1" group.long 0x800++0x3 line.long 0x00 "AUX_CORE_BOOT_0,This register is used by the ROM code and OS during SMP boot. It is intended to store the execution start address of CPU1. When needed, the SMP OS (executing on CPU0) wakes up CPU1 by executing a SEV command. CPU0 must communicate some .." hexmask.long 0x00 0.--31. 1. " AUX_CORE_BOOT_0 ,SMP boot" group.long 0x804++0x3 line.long 0x00 "AUX_CORE_BOOT_1,This register is used by the ROM code and OS during SMP boot. It is used to indicate the boot status to either CPU. When CPU1 receives an event (caused by the SEV command), it continues execution in the ROM, which set up the code to bra.." hexmask.long 0x00 0.--31. 1. " AUX_CORE_BOOT_1 ,SMP boot" tree.end tree "CORTEXA9_PRM" base ad:0x48243200 width 17. group.long 0x0++0x3 line.long 0x00 "PRM_RSTST,This register logs the global reset sources, thus contains information regarding the cold/warm reset events generated by global PRCM. Each bit is set upon release of the domain reset signal. Must be cleared by software." eventfld.long 0x00 1. " GLOBAL_WARM_RST ,Global warm reset event generated by Global PRCM - . - ." "0,1" eventfld.long 0x00 0. " GLOBAL_COLD_RST ,Power-on (cold) reset event generated by global PRCM - . - ." "No_reset,Reset" group.long 0x4++0x3 line.long 0x00 "PRM_PSCON_COUNT,Programmable Precharge count for L1Cache. This register is useful to ensure the correct delay between toggles of pscon lines and therefore to avoid Any problem of power switch transitions. The register corresponds to the number of devic.." bitfld.long 0x00 28.--31. " SPAREUSED ,4 bits consumed for Last Power State Entered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 8.--27. 1. " SPARE ,Spare programmable bits" hexmask.long.byte 0x00 0.--7. 1. " PCHARGE_TIME ,Programmable Precharge count during retention" tree.end tree.end tree.open "IVA_HD" tree.open "SYSCTRL_iCONT" tree "SYSCTRL_L3Interconnect" base ad:0x5A05A400 width 26. rgroup.long 0x0++0x3 line.long 0x00 "IVAHD_REVISION,IP revision identifier (X.Y.R). Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" rgroup.long 0x4++0x3 line.long 0x00 "IVAHD_HWINFO,Information about the IP module's hardware configuration." bitfld.long 0x00 14. " ECD3 ,ECD3 available 0: ECD3 not present 1: ECD3 present" "0,1" bitfld.long 0x00 13. " MC3 ,MC3 available 0: MC3 not present 1: MC3 present" "0,1" bitfld.long 0x00 12. " IPE3 ,iPE3 available 0: iPE3 not present 1: iPE3 present" "0,1" textline " " bitfld.long 0x00 11. " CALC3 ,CALC3 available 0: CALC3 not present 1: CALC3 present" "0,1" bitfld.long 0x00 10. " IME3 ,iME3 available 0: iME3 not present 1: iME3 present" "0,1" bitfld.long 0x00 9. " ILF3 ,iLF3 available 0: iLF3 not present 1: iLF3 present" "0,1" textline " " bitfld.long 0x00 8. " VDMA ,vDMA available 0: vDMA not present 1: vDMA present" "0,1" bitfld.long 0x00 7. " ICONT2 ,iCONT2 available 0: iCONT2 not present 1: iCONT2 present" "0,1" bitfld.long 0x00 6. " ICONT1 ,iCONT1 available 0: iCONT1 not present 1: iCONT1 present" "0,1" textline " " bitfld.long 0x00 4.--5. " SL2BANK ,- . - . - . - ." "1bank,2bank,4bank,8bank" bitfld.long 0x00 0.--3. " SL2SIZE ,Size of SL2 memory - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "0,16kB,32kB,48kB,64kB,96kB,128kB,160kB,192kB,224kB,256kB,320kB,384kB,448kB,512kB,15" group.long 0x10++0x3 line.long 0x00 "IVAHD_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state.0x0 and 0x3: Reserved. - . - . - ." "0,no,smart,3" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state.0x0 and 0x3: Reserved. - . - . - ." "0,no,smart,3" group.long 0x24++0x3 line.long 0x00 "IVAHD_IRQSTATUS_RAW,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 0. " SYSCTRL_CLKERR ,Settable raw status for Clock Programming Error event - . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x28++0x3 line.long 0x00 "IVAHD_IRQSTATUS,Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x00 0. " SYSCTRL_CLKERR ,Clearable, enabled status for Clock Programming Error event - . - . - . - ." "noaction_/_noevent,clear_/_pending" group.long 0x2C++0x3 line.long 0x00 "IVAHD_IRQENABLE_SET,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 0. " SYSCTRL_CLKERR ,Clock Programing Error - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x30++0x3 line.long 0x00 "IVAHD_IRQENABLE_CLR,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 0. " SYSCTRL_CLKERR ,Clock Programing Error - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x34++0x3 line.long 0x00 "IVAHD_SYNC_IRQSTATUS_RAW,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." hexmask.long.byte 0x00 0.--7. 1. " SYNC_INPUT7_0 ,Settable raw status for SYNC INPUT event. For each bit of the bit field: Read 0: No event pending Read 1: Event pending Write 0: No action Write 1: Set event (debug)" group.long 0x38++0x3 line.long 0x00 "IVAHD_SYNC_IRQSTATUS,Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." hexmask.long.byte 0x00 0.--7. 1. " SYNC_INPUT7_0 ,Clearable, enabled status for SYNC INPUT event. For each bit of the bit field: Read 0: No (enabled) event pending Read 1: Event pending Write 0: No action Write 1: Clear (raw) event" group.long 0x3C++0x3 line.long 0x00 "IVAHD_SYNC_IRQENABLE_SET,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." hexmask.long.byte 0x00 0.--7. 1. " SYNC_INPUT7_0 ,Enable for interrupt event. For each bit of the bit field: Read 0: Interrupt disabled (masked) Read 1: Interrupt enabled Write 0: No action Write 1: Enable interrupt" group.long 0x40++0x3 line.long 0x00 "IVAHD_SYNC_IRQENABLE_CLR,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." hexmask.long.byte 0x00 0.--7. 1. " SYNC_INPUT7_0 ,Enable for interrupt event. For each bit of the bitfiled: Read 0: Interrupt disabled (masked) Read 1: Interrupt enabled Write 0: No action Write 1: Disable interrupt" group.long 0x50++0x3 line.long 0x00 "IVAHD_CLKCTRL,IVA-HD clock control register" bitfld.long 0x00 10. " SMSET ,Clock control of SMSET 0: Exit idle state and start SMSET clock 1: Request SMSET to go to idle state and stop SMSET clock Note: Shutting down SMSET clock may hang system if software performs software instrumentation and/or access to it.." "0,1" bitfld.long 0x00 9. " MSGIF ,Clock control of MSGIF 0: Exit idle state and start MSGIF clock 1: Request MSGIF to go to idle state and stop MSGIF clock" "0,1" bitfld.long 0x00 8. " ECD3 ,Clock control of ECD3 0: Exit idle state and start ECD3 clock 1: Request ECD3 to go to idle state and stop ECD3 clock" "0,1" textline " " bitfld.long 0x00 7. " MC3 ,Clock control of MC3 0: Exit idle state and start MC3 clock 1: Request MC3 to go to idle state and stop MC3 clock" "0,1" bitfld.long 0x00 6. " IPE3 ,Clock control of iPE3 0: Exit idle state and start iPE3 clock 1: Request iME3 to go to idle state and stop iPE3 clock" "0,1" bitfld.long 0x00 5. " CALC3 ,Clock control of CALC3 0: Exit idle state and start CALC3 clock 1: Request CALC3 to go to idle state and stop CALC3 clock" "0,1" textline " " bitfld.long 0x00 4. " ILF3 ,Clock control of iLF3 0: Exit idle state and start iLF3 clock 1: Request iLF3 to go to idle state and stop iLF3 clock" "0,1" bitfld.long 0x00 3. " IME3 ,Clock control of iME3 0: Exit idle state and start iME3 clock 1: Request iME3 to go to idle state and stop iME3 clock" "0,1" bitfld.long 0x00 2. " VDMA ,Clock control of vDMA 0: Exit idle state and start vDMA clock 1: Request vDMA to go to idle state and stop vDMA clock" "0,1" textline " " bitfld.long 0x00 1. " ICONT2 ,Clock control of iCONT2 0: Exit idle state and start iCONT2 clock 1: Request iCONT2 to go to idle state and stop iCONT2 clock" "0,1" bitfld.long 0x00 0. " ICONT1 ,Clock control of iCONT1 0: Exit idle state and start iCONT1 clock 1: Request iCONT1 to go to idle state and stop iCONT1 clock" "0,1" rgroup.long 0x54++0x3 line.long 0x00 "IVAHD_CLKST,IVA-HD clock status register" bitfld.long 0x00 10. " SMSET ,Clock status of SMSET 1: SMSET clock is active 0: SMSET clock is idled" "0,1" bitfld.long 0x00 9. " MSGIF ,Clock status of MSGIF 1: MSGIF clock is active 0: MSGIF clock is idled" "0,1" bitfld.long 0x00 8. " ECD3 ,Clock status of ECD3 1: ECD3 clock is active 0: ECD3 clock is idled" "0,1" textline " " bitfld.long 0x00 7. " MC3 ,Clock status of MC3 1: MC3 clock is active 0: MC3 clock is idled" "0,1" bitfld.long 0x00 6. " IPE3 ,Clock status of iPE3 1: iPE3 clock is active 0: iPE3 clock is idled" "0,1" bitfld.long 0x00 5. " CALC3 ,Clock status of CALC3 1: CALC3 clock is active 0: CALC3 clock is idled" "0,1" textline " " bitfld.long 0x00 4. " ILF3 ,Clock status of iLF3 1: iLF3 clock is active 0: iLF3 clock is idled" "0,1" bitfld.long 0x00 3. " IME3 ,Clock status of iME3 1: iME3 clock is active 0: iME3 clock is idled" "0,1" bitfld.long 0x00 2. " VDMA ,Clock status of vDMA 1: vDMA clock is active 0: vDMA clock is idled" "0,1" textline " " bitfld.long 0x00 1. " ICONT2 ,Clock status of iCONT2 1: iCONT2 clock is active 0: iCONT2 clock is idled" "0,1" bitfld.long 0x00 0. " ICONT1 ,Clock status of iCONT1 1: iCONT1 clock is active 0: iCONT1 clock is idled" "0,1" rgroup.long 0x58++0x3 line.long 0x00 "IVAHD_STDBYST,IVA-HD STANDBY status" bitfld.long 0x00 2. " vDMA ,vDMA Standby status 0: module is not in Standby 1: module is in Standby" "0,1" bitfld.long 0x00 1. " ICONT2 ,iCONT2 Standby status 0: module is not in Standby 1: module is in Standby" "0,1" bitfld.long 0x00 0. " ICONT1 ,iCONT1 Standby status 0: module is not in Standby 1: module is in Standby" "0,1" tree.end tree.end tree.end tree.open "Dual_Cortex_M3_MPU_Subsystem" tree "CORTEXM3_WKUP" base ad:0x55081000 width 24. group.long 0x0++0x3 line.long 0x00 "CORTEXM3_CTRL_REG,The register is used by one CPU to interrupt the other, thus used as a handshake between the two CPUs 0x0: Interrupt is cleared; 0x1: Interrupt is set." bitfld.long 0x00 16. " INT_CORTEX_2 ,Interrupt to ARM Cortex-M3 CPU2" "0,1" bitfld.long 0x00 0. " INT_CORTEX_1 ,Interrupt to ARM Cortex-M3 CPU1" "0,1" group.long 0x4++0x3 line.long 0x00 "STANDBY_CORE_SYSCONFIG,Standby protocol" bitfld.long 0x00 0.--1. " STANDBYMODE ,0x0: Force-standby mode - . - . - ." "0,No-standby_mode,Smart-standby_mode,3" group.long 0x8++0x3 line.long 0x00 "IDLE_CORE_SYSCONFIG,Idle protocol" bitfld.long 0x00 0.--1. " IDLEMODE ,0x0: Force-idle mode - . - . - ." "0,No-idle_mode,Smart-idle_mode,3" group.long 0xC++0x3 line.long 0x00 "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x00 31. " MIRQ31 ,Interrupt Mask bit 31" "0,1" bitfld.long 0x00 29. " MIRQ29 ,Interrupt Mask bit 29" "0,1" bitfld.long 0x00 28. " MIRQ28 ,Interrupt Mask bit 28" "0,1" textline " " bitfld.long 0x00 27. " MIRQ27 ,Interrupt Mask bit 27" "0,1" bitfld.long 0x00 26. " MIRQ26 ,Interrupt Mask bit 26" "0,1" bitfld.long 0x00 25. " MIRQ25 ,Interrupt Mask bit 25" "0,1" textline " " bitfld.long 0x00 24. " MIRQ24 ,Interrupt Mask bit 24" "0,1" bitfld.long 0x00 23. " MIRQ23 ,Interrupt Mask bit 23" "0,1" bitfld.long 0x00 22. " MIRQ22 ,Interrupt Mask bit 22" "0,1" textline " " bitfld.long 0x00 21. " MIRQ21 ,Interrupt Mask bit 21" "0,1" bitfld.long 0x00 20. " MIRQ20 ,Interrupt Mask bit 20" "0,1" bitfld.long 0x00 19. " MIRQ19 ,Interrupt Mask bit 19" "0,1" textline " " bitfld.long 0x00 18. " MIRQ18 ,Interrupt Mask bit 18" "0,1" bitfld.long 0x00 17. " MIRQ17 ,Interrupt Mask bit 17" "0,1" bitfld.long 0x00 16. " MIRQ16 ,Interrupt Mask bit 16" "0,1" textline " " bitfld.long 0x00 15. " MIRQ15 ,Interrupt Mask bit 15" "0,1" bitfld.long 0x00 14. " MIRQ14 ,Interrupt Mask bit 14" "0,1" bitfld.long 0x00 13. " MIRQ13 ,Interrupt Mask bit 13" "0,1" textline " " bitfld.long 0x00 12. " MIRQ12 ,Interrupt Mask bit 12" "0,1" bitfld.long 0x00 11. " MIRQ11 ,Interrupt Mask bit 11" "0,1" bitfld.long 0x00 10. " MIRQ10 ,Interrupt Mask bit 10" "0,1" textline " " bitfld.long 0x00 9. " MIRQ9 ,Interrupt Mask bit 9" "0,1" bitfld.long 0x00 8. " MIRQ8 ,Interrupt Mask bit 8" "0,1" bitfld.long 0x00 7. " MIRQ7 ,Interrupt Mask bit 7" "0,1" group.long 0x10++0x3 line.long 0x00 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x00 31. " MIRQ63 ,Interrupt Mask bit 63" "0,1" bitfld.long 0x00 30. " MIRQ62 ,Interrupt Mask bit 62" "0,1" bitfld.long 0x00 29. " MIRQ61 ,Interrupt Mask bit 61" "0,1" textline " " bitfld.long 0x00 28. " MIRQ60 ,Interrupt Mask bit 60" "0,1" bitfld.long 0x00 27. " MIRQ59 ,Interrupt Mask bit 59" "0,1" bitfld.long 0x00 26. " MIRQ58 ,Interrupt Mask bit 58" "0,1" textline " " bitfld.long 0x00 25. " MIRQ57 ,Interrupt Mask bit 57" "0,1" bitfld.long 0x00 24. " MIRQ56 ,Interrupt Mask bit 56" "0,1" bitfld.long 0x00 22. " MIRQ54 ,Interrupt Mask bit 54" "0,1" textline " " bitfld.long 0x00 21. " MIRQ53 ,Interrupt Mask bit 53" "0,1" bitfld.long 0x00 20. " MIRQ52 ,Interrupt Mask bit 52" "0,1" bitfld.long 0x00 19. " MIRQ51 ,Interrupt Mask bit 51" "0,1" textline " " bitfld.long 0x00 18. " MIRQ50 ,Interrupt Mask bit 50" "0,1" bitfld.long 0x00 16. " MIRQ48 ,Interrupt Mask bit 48" "0,1" bitfld.long 0x00 15. " MIRQ47 ,Interrupt Mask bit 47" "0,1" textline " " bitfld.long 0x00 14. " MIRQ46 ,Interrupt Mask bit 46" "0,1" bitfld.long 0x00 10. " MIRQ42 ,Interrupt Mask bit 42" "0,1" bitfld.long 0x00 9. " MIRQ41 ,Interrupt Mask bit 41" "0,1" textline " " bitfld.long 0x00 8. " MIRQ40 ,Interrupt Mask bit 40" "0,1" bitfld.long 0x00 7. " MIRQ39 ,Interrupt Mask bit 39" "0,1" bitfld.long 0x00 6. " MIRQ38 ,Interrupt Mask bit 38" "0,1" textline " " bitfld.long 0x00 5. " MIRQ37 ,Interrupt Mask bit 37" "0,1" bitfld.long 0x00 4. " MIRQ36 ,Interrupt Mask bit 36" "0,1" bitfld.long 0x00 3. " MIRQ35 ,Interrupt Mask bit 35" "0,1" textline " " bitfld.long 0x00 2. " MIRQ34 ,Interrupt Mask bit 34" "0,1" bitfld.long 0x00 1. " MIRQ33 ,Interrupt Mask bit 33" "0,1" tree.end tree "CM3_RW_Table" base ad:0xE00FE000 width 18. group.long 0x0++0x3 line.long 0x00 "CORTEXM3_RW_PID1,Peripheral Identification register - allows the user software to differentiate between the two ARM Cortex-M3 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (in example branch to .." hexmask.long 0x00 0.--31. 1. " BASEADD1 ,ROM memory address" group.long 0x4++0x3 line.long 0x00 "CORTEXM3_RW_PID2,Peripheral Identification register - allows the user software to differentiate between the two ARM Cortex-M3 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (in example branch to .." hexmask.long 0x00 0.--31. 1. " BASEADD2 ,ROM memory address" tree.end tree.end tree.open "ISS_Overview" tree "ISS_TOP" base ad:0x52000000 tree "IRQ_Line_0" width 26. group.long 0x2C++0x3 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" eventfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 11. " BTE_IRQ ,Event generated by the BTE - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the CBUFF - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver b - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver a - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x28++0x3 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x20++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_RAW_i_0,Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "No_event_pending,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" group.long 0x24++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_i_0,Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" tree.end tree "IRQ_Line_1" width 26. group.long 0x3C++0x3 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" eventfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 11. " BTE_IRQ ,Event generated by the BTE - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the CBUFF - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver b - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver a - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x38++0x3 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x30++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_RAW_i_1,Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "No_event_pending,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" group.long 0x34++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_i_1,Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" tree.end tree "IRQ_Line_2" width 26. group.long 0x4C++0x3 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" eventfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 11. " BTE_IRQ ,Event generated by the BTE - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the CBUFF - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver b - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver a - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x48++0x3 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x40++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_RAW_i_2,Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "No_event_pending,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" group.long 0x44++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_i_2,Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" tree.end tree "IRQ_Line_3" width 26. group.long 0x5C++0x3 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" eventfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 11. " BTE_IRQ ,Event generated by the BTE - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the CBUFF - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver b - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver a - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x58++0x3 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x50++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_RAW_i_3,Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "No_event_pending,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" group.long 0x54++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_i_3,Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" tree.end tree "IRQ_Line_4" width 26. group.long 0x6C++0x3 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_4,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" eventfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 11. " BTE_IRQ ,Event generated by the BTE - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the CBUFF - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver b - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver a - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x68++0x3 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_4,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x60++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_RAW_i_4,Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "No_event_pending,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" group.long 0x64++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_i_4,Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" tree.end tree "IRQ_Line_5" width 26. group.long 0x7C++0x3 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_5,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" eventfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 11. " BTE_IRQ ,Event generated by the BTE - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the CBUFF - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver b - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver a - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x78++0x3 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_5,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,1" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x70++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_RAW_i_5,Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "No_event_pending,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" group.long 0x74++0x3 line.long 0x00 "ISS_HL_IRQSTATUS_i_5,Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." bitfld.long 0x00 17. " HS_VS_IRQ ,HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SY.." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 16. " CCP2_IRQ8 ,Event generated by the CCP2 receiver - . - ." "0,Event_pending" bitfld.long 0x00 15. " SIMCOP_IRQ3 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 14. " SIMCOP_IRQ2 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 13. " SIMCOP_IRQ1 ,Event generated by SIMCOP - . - ." "noevent,pending" bitfld.long 0x00 12. " SIMCOP_IRQ0 ,Event generated by SIMCOP - . - ." "noevent,pending" textline " " bitfld.long 0x00 11. " BTE_IRQ ,Event generated by the burst translation engine - . - ." "noevent,pending" bitfld.long 0x00 10. " CBUFF_IRQ ,Event generated by the circular buffer - . - ." "noevent,pending" bitfld.long 0x00 9. " CCP2_IRQ3 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 8. " CCP2_IRQ2 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 7. " CCP2_IRQ1 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" bitfld.long 0x00 6. " CCP2_IRQ0 ,Event generated by the CCP2 receiver - . - ." "noevent,pending" textline " " bitfld.long 0x00 5. " CSIB_IRQ ,Event generated by the CSI2 receiver #b - . - ." "noevent,pending" bitfld.long 0x00 4. " CSIA_IRQ ,Event generated by the CSI2 receiver #a - . - ." "noevent,pending" bitfld.long 0x00 3. " ISP_IRQ3 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" textline " " bitfld.long 0x00 2. " ISP_IRQ2 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 1. " ISP_IRQ1 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" bitfld.long 0x00 0. " ISP_IRQ0 ,Combined interrupt event provided by the ISP. - . - ." "noevent,pending" tree.end textline "" width 18. rgroup.long 0x0++0x3 line.long 0x00 "ISS_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "ISS_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Master interface power management, standby/Wait control - . - . - . - ." "FORCE,NO,SMART1,SMART2" bitfld.long 0x00 2.--3. " IDLEMODE ,IDLE protocol configuration - . - . - . - ." "FORCE,NO,SMART1,SMART2" bitfld.long 0x00 0. " SOFTRESET ,Software reset. - . - . - . - ." "done_/_noaction,pending_/_reset" group.long 0x80++0x3 line.long 0x00 "ISS_CTRL,ISS control register" bitfld.long 0x00 28.--31. " CSI2_B_TAG_CNT ,Defines the maximum number of tags that could be used by the CSI2 b write bridge. Note: Tag count must be set to 16 for best performance." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CSI2_A_TAG_CNT ,Defines the maximum number of tags that could be used by the CSI2 a write bridge. Note: Tag count must be set to 16 for best performance." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CCP2W_TAG_CNT ,Defines the maximum number of tags that could be used by the CCP2 write bridge Note: Tag count must be set to 16 for best performance." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " CCP2R_TAG_CNT ,Defines the maximum number of tags that could be used by the CCP2 read bridge Note: Tag count must be set to 16 for best performance." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ISS_CLK_DIV ,ISS functional clock division CLK refers to the input clock provided to the ISS. FCLK is the functional clock provided to ISS top level and submodules. CFGCLK is the clock used for the configuration network. - . - . - . - ." "NONE,DIV2,DIV4,RSZ" bitfld.long 0x00 2.--3. " INPUT_SEL ,Selects ISP input - . - . - ." "CSI2_A,CSI2_B,CCP2,3" textline " " bitfld.long 0x00 0.--1. " SYNC_DETECT ,Chooses among rising and falling edge for the HS_VS_IRQ synchronization event - . - . - . - ." "HSF,HSR,VSF,VSR" group.long 0x84++0x3 line.long 0x00 "ISS_CLKCTRL,ISS clock control register. Use to enable/disable the interface and functional clock of ISS submodules." bitfld.long 0x00 30. " VPORT2_CLK ,Enables the pixel clock from the CCP2 protocol engine - . - ." "Disabled,Enabled" bitfld.long 0x00 29. " VPORT1_CLK ,Enables the pixel clock from the CSI2_B protocol engine - . - ." "Disabled,Enabled" bitfld.long 0x00 28. " VPORT0_CLK ,Enables the pixel clock from the CSI2_A protocol engine - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " CCP2 ,CCP2 - . - ." "OFF,ON" bitfld.long 0x00 3. " CSI2_B ,CSI2_B - . - ." "OFF,ON" bitfld.long 0x00 2. " CSI2_A ,CSI2_A - . - ." "OFF,ON" textline " " bitfld.long 0x00 1. " ISP ,ISP - . - ." "OFF,ON" bitfld.long 0x00 0. " SIMCOP ,SIMCOP - . - ." "OFF,ON" rgroup.long 0x88++0x3 line.long 0x00 "ISS_CLKSTAT,ISS clock status register." bitfld.long 0x00 30. " VPORT2_CLK ,Status of the pixel clock from the CCP2 protocol engine - . - ." "Disabled,Enabled" bitfld.long 0x00 29. " VPORT1_CLK ,Status of the pixel clock from the CSI2_B protocol engine - . - ." "Disabled,Enabled" bitfld.long 0x00 28. " VPORT0_CLK ,Status of the pixel clock from the CSI2_A protocol engine - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " CCP2 ,CCP2 - . - ." "OFF,ON" bitfld.long 0x00 3. " CSI2_B ,CSI2_B - . - ." "OFF,ON" bitfld.long 0x00 2. " CSI2_A ,CSI2_A - . - ." "OFF,ON" textline " " bitfld.long 0x00 1. " ISP ,ISP - . - ." "OFF,ON" bitfld.long 0x00 0. " SIMCOP ,SIMCOP - . - ." "OFF,ON" rgroup.long 0x8C++0x3 line.long 0x00 "ISS_PM_STATUS,ISS power manager status register. Software could know what modules are in functional or STANDBY/IDLE state. This feature could be particularly useful to debug when ISS does not go into STANDBY mode" bitfld.long 0x00 12.--13. " CBUFF_PM ,Power status of the CBUFF. - . - . - ." "IDLE,TRANS,FUNC,3" bitfld.long 0x00 10.--11. " BTE_PM ,Power status of the BTE. - . - . - ." "IDLE,TRANS,FUNC,3" bitfld.long 0x00 8.--9. " SIMCOP_PM ,Power status of the SIMCOP. - . - . - ." "STANDBY,TRANS,FUNC,3" textline " " bitfld.long 0x00 6.--7. " ISP_PM ,Power status of the ISP. - . - . - ." "STANDBY,TRANS,FUNC,3" bitfld.long 0x00 4.--5. " CCP2_PM ,Power status of the CCP2. - . - . - ." "STANDBY,TRANS,FUNC,3" bitfld.long 0x00 2.--3. " CSI2_B_PM ,Power status of the CSI2 module b - . - . - ." "STANDBY,TRANS,FUNC,3" textline " " bitfld.long 0x00 0.--1. " CSI2_A_PM ,Power status of the CSI2 module a - . - . - ." "STANDBY,TRANS,FUNC,3" tree.end tree.end tree.open "ISS_Interfaces" tree.open "ISS_CAMERARX_CORE1" tree "ISS_CAMERARX_CORE1" base ad:0x52001170 width 11. group.long 0x0++0x3 line.long 0x00 "REGISTER0,First register" bitfld.long 0x00 24. " HSCLOCKCONFIG ,Disable clock missing detector" "0,1" hexmask.long.byte 0x00 8.--15. 1. " THS_TERM ,THS_TERM timing parameter in multiples of DDR clock Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1?2)* DDRCLK + THS-TERM + ~ (1 ?15) ns Programmed.." hexmask.long.byte 0x00 0.--7. 1. " THS_SETTLE ,THS_SETTLE timing parameter in multiples of DDR clock frequency Effective THS_SETTLE seen on line (starting to look for sync pattern) = synchronizer delay + timer delay + LPRX delay + combinational routing delay ? pipe.." group.long 0x4++0x3 line.long 0x00 "REGISTER1,Second register" bitfld.long 0x00 30.--31. " RESVD_READ_BIT ,Reserved bit" "0,1,2,3" bitfld.long 0x00 28.--29. " RESET_DONE_STATUS ,Reset done read bits. - . - ." "0,1,2,3" bitfld.long 0x00 25. " CLOCK_MISS_DETECTOR_STATUS ,1: Error in clock missing detector. - ." "0,1" textline " " hexmask.long.byte 0x00 18.--24. 1. " TCLK_TERM ,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1?2)* CTRLCLK + TCLK_TERM + ~ (1?15) ns Programmed v.." hexmask.long.byte 0x00 10.--17. 1. " DPHY_HS_SYNC_PATTERN ,DPHY mode HS sync pattern in byte order (reverse of received order) See," bitfld.long 0x00 8.--9. " CTRLCLK_DIV_FACTOR ,Divide factor for CTRLCLK for CLKMISS detector" "0,1,2,3" textline " " hexmask.long.byte 0x00 0.--7. 1. " TCLK_SETTLE ,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1?2)* CTRLCLK + Tclk-settle + ~ (1 ?15) ns Programmed value = max.." group.long 0x8++0x3 line.long 0x00 "REGISTER2,Third register" bitfld.long 0x00 30.--31. " TRIGGER_CMD_RXTRIGESC0 ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "0,1,2,3" bitfld.long 0x00 28.--29. " TRIGGER_CMD_RXTRIGESC1 ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "0,1,2,3" bitfld.long 0x00 26.--27. " TRIGGER_CMD_RXTRIGESC2 ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " TRIGGER_CMD_RXTRIGESC3 ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " CCP2_SYNC_PATTERN ,CCP2 mode sync pattern in byte order See ," tree.end tree "ISS_CAMERARX_CORE2" base ad:0x52001570 width 11. group.long 0x0++0x3 line.long 0x00 "REGISTER0,First register" bitfld.long 0x00 24. " HSCLOCKCONFIG ,Disable clock missing detector" "0,1" hexmask.long.byte 0x00 8.--15. 1. " THS_TERM ,THS_TERM timing parameter in multiples of DDR clock Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1?2)* DDRCLK + THS-TERM + ~ (1 ?15) ns Programmed.." hexmask.long.byte 0x00 0.--7. 1. " THS_SETTLE ,THS_SETTLE timing parameter in multiples of DDR clock frequency Effective THS_SETTLE seen on line (starting to look for sync pattern) = synchronizer delay + timer delay + LPRX delay + combinational routing delay ? pipe.." group.long 0x4++0x3 line.long 0x00 "REGISTER1,Second register" bitfld.long 0x00 30.--31. " RESVD_READ_BIT ,Reserved bit" "0,1,2,3" bitfld.long 0x00 28.--29. " RESET_DONE_STATUS ,Reset done read bits. - . - ." "0,1,2,3" bitfld.long 0x00 25. " CLOCK_MISS_DETECTOR_STATUS ,1: Error in clock missing detector. - ." "0,1" textline " " hexmask.long.byte 0x00 18.--24. 1. " TCLK_TERM ,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1?2)* CTRLCLK + TCLK_TERM + ~ (1?15) ns Programmed v.." hexmask.long.byte 0x00 10.--17. 1. " DPHY_HS_SYNC_PATTERN ,DPHY mode HS sync pattern in byte order (reverse of received order) See," bitfld.long 0x00 8.--9. " CTRLCLK_DIV_FACTOR ,Divide factor for CTRLCLK for CLKMISS detector" "0,1,2,3" textline " " hexmask.long.byte 0x00 0.--7. 1. " TCLK_SETTLE ,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1?2)* CTRLCLK + Tclk-settle + ~ (1 ?15) ns Programmed value = max.." group.long 0x8++0x3 line.long 0x00 "REGISTER2,Third register" bitfld.long 0x00 30.--31. " TRIGGER_CMD_RXTRIGESC0 ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "0,1,2,3" bitfld.long 0x00 28.--29. " TRIGGER_CMD_RXTRIGESC1 ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "0,1,2,3" bitfld.long 0x00 26.--27. " TRIGGER_CMD_RXTRIGESC2 ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " TRIGGER_CMD_RXTRIGESC3 ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " CCP2_SYNC_PATTERN ,CCP2 mode sync pattern in byte order See ," tree.end tree.end tree "ISS_CCP2" base ad:0x52001C00 tree "Channel_0" width 26. group.long 0x54++0x3 line.long 0x00 "CCP2_LCx_CODE_0,CODE REGISTER - LOG CHAN 0 This register sets the codes that are used in the 32-bit synchronization codes to recognize the logical channel, frame start, frame end, line start and line end codes. This register applies for logical channel.." bitfld.long 0x00 16.--19. " CHAN_ID ,Log chan 0 identifier. The channel identifier is located between bits 4 to 7 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " FEC ,Log chan 0 frame end sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " FSC ,Log chan 0 frame start sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " LEC ,Log chan 0 line end sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LSC ,Log chan 0 line start sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x3 line.long 0x00 "CCP2_LCx_CTRL_0,CONTROL REGISTER - LOG CHAN 0 This register controls the logical channel 0. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.byte 0x00 24.--31. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the COUNT_IRQ interrupt is triggered and CHAN_EN is set to 0. Writes to this bit field are contr.." bitfld.long 0x00 19. " CRC_EN ,Enables the cyclic redundancy check. - . - ." "Disabled,Enabled" bitfld.long 0x00 18. " DPCM_PRED ,Selects the DPCM predictor to be used for the RAW6+DPCM10, RAW7+DPCM10 and RAW8+DPCM12 data formats. The RAW8+DPCM10 data format always use the simple predictor. - . - ." "0,1" textline " " bitfld.long 0x00 17. " PING_PONG ,Indicates whether the PING or PONG destination address (CCP2_LC0_DAT_PING_ADDR or CCP2_LC0_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC sync code. - . - ." "PING_buffer,PONG_buffer" bitfld.long 0x00 16. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "0,1" hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha value for RGB888 and RBG444." textline " " bitfld.long 0x00 2.--7. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "YUV4:2:2_BIG_ENDIAN,YUV4:2:2_LITTLE_ENDIAN,YUV4:2:0,3,RGB444_+_EXP16,RGB565,RGB888,RGB888_+_EXP32,RAW6_+_EXP8,9,10,11,RAW7_+_EXP8,13,14,15,16,17,18,19,RAW10,RAW10_+_EXP16,RAW10_+_VP,23,RAW12,RAW12_+_EXP16,RAW12_+_VP,27,JPEG8_+_FSP,JPEG8,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. " REGION_EN ,Enables the setting of regions of interest in the frame: SOF region, EOF region and DAT region. - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " CHAN_EN ,Enables the logical channel - 0x0 for LC3 . - ." "0,1" group.long 0x78++0x3 line.long 0x00 "CCP2_LCx_DAT_OFST_0,DATA MEM ADDRESS OFFSET REGISTER - LOG CHAN 0 This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CCP2_LC0_DAT_PING_ADDR and CCP2_LC0_DAT_PO.." hexmask.long 0x00 5.--31. 1. " OFST ,Line offset programmed in bytes. If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line. NOTE: An OCP access .." group.long 0x70++0x3 line.long 0x00 "CCP2_LCx_DAT_PING_ADDR_0,DATA MEM PING ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0x74++0x3 line.long 0x00 "CCP2_LCx_DAT_PONG_ADDR_0,DATA MEM PONG ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0x6C++0x3 line.long 0x00 "CCP2_LCx_DAT_SIZE_0,DATA SIZE REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " VERT ,Sets the vertical size of the data window. From 0 to 4095 lines. If VERT = '0', no data is output." group.long 0x68++0x3 line.long 0x00 "CCP2_LCx_DAT_START_0,DATA START REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " VERT ,Sets the vertical position of the data in regards of the FSC sync code. From 0 to 4095 lines." group.long 0x64++0x3 line.long 0x00 "CCP2_LCx_EOF_ADDR_0,EOF STATUS LINE MEM ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the EOF data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary. This register is shadowed: mod.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0x60++0x3 line.long 0x00 "CCP2_LCx_SOF_ADDR_0,SOF STATUS LINE MEM ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the SOF data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary. This register is shadowed: mod.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0x5C++0x3 line.long 0x00 "CCP2_LCx_STAT_SIZE_0,STATUS LINE SIZE REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " EOF ,Sets the number of EOF status lines From 0 to 4095" hexmask.long.word 0x00 0.--11. 1. " SOF ,Sets the number of SOF status line(s) From 0 to 4095" group.long 0x58++0x3 line.long 0x00 "CCP2_LCx_STAT_START_0,STATUS LINE START REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " EOF ,Sets the vertical position of the EOF status lines in regards of the FSC sync code. From 0 to 4095." hexmask.long.word 0x00 0.--11. 1. " SOF ,Sets the vertical position of the EOF status lines in regards of the FSC sync code. Should always be 0." tree.end tree "Channel_1" width 26. group.long 0x84++0x3 line.long 0x00 "CCP2_LCx_CODE_1,CODE REGISTER - LOG CHAN 0 This register sets the codes that are used in the 32-bit synchronization codes to recognize the logical channel, frame start, frame end, line start and line end codes. This register applies for logical channel.." bitfld.long 0x00 16.--19. " CHAN_ID ,Log chan 0 identifier. The channel identifier is located between bits 4 to 7 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " FEC ,Log chan 0 frame end sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " FSC ,Log chan 0 frame start sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " LEC ,Log chan 0 line end sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LSC ,Log chan 0 line start sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x3 line.long 0x00 "CCP2_LCx_CTRL_1,CONTROL REGISTER - LOG CHAN 0 This register controls the logical channel 0. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.byte 0x00 24.--31. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the COUNT_IRQ interrupt is triggered and CHAN_EN is set to 0. Writes to this bit field are contr.." bitfld.long 0x00 19. " CRC_EN ,Enables the cyclic redundancy check. - . - ." "Disabled,Enabled" bitfld.long 0x00 18. " DPCM_PRED ,Selects the DPCM predictor to be used for the RAW6+DPCM10, RAW7+DPCM10 and RAW8+DPCM12 data formats. The RAW8+DPCM10 data format always use the simple predictor. - . - ." "0,1" textline " " bitfld.long 0x00 17. " PING_PONG ,Indicates whether the PING or PONG destination address (CCP2_LC0_DAT_PING_ADDR or CCP2_LC0_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC sync code. - . - ." "PING_buffer,PONG_buffer" bitfld.long 0x00 16. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "0,1" hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha value for RGB888 and RBG444." textline " " bitfld.long 0x00 2.--7. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "YUV4:2:2_BIG_ENDIAN,YUV4:2:2_LITTLE_ENDIAN,YUV4:2:0,3,RGB444_+_EXP16,RGB565,RGB888,RGB888_+_EXP32,RAW6_+_EXP8,9,10,11,RAW7_+_EXP8,13,14,15,16,17,18,19,RAW10,RAW10_+_EXP16,RAW10_+_VP,23,RAW12,RAW12_+_EXP16,RAW12_+_VP,27,JPEG8_+_FSP,JPEG8,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. " REGION_EN ,Enables the setting of regions of interest in the frame: SOF region, EOF region and DAT region. - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " CHAN_EN ,Enables the logical channel - 0x0 for LC3 . - ." "0,1" group.long 0xA8++0x3 line.long 0x00 "CCP2_LCx_DAT_OFST_1,DATA MEM ADDRESS OFFSET REGISTER - LOG CHAN 0 This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CCP2_LC0_DAT_PING_ADDR and CCP2_LC0_DAT_PO.." hexmask.long 0x00 5.--31. 1. " OFST ,Line offset programmed in bytes. If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line. NOTE: An OCP access .." group.long 0xA0++0x3 line.long 0x00 "CCP2_LCx_DAT_PING_ADDR_1,DATA MEM PING ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0xA4++0x3 line.long 0x00 "CCP2_LCx_DAT_PONG_ADDR_1,DATA MEM PONG ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0x9C++0x3 line.long 0x00 "CCP2_LCx_DAT_SIZE_1,DATA SIZE REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " VERT ,Sets the vertical size of the data window. From 0 to 4095 lines. If VERT = '0', no data is output." group.long 0x98++0x3 line.long 0x00 "CCP2_LCx_DAT_START_1,DATA START REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " VERT ,Sets the vertical position of the data in regards of the FSC sync code. From 0 to 4095 lines." group.long 0x94++0x3 line.long 0x00 "CCP2_LCx_EOF_ADDR_1,EOF STATUS LINE MEM ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the EOF data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary. This register is shadowed: mod.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0x90++0x3 line.long 0x00 "CCP2_LCx_SOF_ADDR_1,SOF STATUS LINE MEM ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the SOF data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary. This register is shadowed: mod.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0x8C++0x3 line.long 0x00 "CCP2_LCx_STAT_SIZE_1,STATUS LINE SIZE REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " EOF ,Sets the number of EOF status lines From 0 to 4095" hexmask.long.word 0x00 0.--11. 1. " SOF ,Sets the number of SOF status line(s) From 0 to 4095" group.long 0x88++0x3 line.long 0x00 "CCP2_LCx_STAT_START_1,STATUS LINE START REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " EOF ,Sets the vertical position of the EOF status lines in regards of the FSC sync code. From 0 to 4095." hexmask.long.word 0x00 0.--11. 1. " SOF ,Sets the vertical position of the EOF status lines in regards of the FSC sync code. Should always be 0." tree.end tree "Channel_2" width 26. group.long 0xB4++0x3 line.long 0x00 "CCP2_LCx_CODE_2,CODE REGISTER - LOG CHAN 0 This register sets the codes that are used in the 32-bit synchronization codes to recognize the logical channel, frame start, frame end, line start and line end codes. This register applies for logical channel.." bitfld.long 0x00 16.--19. " CHAN_ID ,Log chan 0 identifier. The channel identifier is located between bits 4 to 7 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " FEC ,Log chan 0 frame end sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " FSC ,Log chan 0 frame start sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " LEC ,Log chan 0 line end sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LSC ,Log chan 0 line start sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x3 line.long 0x00 "CCP2_LCx_CTRL_2,CONTROL REGISTER - LOG CHAN 0 This register controls the logical channel 0. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.byte 0x00 24.--31. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the COUNT_IRQ interrupt is triggered and CHAN_EN is set to 0. Writes to this bit field are contr.." bitfld.long 0x00 19. " CRC_EN ,Enables the cyclic redundancy check. - . - ." "Disabled,Enabled" bitfld.long 0x00 18. " DPCM_PRED ,Selects the DPCM predictor to be used for the RAW6+DPCM10, RAW7+DPCM10 and RAW8+DPCM12 data formats. The RAW8+DPCM10 data format always use the simple predictor. - . - ." "0,1" textline " " bitfld.long 0x00 17. " PING_PONG ,Indicates whether the PING or PONG destination address (CCP2_LC0_DAT_PING_ADDR or CCP2_LC0_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC sync code. - . - ." "PING_buffer,PONG_buffer" bitfld.long 0x00 16. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "0,1" hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha value for RGB888 and RBG444." textline " " bitfld.long 0x00 2.--7. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "YUV4:2:2_BIG_ENDIAN,YUV4:2:2_LITTLE_ENDIAN,YUV4:2:0,3,RGB444_+_EXP16,RGB565,RGB888,RGB888_+_EXP32,RAW6_+_EXP8,9,10,11,RAW7_+_EXP8,13,14,15,16,17,18,19,RAW10,RAW10_+_EXP16,RAW10_+_VP,23,RAW12,RAW12_+_EXP16,RAW12_+_VP,27,JPEG8_+_FSP,JPEG8,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. " REGION_EN ,Enables the setting of regions of interest in the frame: SOF region, EOF region and DAT region. - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " CHAN_EN ,Enables the logical channel - 0x0 for LC3 . - ." "0,1" group.long 0xD8++0x3 line.long 0x00 "CCP2_LCx_DAT_OFST_2,DATA MEM ADDRESS OFFSET REGISTER - LOG CHAN 0 This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CCP2_LC0_DAT_PING_ADDR and CCP2_LC0_DAT_PO.." hexmask.long 0x00 5.--31. 1. " OFST ,Line offset programmed in bytes. If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line. NOTE: An OCP access .." group.long 0xD0++0x3 line.long 0x00 "CCP2_LCx_DAT_PING_ADDR_2,DATA MEM PING ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0xD4++0x3 line.long 0x00 "CCP2_LCx_DAT_PONG_ADDR_2,DATA MEM PONG ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0xCC++0x3 line.long 0x00 "CCP2_LCx_DAT_SIZE_2,DATA SIZE REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " VERT ,Sets the vertical size of the data window. From 0 to 4095 lines. If VERT = '0', no data is output." group.long 0xC8++0x3 line.long 0x00 "CCP2_LCx_DAT_START_2,DATA START REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " VERT ,Sets the vertical position of the data in regards of the FSC sync code. From 0 to 4095 lines." group.long 0xC4++0x3 line.long 0x00 "CCP2_LCx_EOF_ADDR_2,EOF STATUS LINE MEM ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the EOF data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary. This register is shadowed: mod.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0xC0++0x3 line.long 0x00 "CCP2_LCx_SOF_ADDR_2,SOF STATUS LINE MEM ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the SOF data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary. This register is shadowed: mod.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0xBC++0x3 line.long 0x00 "CCP2_LCx_STAT_SIZE_2,STATUS LINE SIZE REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " EOF ,Sets the number of EOF status lines From 0 to 4095" hexmask.long.word 0x00 0.--11. 1. " SOF ,Sets the number of SOF status line(s) From 0 to 4095" group.long 0xB8++0x3 line.long 0x00 "CCP2_LCx_STAT_START_2,STATUS LINE START REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " EOF ,Sets the vertical position of the EOF status lines in regards of the FSC sync code. From 0 to 4095." hexmask.long.word 0x00 0.--11. 1. " SOF ,Sets the vertical position of the EOF status lines in regards of the FSC sync code. Should always be 0." tree.end tree "Channel_3" width 26. group.long 0xE4++0x3 line.long 0x00 "CCP2_LCx_CODE_3,CODE REGISTER - LOG CHAN 0 This register sets the codes that are used in the 32-bit synchronization codes to recognize the logical channel, frame start, frame end, line start and line end codes. This register applies for logical channel.." bitfld.long 0x00 16.--19. " CHAN_ID ,Log chan 0 identifier. The channel identifier is located between bits 4 to 7 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " FEC ,Log chan 0 frame end sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " FSC ,Log chan 0 frame start sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " LEC ,Log chan 0 line end sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LSC ,Log chan 0 line start sync code identifier. The sync code identifier is located between bits 0 to 3 in the 32-bit synchronization codes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE0++0x3 line.long 0x00 "CCP2_LCx_CTRL_3,CONTROL REGISTER - LOG CHAN 0 This register controls the logical channel 0. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.byte 0x00 24.--31. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the COUNT_IRQ interrupt is triggered and CHAN_EN is set to 0. Writes to this bit field are contr.." bitfld.long 0x00 19. " CRC_EN ,Enables the cyclic redundancy check. - . - ." "Disabled,Enabled" bitfld.long 0x00 18. " DPCM_PRED ,Selects the DPCM predictor to be used for the RAW6+DPCM10, RAW7+DPCM10 and RAW8+DPCM12 data formats. The RAW8+DPCM10 data format always use the simple predictor. - . - ." "0,1" textline " " bitfld.long 0x00 17. " PING_PONG ,Indicates whether the PING or PONG destination address (CCP2_LC0_DAT_PING_ADDR or CCP2_LC0_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC sync code. - . - ." "PING_buffer,PONG_buffer" bitfld.long 0x00 16. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "0,1" hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha value for RGB888 and RBG444." textline " " bitfld.long 0x00 2.--7. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "YUV4:2:2_BIG_ENDIAN,YUV4:2:2_LITTLE_ENDIAN,YUV4:2:0,3,RGB444_+_EXP16,RGB565,RGB888,RGB888_+_EXP32,RAW6_+_EXP8,9,10,11,RAW7_+_EXP8,13,14,15,16,17,18,19,RAW10,RAW10_+_EXP16,RAW10_+_VP,23,RAW12,RAW12_+_EXP16,RAW12_+_VP,27,JPEG8_+_FSP,JPEG8,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. " REGION_EN ,Enables the setting of regions of interest in the frame: SOF region, EOF region and DAT region. - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " CHAN_EN ,Enables the logical channel - 0x0 for LC3 . - ." "0,1" group.long 0x108++0x3 line.long 0x00 "CCP2_LCx_DAT_OFST_3,DATA MEM ADDRESS OFFSET REGISTER - LOG CHAN 0 This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CCP2_LC0_DAT_PING_ADDR and CCP2_LC0_DAT_PO.." hexmask.long 0x00 5.--31. 1. " OFST ,Line offset programmed in bytes. If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line. NOTE: An OCP access .." group.long 0x100++0x3 line.long 0x00 "CCP2_LCx_DAT_PING_ADDR_3,DATA MEM PING ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0x104++0x3 line.long 0x00 "CCP2_LCx_DAT_PONG_ADDR_3,DATA MEM PONG ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0xFC++0x3 line.long 0x00 "CCP2_LCx_DAT_SIZE_3,DATA SIZE REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " VERT ,Sets the vertical size of the data window. From 0 to 4095 lines. If VERT = '0', no data is output." group.long 0xF8++0x3 line.long 0x00 "CCP2_LCx_DAT_START_3,DATA START REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " VERT ,Sets the vertical position of the data in regards of the FSC sync code. From 0 to 4095 lines." group.long 0xF4++0x3 line.long 0x00 "CCP2_LCx_EOF_ADDR_3,EOF STATUS LINE MEM ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the EOF data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary. This register is shadowed: mod.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0xF0++0x3 line.long 0x00 "CCP2_LCx_SOF_ADDR_3,SOF STATUS LINE MEM ADDRESS REGISTER - LOG CHAN 0 This register sets the 32-bit memory address where the SOF data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary. This register is shadowed: mod.." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0xEC++0x3 line.long 0x00 "CCP2_LCx_STAT_SIZE_3,STATUS LINE SIZE REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " EOF ,Sets the number of EOF status lines From 0 to 4095" hexmask.long.word 0x00 0.--11. 1. " SOF ,Sets the number of SOF status line(s) From 0 to 4095" group.long 0xE8++0x3 line.long 0x00 "CCP2_LCx_STAT_START_3,STATUS LINE START REGISTER - LOG CHAN 0 This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--27. 1. " EOF ,Sets the vertical position of the EOF status lines in regards of the FSC sync code. From 0 to 4095." hexmask.long.word 0x00 0.--11. 1. " SOF ,Sets the vertical position of the EOF status lines in regards of the FSC sync code. Should always be 0." tree.end textline "" width 21. rgroup.long 0x0++0x3 line.long 0x00 "CCP2_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x4++0x3 line.long 0x00 "CCP2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register." bitfld.long 0x00 12.--13. " MSTANDBY_MODE ,Sets the behavior of the master port power management signals. - . - . - ." "ForceStby,NoStdby,SmartStdby,3" bitfld.long 0x00 1. " SOFT_RESET ,Software reset. Set the bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads return 0. - . - ." "Normal,Reset" bitfld.long 0x00 0. " AUTO_IDLE ,Internal OCP clock gating strategy. - . - ." "Free,Gated" rgroup.long 0x8++0x3 line.long 0x00 "CCP2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module, excluding the interrupt status register." bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring - . - ." "ResetOngoing,ResetCompleted" group.long 0xC++0x3 line.long 0x00 "CCP2_LC01_IRQENABLE,INTERRUPT ENABLE REGISTER - LOG CHAN 0 & 1 This register regroups all the events related to logical channel 0 and logical channel 1. The events related to logical channel 0 trigger SINTERRUPTN[0]. The events related to logical c.." bitfld.long 0x00 31. " LC1_OCPERROR_IRQ ,An OCP error occurred on the master write port. - . - ." "Disable,Enable" bitfld.long 0x00 27. " LC1_FS_IRQ ,Logical channel 1 - Frame start sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 26. " LC1_LE_IRQ ,Logical channel 1 - Line end sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 25. " LC1_LS_IRQ ,Logical channel 1 - Line start sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 24. " LC1_FE_IRQ ,Logical channel 1 - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 23. " LC1_COUNT_IRQ ,Logical channel 1 - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 21. " LC1_FIFO_OVF_IRQ ,Logical channel 1 - FIFO overflow error. - . - ." "Disable,Enable" bitfld.long 0x00 20. " LC1_CRC_IRQ ,Logical channel 1 - CRC error. - . - ." "Disable,Enable" bitfld.long 0x00 19. " LC1_FSP_IRQ ,Logical channel 1 - FSP error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 18. " LC1_FW_IRQ ,Logical channel 1 - Frame width error. - . - ." "Disable,Enable" bitfld.long 0x00 17. " LC1_FSC_IRQ ,Logical channel 1 - False sync code error. - . - ." "Disable,Enable" bitfld.long 0x00 15. " LC0_OCPERROR_IRQ ,An OCP error occurred on the master write port. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 11. " LC0_FS_IRQ ,Logical channel 0 - Frame start sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 10. " LC0_LE_IRQ ,Logical channel 0 - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 9. " LC0_LS_IRQ ,Logical channel 0 - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 8. " LC0_FE_IRQ ,Logical channel 0 - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 7. " LC0_COUNT_IRQ ,Logical channel 0 - Frame counter reached. - . - ." "Disable,Enable" bitfld.long 0x00 5. " LC0_FIFO_OVF_IRQ ,Logical channel 0 - FIFO overflow error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " LC0_CRC_IRQ ,Logical channel 0 - CRC error. - . - ." "Disable,Enable" bitfld.long 0x00 3. " LC0_FSP_IRQ ,Logical channel 0 - FSP error. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LC0_FW_IRQ ,Logical channel 0 - Frame width error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " LC0_FSC_IRQ ,Logical channel 0 - False sync code error. - . - ." "Disable,Enable" group.long 0x10++0x3 line.long 0x00 "CCP2_LC01_IRQSTATUS,INTERRUPT STATUS REGISTER - LOG CHAN 0 & 1 This register regroups all the events related to logical channel 0 and logical channel 1. The events related to logical channel 0 trigger SINTERRUPTN[0]. The events related to logical c.." eventfld.long 0x00 31. " LC1_OCPERROR_IRQ ,An OCP error occurred on the master write port. - . - ." "False,True" eventfld.long 0x00 27. " LC1_FS_IRQ ,Logical channel 1 - Frame start sync code detection status. - . - ." "False,True" eventfld.long 0x00 26. " LC1_LE_IRQ ,Logical channel 1 - Line end sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 25. " LC1_LS_IRQ ,Logical channel 1 - Line start sync code detection status. - . - ." "False,True" eventfld.long 0x00 24. " LC1_FE_IRQ ,Logical channel 1 - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 23. " LC1_COUNT_IRQ ,Logical channel 1 - Frame counter reached status. - . - ." "False,True" textline " " eventfld.long 0x00 21. " LC1_FIFO_OVF_IRQ ,Logical channel 1 - FIFO overflow error status. - . - ." "False,True" eventfld.long 0x00 20. " LC1_CRC_IRQ ,Logical channel 1 - CRC error status. - . - ." "False,True" eventfld.long 0x00 19. " LC1_FSP_IRQ ,Logical channel 1 - FSP error status. - . - ." "False,True" textline " " eventfld.long 0x00 18. " LC1_FW_IRQ ,Logical channel 1 - Frame width error status. - . - ." "False,True" eventfld.long 0x00 17. " LC1_FSC_IRQ ,Logical channel 1 - False sync code error status. - . - ." "False,True" eventfld.long 0x00 15. " LC0_OCPERROR_IRQ ,An OCP error occurred on the master write port. - . - ." "False,True" textline " " eventfld.long 0x00 11. " LC0_FS_IRQ ,Logical channel 0 - Frame start sync code detection status. - . - ." "False,True" eventfld.long 0x00 10. " LC0_LE_IRQ ,Logical channel 0 - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 9. " LC0_LS_IRQ ,Logical channel 0 - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 8. " LC0_FE_IRQ ,Logical channel 0 - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 7. " LC0_COUNT_IRQ ,Logical channel 0 - Frame counter reached status - . - ." "False,True" eventfld.long 0x00 5. " LC0_FIFO_OVF_IRQ ,Logical channel 0 - FIFO overflow error status. - . - ." "False,True" textline " " eventfld.long 0x00 4. " LC0_CRC_IRQ ,Logical channel 0 - CRC error status. - . - ." "False,True" eventfld.long 0x00 3. " LC0_FSP_IRQ ,Logical channel 0 - FSP error status. - . - ." "False,True" eventfld.long 0x00 2. " LC0_FW_IRQ ,Logical channel 0 - Frame width error status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " LC0_FSC_IRQ ,Logical channel 0 - False sync code error status. - . - ." "False,True" group.long 0x14++0x3 line.long 0x00 "CCP2_LC23_IRQENABLE,INTERRUPT ENABLE REGISTER - LOG CHAN 2 & 3 This register regroups all the events related to logical channel 2 and logical channel 3. The events related to logical channel 2 trigger SINTERRUPTN[2]. The events related to logical c.." bitfld.long 0x00 31. " LC3_OCPERROR_IRQ ,An OCP error occurred on the master write port. - . - ." "Disable,Enable" bitfld.long 0x00 27. " LC3_FS_IRQ ,Logical channel 3 - Frame start sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 26. " LC3_LE_IRQ ,Logical channel 3 - Line end sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 25. " LC3_LS_IRQ ,Logical channel 3 - Line start sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 24. " LC3_FE_IRQ ,Logical channel 3 - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 23. " LC3_COUNT_IRQ ,Logical channel 3 - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 21. " LC3_FIFO_OVF_IRQ ,Logical channel 3 - FIFO overflow error. - . - ." "Disable,Enable" bitfld.long 0x00 20. " LC3_CRC_IRQ ,Logical channel 3 - CRC error. - . - ." "Disable,Enable" bitfld.long 0x00 19. " LC3_FSP_IRQ ,Logical channel 3 - FSP error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 18. " LC3_FW_IRQ ,Logical channel 3 - Frame width error. - . - ." "Disable,Enable" bitfld.long 0x00 17. " LC3_FSC_IRQ ,Logical channel 3 - False sync code error. - . - ." "Disable,Enable" bitfld.long 0x00 15. " LC2_OCPERROR_IRQ ,An OCP error occurred on the master write port. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 11. " LC2_FS_IRQ ,Logical channel 2 - Frame start sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 10. " LC2_LE_IRQ ,Logical channel 2 - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 9. " LC2_LS_IRQ ,Logical channel 2 - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 8. " LC2_FE_IRQ ,Logical channel 2 - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 7. " LC2_COUNT_IRQ ,Logical channel 2 - Frame counter reached. - . - ." "Disable,Enable" bitfld.long 0x00 5. " LC2_FIFO_OVF_IRQ ,Logical channel 2 - FIFO overflow error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " LC2_CRC_IRQ ,Logical channel 2 - CRC error. - . - ." "Disable,Enable" bitfld.long 0x00 3. " LC2_FSP_IRQ ,Logical channel 2 - FSP error. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LC2_FW_IRQ ,Logical channel 2 - Frame width error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " LC2_FSC_IRQ ,Logical channel 2 - False sync code error. - . - ." "Disable,Enable" group.long 0x18++0x3 line.long 0x00 "CCP2_LC23_IRQSTATUS,INTERRUPT STATUS REGISTER - LOG CHAN 2 & 3 This register regroups all the events related to logical channel 2 and logical channel 3. The events related to logical channel 2 trigger SINTERRUPTN[2]. The events related to logical c.." eventfld.long 0x00 31. " LC3_OCPERROR_IRQ ,An OCP error occurred on the master write port. - . - ." "False,True" eventfld.long 0x00 27. " LC3_FS_IRQ ,Logical channel 3 - Frame start sync code detection status. - . - ." "False,True" eventfld.long 0x00 26. " LC3_LE_IRQ ,Logical channel 3 - Line end sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 25. " LC3_LS_IRQ ,Logical channel 3 - Line start sync code detection status. - . - ." "False,True" eventfld.long 0x00 24. " LC3_FE_IRQ ,Logical channel 3 - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 23. " LC3_COUNT_IRQ ,Logical channel 3 - Frame counter reached status. - . - ." "False,True" textline " " eventfld.long 0x00 21. " LC3_FIFO_OVF_IRQ ,Logical channel 3 - FIFO overflow error status. - . - ." "False,True" eventfld.long 0x00 20. " LC3_CRC_IRQ ,Logical channel 3 - CRC error status. - . - ." "False,True" eventfld.long 0x00 19. " LC3_FSP_IRQ ,Logical channel 3 - FSP error status. - . - ." "False,True" textline " " eventfld.long 0x00 18. " LC3_FW_IRQ ,Logical channel 3 - Frame width error status. - . - ." "False,True" eventfld.long 0x00 17. " LC3_FSC_IRQ ,Logical channel 3 - False sync code error status. - . - ." "False,True" eventfld.long 0x00 15. " LC2_OCPERROR_IRQ ,An OCP error occurred on the master write port. - . - ." "False,True" textline " " eventfld.long 0x00 11. " LC2_FS_IRQ ,Logical channel 2 - Frame start sync code detection status. - . - ." "False,True" eventfld.long 0x00 10. " LC2_LE_IRQ ,Logical channel 2 - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 9. " LC2_LS_IRQ ,Logical channel 2 - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 8. " LC2_FE_IRQ ,Logical channel 2 - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 7. " LC2_COUNT_IRQ ,Logical channel 2 - Frame counter reached status - . - ." "False,True" eventfld.long 0x00 5. " LC2_FIFO_OVF_IRQ ,Logical channel 2 - FIFO overflow error status. - . - ." "False,True" textline " " eventfld.long 0x00 4. " LC2_CRC_IRQ ,Logical channel 2 - CRC error status. - . - ." "False,True" eventfld.long 0x00 3. " LC2_FSP_IRQ ,Logical channel 2 - FSP error status. - . - ." "False,True" eventfld.long 0x00 2. " LC2_FW_IRQ ,Logical channel 2 - Frame width error status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " LC2_FSC_IRQ ,Logical channel 2 - False sync code error status. - . - ." "False,True" group.long 0x2C++0x3 line.long 0x00 "CCP2_LCM_IRQENABLE,INTERRUPT ENABLE REGISTER - Memory channel This register regroups all the events related to the memory channel 2. The events related to memory channel trigger SINTERRUPTN[8]. The channel shall be enabled for events to be generated on.." bitfld.long 0x00 1. " LCM_OCPERROR ,An interconnect error has been returned for a read (interconnect read master) or write (interconnect write master) transaction related to LCM operation - . - ." "Disable,Enable" bitfld.long 0x00 0. " LCM_EOF ,Memory read channel - End of frame - . - ." "Disable,Enable" group.long 0x30++0x3 line.long 0x00 "CCP2_LCM_IRQSTATUS,INTERRUPT STATUS REGISTER - Memory channel This register regroups all the events related to memory channel. The events related to memory channel trigger SINTERRUPTN[8]. The channel shall be enabled for events to be generated on that .." eventfld.long 0x00 1. " LCM_OCPERROR ,An interconnect error has been returned for a read (interconnect read master) or write (interconnect write master) transaction related to LCM operation - . - ." "False,True" eventfld.long 0x00 0. " LCM_EOF ,Memory read channel - End of frame - . - ." "False,True" group.long 0x40++0x3 line.long 0x00 "CCP2_CTRL,GLOBAL CONTROL REGISTER This register controls the CCP2 receiver. This register shall not be modified dynamically (except IF_EN bit field)." hexmask.long.tbyte 0x00 15.--31. 1. " FRACDIV ,Fractional clock divider control for the video port. The mean video port clock is VPBASECLOCK * FRACDIV/65536. Valid range: 1-65536" bitfld.long 0x00 14. " POSTED ,Selects between posted and non posted writes. - . - ." "NONPOSTED,Posted" bitfld.long 0x00 13. " DBG_EN ,Enables the debug mode. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 12. " VP_CLK_POL ,VP clock polarity - . - ." "Falling,Rising" bitfld.long 0x00 11. " VP_ONLY_EN ,VP only enable. - . - ." "Disable,Enable" bitfld.long 0x00 9. " VP_CLK_FORCE_ON ,Controls VP_PCLK gating during frame blanking periods. - . - ." "GATED,FREE_RUNNING" textline " " bitfld.long 0x00 5.--7. " BURST ,Forces the write burst size used by the module. The write burst size shall never exceed the output FIFO size. The output FIFO size can be read with the CCP2_GNQ.FIFODEPTH bit field. - . - . - . - . - ." "B1x64,B2x64,B4x64,B8x64,B16x64,5,6,7" bitfld.long 0x00 4. " MODE ,Selects the receiver operating mode. This bit is only writable when the CCP2MODE input is 1. - . - ." "CCP1,CCP2" bitfld.long 0x00 3. " FRAME ,Set the modality in which IF_EN works. - . - ." "Immediate,Frame" textline " " bitfld.long 0x00 0. " IF_EN ,Enables the physical interface to the module. - . - ." "Disable,Enable" wgroup.long 0x44++0x3 line.long 0x00 "CCP2_DBG,DEBUG REGISTER This register provides a way to debug the CCP2 receiver with no image sensor connected to the module. The debug mode is enabled by .DBG_EN. Each write to this register provides a full 32bit word to the CCP2 receiver, even when o.." hexmask.long 0x00 0.--31. 1. " DBG ,32-bit input value. Write only register. Reads return 0." rgroup.long 0x48++0x3 line.long 0x00 "CCP2_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design." bitfld.long 0x00 5. " OCPREADPORT ,The OCP master read port, the DPCM encoder and ALAW decompression are only present when this bit is set." "0,1" bitfld.long 0x00 2.--4. " FIFODEPTH ,Output FIFO size in multiple of 64 bits. - . - . - . - . - . - ." "f3,f4,f8,f16,f32,f64,6,7" bitfld.long 0x00 0.--1. " NBCHANNELS ,Number of logical channels supported by the module. - . - . - . - ." "lc1,lc2,lc4,lc8" group.long 0x4C++0x3 line.long 0x00 "CCP2_CTRL1,GLOBAL CONTROL REGISTER (2) This register controls the CCP2 receiver." bitfld.long 0x00 0.--1. " BLANKING ,Controls the number of clock pulses provided during vertical and horizontal clock periods. When the blanking period provided by the camera is lower than the value set here, the blanking period is shortened by the CCP2 to prevent inte.." "C0,C1,C2,C3" group.long 0x1D0++0x3 line.long 0x00 "CCP2_LCM_CTRL,Control register for the memory channel. It defines the data format of the source frame stored in memory and how this frame is processed." bitfld.long 0x00 31. " DST_PACK ,Data is packed before it is send to memory. Applies to RAW6, RAW7, RAW10, and RAW12 only. - . - ." "DISABLE,ENABLE" bitfld.long 0x00 30. " DST_DPCM_PRED ,Selects the DPCM predictor to be used for the RAW6+DPCM10 and RAW7+DPCM10 data formats. The RAW8+DPCM10 data format always use the simple predictor. - . - ." "Advanced,Simple" bitfld.long 0x00 28.--29. " DST_COMPR ,Enables data compression of data sent to memory - . - . - ." "DISABLE,ALAW,2,3" textline " " bitfld.long 0x00 24.--26. " DST_FORMAT ,Output format selection. Not every combination between input and output formats are possible. - . - . - . - . - . - . - ." "RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,RAW16,7" bitfld.long 0x00 23. " SRC_PACK ,Data stored in memory is packed and must be unpacked. - . - ." "DISABLE,ENABLE" bitfld.long 0x00 22. " SRC_DPCM_PRED ,Selects the DPCM predictor to be used for the RAW6+DPCM10, RAW7+DPCM10 and RAW8+DPCM12 data formats. The RAW8+DPCM10 and RAW6 + DPCM12 data format always use the simple predictor. - . - ." "Advanced,Simple" textline " " bitfld.long 0x00 20.--21. " SRC_DECOMPR ,Enable decompression of incoming data - . - . - . - ." "DISABLE,ALAW,2,3" bitfld.long 0x00 16.--19. " SRC_FORMAT ,Data format of the data stored in memory. As there is no header embedded in the data sent to memory the user is responsible of choosing the adequate format. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,RAW16,?..." bitfld.long 0x00 5.--7. " BURST_SIZE ,Defines the burst size of the master read port - . - . - . - . - ." "B1x64,B2x64,4x_64-bit_bursts.,8x_64-bit_bursts.,16x_64-bit_bursts.,5,6,7" textline " " bitfld.long 0x00 3.--4. " READ_THROTTLE ,Limit maximum data read speed for memory to memory operation - . - . - . - ." "FULL,TWO,1/4_speed,1/8_speed" bitfld.long 0x00 2. " DST_PORT ,Select the destination port - . - ." "VPORT,MEMWRITE" bitfld.long 0x00 0. " CHAN_EN ,Enables the read from memory channel. Before enabling the memory read channel software shall: - disable the physical interface using the IF_EN bit - wait until disabling of the physical interface is effective (depends on the FRAME .." "Disable,Enable" group.long 0x1D4++0x3 line.long 0x00 "CCP2_LCM_VSIZE,Memory channel vertical framing register" hexmask.long.word 0x00 16.--28. 1. " COUNT ,Defines the line count to be read from memory. From 1 to 8191 lines." group.long 0x1D8++0x3 line.long 0x00 "CCP2_LCM_HSIZE,Memory read channel horizontal framing register." hexmask.long.word 0x00 16.--30. 1. " COUNT ,Horizontal count ofsamples to output after the skipped pixels. Valid values: 1 to 32767." hexmask.long.word 0x00 0.--14. 1. " SKIP ,Horizontal count ofsamples to skip after the start of the line. When DPCM compressed data is read from memory using this feature is the only valid way to set a horizontal starting position. Valid values: 0 to32767. 0 disables.." group.long 0x1DC++0x3 line.long 0x00 "CCP2_LCM_PREFETCH,This register defines the amount of data to be fetched from memory. It must be consistent with the register (check programming model)." hexmask.long.word 0x00 3.--15. 1. " HWORDS ,64 bit words to read from memory for each line of the image. Possible values 1..8191" group.long 0x1E0++0x3 line.long 0x00 "CCP2_LCM_SRC_ADDR,Memory channel source address register This register sets the 32-bit memory address where the pixel data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address" group.long 0x1E4++0x3 line.long 0x00 "CCP2_LCM_SRC_OFST,Memory channel source offset register. This register sets the offset, which is applied on the source address after each line is read from memory. For example, it enables to perform 2D data transfers of the pixel data from a frame buff.." hexmask.long 0x00 5.--31. 1. " OFST ,Line offset programmed in bytes. If OFST = 0, the data is read contiguously from memory. Otherwise, OFST sets the source offset between the first pixel of the previous line and the first pixel of the current line." group.long 0x1E8++0x3 line.long 0x00 "CCP2_LCM_DST_ADDR,Memory channel destination address. This register sets the 32-bit memory address where the pixel data are stored. The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most significant bits of the 32-bit address." group.long 0x1EC++0x3 line.long 0x00 "CCP2_LCM_DST_OFST,Memory channel destination offset register. This register sets the offset, which is applied on the destination address after each line is written to memory. For example, it enables to perform 2D data transfers of the pixel data into a.." hexmask.long 0x00 5.--31. 1. " OFST ,Line offset programmed in bytes. If OFST = 0, the data is written contiguously to memory if possible. At the end of a line only full 32 bit words will be written, creating eventually gaps at the end of lines. Otherwise, OFST sets the.." group.long 0x1F0++0x3 line.long 0x00 "CCP2_LCM_HISTORY,Controls operation of the DPCM history read/write feature" bitfld.long 0x00 17. " EN_HIST_RD ,Enable DPCM history read - . - ." "Disable,Enable" bitfld.long 0x00 16. " EN_HIST_WR ,Enable DPCM history write - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--15. 1. " HIST_EXPORT ,Defines the horizontal position at which DPCM history information is written. The first decoded sample of a line has position 0 The last decoded sample has position SKIP+COUNT?1 Valid range [3..SKIP+COUNT?1]" tree.end tree.open "ISS_CSI2_A_REGS2" tree "ISS_CSI2_A_REGS2" base ad:0x520011C0 tree "CTX_Line_0" width 25. group.long 0x0++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_0,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x4++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_0,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_1" width 25. group.long 0x8++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_1,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0xC++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_1,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_2" width 25. group.long 0x10++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_2,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x14++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_2,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_3" width 25. group.long 0x18++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_3,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x1C++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_3,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_4" width 25. group.long 0x20++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_4,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x24++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_4,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_5" width 25. group.long 0x28++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_5,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x2C++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_5,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_6" width 25. group.long 0x30++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_6,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x34++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_6,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_7" width 25. group.long 0x38++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_7,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x3C++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_7,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree.end tree "ISS_CSI2_B_REGS2" base ad:0x520015C0 tree "CTX_Line_0" width 25. group.long 0x0++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_0,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x4++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_0,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_1" width 25. group.long 0x8++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_1,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0xC++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_1,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_2" width 25. group.long 0x10++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_2,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x14++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_2,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_3" width 25. group.long 0x18++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_3,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x1C++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_3,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_4" width 25. group.long 0x20++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_4,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x24++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_4,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_5" width 25. group.long 0x28++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_5,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x2C++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_5,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_6" width 25. group.long 0x30++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_6,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x34++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_6,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree "CTX_Line_7" width 25. group.long 0x38++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEH_i_7,Transcode configuration register: defines horizontal frame cropping" hexmask.long.word 0x00 16.--28. 1. " HCOUNT ,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " HSKIP ,Pixel to skip horizontally. Valid values: 0-8191" group.long 0x3C++0x3 line.long 0x00 "CSI2_CTX_TRANSCODEV_i_7,Transcode configuration register: defines vertical frame cropping" hexmask.long.word 0x00 16.--28. 1. " VCOUNT ,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor." hexmask.long.word 0x00 0.--12. 1. " VSKIP ,Pixel to skip vertically Valid values: 0-8191" tree.end tree.end tree.end tree.open "ISS_CSI2_A_REGS1" tree "ISS_CSI2_A_REGS1" base ad:0x52001000 tree "CTX_Line_0" width 28. group.long 0x70++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_0,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x74++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_0,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x8C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_0,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x78++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_0,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x7C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_0,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x80++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_0,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x84++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_0,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x88++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_0,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_1" width 28. group.long 0x90++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x94++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0xAC++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x98++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_1,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x9C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_1,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xA0++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_1,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xA4++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_1,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0xA8++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_1,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_2" width 28. group.long 0xB0++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0xB4++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0xCC++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0xB8++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_2,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0xBC++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_2,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xC0++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_2,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xC4++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_2,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0xC8++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_2,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_3" width 28. group.long 0xD0++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0xD4++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0xEC++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0xD8++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_3,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0xDC++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_3,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xE0++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_3,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xE4++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_3,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0xE8++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_3,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_4" width 28. group.long 0xF0++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_4,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0xF4++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_4,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x10C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_4,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0xF8++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_4,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0xFC++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_4,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x100++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_4,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x104++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_4,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x108++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_4,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_5" width 28. group.long 0x110++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_5,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x114++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_5,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x12C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_5,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x118++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_5,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x11C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_5,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x120++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_5,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x124++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_5,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x128++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_5,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_6" width 28. group.long 0x130++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_6,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x134++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_6,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x14C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_6,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x138++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_6,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x13C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_6,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x140++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_6,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x144++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_6,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x148++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_6,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_7" width 28. group.long 0x150++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_7,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x154++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_7,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x16C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_7,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x158++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_7,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x15C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_7,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x160++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_7,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x164++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_7,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x168++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_7,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end textline "" width 26. rgroup.long 0x0++0x3 line.long 0x00 "CSI2_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "CSI2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register." bitfld.long 0x00 12.--13. " MSTANDBY_MODE ,Sets the behavior of the master port power management signals. - . - . - ." "ForceStby,NoStdby,SmartStdby,3" bitfld.long 0x00 1. " SOFT_RESET ,Software reset. Set the bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads return 0. - . - ." "Normal,Reset" bitfld.long 0x00 0. " AUTO_IDLE ,Internal OCP gating strategy - . - ." "Free,Gated" rgroup.long 0x14++0x3 line.long 0x00 "CSI2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module, excluding the interrupt status register." bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring - . - ." "ResetOngoing,ResetCompleted" group.long 0x18++0x3 line.long 0x00 "CSI2_IRQSTATUS,INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt. The context shall be enabled for events to be generated on that context. If the c.." eventfld.long 0x00 14. " OCP_ERR_IRQ ,OCP Error Interrupt - . - ." "False,True" eventfld.long 0x00 13. " SHORT_PACKET_IRQ ,Short packet reception status (other than synch events: Line Start, Line End, Frame Start, and Frame End: data type between 0x8 and x0F only shall be considered). - . - ." "False,True" eventfld.long 0x00 12. " ECC_CORRECTION_IRQ ,ECC has been used to do the correction of the only 1-bit error status (short packet only). - . - ." "False,True" textline " " eventfld.long 0x00 11. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" bitfld.long 0x00 9. " COMPLEXIO_ERR_IRQ ,Error signaling from complex I/O: status of the PHY errors received from the complex I/O (events are defined inCSI2_COMPLEXIO_IRQSTATUS for the complex I/O). - . - ." "0,1" eventfld.long 0x00 8. " FIFO_OVF_IRQ ,FIFO overflow error status. - . - ." "False,True" textline " " bitfld.long 0x00 7. " CONTEXT7 ,Context 7 - . - ." "False,True" bitfld.long 0x00 6. " CONTEXT6 ,Context 6 - . - ." "False,True" bitfld.long 0x00 5. " CONTEXT5 ,Context 5 - . - ." "False,True" textline " " bitfld.long 0x00 4. " CONTEXT4 ,Context 4 - . - ." "False,True" bitfld.long 0x00 3. " CONTEXT3 ,Context 3 - . - ." "False,True" bitfld.long 0x00 2. " CONTEXT2 ,Context 2 - . - ." "False,True" textline " " bitfld.long 0x00 1. " CONTEXT1 ,Context 1 - . - ." "False,True" bitfld.long 0x00 0. " CONTEXT0 ,Context 0 - . - ." "False,True" group.long 0x1C++0x3 line.long 0x00 "CSI2_IRQENABLE,INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually." bitfld.long 0x00 14. " OCP_ERR_IRQ ,OCP Error Interrupt - . - ." "Disable,Enable" bitfld.long 0x00 13. " SHORT_PACKET_IRQ ,Short packet reception (other than synch events: Line Start, Line End, Frame Start, and Frame End: data type between 0x8 and x0F only shall be considered). - . - ." "Disable,Enable" bitfld.long 0x00 12. " ECC_CORRECTION_IRQ ,ECC has been used to correct the only 1-bit error (short packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 11. " ECC_NO_CORRECTION_IRQ ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" bitfld.long 0x00 9. " COMPLEXIO_ERR_IRQ ,Error signaling from complex I/O: the interrupt is triggered when any error is received from the complex I/O (events are defined inCSI2_COMPLEXIO_IRQSTATUS for the complex I/O). - . - ." "Event_is_masked,1" bitfld.long 0x00 8. " FIFO_OVF_IRQ ,FIFO overflow enable - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CONTEXT7 ,Context 7 - . - ." "Disable,Enable" bitfld.long 0x00 6. " CONTEXT6 ,Context 6 - . - ." "Disable,Enable" bitfld.long 0x00 5. " CONTEXT5 ,Context 5 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " CONTEXT4 ,Context 4 - . - ." "Disable,Enable" bitfld.long 0x00 3. " CONTEXT3 ,Context 3 - . - ." "Disable,Enable" bitfld.long 0x00 2. " CONTEXT2 ,Context 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " CONTEXT1 ,Context 1 - . - ." "Disable,Enable" bitfld.long 0x00 0. " CONTEXT0 ,Context 0 - . - ." "Disable,Enable" group.long 0x40++0x3 line.long 0x00 "CSI2_CTRL,GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified dynamically (except IF_EN bit field)." bitfld.long 0x00 16. " BURST_SIZE_EXPAND ,Sets the DMA burst size on the L3 interconnect. - . - ." "DIS,EN" bitfld.long 0x00 15. " VP_CLK_EN ,VP clock enable. - . - ." "Disable,Enable" bitfld.long 0x00 13. " NON_POSTED_WRITE ,Not posted writes - . - ." "Disable,Enable" textline " " bitfld.long 0x00 11. " VP_ONLY_EN ,VP only enable. - . - ." "VP_OCP,VP" bitfld.long 0x00 10. " STREAMING_32_BIT ,Indicates if 64-bit or 32-bit streaming burst is used. Valid only if CSI2_CTRL.STREAMING=1 - . - ." "STREAM64,STREAM32" bitfld.long 0x00 8.--9. " VP_OUT_CTRL ,VP_PCLK control. Sets the VP_PCLK as a function of the ISS interconnect interface clock (OCPCLK). - . - . - . - ." "div1,div2,div3,div4" textline " " bitfld.long 0x00 7. " DBG_EN ,Enables the debug mode. - . - ." "Disable,Enable" bitfld.long 0x00 5.--6. " BURST_SIZE ,Sets the DMA burst size on the L3 interconnect. - . - . - . - ." "single,burst2x64,burst4x64,burst8x64" bitfld.long 0x00 4. " ENDIANNESS ,Select endianness for YUV4:2:2 8 bit and YUV4:2:0 legacy formats. - . - ." "NATIVE,ALL_LE" textline " " bitfld.long 0x00 3. " FRAME ,Set the modality in which IF_EN works. - . - ." "Immediate,Frame" bitfld.long 0x00 2. " ECC_EN ,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids). - . - ." "Disable,Enable" bitfld.long 0x00 0. " IF_EN ,Enables the physical interface to the module. - . - ." "Disable,Enable" wgroup.long 0x44++0x3 line.long 0x00 "CSI2_DBG_H,DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by .DBG_EN. Only full 32-bit values shall be written. The register is used to writ.." hexmask.long 0x00 0.--31. 1. " DBG ,32-bit input value." group.long 0x50++0x3 line.long 0x00 "CSI2_COMPLEXIO_CFG,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in add.." bitfld.long 0x00 30. " RESET_CTRL ,Controls the reset of the complex I/O - . - ." "0,1" bitfld.long 0x00 29. " RESET_DONE ,Internal reset monitoring of the power domain using the byte clock provided by the associated CSIPHY (see, .Caution:For the [29] RESET_DONE bit to be set to 0x1 (reset completed), the external sensor must to be activ.." "0,Reset_completed." bitfld.long 0x00 27.--28. " PWR_CMD ,Command for power control of the complex I/O - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 25.--26. " PWR_STATUS ,Status of the power control of the complex I/O - . - . - ." "0,1,2,3" bitfld.long 0x00 24. " PWR_AUTO ,Automatic switch between ULP and ON states based on ULPM signals from complex I/O - . - ." "Disable,Enable" bitfld.long 0x00 19. " DATA4_POL ,+/- differential pin order of data lane 4. - . - ." "+/-_pin_order,-/+_pin_order" textline " " bitfld.long 0x00 16.--18. " DATA4_POSITION ,Position and order of the data lane 4. The values 6 and 7 are reserved. This lane is not available to the CSI2-B receiver. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,?..." bitfld.long 0x00 15. " DATA3_POL ,+/- differential pin order of data lane 3. - . - ." "+/-_pin_order,-/+_pin_order" bitfld.long 0x00 12.--14. " DATA3_POSITION ,Position and order of the data lane 3. The values 6 and 7 are reserved. This lane is not available to the CSI2-B receiver. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,?..." textline " " bitfld.long 0x00 11. " DATA2_POL ,+/- differential pin order of DATA lane 2. - . - ." "0,1" bitfld.long 0x00 8.--10. " DATA2_POSITION ,Position and order of the data lane 2. The values 6 and 7 are reserved. This lane is not available to the CSI2-B receiver. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,?..." bitfld.long 0x00 7. " DATA1_POL ,+/- differential pin order of data lane 1. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " DATA1_POSITION ,Position and order of the DATA lane 1.The values 6 and 7 are reserved. When CSI2 is used, the data lane 1 position must be different from 0, 6, or 7. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,?..." bitfld.long 0x00 3. " CLOCK_POL ,+/- differential pin order of clock lane. - . - ." "0,1" bitfld.long 0x00 0.--2. " CLOCK_POSITION ,Position and order of the clock lane. The values 5, 6, and 7 are reserved. When CSI2 is used, the clock lane position must be different from 0, 5, 6, or 7. - . - . - . - . - . - . - . - ." "0,1,2,3,4,?..." group.long 0x54++0x3 line.long 0x00 "CSI2_COMPLEXIO_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex I/O #1" eventfld.long 0x00 26. " STATEALLULPMEXIT ,At least one of the active lanes has exit the ULPM - . - ." "0,1" eventfld.long 0x00 25. " STATEALLULPMENTER ,All active lanes are entering in ULPM. - . - ." "0,1" eventfld.long 0x00 24. " STATEULPM5 ,Lane 5 in ULPM - . - ." "0,1" textline " " eventfld.long 0x00 23. " STATEULPM4 ,Lane 4 in ULPM - . - ." "0,1" eventfld.long 0x00 22. " STATEULPM3 ,Lane 3 in ULPM - . - ." "0,1" eventfld.long 0x00 21. " STATEULPM2 ,Lane 2 in ULPM - . - ." "0,1" textline " " eventfld.long 0x00 20. " STATEULPM1 ,Lane 1 in ULPM - . - ." "0,1" eventfld.long 0x00 19. " ERRCONTROL5 ,Control error for lane 5 - . - ." "0,1" eventfld.long 0x00 18. " ERRCONTROL4 ,Control error for lane 4 - . - ." "0,1" textline " " eventfld.long 0x00 17. " ERRCONTROL3 ,Control error for lane 3 - . - ." "0,1" eventfld.long 0x00 16. " ERRCONTROL2 ,Control error for lane 2 - . - ." "0,1" eventfld.long 0x00 15. " ERRCONTROL1 ,Control error for lane 1 - . - ." "0,1" textline " " eventfld.long 0x00 14. " ERRESC5 ,Escape entry error for lane 5 - . - ." "0,1" eventfld.long 0x00 13. " ERRESC4 ,Escape entry error for lane 4 - . - ." "0,1" eventfld.long 0x00 12. " ERRESC3 ,Escape entry error for lane 3 - . - ." "0,1" textline " " eventfld.long 0x00 11. " ERRESC2 ,Escape entry error for lane 2 - . - ." "0,1" eventfld.long 0x00 10. " ERRESC1 ,Escape entry error for lane 1 - . - ." "0,1" eventfld.long 0x00 9. " ERRSOTSYNCHS5 ,Start of transmission sync error for lane 5 - . - ." "0,1" textline " " eventfld.long 0x00 8. " ERRSOTSYNCHS4 ,Start of transmission sync error for lane 4 - . - ." "0,1" eventfld.long 0x00 7. " ERRSOTSYNCHS3 ,Start of transmission sync error for lane 3 - . - ." "0,1" eventfld.long 0x00 6. " ERRSOTSYNCHS2 ,Start of transmission sync error for lane 2 - . - ." "0,1" textline " " eventfld.long 0x00 5. " ERRSOTSYNCHS1 ,Start of transmission sync error for lane 1 - . - ." "0,1" eventfld.long 0x00 4. " ERRSOTHS5 ,Start of transmission error for lane 5 - . - ." "0,1" eventfld.long 0x00 3. " ERRSOTHS4 ,Start of transmission error for lane 4 - . - ." "0,1" textline " " eventfld.long 0x00 2. " ERRSOTHS3 ,Start of transmission error for lane 3 - . - ." "0,1" eventfld.long 0x00 1. " ERRSOTHS2 ,Start of transmission error for lane 2 - . - ." "0,1" eventfld.long 0x00 0. " ERRSOTHS1 ,Start of transmission error for lane 1 - . - ." "0,1" rgroup.long 0x5C++0x3 line.long 0x00 "CSI2_SHORT_PACKET,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.tbyte 0x00 0.--23. 1. " SHORT_PACKET ,Short Packet information: DATA ID + DATA FIELD" group.long 0x60++0x3 line.long 0x00 "CSI2_COMPLEXIO_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex I/O" bitfld.long 0x00 26. " STATEALLULPMEXIT ,At least one of the active lanes has exit the ULPM - . - ." "Event_is_masked,1" bitfld.long 0x00 25. " STATEALLULPMENTER ,All active lanes are entering in ULPM. - . - ." "Event_is_masked,1" bitfld.long 0x00 24. " STATEULPM5 ,Lane 5 in ULPM - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 23. " STATEULPM4 ,Lane 4 in ULPM - . - ." "Event_is_masked,1" bitfld.long 0x00 22. " STATEULPM3 ,Lane 3 in ULPM - . - ." "Event_is_masked,1" bitfld.long 0x00 21. " STATEULPM2 ,Lane 2 in ULPM - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 20. " STATEULPM1 ,Lane 1 in ULPM - . - ." "Event_is_masked,1" bitfld.long 0x00 19. " ERRCONTROL5 ,Control error for lane 5 - . - ." "Event_is_masked,1" bitfld.long 0x00 18. " ERRCONTROL4 ,Control error for lane 4 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 17. " ERRCONTROL3 ,Control error for lane 3 - . - ." "Event_is_masked,1" bitfld.long 0x00 16. " ERRCONTROL2 ,Control error for lane 2 - . - ." "Event_is_masked,1" bitfld.long 0x00 15. " ERRCONTROL1 ,Control error for lane 1 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 14. " ERRESC5 ,Escape entry error for lane 5 - . - ." "Event_is_masked,1" bitfld.long 0x00 13. " ERRESC4 ,Escape entry error for lane 4 - . - ." "Event_is_masked,1" bitfld.long 0x00 12. " ERRESC3 ,Escape entry error for lane 3 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 11. " ERRESC2 ,Escape entry error for lane 2 - . - ." "Event_is_masked,1" bitfld.long 0x00 10. " ERRESC1 ,Escape entry error for lane 1 - . - ." "Event_is_masked,1" bitfld.long 0x00 9. " ERRSOTSYNCHS5 ,Start of transmission sync error for lane 5 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 8. " ERRSOTSYNCHS4 ,Start of transmission sync error for lane 4 - . - ." "Event_is_masked,1" bitfld.long 0x00 7. " ERRSOTSYNCHS3 ,Start of transmission sync error for lane 3 - . - ." "Event_is_masked,1" bitfld.long 0x00 6. " ERRSOTSYNCHS2 ,Start of transmission sync error for lane 2 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 5. " ERRSOTSYNCHS1 ,Start of transmission sync error for lane 1 - . - ." "Event_is_masked,1" bitfld.long 0x00 4. " ERRSOTHS5 ,Start of transmission error for lane 5 - . - ." "Event_is_masked,1" bitfld.long 0x00 3. " ERRSOTHS4 ,Start of transmission error for lane 4 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 2. " ERRSOTHS3 ,Start of transmission error for lane 3 - . - ." "Event_is_masked,1" bitfld.long 0x00 1. " ERRSOTHS2 ,Start of transmission error for lane 2 - . - ." "Event_is_masked,1" bitfld.long 0x00 0. " ERRSOTHS1 ,Start of transmission error for lane 1 - . - ." "Event_is_masked,1" wgroup.long 0x68++0x3 line.long 0x00 "CSI2_DBG_P,DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by .DBG_EN. Only full 32-bit values shall be written. The register is used to wri.." hexmask.long 0x00 0.--31. 1. " DBG ,32-bit input value." group.long 0x6C++0x3 line.long 0x00 "CSI2_TIMING,TIMING REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified while .IF_EN is set to 1. It is used to indicate the number of L3 cycles for the Stop State monitoring." bitfld.long 0x00 15. " FORCE_RX_MODE_IO1 ,Control of ForceRxMode signal - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " STOP_STATE_X16_IO1 ,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit field - . - ." "Disable,Enable" bitfld.long 0x00 13. " STOP_STATE_X4_IO1 ,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit field - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 0.--12. 1. " STOP_STATE_COUNTER_IO1 ,Stop State counter for monitoring. It indicates the number of L3 to monitor for Stop State before deasserting ForceRxMode (complex I/O 1). The value is from 0 to 8191." tree.end tree "ISS_CSI2_B_REGS1" base ad:0x52001400 tree "CTX_Line_0" width 28. group.long 0x70++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_0,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x74++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_0,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x8C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_0,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x78++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_0,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x7C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_0,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x80++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_0,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x84++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_0,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x88++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_0,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_1" width 28. group.long 0x90++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x94++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0xAC++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x98++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_1,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x9C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_1,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xA0++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_1,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xA4++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_1,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0xA8++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_1,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_2" width 28. group.long 0xB0++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0xB4++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0xCC++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0xB8++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_2,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0xBC++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_2,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xC0++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_2,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xC4++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_2,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0xC8++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_2,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_3" width 28. group.long 0xD0++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0xD4++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0xEC++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0xD8++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_3,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0xDC++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_3,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xE0++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_3,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0xE4++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_3,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0xE8++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_3,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_4" width 28. group.long 0xF0++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_4,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0xF4++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_4,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x10C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_4,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0xF8++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_4,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0xFC++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_4,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x100++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_4,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x104++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_4,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x108++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_4,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_5" width 28. group.long 0x110++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_5,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x114++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_5,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x12C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_5,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x118++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_5,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x11C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_5,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x120++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_5,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x124++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_5,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x128++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_5,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_6" width 28. group.long 0x130++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_6,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x134++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_6,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x14C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_6,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x138++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_6,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x13C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_6,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x140++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_6,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x144++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_6,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x148++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_6,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end tree "CTX_Line_7" width 28. group.long 0x150++0x3 line.long 0x00 "CSI2_CTX_CTRL1_i_7,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." bitfld.long 0x00 31. " BYTESWAP ,Allows swapping bytes two by two in the payload data. It does not affect: - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port - . - ." "DIS,EN" bitfld.long 0x00 30. " GENERIC ,Enables the generic mode. - . - ." "DIS,EN" bitfld.long 0x00 28. " HSCALE ,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x00 24.--27. " TRANSCODE ,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port format.." "DISABLED,RAW8_DPCM10,RAW8_DPCM12,RAW8_ALAW10,RAW8,RAW10,RAW10_PACKED,RAW12,RAW12_PACKED,RAW14,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FEC_NUMBER ,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory (must be used only in interlace mode, otherwise set to 1)." hexmask.long.byte 0x00 8.--15. 1. " COUNT ,Sets the number of frame to acquire. Once the frame acquisition starts, the COUNT value is decremented after every frame. When COUNT reaches 0, the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to 0. Writes to this.." textline " " bitfld.long 0x00 7. " EOF_EN ,Indicates if the end of frame signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " EOL_EN ,Indicates if the end of line signal shall be asserted at the end of the line. - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " CS_EN ,Enables the checksum check for the received payload (long packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " COUNT_UNLOCK ,Unlock writes to the COUNT bit field. - . - ." "Locked,Unlocked" bitfld.long 0x00 3. " PING_PONG ,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current con.." "Ping,Pong" bitfld.long 0x00 2. " VP_FORCE ,Forces sending of the data to both VPORT and OCP. Only applies to formats that existing in two versions: - One sending data to OCP port only - One sending data to VPORT only (tagged with the +VP extension) The format version sen.." "DIS,EN" textline " " bitfld.long 0x00 1. " LINE_MODULO ,Line modulo configuration - . - ." "Disable,Enable" bitfld.long 0x00 0. " CTX_EN ,Enables the context - . - ." "Disable,Enable" group.long 0x154++0x3 line.long 0x00 "CSI2_CTX_CTRL2_i_7,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORM.." hexmask.long.word 0x00 16.--31. 1. " FRAME ,Frame number received" bitfld.long 0x00 13.--14. " USER_DEF_MAPPING ,Selects the pixel format of USER_DEFINED in FORMAT - . - . - ." "RAW6,RAW7,RAW8,3" bitfld.long 0x00 11.--12. " VIRTUAL_ID ,Virtual channel ID - . - . - . - ." "V_ID_0,V_ID_1,V_ID_2,V_ID_3" textline " " bitfld.long 0x00 10. " DPCM_PRED ,Selects the DPCM predictor. - . - ." "Advanced,Simple" hexmask.long.word 0x00 0.--9. 1. " FORMAT ,Data format selection. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x16C++0x3 line.long 0x00 "CSI2_CTX_CTRL3_i_7,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code." hexmask.long.word 0x00 16.--29. 1. " ALPHA ,Alpha value for RGB888, RGB666 and RBG444." hexmask.long.word 0x00 0.--15. 1. " LINE_NUMBER ,Line number for the interrupt generation" group.long 0x158++0x3 line.long 0x00 "CSI2_CTX_DAT_OFST_i_7,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset, which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PON.." hexmask.long.word 0x00 5.--16. 1. " OFST ,Line offset programmed in bytes (signed value 2s complement). If OFST = 0, the data is written contiguously in memory. Otherwise, OFST sets the destination offset between the first pixel of the previous line and the first pixel of .." group.long 0x15C++0x3 line.long 0x00 "CSI2_CTX_DAT_PING_ADDR_i_7,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x160++0x3 line.long 0x00 "CSI2_CTX_DAT_PONG_ADDR_i_7,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double-buffered: this register sets the PONG address. Double-buffering is enabled when .." hexmask.long 0x00 5.--31. 1. " ADDR ,27 most-significant bits of the 32-bit address." group.long 0x164++0x3 line.long 0x00 "CSI2_CTX_IRQENABLE_i_7,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to context." bitfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to correct the only 1-bit error (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number is reached. - . - ." "Disable,Enable" bitfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum of the payload mismatch detection - . - ." "Disable,Enable" bitfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection. - . - ." "Disable,Enable" bitfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection. - . - ." "Disable,Enable" group.long 0x168++0x3 line.long 0x00 "CSI2_CTX_IRQSTATUS_i_7,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context." eventfld.long 0x00 8. " ECC_CORRECTION_IRQ ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). - . - ." "False,True" eventfld.long 0x00 7. " LINE_NUMBER_IRQ ,Context - Line number reached status. - . - ." "False,True" eventfld.long 0x00 6. " FRAME_NUMBER_IRQ ,Context - Frame counter reached status - . - ." "False,True" textline " " eventfld.long 0x00 5. " CS_IRQ ,Context - Check-Sum mismatch status. - . - ." "False,True" eventfld.long 0x00 3. " LE_IRQ ,Context - Line end sync code detection status. - . - ." "False,True" eventfld.long 0x00 2. " LS_IRQ ,Context - Line start sync code detection status. - . - ." "False,True" textline " " eventfld.long 0x00 1. " FE_IRQ ,Context - Frame end sync code detection status. - . - ." "False,True" eventfld.long 0x00 0. " FS_IRQ ,Context - Frame start sync code detection status. - . - ." "False,True" tree.end textline "" width 26. rgroup.long 0x0++0x3 line.long 0x00 "CSI2_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "CSI2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register." bitfld.long 0x00 12.--13. " MSTANDBY_MODE ,Sets the behavior of the master port power management signals. - . - . - ." "ForceStby,NoStdby,SmartStdby,3" bitfld.long 0x00 1. " SOFT_RESET ,Software reset. Set the bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads return 0. - . - ." "Normal,Reset" bitfld.long 0x00 0. " AUTO_IDLE ,Internal OCP gating strategy - . - ." "Free,Gated" rgroup.long 0x14++0x3 line.long 0x00 "CSI2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module, excluding the interrupt status register." bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring - . - ." "ResetOngoing,ResetCompleted" group.long 0x18++0x3 line.long 0x00 "CSI2_IRQSTATUS,INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt. The context shall be enabled for events to be generated on that context. If the c.." eventfld.long 0x00 14. " OCP_ERR_IRQ ,OCP Error Interrupt - . - ." "False,True" eventfld.long 0x00 13. " SHORT_PACKET_IRQ ,Short packet reception status (other than synch events: Line Start, Line End, Frame Start, and Frame End: data type between 0x8 and x0F only shall be considered). - . - ." "False,True" eventfld.long 0x00 12. " ECC_CORRECTION_IRQ ,ECC has been used to do the correction of the only 1-bit error status (short packet only). - . - ." "False,True" textline " " eventfld.long 0x00 11. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" bitfld.long 0x00 9. " COMPLEXIO_ERR_IRQ ,Error signaling from complex I/O: status of the PHY errors received from the complex I/O (events are defined inCSI2_COMPLEXIO_IRQSTATUS for the complex I/O). - . - ." "0,1" eventfld.long 0x00 8. " FIFO_OVF_IRQ ,FIFO overflow error status. - . - ." "False,True" textline " " bitfld.long 0x00 7. " CONTEXT7 ,Context 7 - . - ." "False,True" bitfld.long 0x00 6. " CONTEXT6 ,Context 6 - . - ." "False,True" bitfld.long 0x00 5. " CONTEXT5 ,Context 5 - . - ." "False,True" textline " " bitfld.long 0x00 4. " CONTEXT4 ,Context 4 - . - ." "False,True" bitfld.long 0x00 3. " CONTEXT3 ,Context 3 - . - ." "False,True" bitfld.long 0x00 2. " CONTEXT2 ,Context 2 - . - ." "False,True" textline " " bitfld.long 0x00 1. " CONTEXT1 ,Context 1 - . - ." "False,True" bitfld.long 0x00 0. " CONTEXT0 ,Context 0 - . - ." "False,True" group.long 0x1C++0x3 line.long 0x00 "CSI2_IRQENABLE,INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually." bitfld.long 0x00 14. " OCP_ERR_IRQ ,OCP Error Interrupt - . - ." "Disable,Enable" bitfld.long 0x00 13. " SHORT_PACKET_IRQ ,Short packet reception (other than synch events: Line Start, Line End, Frame Start, and Frame End: data type between 0x8 and x0F only shall be considered). - . - ." "Disable,Enable" bitfld.long 0x00 12. " ECC_CORRECTION_IRQ ,ECC has been used to correct the only 1-bit error (short packet only). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 11. " ECC_NO_CORRECTION_IRQ ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" bitfld.long 0x00 9. " COMPLEXIO_ERR_IRQ ,Error signaling from complex I/O: the interrupt is triggered when any error is received from the complex I/O (events are defined inCSI2_COMPLEXIO_IRQSTATUS for the complex I/O). - . - ." "Event_is_masked,1" bitfld.long 0x00 8. " FIFO_OVF_IRQ ,FIFO overflow enable - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CONTEXT7 ,Context 7 - . - ." "Disable,Enable" bitfld.long 0x00 6. " CONTEXT6 ,Context 6 - . - ." "Disable,Enable" bitfld.long 0x00 5. " CONTEXT5 ,Context 5 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " CONTEXT4 ,Context 4 - . - ." "Disable,Enable" bitfld.long 0x00 3. " CONTEXT3 ,Context 3 - . - ." "Disable,Enable" bitfld.long 0x00 2. " CONTEXT2 ,Context 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " CONTEXT1 ,Context 1 - . - ." "Disable,Enable" bitfld.long 0x00 0. " CONTEXT0 ,Context 0 - . - ." "Disable,Enable" group.long 0x40++0x3 line.long 0x00 "CSI2_CTRL,GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified dynamically (except IF_EN bit field)." bitfld.long 0x00 16. " BURST_SIZE_EXPAND ,Sets the DMA burst size on the L3 interconnect. - . - ." "DIS,EN" bitfld.long 0x00 15. " VP_CLK_EN ,VP clock enable. - . - ." "Disable,Enable" bitfld.long 0x00 13. " NON_POSTED_WRITE ,Not posted writes - . - ." "Disable,Enable" textline " " bitfld.long 0x00 11. " VP_ONLY_EN ,VP only enable. - . - ." "VP_OCP,VP" bitfld.long 0x00 10. " STREAMING_32_BIT ,Indicates if 64-bit or 32-bit streaming burst is used. Valid only if CSI2_CTRL.STREAMING=1 - . - ." "STREAM64,STREAM32" bitfld.long 0x00 8.--9. " VP_OUT_CTRL ,VP_PCLK control. Sets the VP_PCLK as a function of the ISS interconnect interface clock (OCPCLK). - . - . - . - ." "div1,div2,div3,div4" textline " " bitfld.long 0x00 7. " DBG_EN ,Enables the debug mode. - . - ." "Disable,Enable" bitfld.long 0x00 5.--6. " BURST_SIZE ,Sets the DMA burst size on the L3 interconnect. - . - . - . - ." "single,burst2x64,burst4x64,burst8x64" bitfld.long 0x00 4. " ENDIANNESS ,Select endianness for YUV4:2:2 8 bit and YUV4:2:0 legacy formats. - . - ." "NATIVE,ALL_LE" textline " " bitfld.long 0x00 3. " FRAME ,Set the modality in which IF_EN works. - . - ." "Immediate,Frame" bitfld.long 0x00 2. " ECC_EN ,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids). - . - ." "Disable,Enable" bitfld.long 0x00 0. " IF_EN ,Enables the physical interface to the module. - . - ." "Disable,Enable" wgroup.long 0x44++0x3 line.long 0x00 "CSI2_DBG_H,DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by .DBG_EN. Only full 32-bit values shall be written. The register is used to writ.." hexmask.long 0x00 0.--31. 1. " DBG ,32-bit input value." group.long 0x50++0x3 line.long 0x00 "CSI2_COMPLEXIO_CFG,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in add.." bitfld.long 0x00 30. " RESET_CTRL ,Controls the reset of the complex I/O - . - ." "0,1" bitfld.long 0x00 29. " RESET_DONE ,Internal reset monitoring of the power domain using the byte clock provided by the associated CSIPHY (see, .Caution:For the [29] RESET_DONE bit to be set to 0x1 (reset completed), the external sensor must to be activ.." "0,Reset_completed." bitfld.long 0x00 27.--28. " PWR_CMD ,Command for power control of the complex I/O - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 25.--26. " PWR_STATUS ,Status of the power control of the complex I/O - . - . - ." "0,1,2,3" bitfld.long 0x00 24. " PWR_AUTO ,Automatic switch between ULP and ON states based on ULPM signals from complex I/O - . - ." "Disable,Enable" bitfld.long 0x00 19. " DATA4_POL ,+/- differential pin order of data lane 4. - . - ." "+/-_pin_order,-/+_pin_order" textline " " bitfld.long 0x00 16.--18. " DATA4_POSITION ,Position and order of the data lane 4. The values 6 and 7 are reserved. This lane is not available to the CSI2-B receiver. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,?..." bitfld.long 0x00 15. " DATA3_POL ,+/- differential pin order of data lane 3. - . - ." "+/-_pin_order,-/+_pin_order" bitfld.long 0x00 12.--14. " DATA3_POSITION ,Position and order of the data lane 3. The values 6 and 7 are reserved. This lane is not available to the CSI2-B receiver. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,?..." textline " " bitfld.long 0x00 11. " DATA2_POL ,+/- differential pin order of DATA lane 2. - . - ." "0,1" bitfld.long 0x00 8.--10. " DATA2_POSITION ,Position and order of the data lane 2. The values 6 and 7 are reserved. This lane is not available to the CSI2-B receiver. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,?..." bitfld.long 0x00 7. " DATA1_POL ,+/- differential pin order of data lane 1. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " DATA1_POSITION ,Position and order of the DATA lane 1.The values 6 and 7 are reserved. When CSI2 is used, the data lane 1 position must be different from 0, 6, or 7. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,?..." bitfld.long 0x00 3. " CLOCK_POL ,+/- differential pin order of clock lane. - . - ." "0,1" bitfld.long 0x00 0.--2. " CLOCK_POSITION ,Position and order of the clock lane. The values 5, 6, and 7 are reserved. When CSI2 is used, the clock lane position must be different from 0, 5, 6, or 7. - . - . - . - . - . - . - . - ." "0,1,2,3,4,?..." group.long 0x54++0x3 line.long 0x00 "CSI2_COMPLEXIO_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex I/O #1" eventfld.long 0x00 26. " STATEALLULPMEXIT ,At least one of the active lanes has exit the ULPM - . - ." "0,1" eventfld.long 0x00 25. " STATEALLULPMENTER ,All active lanes are entering in ULPM. - . - ." "0,1" eventfld.long 0x00 24. " STATEULPM5 ,Lane 5 in ULPM - . - ." "0,1" textline " " eventfld.long 0x00 23. " STATEULPM4 ,Lane 4 in ULPM - . - ." "0,1" eventfld.long 0x00 22. " STATEULPM3 ,Lane 3 in ULPM - . - ." "0,1" eventfld.long 0x00 21. " STATEULPM2 ,Lane 2 in ULPM - . - ." "0,1" textline " " eventfld.long 0x00 20. " STATEULPM1 ,Lane 1 in ULPM - . - ." "0,1" eventfld.long 0x00 19. " ERRCONTROL5 ,Control error for lane 5 - . - ." "0,1" eventfld.long 0x00 18. " ERRCONTROL4 ,Control error for lane 4 - . - ." "0,1" textline " " eventfld.long 0x00 17. " ERRCONTROL3 ,Control error for lane 3 - . - ." "0,1" eventfld.long 0x00 16. " ERRCONTROL2 ,Control error for lane 2 - . - ." "0,1" eventfld.long 0x00 15. " ERRCONTROL1 ,Control error for lane 1 - . - ." "0,1" textline " " eventfld.long 0x00 14. " ERRESC5 ,Escape entry error for lane 5 - . - ." "0,1" eventfld.long 0x00 13. " ERRESC4 ,Escape entry error for lane 4 - . - ." "0,1" eventfld.long 0x00 12. " ERRESC3 ,Escape entry error for lane 3 - . - ." "0,1" textline " " eventfld.long 0x00 11. " ERRESC2 ,Escape entry error for lane 2 - . - ." "0,1" eventfld.long 0x00 10. " ERRESC1 ,Escape entry error for lane 1 - . - ." "0,1" eventfld.long 0x00 9. " ERRSOTSYNCHS5 ,Start of transmission sync error for lane 5 - . - ." "0,1" textline " " eventfld.long 0x00 8. " ERRSOTSYNCHS4 ,Start of transmission sync error for lane 4 - . - ." "0,1" eventfld.long 0x00 7. " ERRSOTSYNCHS3 ,Start of transmission sync error for lane 3 - . - ." "0,1" eventfld.long 0x00 6. " ERRSOTSYNCHS2 ,Start of transmission sync error for lane 2 - . - ." "0,1" textline " " eventfld.long 0x00 5. " ERRSOTSYNCHS1 ,Start of transmission sync error for lane 1 - . - ." "0,1" eventfld.long 0x00 4. " ERRSOTHS5 ,Start of transmission error for lane 5 - . - ." "0,1" eventfld.long 0x00 3. " ERRSOTHS4 ,Start of transmission error for lane 4 - . - ." "0,1" textline " " eventfld.long 0x00 2. " ERRSOTHS3 ,Start of transmission error for lane 3 - . - ." "0,1" eventfld.long 0x00 1. " ERRSOTHS2 ,Start of transmission error for lane 2 - . - ." "0,1" eventfld.long 0x00 0. " ERRSOTHS1 ,Start of transmission error for lane 1 - . - ." "0,1" rgroup.long 0x5C++0x3 line.long 0x00 "CSI2_SHORT_PACKET,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.tbyte 0x00 0.--23. 1. " SHORT_PACKET ,Short Packet information: DATA ID + DATA FIELD" group.long 0x60++0x3 line.long 0x00 "CSI2_COMPLEXIO_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex I/O" bitfld.long 0x00 26. " STATEALLULPMEXIT ,At least one of the active lanes has exit the ULPM - . - ." "Event_is_masked,1" bitfld.long 0x00 25. " STATEALLULPMENTER ,All active lanes are entering in ULPM. - . - ." "Event_is_masked,1" bitfld.long 0x00 24. " STATEULPM5 ,Lane 5 in ULPM - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 23. " STATEULPM4 ,Lane 4 in ULPM - . - ." "Event_is_masked,1" bitfld.long 0x00 22. " STATEULPM3 ,Lane 3 in ULPM - . - ." "Event_is_masked,1" bitfld.long 0x00 21. " STATEULPM2 ,Lane 2 in ULPM - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 20. " STATEULPM1 ,Lane 1 in ULPM - . - ." "Event_is_masked,1" bitfld.long 0x00 19. " ERRCONTROL5 ,Control error for lane 5 - . - ." "Event_is_masked,1" bitfld.long 0x00 18. " ERRCONTROL4 ,Control error for lane 4 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 17. " ERRCONTROL3 ,Control error for lane 3 - . - ." "Event_is_masked,1" bitfld.long 0x00 16. " ERRCONTROL2 ,Control error for lane 2 - . - ." "Event_is_masked,1" bitfld.long 0x00 15. " ERRCONTROL1 ,Control error for lane 1 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 14. " ERRESC5 ,Escape entry error for lane 5 - . - ." "Event_is_masked,1" bitfld.long 0x00 13. " ERRESC4 ,Escape entry error for lane 4 - . - ." "Event_is_masked,1" bitfld.long 0x00 12. " ERRESC3 ,Escape entry error for lane 3 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 11. " ERRESC2 ,Escape entry error for lane 2 - . - ." "Event_is_masked,1" bitfld.long 0x00 10. " ERRESC1 ,Escape entry error for lane 1 - . - ." "Event_is_masked,1" bitfld.long 0x00 9. " ERRSOTSYNCHS5 ,Start of transmission sync error for lane 5 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 8. " ERRSOTSYNCHS4 ,Start of transmission sync error for lane 4 - . - ." "Event_is_masked,1" bitfld.long 0x00 7. " ERRSOTSYNCHS3 ,Start of transmission sync error for lane 3 - . - ." "Event_is_masked,1" bitfld.long 0x00 6. " ERRSOTSYNCHS2 ,Start of transmission sync error for lane 2 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 5. " ERRSOTSYNCHS1 ,Start of transmission sync error for lane 1 - . - ." "Event_is_masked,1" bitfld.long 0x00 4. " ERRSOTHS5 ,Start of transmission error for lane 5 - . - ." "Event_is_masked,1" bitfld.long 0x00 3. " ERRSOTHS4 ,Start of transmission error for lane 4 - . - ." "Event_is_masked,1" textline " " bitfld.long 0x00 2. " ERRSOTHS3 ,Start of transmission error for lane 3 - . - ." "Event_is_masked,1" bitfld.long 0x00 1. " ERRSOTHS2 ,Start of transmission error for lane 2 - . - ." "Event_is_masked,1" bitfld.long 0x00 0. " ERRSOTHS1 ,Start of transmission error for lane 1 - . - ." "Event_is_masked,1" wgroup.long 0x68++0x3 line.long 0x00 "CSI2_DBG_P,DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by .DBG_EN. Only full 32-bit values shall be written. The register is used to wri.." hexmask.long 0x00 0.--31. 1. " DBG ,32-bit input value." group.long 0x6C++0x3 line.long 0x00 "CSI2_TIMING,TIMING REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified while .IF_EN is set to 1. It is used to indicate the number of L3 cycles for the Stop State monitoring." bitfld.long 0x00 15. " FORCE_RX_MODE_IO1 ,Control of ForceRxMode signal - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " STOP_STATE_X16_IO1 ,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit field - . - ." "Disable,Enable" bitfld.long 0x00 13. " STOP_STATE_X4_IO1 ,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit field - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 0.--12. 1. " STOP_STATE_COUNTER_IO1 ,Stop State counter for monitoring. It indicates the number of L3 to monitor for Stop State before deasserting ForceRxMode (complex I/O 1). The value is from 0 to 8191." tree.end tree.end tree "ISS_TCTRL" base ad:0x52000400 width 21. rgroup.long 0x0++0x3 line.long 0x00 "TCTRL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x4++0x3 line.long 0x00 "TCTRL_SYSCONFIG,OCP-SOCKET SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 1. " SOFT_RESET ,Software reset. Set the bit to 1 to trigger the module reset. The bit is automatically reset be the hardware. During reads return 0. - . - ." "Normal,Reset" bitfld.long 0x00 0. " AUTO_IDLE ,Internal OCP and functional clock gating strategy - . - ." "Free,Gated" rgroup.long 0x8++0x3 line.long 0x00 "TCTRL_SYSSTATUS,OCP-SOCKET SYSTEM STATUS REGISTER" bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring - . - ." "Ongoing,Completed" group.long 0x10++0x3 line.long 0x00 "TCTRL_STRB_LENGTH,TIMING CONTROL - STROBE LENGTH REGISTER This register is used by the TIMING CTRL module to generate the STROBE signal." hexmask.long.tbyte 0x00 0.--23. 1. " LENGTH ,Sets the length of the CAM_STROBE signal assertion in cycles of the CNTCLK clock. The CNTCLK frequency is generated with theTCTRL_CTRL.DIVC bit field. After signal assertion, the TCTRL_CTRL.STRBEN bit is automatically cleared. The possible.." group.long 0x14++0x3 line.long 0x00 "TCTRL_PSTRB_LENGTH,TIMING CONTROL - PRESTROBE LENGTH REGISTER This register is used by the TIMING CTRL module to generate the PRESTROBE signal." hexmask.long.tbyte 0x00 0.--23. 1. " LENGTH ,Sets the length of the CAM_PRESTROBE signal assertion in cycles of the CNTCLK clock. The CNTCLK frequency is generated with theTCTRL_CTRL.DIVC bit field. After signal assertion, the TCTRL_CTRL.PSTRBEN bit is automatically cleared. The poss.." group.long 0x18++0x3 line.long 0x00 "TCTRL_SHUT_LENGTH,TIMING CONTROL - SHUTTER LENGTH REGISTER This register is used by the TIMING CTRL module to generate the SHUTTER signal." hexmask.long.tbyte 0x00 0.--23. 1. " LENGTH ,Sets the length of the CAM_SHUTTER signal assertion in cycles of the CNTCLK clock. The CNTCLK frequency is generated with theTCTRL_CTRL.DIVC bit field. After signal assertion, the TCTRL_CTRL.SHUTEN bit is automatically cleared. The possibl.." group.long 0x1C++0x3 line.long 0x00 "TCTRL_GRESET_LENGTH,TIMING CONTROL - GLOBAL SHUTTER LENGTH REGISTER This register is used by the TIMING CTRL module to generate the CAM.GRESET signal." hexmask.long.tbyte 0x00 0.--23. 1. " LENGTH ,Sets the length of the CAM_GLOBAL_RESET signal assertion in cycles of the CNTCLK clock. The CNTCLK frequency is generated with the TCTRL_CTRL.DIVC bit field. After signal assertion, the TCTRL_CTRL.GRESETEN bit is automatically cleared. The.." group.long 0x20++0x3 line.long 0x00 "TCTRL_STRB_DELAY,TIMING CONTROL - STROBE DELAY REGISTER This register is used by the TIMING CTRL module to generate the STROBE signal." hexmask.long 0x00 0.--24. 1. " DELAY ,Sets the delay for the CAM_STROBE signal assertion in cycles of the CNTCLK clock. The CNTCLK frequency is generated with theTCTRL_CTRL.DIVC bit field. The possible values are 0 to 2-1 cycles." group.long 0x24++0x3 line.long 0x00 "TCTRL_PSTRB_DELAY,TIMING CONTROL - PRE STROBE DELAY REGISTER This register is used by the TIMING CTRL module to generate the PRESTROBE signal." hexmask.long 0x00 0.--24. 1. " DELAY ,Sets the delay for the CAM_PSTROBE signal assertion in cycles of the CNTCLK clock. The CNTCLK frequency is generated with theTCTRL_CTRL.DIVC bit field. The possible values are 0 to 2-1 cycles." group.long 0x28++0x3 line.long 0x00 "TCTRL_SHUT_DELAY,TIMING CONTROL - SHUTTER DELAY REGISTER This register is used by the TIMING CTRL module to generate the SHUTTER signal." hexmask.long 0x00 0.--24. 1. " DELAY ,Sets the delay for the CAM_SHUTTER signal assertion in cycles of the CNTCLK clock. The CNTCLK frequency is generated with theTCTRL_CTRL.DIVC bit field. The possible values are 0 to 2-1 cycles." group.long 0x30++0x3 line.long 0x00 "TCTRL_CTRL,TIMING CONTROL - CONTROL REGISTER" bitfld.long 0x00 31. " GRESETDIR ,Sets the direction of the GLOBAL_RESET signal. 0x0: INPUT ? GLOBAL_RESET is an input to the TIMING CONTROL module. GLOBAL_RESET is externally generated. 0x1: OUTPUT ? GLOBAL_RESET is an output of the TIMING CONTROL module. GLOBAL_RESET is .." "0,1" bitfld.long 0x00 30. " GRESETPOL ,Sets the polarity of the global reset signal: CAM_GLOBAL_RESET. It applies whatever the direction of the GLOBAL_RESET signal: input or output. 0x0: active high 0x1: active low" "0,1" bitfld.long 0x00 29. " GRESETEN ,Triggers the generation of the CAM_GLOBAL_RESET signal. The signal is asserted immediately. If enabled, the CAM_GLOBAL_RESET signal will be asserted forTCTRL_GRESET_LENGTH cycles. After the signal assertion, the enable bit is automat.." "0,1" textline " " bitfld.long 0x00 27.--28. " INSEL ,Sets the mode that will trigger the SHUTTER, PRESTROBE and STROBE signals. - . - . - . - ." "CAMEVT0,CAMEVT1,CAMEVT2,GRESET" bitfld.long 0x00 26. " STRBPSTRBPOL ,Sets the polarity of the strobe and prestrobe signals. - . - ." "High,Low" bitfld.long 0x00 24. " SHUTPOL ,Sets the polarity of the mechanical shutter signal: CAM_SHUTTER - . - ." "High,Low" textline " " bitfld.long 0x00 23. " STRBEN ,Flash strobe signal enable. If enabled, the STROBE signal will be asserted afterTCTRL_FRAME.STRB frames have been received and a delay of TCTRL_STRB_DELAY cycles have passed. The STROBE signal is asserted for TCTRL_STRB_LENGTH cycles. Afte.." "0,1" bitfld.long 0x00 22. " PSTRBEN ,Flash prestrobe signal enable. If enabled, the PRESTROBE signal will be asserted afterTCTRL_FRAME.PSTRB frames have been received and a delay of TCTRL_PSTRB_DELAY cycles have passed. The PRESTROBE signal is asserted for TCTRL_PS.." "0,1" bitfld.long 0x00 21. " SHUTEN ,Mechanical shutter signal enable. If enabled, the SHUTTER signal will be asserted afterTCTRL_FRAME.SHUT frames have been received and a delay of TCTRL_SHUT_DELAY cycles have passed. The SHUTTER signal is asserted for TCTRL_SHUT_LENGT.." "0,1" textline " " hexmask.long.word 0x00 10.--18. 1. " DIVC ,Sets the clock divisor value for the CNTCLK clock generation based on the CLK input clock. CNTCLK is an internal clock used by the TIMING CTRL module counters. Usually, CNTCLK = CLK / DIVC, except for some particular values shown hereafter.." group.long 0x34++0x3 line.long 0x00 "TCTRL_PSTRB_REPLAY,TIMING CONTROL - PRESTROBE REPLAY REGISTER This register is used by the TIMING CTRL module to generate the prestrobe signal." hexmask.long.byte 0x00 25.--31. 1. " COUNTER ,Sets the number of PRESTROBE pulses after the original pulse. If this bit is set to 0, the PRESTROBE signal behavior is only controlled by TCTRL_FRAME.STRB, TCTRL_PSTRB_DELAY, and TCTRL_PSTRB_LENGTH. If TCTRL_PSTRB_LENGTH=0, there is no re.." hexmask.long 0x00 0.--24. 1. " DELAY ,Sets the delay for the PRESTROBE signal reassertion in cycles of the CNTCLK clock. The CNTCLK frequency is generated with theTCTRL_CTRL.DIVC bit field. The possible values are 0 to 2-1 cycles. If TCTRL_PSTRB_LENGTH=0, there is no.." group.long 0x38++0x3 line.long 0x00 "TCTRL_FRAME,TIMING CONTROL - FRAME REGISTER This register is used by the TIMING CTRL module to generate the SHUTTER, PRESTROBE, and STROBE signals." bitfld.long 0x00 12.--17. " STRB ,Frame counter for the STROBE signal generation. From 0 to 63 frames. This bit field is ignored if TCTRL.INSEL=GRESET." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " PSTRB ,Frame counter for the PRESTROBE signal generation. From 0 to 63 frames. This bit field is ignored if TCTRL.INSEL=GRESET." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " SHUT ,Frame counter for the SHUTTER signal generation. From 0 to 63 frames. This bit field is ignored if TCTRL.INSEL=GRESET." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "ISS_BTE" base ad:0x52002000 tree "Channel_0" width 23. group.long 0x44++0x3 line.long 0x00 "BTE_CONTEXT_BASE_i_0,Address of the frame buffer in the TILER address space." hexmask.long 0x00 5.--31. 1. " ADDR ,Address" group.long 0x40++0x3 line.long 0x00 "BTE_CONTEXT_CTRL_i_0,Context control register" hexmask.long.word 0x00 16.--29. 1. " TRIGGER ,Threshold used to trigger translated requests to OCPO. Unit: words or 16 bytes Valid range: 3 lines + 2 ... 4 lines WRITE: a 2D write is issued to OCPO when the internal buffer level (including masked accesses) is superior or equal to TRIGGER.." bitfld.long 0x00 15. " INITSX ,Reset value to be used for SX__x. Check the section describing the local buffer management for details." "0,1" bitfld.long 0x00 13.--14. " INITSY ,Reset value to be used for SY__x. Check the section describing the local buffer management for details. Must be 0 when ONESHOT = 0" "0,1,2,3" textline " " bitfld.long 0x00 12. " ADDR32 ,Controls the value of the OCP address bit 32 to be used for translated accesses" "0,1" bitfld.long 0x00 11. " AUTOFLUSH ,Controls automatic context flushing when an IDLE request is received - . - ." "DIS,EN" bitfld.long 0x00 10. " ONESHOT ,Selects one-shot or continuous mode - . - ." "CONTINOUS,ONESHOT" textline " " bitfld.long 0x00 8.--9. " GRID ,Grid used to access the TILER - . - . - . - ." "G0,G1,G2,G3" bitfld.long 0x00 6.--7. " MODE ,Select the translation mode for the context - . - . - . - ." "WRITE,READ,MEMORY,RSZ" bitfld.long 0x00 2. " FLUSH ,Flushes all remaining data of the context to the TILER. - . - ." "NOEFF,GO" textline " " bitfld.long 0x00 1. " STOP ,Stops the context on a clean OCP transaction boundary. - . - ." "NOEFFECT,STOP" bitfld.long 0x00 0. " START ,Resets the contexts internal state and enables the context on a clean OCP transaction boundary. - . - ." "NOEFFECT,ENABLE" group.long 0x4C++0x3 line.long 0x00 "BTE_CONTEXT_END_i_0,Bottom-right corner of the context." hexmask.long.word 0x00 16.--28. 1. " Y ,Last line number for the context (0 corresponds to a context of 1 line) Must be 7 when ONESHOT = 0" hexmask.long.word 0x00 4.--15. 1. " X ,Address, in 128-bit words, of the last column of the context" group.long 0x48++0x3 line.long 0x00 "BTE_CONTEXT_START_i_0,Top-left corner of the context." hexmask.long.word 0x00 7.--15. 1. " X ,Address, in 128-byte words" tree.end tree "Channel_1" width 23. group.long 0x64++0x3 line.long 0x00 "BTE_CONTEXT_BASE_i_1,Address of the frame buffer in the TILER address space." hexmask.long 0x00 5.--31. 1. " ADDR ,Address" group.long 0x60++0x3 line.long 0x00 "BTE_CONTEXT_CTRL_i_1,Context control register" hexmask.long.word 0x00 16.--29. 1. " TRIGGER ,Threshold used to trigger translated requests to OCPO. Unit: words or 16 bytes Valid range: 3 lines + 2 ... 4 lines WRITE: a 2D write is issued to OCPO when the internal buffer level (including masked accesses) is superior or equal to TRIGGER.." bitfld.long 0x00 15. " INITSX ,Reset value to be used for SX__x. Check the section describing the local buffer management for details." "0,1" bitfld.long 0x00 13.--14. " INITSY ,Reset value to be used for SY__x. Check the section describing the local buffer management for details. Must be 0 when ONESHOT = 0" "0,1,2,3" textline " " bitfld.long 0x00 12. " ADDR32 ,Controls the value of the OCP address bit 32 to be used for translated accesses" "0,1" bitfld.long 0x00 11. " AUTOFLUSH ,Controls automatic context flushing when an IDLE request is received - . - ." "DIS,EN" bitfld.long 0x00 10. " ONESHOT ,Selects one-shot or continuous mode - . - ." "CONTINOUS,ONESHOT" textline " " bitfld.long 0x00 8.--9. " GRID ,Grid used to access the TILER - . - . - . - ." "G0,G1,G2,G3" bitfld.long 0x00 6.--7. " MODE ,Select the translation mode for the context - . - . - . - ." "WRITE,READ,MEMORY,RSZ" bitfld.long 0x00 2. " FLUSH ,Flushes all remaining data of the context to the TILER. - . - ." "NOEFF,GO" textline " " bitfld.long 0x00 1. " STOP ,Stops the context on a clean OCP transaction boundary. - . - ." "NOEFFECT,STOP" bitfld.long 0x00 0. " START ,Resets the contexts internal state and enables the context on a clean OCP transaction boundary. - . - ." "NOEFFECT,ENABLE" group.long 0x6C++0x3 line.long 0x00 "BTE_CONTEXT_END_i_1,Bottom-right corner of the context." hexmask.long.word 0x00 16.--28. 1. " Y ,Last line number for the context (0 corresponds to a context of 1 line) Must be 7 when ONESHOT = 0" hexmask.long.word 0x00 4.--15. 1. " X ,Address, in 128-bit words, of the last column of the context" group.long 0x68++0x3 line.long 0x00 "BTE_CONTEXT_START_i_1,Top-left corner of the context." hexmask.long.word 0x00 7.--15. 1. " X ,Address, in 128-byte words" tree.end tree "Channel_2" width 23. group.long 0x84++0x3 line.long 0x00 "BTE_CONTEXT_BASE_i_2,Address of the frame buffer in the TILER address space." hexmask.long 0x00 5.--31. 1. " ADDR ,Address" group.long 0x80++0x3 line.long 0x00 "BTE_CONTEXT_CTRL_i_2,Context control register" hexmask.long.word 0x00 16.--29. 1. " TRIGGER ,Threshold used to trigger translated requests to OCPO. Unit: words or 16 bytes Valid range: 3 lines + 2 ... 4 lines WRITE: a 2D write is issued to OCPO when the internal buffer level (including masked accesses) is superior or equal to TRIGGER.." bitfld.long 0x00 15. " INITSX ,Reset value to be used for SX__x. Check the section describing the local buffer management for details." "0,1" bitfld.long 0x00 13.--14. " INITSY ,Reset value to be used for SY__x. Check the section describing the local buffer management for details. Must be 0 when ONESHOT = 0" "0,1,2,3" textline " " bitfld.long 0x00 12. " ADDR32 ,Controls the value of the OCP address bit 32 to be used for translated accesses" "0,1" bitfld.long 0x00 11. " AUTOFLUSH ,Controls automatic context flushing when an IDLE request is received - . - ." "DIS,EN" bitfld.long 0x00 10. " ONESHOT ,Selects one-shot or continuous mode - . - ." "CONTINOUS,ONESHOT" textline " " bitfld.long 0x00 8.--9. " GRID ,Grid used to access the TILER - . - . - . - ." "G0,G1,G2,G3" bitfld.long 0x00 6.--7. " MODE ,Select the translation mode for the context - . - . - . - ." "WRITE,READ,MEMORY,RSZ" bitfld.long 0x00 2. " FLUSH ,Flushes all remaining data of the context to the TILER. - . - ." "NOEFF,GO" textline " " bitfld.long 0x00 1. " STOP ,Stops the context on a clean OCP transaction boundary. - . - ." "NOEFFECT,STOP" bitfld.long 0x00 0. " START ,Resets the contexts internal state and enables the context on a clean OCP transaction boundary. - . - ." "NOEFFECT,ENABLE" group.long 0x8C++0x3 line.long 0x00 "BTE_CONTEXT_END_i_2,Bottom-right corner of the context." hexmask.long.word 0x00 16.--28. 1. " Y ,Last line number for the context (0 corresponds to a context of 1 line) Must be 7 when ONESHOT = 0" hexmask.long.word 0x00 4.--15. 1. " X ,Address, in 128-bit words, of the last column of the context" group.long 0x88++0x3 line.long 0x00 "BTE_CONTEXT_START_i_2,Top-left corner of the context." hexmask.long.word 0x00 7.--15. 1. " X ,Address, in 128-byte words" tree.end tree "Channel_3" width 23. group.long 0xA4++0x3 line.long 0x00 "BTE_CONTEXT_BASE_i_3,Address of the frame buffer in the TILER address space." hexmask.long 0x00 5.--31. 1. " ADDR ,Address" group.long 0xA0++0x3 line.long 0x00 "BTE_CONTEXT_CTRL_i_3,Context control register" hexmask.long.word 0x00 16.--29. 1. " TRIGGER ,Threshold used to trigger translated requests to OCPO. Unit: words or 16 bytes Valid range: 3 lines + 2 ... 4 lines WRITE: a 2D write is issued to OCPO when the internal buffer level (including masked accesses) is superior or equal to TRIGGER.." bitfld.long 0x00 15. " INITSX ,Reset value to be used for SX__x. Check the section describing the local buffer management for details." "0,1" bitfld.long 0x00 13.--14. " INITSY ,Reset value to be used for SY__x. Check the section describing the local buffer management for details. Must be 0 when ONESHOT = 0" "0,1,2,3" textline " " bitfld.long 0x00 12. " ADDR32 ,Controls the value of the OCP address bit 32 to be used for translated accesses" "0,1" bitfld.long 0x00 11. " AUTOFLUSH ,Controls automatic context flushing when an IDLE request is received - . - ." "DIS,EN" bitfld.long 0x00 10. " ONESHOT ,Selects one-shot or continuous mode - . - ." "CONTINOUS,ONESHOT" textline " " bitfld.long 0x00 8.--9. " GRID ,Grid used to access the TILER - . - . - . - ." "G0,G1,G2,G3" bitfld.long 0x00 6.--7. " MODE ,Select the translation mode for the context - . - . - . - ." "WRITE,READ,MEMORY,RSZ" bitfld.long 0x00 2. " FLUSH ,Flushes all remaining data of the context to the TILER. - . - ." "NOEFF,GO" textline " " bitfld.long 0x00 1. " STOP ,Stops the context on a clean OCP transaction boundary. - . - ." "NOEFFECT,STOP" bitfld.long 0x00 0. " START ,Resets the contexts internal state and enables the context on a clean OCP transaction boundary. - . - ." "NOEFFECT,ENABLE" group.long 0xAC++0x3 line.long 0x00 "BTE_CONTEXT_END_i_3,Bottom-right corner of the context." hexmask.long.word 0x00 16.--28. 1. " Y ,Last line number for the context (0 corresponds to a context of 1 line) Must be 7 when ONESHOT = 0" hexmask.long.word 0x00 4.--15. 1. " X ,Address, in 128-bit words, of the last column of the context" group.long 0xA8++0x3 line.long 0x00 "BTE_CONTEXT_START_i_3,Top-left corner of the context." hexmask.long.word 0x00 7.--15. 1. " X ,Address, in 128-byte words" tree.end textline "" width 22. rgroup.long 0x0++0x3 line.long 0x00 "BTE_HL_REVISION,IP revision identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" rgroup.long 0x4++0x3 line.long 0x00 "BTE_HL_HWINFO,Information about the hardware configuration of the IP module; that is, typically, the HDL generics (if any) of the module." bitfld.long 0x00 21.--23. " RESPFIFO ,Response FIFO size - . - . - . - . - . - . - . - ." "RSZ1,S16,S32,S64,S128,RSZ2,RSZ3,RSZ4" bitfld.long 0x00 19.--20. " CONTEXTS ,Number of contexts - . - . - . - ." "C2,C4,C8,RSV" group.long 0x10++0x3 line.long 0x00 "BTE_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "FORCEIDLE,NOIDLE,SMARTIDLE1,SMARTIDLE2" bitfld.long 0x00 0. " SOFTRESET ,Software reset. - . - . - . - ." "done_/_noaction,pending_/_reset" group.long 0x20++0x3 line.long 0x00 "BTE_HL_IRQSTATUS_RAW,Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 27. " IRQ_CTX3_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 26. " IRQ_CTX2_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 25. " IRQ_CTX1_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 24. " IRQ_CTX0_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 19. " IRQ_CTX3_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 18. " IRQ_CTX2_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 17. " IRQ_CTX1_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " IRQ_CTX0_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " IRQ_CTX3_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 10. " IRQ_CTX2_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 9. " IRQ_CTX1_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 8. " IRQ_CTX0_DONE ,Write mode: Context has been fully transferred to the TILER Read mode: Context prefetch has completed. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 1. " IRQ_INVALID ,Invalid access to the virtual space - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 0. " IRQ_OCP_ERR ,OCP error received from OCP master port. - . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x24++0x3 line.long 0x00 "BTE_HL_IRQSTATUS,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 27. " IRQ_CTX3_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 26. " IRQ_CTX2_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 25. " IRQ_CTX1_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 24. " IRQ_CTX0_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 19. " IRQ_CTX3_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 18. " IRQ_CTX2_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 17. " IRQ_CTX1_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 16. " IRQ_CTX0_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " IRQ_CTX3_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 10. " IRQ_CTX2_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 9. " IRQ_CTX1_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 8. " IRQ_CTX0_DONE ,Write mode: Context has been fully transferred to the TILER Read mode: Context prefetch has completed. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 1. " IRQ_INVALID ,Invalid access to the virtual space - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 0. " IRQ_OCP_ERR ,OCP error received from OCP master port. - . - . - . - ." "noaction_/_noevent,clear_/_pending" group.long 0x28++0x3 line.long 0x00 "BTE_HL_IRQENABLE_SET,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 27. " IRQ_CTX3_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 26. " IRQ_CTX2_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 25. " IRQ_CTX1_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 24. " IRQ_CTX0_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 19. " IRQ_CTX3_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 18. " IRQ_CTX2_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 17. " IRQ_CTX1_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " IRQ_CTX0_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " IRQ_CTX3_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 10. " IRQ_CTX2_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " IRQ_CTX1_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 8. " IRQ_CTX0_DONE ,Write mode: Context has been fully transferred to the TILER Read mode: Context prefetch has completed. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 1. " IRQ_INVALID ,Invalid access to the virtual space - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " IRQ_OCP_ERR ,OCP error received from OCP master port. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x2C++0x3 line.long 0x00 "BTE_HL_IRQENABLE_CLR,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 27. " IRQ_CTX3_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 26. " IRQ_CTX2_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 25. " IRQ_CTX1_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 24. " IRQ_CTX0_ERR ,Read request received before sufficient data has been prefetched. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 19. " IRQ_CTX3_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 18. " IRQ_CTX2_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 17. " IRQ_CTX1_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 16. " IRQ_CTX0_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " IRQ_CTX3_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 10. " IRQ_CTX2_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " IRQ_CTX1_DONE ,Context has been fully transferred to the TILER - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 8. " IRQ_CTX0_DONE ,Write mode: Context has been fully transferred to the TILER Read mode: Context prefetch has completed. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 1. " IRQ_INVALID ,Invalid access to the virtual space - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " IRQ_OCP_ERR ,OCP error received from OCP master port. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x30++0x3 line.long 0x00 "BTE_CTRL,BTE control register" hexmask.long.word 0x00 22.--31. 1. " BW_LIMITER ,Minimum number of OCP cycles between two consecutive buffer flushing or prefetch requests. Used to limit the bandwidth used to fill/empty buffers. 0: Maximum speed. Up to 1 request every 8 cycles (3.2GB @ 200 MHz) 1: Up to 1 request .." bitfld.long 0x00 8.--11. " BASE ,Base address of the virtual space translated by the BTE. Start address = BASE*512MB End address = (BASE+1)*512MB ? 1 For example: BASE=3 =&gt; 0x 0 6000 0000 - 0x 0 7FFF FFFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " POSTED ,Select among posted and nonposted writes for translated requests. - . - ." "NONPOSTED,POSTED" textline " " bitfld.long 0x00 0.--3. " TAG_CNT ,BTE could use up to TAG_CNT+1 tags on OCPO. There could only be one outstanding request per tag. TAG_CNT does not control the number of requests it could handle on OCPI. This register is internally shadowed. Modifications are taken i.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x3 line.long 0x00 "BTE_CTRL1,BTE control register" hexmask.long.byte 0x00 0.--6. 1. " RESP_FIFO_THR ,The BTE stops accepting new requests from OCPI (on a clean burst boundary) when the response FIFO contains more than RESP_FIFO_THR words. The reset value is FIFO_SIZE - 16 - 1. FIFO_SIZE = 8 * 2" tree.end tree "ISS_CBUFF" base ad:0x52001800 tree "CTX_Line_0" width 27. group.long 0x100++0x3 line.long 0x00 "CBUFF_CTX_CTRL_i_0,Context control register" bitfld.long 0x00 11. " TILERMODE ,Sets the expected value for ADDR[32]. If ADDR[32]=TILERMODE, ADDR[31:4] is processed and eventually translated. Otherwise, the access is handled as transparent, regardless of the other address bits." "0,1" bitfld.long 0x00 10. " DONE ,Write this bit to 1 to indicate the CPU has finished processing its physical buffer. This bit is automatically cleared by hardware, reads always return 0. This bit has no effect when MODE=2 (read/write) - . - ." "ZERO,ONE" bitfld.long 0x00 8.--9. " WCOUNT ,Window count - . - . - . - ." "W2,W4,W8,W16" textline " " bitfld.long 0x00 4.--7. " BCF ,This register controls the bandwidth control feedback loop output. 0: Control loop disabled. 1-15: The control feedback loop enabled. Behavior depends on functional mode, see , ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " MODE ,Selects the functional mode of this context - . - . - ." "WRITE,READ,RWMODE,3" bitfld.long 0x00 0. " ENABLE ,Enable/disable - . - ." "DI,EN" group.long 0x108++0x3 line.long 0x00 "CBUFF_CTX_END_i_0,End address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0x11C++0x3 line.long 0x00 "CBUFF_CTX_PHY_i_0,Start address of the first physical buffer managed by the context when fragmentation support is disabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128 bit words." group.long 0x104++0x3 line.long 0x00 "CBUFF_CTX_START_i_0,Start address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" rgroup.long 0x118++0x3 line.long 0x00 "CBUFF_CTX_STATUS_i_0,Status register" bitfld.long 0x00 8.--11. " WA ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " WB ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x110++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_F_i_0,Threshold value used to check if a write window is full" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x114++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_S_i_0,Threshold value used to control the BCF synchronization mechanism" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x10C++0x3 line.long 0x00 "CBUFF_CTX_WINDOWSIZE_i_0,Defines the size of a window" hexmask.long.tbyte 0x00 4.--23. 1. " SIZE ,Size, in 128-bit words" group.long 0x80++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_0,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" tree.end tree "CTX_Line_1" width 27. group.long 0x120++0x3 line.long 0x00 "CBUFF_CTX_CTRL_i_1,Context control register" bitfld.long 0x00 11. " TILERMODE ,Sets the expected value for ADDR[32]. If ADDR[32]=TILERMODE, ADDR[31:4] is processed and eventually translated. Otherwise, the access is handled as transparent, regardless of the other address bits." "0,1" bitfld.long 0x00 10. " DONE ,Write this bit to 1 to indicate the CPU has finished processing its physical buffer. This bit is automatically cleared by hardware, reads always return 0. This bit has no effect when MODE=2 (read/write) - . - ." "ZERO,ONE" bitfld.long 0x00 8.--9. " WCOUNT ,Window count - . - . - . - ." "W2,W4,W8,W16" textline " " bitfld.long 0x00 4.--7. " BCF ,This register controls the bandwidth control feedback loop output. 0: Control loop disabled. 1-15: The control feedback loop enabled. Behavior depends on functional mode, see , ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " MODE ,Selects the functional mode of this context - . - . - ." "WRITE,READ,RWMODE,3" bitfld.long 0x00 0. " ENABLE ,Enable/disable - . - ." "DI,EN" group.long 0x128++0x3 line.long 0x00 "CBUFF_CTX_END_i_1,End address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0x13C++0x3 line.long 0x00 "CBUFF_CTX_PHY_i_1,Start address of the first physical buffer managed by the context when fragmentation support is disabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128 bit words." group.long 0x124++0x3 line.long 0x00 "CBUFF_CTX_START_i_1,Start address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" rgroup.long 0x138++0x3 line.long 0x00 "CBUFF_CTX_STATUS_i_1,Status register" bitfld.long 0x00 8.--11. " WA ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " WB ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_F_i_1,Threshold value used to check if a write window is full" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x134++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_S_i_1,Threshold value used to control the BCF synchronization mechanism" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x12C++0x3 line.long 0x00 "CBUFF_CTX_WINDOWSIZE_i_1,Defines the size of a window" hexmask.long.tbyte 0x00 4.--23. 1. " SIZE ,Size, in 128-bit words" group.long 0x84++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_1,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" tree.end tree "CTX_Line_2" width 27. group.long 0x140++0x3 line.long 0x00 "CBUFF_CTX_CTRL_i_2,Context control register" bitfld.long 0x00 11. " TILERMODE ,Sets the expected value for ADDR[32]. If ADDR[32]=TILERMODE, ADDR[31:4] is processed and eventually translated. Otherwise, the access is handled as transparent, regardless of the other address bits." "0,1" bitfld.long 0x00 10. " DONE ,Write this bit to 1 to indicate the CPU has finished processing its physical buffer. This bit is automatically cleared by hardware, reads always return 0. This bit has no effect when MODE=2 (read/write) - . - ." "ZERO,ONE" bitfld.long 0x00 8.--9. " WCOUNT ,Window count - . - . - . - ." "W2,W4,W8,W16" textline " " bitfld.long 0x00 4.--7. " BCF ,This register controls the bandwidth control feedback loop output. 0: Control loop disabled. 1-15: The control feedback loop enabled. Behavior depends on functional mode, see , ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " MODE ,Selects the functional mode of this context - . - . - ." "WRITE,READ,RWMODE,3" bitfld.long 0x00 0. " ENABLE ,Enable/disable - . - ." "DI,EN" group.long 0x148++0x3 line.long 0x00 "CBUFF_CTX_END_i_2,End address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0x15C++0x3 line.long 0x00 "CBUFF_CTX_PHY_i_2,Start address of the first physical buffer managed by the context when fragmentation support is disabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128 bit words." group.long 0x144++0x3 line.long 0x00 "CBUFF_CTX_START_i_2,Start address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" rgroup.long 0x158++0x3 line.long 0x00 "CBUFF_CTX_STATUS_i_2,Status register" bitfld.long 0x00 8.--11. " WA ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " WB ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x150++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_F_i_2,Threshold value used to check if a write window is full" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x154++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_S_i_2,Threshold value used to control the BCF synchronization mechanism" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x14C++0x3 line.long 0x00 "CBUFF_CTX_WINDOWSIZE_i_2,Defines the size of a window" hexmask.long.tbyte 0x00 4.--23. 1. " SIZE ,Size, in 128-bit words" group.long 0x88++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_2,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" tree.end tree "CTX_Line_3" width 27. group.long 0x160++0x3 line.long 0x00 "CBUFF_CTX_CTRL_i_3,Context control register" bitfld.long 0x00 11. " TILERMODE ,Sets the expected value for ADDR[32]. If ADDR[32]=TILERMODE, ADDR[31:4] is processed and eventually translated. Otherwise, the access is handled as transparent, regardless of the other address bits." "0,1" bitfld.long 0x00 10. " DONE ,Write this bit to 1 to indicate the CPU has finished processing its physical buffer. This bit is automatically cleared by hardware, reads always return 0. This bit has no effect when MODE=2 (read/write) - . - ." "ZERO,ONE" bitfld.long 0x00 8.--9. " WCOUNT ,Window count - . - . - . - ." "W2,W4,W8,W16" textline " " bitfld.long 0x00 4.--7. " BCF ,This register controls the bandwidth control feedback loop output. 0: Control loop disabled. 1-15: The control feedback loop enabled. Behavior depends on functional mode, see , ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " MODE ,Selects the functional mode of this context - . - . - ." "WRITE,READ,RWMODE,3" bitfld.long 0x00 0. " ENABLE ,Enable/disable - . - ." "DI,EN" group.long 0x168++0x3 line.long 0x00 "CBUFF_CTX_END_i_3,End address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0x17C++0x3 line.long 0x00 "CBUFF_CTX_PHY_i_3,Start address of the first physical buffer managed by the context when fragmentation support is disabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128 bit words." group.long 0x164++0x3 line.long 0x00 "CBUFF_CTX_START_i_3,Start address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" rgroup.long 0x178++0x3 line.long 0x00 "CBUFF_CTX_STATUS_i_3,Status register" bitfld.long 0x00 8.--11. " WA ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " WB ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x170++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_F_i_3,Threshold value used to check if a write window is full" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x174++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_S_i_3,Threshold value used to control the BCF synchronization mechanism" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x16C++0x3 line.long 0x00 "CBUFF_CTX_WINDOWSIZE_i_3,Defines the size of a window" hexmask.long.tbyte 0x00 4.--23. 1. " SIZE ,Size, in 128-bit words" group.long 0x8C++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_3,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" tree.end tree "CTX_Line_4" width 27. group.long 0x180++0x3 line.long 0x00 "CBUFF_CTX_CTRL_i_4,Context control register" bitfld.long 0x00 11. " TILERMODE ,Sets the expected value for ADDR[32]. If ADDR[32]=TILERMODE, ADDR[31:4] is processed and eventually translated. Otherwise, the access is handled as transparent, regardless of the other address bits." "0,1" bitfld.long 0x00 10. " DONE ,Write this bit to 1 to indicate the CPU has finished processing its physical buffer. This bit is automatically cleared by hardware, reads always return 0. This bit has no effect when MODE=2 (read/write) - . - ." "ZERO,ONE" bitfld.long 0x00 8.--9. " WCOUNT ,Window count - . - . - . - ." "W2,W4,W8,W16" textline " " bitfld.long 0x00 4.--7. " BCF ,This register controls the bandwidth control feedback loop output. 0: Control loop disabled. 1-15: The control feedback loop enabled. Behavior depends on functional mode, see , ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " MODE ,Selects the functional mode of this context - . - . - ." "WRITE,READ,RWMODE,3" bitfld.long 0x00 0. " ENABLE ,Enable/disable - . - ." "DI,EN" group.long 0x188++0x3 line.long 0x00 "CBUFF_CTX_END_i_4,End address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0x19C++0x3 line.long 0x00 "CBUFF_CTX_PHY_i_4,Start address of the first physical buffer managed by the context when fragmentation support is disabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128 bit words." group.long 0x184++0x3 line.long 0x00 "CBUFF_CTX_START_i_4,Start address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" rgroup.long 0x198++0x3 line.long 0x00 "CBUFF_CTX_STATUS_i_4,Status register" bitfld.long 0x00 8.--11. " WA ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " WB ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x190++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_F_i_4,Threshold value used to check if a write window is full" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x194++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_S_i_4,Threshold value used to control the BCF synchronization mechanism" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x18C++0x3 line.long 0x00 "CBUFF_CTX_WINDOWSIZE_i_4,Defines the size of a window" hexmask.long.tbyte 0x00 4.--23. 1. " SIZE ,Size, in 128-bit words" group.long 0x90++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_4,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" tree.end tree "CTX_Line_5" width 27. group.long 0x1A0++0x3 line.long 0x00 "CBUFF_CTX_CTRL_i_5,Context control register" bitfld.long 0x00 11. " TILERMODE ,Sets the expected value for ADDR[32]. If ADDR[32]=TILERMODE, ADDR[31:4] is processed and eventually translated. Otherwise, the access is handled as transparent, regardless of the other address bits." "0,1" bitfld.long 0x00 10. " DONE ,Write this bit to 1 to indicate the CPU has finished processing its physical buffer. This bit is automatically cleared by hardware, reads always return 0. This bit has no effect when MODE=2 (read/write) - . - ." "ZERO,ONE" bitfld.long 0x00 8.--9. " WCOUNT ,Window count - . - . - . - ." "W2,W4,W8,W16" textline " " bitfld.long 0x00 4.--7. " BCF ,This register controls the bandwidth control feedback loop output. 0: Control loop disabled. 1-15: The control feedback loop enabled. Behavior depends on functional mode, see , ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " MODE ,Selects the functional mode of this context - . - . - ." "WRITE,READ,RWMODE,3" bitfld.long 0x00 0. " ENABLE ,Enable/disable - . - ." "DI,EN" group.long 0x1A8++0x3 line.long 0x00 "CBUFF_CTX_END_i_5,End address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0x1BC++0x3 line.long 0x00 "CBUFF_CTX_PHY_i_5,Start address of the first physical buffer managed by the context when fragmentation support is disabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128 bit words." group.long 0x1A4++0x3 line.long 0x00 "CBUFF_CTX_START_i_5,Start address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" rgroup.long 0x1B8++0x3 line.long 0x00 "CBUFF_CTX_STATUS_i_5,Status register" bitfld.long 0x00 8.--11. " WA ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " WB ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1B0++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_F_i_5,Threshold value used to check if a write window is full" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x1B4++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_S_i_5,Threshold value used to control the BCF synchronization mechanism" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x1AC++0x3 line.long 0x00 "CBUFF_CTX_WINDOWSIZE_i_5,Defines the size of a window" hexmask.long.tbyte 0x00 4.--23. 1. " SIZE ,Size, in 128-bit words" group.long 0x94++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_5,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" tree.end tree "CTX_Line_6" width 27. group.long 0x1C0++0x3 line.long 0x00 "CBUFF_CTX_CTRL_i_6,Context control register" bitfld.long 0x00 11. " TILERMODE ,Sets the expected value for ADDR[32]. If ADDR[32]=TILERMODE, ADDR[31:4] is processed and eventually translated. Otherwise, the access is handled as transparent, regardless of the other address bits." "0,1" bitfld.long 0x00 10. " DONE ,Write this bit to 1 to indicate the CPU has finished processing its physical buffer. This bit is automatically cleared by hardware, reads always return 0. This bit has no effect when MODE=2 (read/write) - . - ." "ZERO,ONE" bitfld.long 0x00 8.--9. " WCOUNT ,Window count - . - . - . - ." "W2,W4,W8,W16" textline " " bitfld.long 0x00 4.--7. " BCF ,This register controls the bandwidth control feedback loop output. 0: Control loop disabled. 1-15: The control feedback loop enabled. Behavior depends on functional mode, see , ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " MODE ,Selects the functional mode of this context - . - . - ." "WRITE,READ,RWMODE,3" bitfld.long 0x00 0. " ENABLE ,Enable/disable - . - ." "DI,EN" group.long 0x1C8++0x3 line.long 0x00 "CBUFF_CTX_END_i_6,End address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0x1DC++0x3 line.long 0x00 "CBUFF_CTX_PHY_i_6,Start address of the first physical buffer managed by the context when fragmentation support is disabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128 bit words." group.long 0x1C4++0x3 line.long 0x00 "CBUFF_CTX_START_i_6,Start address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" rgroup.long 0x1D8++0x3 line.long 0x00 "CBUFF_CTX_STATUS_i_6,Status register" bitfld.long 0x00 8.--11. " WA ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " WB ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1D0++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_F_i_6,Threshold value used to check if a write window is full" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x1D4++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_S_i_6,Threshold value used to control the BCF synchronization mechanism" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x1CC++0x3 line.long 0x00 "CBUFF_CTX_WINDOWSIZE_i_6,Defines the size of a window" hexmask.long.tbyte 0x00 4.--23. 1. " SIZE ,Size, in 128-bit words" group.long 0x98++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_6,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" tree.end tree "CTX_Line_7" width 27. group.long 0x1E0++0x3 line.long 0x00 "CBUFF_CTX_CTRL_i_7,Context control register" bitfld.long 0x00 11. " TILERMODE ,Sets the expected value for ADDR[32]. If ADDR[32]=TILERMODE, ADDR[31:4] is processed and eventually translated. Otherwise, the access is handled as transparent, regardless of the other address bits." "0,1" bitfld.long 0x00 10. " DONE ,Write this bit to 1 to indicate the CPU has finished processing its physical buffer. This bit is automatically cleared by hardware, reads always return 0. This bit has no effect when MODE=2 (read/write) - . - ." "ZERO,ONE" bitfld.long 0x00 8.--9. " WCOUNT ,Window count - . - . - . - ." "W2,W4,W8,W16" textline " " bitfld.long 0x00 4.--7. " BCF ,This register controls the bandwidth control feedback loop output. 0: Control loop disabled. 1-15: The control feedback loop enabled. Behavior depends on functional mode, see , ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " MODE ,Selects the functional mode of this context - . - . - ." "WRITE,READ,RWMODE,3" bitfld.long 0x00 0. " ENABLE ,Enable/disable - . - ." "DI,EN" group.long 0x1E8++0x3 line.long 0x00 "CBUFF_CTX_END_i_7,End address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0x1FC++0x3 line.long 0x00 "CBUFF_CTX_PHY_i_7,Start address of the first physical buffer managed by the context when fragmentation support is disabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128 bit words." group.long 0x1E4++0x3 line.long 0x00 "CBUFF_CTX_START_i_7,Start address of the virtual space managed by the context" hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" rgroup.long 0x1F8++0x3 line.long 0x00 "CBUFF_CTX_STATUS_i_7,Status register" bitfld.long 0x00 8.--11. " WA ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " WB ,Valid values depend on the CBUFF_CTX_CTRL__x.WCOUNT register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F0++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_F_i_7,Threshold value used to check if a write window is full" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x1F4++0x3 line.long 0x00 "CBUFF_CTX_THRESHOLD_S_i_7,Threshold value used to control the BCF synchronization mechanism" hexmask.long.tbyte 0x00 0.--23. 1. " THRESHOLD ,Threshold value, in bytes" group.long 0x1EC++0x3 line.long 0x00 "CBUFF_CTX_WINDOWSIZE_i_7,Defines the size of a window" hexmask.long.tbyte 0x00 4.--23. 1. " SIZE ,Size, in 128-bit words" group.long 0x9C++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_7,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0xA0++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_8,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0xA4++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_9,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0xA8++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_10,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0xAC++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_11,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0xB0++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_12,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0xB4++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_13,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0xB8++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_14,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" group.long 0xBC++0x3 line.long 0x00 "CBUFF_FRAG_ADDR_j_15,Start address of the physical buffer of the CBUFF context 0. This register only exists when fragmentation support is enabled." hexmask.long 0x00 4.--31. 1. " ADDR ,Address, in 128-bit words" tree.end textline "" width 24. rgroup.long 0x0++0x3 line.long 0x00 "CBUFF_HL_REVISION,IP revision identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "CBUFF_HL_HWINFO,Information about the IP module's hardware configuration." bitfld.long 0x00 1.--2. " CONTEXTS ,Number of contexts - . - . - . - ." "TWO,FOUR,EIGHT,RSV" bitfld.long 0x00 0. " ENABLE_FRAGMENTATION ,Provides information to software if fragmentation support is available - . - ." "ZERO,ONE" group.long 0x10++0x3 line.long 0x00 "CBUFF_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "force,no,smart,smartwakeup" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - . - . - ." "done_/_noaction,pending_/_reset" group.long 0x20++0x3 line.long 0x00 "CBUFF_HL_IRQSTATUS_RAW,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 31. " IRQ_CTX7_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 30. " IRQ_CTX6_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 29. " IRQ_CTX5_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 28. " IRQ_CTX4_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 27. " IRQ_CTX3_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 26. " IRQ_CTX2_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 25. " IRQ_CTX1_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 24. " IRQ_CTX0_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 23. " IRQ_CTX7_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 22. " IRQ_CTX6_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 21. " IRQ_CTX5_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 20. " IRQ_CTX4_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 19. " IRQ_CTX3_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 18. " IRQ_CTX2_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 17. " IRQ_CTX1_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 16. " IRQ_CTX0_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 15. " IRQ_CTX7_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 14. " IRQ_CTX6_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 13. " IRQ_CTX5_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 12. " IRQ_CTX4_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " IRQ_CTX3_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 10. " IRQ_CTX2_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 9. " IRQ_CTX1_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 8. " IRQ_CTX0_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 0. " IRQ_OCP_ERR ,OCP error received in the master port. - . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x24++0x3 line.long 0x00 "CBUFF_HL_IRQSTATUS,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 31. " IRQ_CTX7_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 30. " IRQ_CTX6_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 29. " IRQ_CTX5_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 28. " IRQ_CTX4_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 27. " IRQ_CTX3_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 26. " IRQ_CTX2_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 25. " IRQ_CTX1_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 24. " IRQ_CTX0_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 23. " IRQ_CTX7_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 22. " IRQ_CTX6_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 21. " IRQ_CTX5_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 20. " IRQ_CTX4_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 19. " IRQ_CTX3_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 18. " IRQ_CTX2_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 17. " IRQ_CTX1_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 16. " IRQ_CTX0_INVALID ,Invalid access. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 15. " IRQ_CTX7_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 14. " IRQ_CTX6_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 13. " IRQ_CTX5_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 12. " IRQ_CTX4_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " IRQ_CTX3_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 10. " IRQ_CTX2_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 9. " IRQ_CTX1_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 8. " IRQ_CTX0_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 0. " IRQ_OCP_ERR ,OCP error received in the master port. - . - . - . - ." "noaction_/_noevent,clear_/_pending" group.long 0x28++0x3 line.long 0x00 "CBUFF_HL_IRQENABLE_SET,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 31. " IRQ_CTX7_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 30. " IRQ_CTX6_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 29. " IRQ_CTX5_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 28. " IRQ_CTX4_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 27. " IRQ_CTX3_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 26. " IRQ_CTX2_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 25. " IRQ_CTX1_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 24. " IRQ_CTX0_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 23. " IRQ_CTX7_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 22. " IRQ_CTX6_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 21. " IRQ_CTX5_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 20. " IRQ_CTX4_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 19. " IRQ_CTX3_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 18. " IRQ_CTX2_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 17. " IRQ_CTX1_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 16. " IRQ_CTX0_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 15. " IRQ_CTX7_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 14. " IRQ_CTX6_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 13. " IRQ_CTX5_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " IRQ_CTX4_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " IRQ_CTX3_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 10. " IRQ_CTX2_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " IRQ_CTX1_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 8. " IRQ_CTX0_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 0. " IRQ_OCP_ERR ,OCP error received in the master port. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x2C++0x3 line.long 0x00 "CBUFF_HL_IRQENABLE_CLR,Per-event interrupt enable bit vector, line 0. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 31. " IRQ_CTX7_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 30. " IRQ_CTX6_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 29. " IRQ_CTX5_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 28. " IRQ_CTX4_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 27. " IRQ_CTX3_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 26. " IRQ_CTX2_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 25. " IRQ_CTX1_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 24. " IRQ_CTX0_OVR ,Buffer overflow event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 23. " IRQ_CTX7_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 22. " IRQ_CTX6_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 21. " IRQ_CTX5_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 20. " IRQ_CTX4_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 19. " IRQ_CTX3_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 18. " IRQ_CTX2_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 17. " IRQ_CTX1_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 16. " IRQ_CTX0_INVALID ,Invalid access. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 15. " IRQ_CTX7_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 14. " IRQ_CTX6_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 13. " IRQ_CTX5_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " IRQ_CTX4_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " IRQ_CTX3_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 10. " IRQ_CTX2_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " IRQ_CTX1_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 8. " IRQ_CTX0_READY ,The WB physical window is ready to be accessed by the CPU. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 0. " IRQ_OCP_ERR ,OCP error received in the master port. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" tree.end tree.end tree.open "ISS_ISP" tree "ISS_IPIPEIF" base ad:0x52011200 width 18. group.long 0x0++0x3 line.long 0x00 "IPIPEIF_ENABLE,IPIPEIF Enable." bitfld.long 0x00 1. " SYNCOFF ,VD output mask This register masks the VD output to the IPIPE module. This can be useful when one wants to read data from SDRAM which are stored in a double buffer. If the VD is not masked each time we start the module an new VD will be gener.." "newEnum1,newEnum2" bitfld.long 0x00 0. " ENABLE ,IPIPE I/F Enable This register is used to start the operation of SDRAM buffer memory read and generates SYNC signals. This register is available when INPSRC1 or INPSCR2 = 1, 2 or 3. - . - ." "newEnum1,newEnum2" group.long 0x4++0x3 line.long 0x00 "IPIPEIF_CFG1,IPIPEIF Configuration #1" bitfld.long 0x00 14.--15. " INPSRC1 ,Selects the source for the mux (VPORT / ISIF / SDRAM) as well as the data format type. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 11.--13. " DATASFT ,SDRAM read data shift This register is available when INPSRC1 or INPSRC2 = 1 or 2, that is, when data are read from SDRAM. - . - . - . - . - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8" bitfld.long 0x00 10. " CLKSEL ,IPIPEIF and IPIPE module pixel clock selection. This register must be set to 1 when INPSRC1 or INPSRC2 = 1 or 3, that is, data are solely read from SDRAM (VPORT inactive). - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 8.--9. " UNPACK ,8-Bit, 12-bit Packed Mode When sensor raw data are stored in 8-bit packed mode or 12-bit packed mode, this register should code 1 or 3. This register is effective when INPSRC = 1 or 2. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 7. " AVGFILT ,Averaging Filter It applies (1,2,1) filter for the RGB/YCbCr data. *This bit field is latched by VD. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2.--3. " INPSRC2 ,Selects the source for the mux (ISIF / SDRAM) as well as the data format type. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" textline " " bitfld.long 0x00 1. " DECIM ,Pixel Decimation The decimation rate defined by RSZ register. *This bit field is latched by VD. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " ONESHOT ,One Shot Mode This register is available when INPSRC = 1 or 3. - . - ." "newEnum1,newEnum2" group.long 0x8++0x3 line.long 0x00 "IPIPEIF_PPLN,IPIPEIF Interval of HD / Start pixel in HD" hexmask.long.word 0x00 0.--12. 1. " PPLN ,Case-1: Interval of Horizontal Sync (HD) Specifies the interval of horizontal sync. This register is available when INPSRC = 1 or 3. Case-2: Start Pixel in Horizontal Sync (HD) Specifies the start pixel in horizontal sync. This register is av.." group.long 0xC++0x3 line.long 0x00 "IPIPEIF_LPFR,IPIPEIF Interval of VD / Start line in VD" hexmask.long.word 0x00 0.--12. 1. " LPFR ,Case-1: Interval of Vertical Sync (VD) Specifies the interval of vertical sync. This register is available when INPSRC = 1 or 3. Case-2: Start Pixel in Vertical Sync (VD) Specifies the start line in vertical sync. This register is available w.." group.long 0x10++0x3 line.long 0x00 "IPIPEIF_HNUM,IPIPEIF Number of valid pixels per line" hexmask.long.word 0x00 0.--12. 1. " HNUM ,The Number of Valid Pixels in a Line Specifies the number of valid pixels in a horizontal line. This register is available when INPSRC = 1, 2 or 3 *This bit field is latched by VD." group.long 0x14++0x3 line.long 0x00 "IPIPEIF_VNUM,IPIPEIF Number of valid lines per frame" hexmask.long.word 0x00 0.--12. 1. " VNUM ,The Number of Valid Line in a Vertical Specifies the number of valid line in a vertical. This register is available when INPSRC = 1, 2 or 3 *This bit field is latched by VD." group.long 0x18++0x3 line.long 0x00 "IPIPEIF_ADDRU,IPIPEIF Memory Address (Upper)" hexmask.long.word 0x00 0.--10. 1. " ADDRU ,Memory Address - Upper Memory address upper 11-bits are specified in units of 32-bytes This register is available when INPSRC = 1, 2 or 3. *This bit field is latched by VD." group.long 0x1C++0x3 line.long 0x00 "IPIPEIF_ADDRL,IPIPEIF Memory Address (Lower)" hexmask.long.word 0x00 0.--15. 1. " ADDRL ,Memory Address - Lower Memory address lower 16-bits are specified in units of 32-bytes. This register is available when INPSRC = 1, 2 or 3. *This bit field is latched by VD." group.long 0x20++0x3 line.long 0x00 "IPIPEIF_ADOFS,IPIPEIF Address offset" hexmask.long.word 0x00 0.--11. 1. " ADOFS ,Specifies the SDRAM stride for each line in units of 32-bytes. This register is available when reading data from SDRAM: INPSRC1 or INPSRC2 = 1, 2 or 3. Assuming that the first line is at position ADDR, the second line is at address ADDR+ ADOF.." group.long 0x24++0x3 line.long 0x00 "IPIPEIF_RSZ,IPIPEIF Horizontal Resizing Parameter on IPIPE data path" hexmask.long.byte 0x00 0.--6. 1. " RSZ ,Horizontal Resizing Parameter for IPIPE data path Specifies the horizontal resizing parameter. The RSZ register can be configured within 16 to 112 range. This resizing ratio is determined by 16/RSZ (= 1/1 to 1/7) *This bit field is latched by.." group.long 0x28++0x3 line.long 0x00 "IPIPEIF_GAIN,IPIPEIF Gain Parameter" hexmask.long.word 0x00 0.--9. 1. " GAIN ,Gain Parameter Specifies the gain applied to RAW data before it is forwarded to the IPIPE module. The gain value is expressed using the U10Q9 fractional format. The range is from 0.00195 (1/512) to 1.99805(1023/512). By default the unity gain.." group.long 0x2C++0x3 line.long 0x00 "IPIPEIF_DPCM,IPIPEIF DPCM configuration This register applies only if .UNPACK = 1, that is, RAW8 data is read from SDRAM." bitfld.long 0x00 2. " BITS ,DPCM bit mode for SDRAM data - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " PRED ,DPCM prediction mode for SDRAM data - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " ENA ,DPCM decompression enable for SDRAM data. - . - ." "newEnum1,newEnum2" group.long 0x30++0x3 line.long 0x00 "IPIPEIF_CFG2,IPIPEIF Configuration #2" bitfld.long 0x00 7. " YUV8P ,8-bit YUV data unpacking to 16 bits When IPIPEIF_CFG1.INPSRC2 = 0 and IPIPEIF_CFG2.YUV16 = 1, the 8-bit YUV data are transformed into 16-bit YUV data. The way the data are unpacked from 8 bits to 16 bits is controlled by the IPIPEIF_CFG2.YUV8.." "newEnum1,newEnum2" bitfld.long 0x00 6. " YUV8 ,YUV 8bit mode When ISIF_CFG1.INPSRC2 = 0 and YUV16 = 1, setting this bit to 1 enables the conversion from 8-bit YUV input to 16-bit YUV. This register is used when the input data from the ISIF module is 8-bit YUV data. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 5. " DFSDIR ,DFS direction Selects the direction of dark frame subtraction. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 3. " YUV16 ,Data type selection. The behavior of this bit field depends upon other register settings. The functionality is best explained with the following pseudo code: if ((CFG1.INPSRC2==0 &amp;&amp; CFG2.YUV16) || CFG1.INPSRC2==3) { data_out[1.." "newEnum1,newEnum2" bitfld.long 0x00 2. " VDPOL ,VD Sync Polarity When input VD is active low SYNC pulse, this bit needs to be set to 1. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " HDPOL ,HD Sync Polarity When input HD is active low SYNC pulse, this bit needs to be set to 1. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 0. " INTSW ,IPIPEIF interrupt source selection. This register select the interrupt source. - . - ." "newEnum1,newEnum2" group.long 0x34++0x3 line.long 0x00 "IPIPEIF_INIRSZ,IPIPEIF resize initial position - IPIPE data path." bitfld.long 0x00 13. " ALNSYNC ,Align the HSYNC, VSYNC to initial position defined by INIRSZ. - . - ." "newEnum1,newEnum2" hexmask.long.word 0x00 0.--12. 1. " INIRSZ ,Offset used to re-initialize the HD/VD position after resizer. From 0 to 8191 PCLK cycles. Skips INIRSZ pixels for every line." group.long 0x38++0x3 line.long 0x00 "IPIPEIF_OCLIP,IPIPEIF output clipping value" hexmask.long.word 0x00 0.--11. 1. " OCLIP ,Output clipping value after gain control on IPIPE data path. This value is in U12Q0 data format." group.long 0x3C++0x3 line.long 0x00 "IPIPEIF_DTUDF,IPIPEIF data underflow detection" bitfld.long 0x00 0. " DTUDF ,Data under flow error status register. Reading 1 shows there is data under flow and at least one data is corrupted while reading from SDRAM. Writing 1 to this register clears (=0) the error (=1) status. Underflow errors are non recoverable at.." "0,1" group.long 0x40++0x3 line.long 0x00 "IPIPEIF_CLKDIV,IPIPEIF CLOCK DIVIDER" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,IPIPEIF clock rate configuration IPIPE/IPIPEIF clock frequency = M/N x ISS_FCLK clock frequency. We have M = CLKDIV[15:8] + 1 and N = CLKDIV[7:0] + 1 This register is available when IPIPEIF_CFG1.CLKSEL = 1." group.long 0x44++0x3 line.long 0x00 "IPIPEIF_DPC1,IPIPEIF defect pixel correction #1" bitfld.long 0x00 12. " ENA ,DPC enable. Applies DPC for video port data, ISIF input path. - . - ." "newEnum1,newEnum2" hexmask.long.word 0x00 0.--11. 1. " TH ,DPC threshold value" group.long 0x48++0x3 line.long 0x00 "IPIPEIF_DPC2,IPIPEIF defect pixel correction #2" bitfld.long 0x00 12. " ENA ,DPC enable. Applies DPC for SDRAM input path. - . - ." "newEnum1,newEnum2" hexmask.long.word 0x00 0.--11. 1. " TH ,DPC threshold value" group.long 0x54++0x3 line.long 0x00 "IPIPEIF_RSZ3A,IPIPEIF HORIZONTAL RESIZING PARAMETER FOR H3A" bitfld.long 0x00 9. " DECIM ,Pixel Decimation Enable The decimation rate defined by the RSZ bit field. *This bit field is latched by VD. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 8. " AVGFILT ,Averaging Filter It applies a (1, 2, 1) filter for the RGB/YCbCr data. *This bit field is latched by VD. - . - ." "newEnum1,newEnum2" hexmask.long.byte 0x00 0.--6. 1. " RSZ ,Horizontal Resizing Parameter for H3A data path Specifies the horizontal resizing parameter. The RSZ register can be configured within 16 to 112 range. This resizing ratio is determined by 16/RSZ (= 1/1 to 1/7) *This bit field is latched by .." group.long 0x58++0x3 line.long 0x00 "IPIPEIF_INIRSZ3A,IPIPEIF resize initial position - H3A data path." bitfld.long 0x00 13. " ALNSYNC ,Align the HD, VD to initial position defined by the INIRSZ bit field. It means that HD and VD are effectively shifted by INIRSZ pixel clock cycles. - . - ." "newEnum1,newEnum2" hexmask.long.word 0x00 0.--12. 1. " INIRSZ ,Offset used to re-initialize the HD/VD position after resizer. From 0 to 8191 PCLK cycles. Skips INIRSZ pixels for every line." tree.end tree "ISS_ISIF" base ad:0x52011000 width 17. group.long 0x0++0x3 line.long 0x00 "ISIF_SYNCEN," bitfld.long 0x00 1. " DWEN ,Controls the storage of image sensor RAW data in memory. This bit is loaded with the timing of the internal VD signal: it becomes active starting at the lead of the VD signal that comes after 1 is written in this bit. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " SYEN ,Controls ON/OFF of VD/HD output. Internal timing generator becomes active and VD/HD output starts when 1 is written in this bit. In case of input, VD/HD loading begins. 0: Disable 1: Enable" "newEnum1,newEnum2" group.long 0x4++0x3 line.long 0x00 "ISIF_MODESET," bitfld.long 0x00 14. " HLPF ,Low pass filter enable. When this bit is enabled, a 3-tap (1/4 + 1/2 Z + 1/4 Z) filtering process is performed on the sensor data. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 12.--13. " INPMOD ,Data input mode: - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 11. " OVF ,ISIF module write port overflow status bit If the write port of the ISIF module overflows when writing data to SDRAM, this bit will toggle. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 8.--10. " CCDW ,This bit enables to shift right (divide) the up-to-12-bit RAW data value when writing out to SDRAM. The effect is that the dynamic of the output signal is decreased. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BS.." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8" bitfld.long 0x00 7. " CCDMD ,Field mode: This bit selects the type of image sensor: interlaced or progressive - . - ." "newEnum1,newEnum2" bitfld.long 0x00 6. " DPOL ,Image sensor input data polarity - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 5. " SWEN ,External WEN selection In case this bit and SYNCEN.DWEN are set to 1, the external WEN signal is used to store image sensor data to memory. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 3. " HDPOL ,HD Sync Signal Polarity - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " VDPOL ,VD Sync Signal Polarity - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 1. " FIDD ,FLD Signal Direction. There must be at least three clock cycles between the time this bit is modified and the HD/VD pulse for the start of frame comes. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " HDVDD ,VD,HD Sync Signal Direction. There must be at least three clock cycles between the time this bit is modified and the HD/VD pulse for the start of frame comes. - . - ." "newEnum1,newEnum2" group.long 0x8++0x3 line.long 0x00 "ISIF_HDW," hexmask.long.word 0x00 0.--11. 1. " HDW ,HD width: Sets width of HD. HD width = HDW + 1 clock" group.long 0xC++0x3 line.long 0x00 "ISIF_VDW," hexmask.long.word 0x00 0.--11. 1. " VDW ,VD width : Sets width of VD. VD width = VDW + 1 line" group.long 0x10++0x3 line.long 0x00 "ISIF_PPLN," hexmask.long.word 0x00 0.--15. 1. " PPLN ,Pixels per line Number of pixel clock periods in one line HD period = PPLN+1 pixel clocks. PPLN is not used when HD and VD are inputs, that is, when VDHDOUT in MODESET is cleared to 0. *This bit field is latched by VD." group.long 0x14++0x3 line.long 0x00 "ISIF_LPFR,Line per Frame/Field" hexmask.long.word 0x00 0.--15. 1. " LPFR ,Half lines per filed or frame Sets number of half lines per frame or field. VD period = (LPFR+1)/2 lines. LPFR is not used when HD and are inputs, that is, when VDHDOUT in MODESET is cleared to 0. *This bit field is latched by VD." group.long 0x18++0x3 line.long 0x00 "ISIF_SPH,Start Pixel Horizontal" hexmask.long.word 0x00 0.--14. 1. " SPH ,The first pixel in a line to be stored to memory." group.long 0x1C++0x3 line.long 0x00 "ISIF_LNH," hexmask.long.word 0x00 0.--14. 1. " LNH ,Number of pixels in an line to be stored to memory. Number of pixels = LNH + 1." group.long 0x28++0x3 line.long 0x00 "ISIF_LNV," hexmask.long.word 0x00 0.--14. 1. " LNV ,The number of lines to be stored to memory. Number of lines = LNV + 1" group.long 0x2C++0x3 line.long 0x00 "ISIF_CULH," hexmask.long.byte 0x00 8.--15. 1. " CLHO ,Culling Pattern in ODD Line: Sets culling pattern when data is loaded into memory (odd lines). Example: 0xAA: 1 / 2 horizontal direction culling. LSB becomes left side on screen. - . - ." hexmask.long.byte 0x00 0.--7. 1. " CLHE ,Culling Pattern in Even Line: Sets culling pattern when data is loaded into memory (even lines). - . - ." group.long 0x30++0x3 line.long 0x00 "ISIF_CULV," hexmask.long.byte 0x00 0.--7. 1. " CULV ,Culling Pattern in Vertical Line Example: 0x88: 1/4 vertical direction culling. LSB becomes top side on screen. - . - ." group.long 0x34++0x3 line.long 0x00 "ISIF_HSIZE,SDRAM OUTPUT CTRL REGISTER" bitfld.long 0x00 12. " ADCR ,SDRAM address decrement. By setting this bit, memory address in a line is automatically decreased so that a line can be Horizontally flipped in memory. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BSWD, ISIF_CCDCF.." "newEnum1,newEnum2" hexmask.long.word 0x00 0.--11. 1. " HSIZE ,Memory address offset between the lines. Specify the offset in 32-byte units." group.long 0x3C++0x3 line.long 0x00 "ISIF_CADU,SDRAM OUTPUT CTRL REGISTER" hexmask.long.word 0x00 0.--10. 1. " CADU ,Memory Address (Upper 11-bits): Specifies the memory destination address. The actual address is the value set here multiplied by 32bytes." group.long 0x40++0x3 line.long 0x00 "ISIF_CADL,SDRAM OUTPUT CTRL REGISTER" hexmask.long.word 0x00 0.--15. 1. " CADL ,Memory Address (Lower 16-bits): Specifies the memory destination address. The actual address is the value set here multiplied by 32bytes." group.long 0x44++0x3 line.long 0x00 "ISIF_LINCFG0,INPUT LINEARIZATION CTRL REGISTER" bitfld.long 0x00 4.--6. " CORRSFT ,Shift up value for the correction value (S10). - . - . - . - . - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8" bitfld.long 0x00 1. " LINMD ,Linearization Mode: - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " LINEN ,Linearization Enable: - . - ." "newEnum1,newEnum2" group.long 0x48++0x3 line.long 0x00 "ISIF_LINCFG1,INPUT LINEARIZATION CTRL REGISTER" hexmask.long.word 0x00 0.--10. 1. " LUTSCL ,Scale factor (U11Q10) for LUT input. Range: 0 - 1+1023/1024 It is applied to the Input Data before looking up the correction factor. The scale factor is only applied to the table input. It is not applied when using the input value to comp.." group.long 0x4C++0x3 line.long 0x00 "ISIF_CCOLP," bitfld.long 0x00 14.--15. " CP0_F1 ,Specifies color pattern for pixel position 0 (Field 1) Pixel position 0 corresponds to pixel count=0 at even line in case of CFAP= 0, and to pixel count=0 in case of CFAP= 1. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 12.--13. " CP1_F1 ,Specifies color pattern for pixel position 1 (Field 1) Pixel position 1 corresponds to pixel count=1 at even line in case of CFAP= 0, and to pixel count=1 in case of CFAP= 1. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 10.--11. " CP2_F1 ,Specifies color pattern for pixel position 2 (Field 1) Pixel position 2 corresponds to pixel count=0 at odd line in case of CFAP= 0, and to pixel count=2 in case of CFAP= 1. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" textline " " bitfld.long 0x00 8.--9. " CP3_F1 ,Specifies color pattern for pixel position 3 (Field 1) Pixel position 3 corresponds to pixel count=1 at odd line in case of CFAP= 0. Not applicable for CFAP= 1. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 6.--7. " CP0_F0 ,Specifies color pattern for pixel position 0 (Field 0) Pixel position 0 corresponds to pixel count=0 at even line in case of CFAP= 0, and to pixel count=0 in case of CFAP= 1. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 4.--5. " CP1_F0 ,Specifies color pattern for pixel position 1 (Field 0) Pixel position 1 corresponds to pixel count=1 at even line in case of CFAP= 0, and to pixel count=1 in case of CFAP= 1. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" textline " " bitfld.long 0x00 2.--3. " CP2_F0 ,Specifies color pattern for pixel position 2 (Field 0) Pixel position 2 corresponds to pixel count=0 at odd line in case of CFAP= 0, and to pixel count=2 in case of CFAP= 1. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 0.--1. " CP3_F0 ,Specifies color pattern for pixel position 3 (Field 0) Pixel position 3 corresponds to pixel count=1 at odd line in case of CFAP= 0. Not applicable for CFAP= 1. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" group.long 0x50++0x3 line.long 0x00 "ISIF_CRGAIN," hexmask.long.word 0x00 0.--11. 1. " CGR ,R/Ye gain: Performs gain adjustment on image sensor data. U12Q9. Range: 0 - 7+511/512" group.long 0x54++0x3 line.long 0x00 "ISIF_CGRGAIN," hexmask.long.word 0x00 0.--11. 1. " CGGR ,Gr/Cy gain: Performs gain adjustment on image sensor data. U12Q9. Range: 0 - 7+511/512" group.long 0x58++0x3 line.long 0x00 "ISIF_CGBGAIN," hexmask.long.word 0x00 0.--11. 1. " CGGB ,Gb/Cy gain: Performs gain adjustment on image sensor data. U12Q9. Range: 0 - 7+511/512" group.long 0x5C++0x3 line.long 0x00 "ISIF_CBGAIN," hexmask.long.word 0x00 0.--11. 1. " CGB ,B/Mg gain: Performs gain adjustment on image sensor data. U12Q9. Range: 0 - 7+511/512" group.long 0x60++0x3 line.long 0x00 "ISIF_COFSTA," hexmask.long.word 0x00 0.--11. 1. " COFT ,Image sensor offset: Performs offset value adjustment on image sensor data (0~4095)." group.long 0x70++0x3 line.long 0x00 "ISIF_VDINT0," hexmask.long.word 0x00 0.--14. 1. " CVD0 ,VD0 Interrupt timing in a field (line number)." group.long 0x74++0x3 line.long 0x00 "ISIF_VDINT1," hexmask.long.word 0x00 0.--14. 1. " CVD1 ,VD1 Interrupt timing in a field (line number)." group.long 0x78++0x3 line.long 0x00 "ISIF_VDINT2," hexmask.long.word 0x00 0.--14. 1. " CVD2 ,VD2 Interrupt timing in a field (line number)." group.long 0x7C++0x3 line.long 0x00 "ISIF_MISC," bitfld.long 0x00 13. " DPCMPRE ,Selects Predictor for DPCM Encoder (12-8) - . - ." "newEnum1,newEnum2" bitfld.long 0x00 12. " DPCMEN ,Enables DPCM Encoding (12-8) - . - ." "newEnum1,newEnum2" group.long 0x80++0x3 line.long 0x00 "ISIF_CGAMMAWD," bitfld.long 0x00 14. " WBEN2 ,White Balance Enable for H3A - . - ." "newEnum1,newEnum2" bitfld.long 0x00 13. " WBEN1 ,White Balance Enable for IPIPE - . - ." "newEnum1,newEnum2" bitfld.long 0x00 12. " WBEN0 ,White Balance Enable for memory capture - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 10. " OFSTEN2 ,Offset control Enable for H3A - . - ." "newEnum1,newEnum2" bitfld.long 0x00 9. " OFSTEN1 ,Offset control Enable for IPIPE - . - ." "newEnum1,newEnum2" bitfld.long 0x00 8. " OFSTEN0 ,Offset control Enable for SDRAM capture - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 5. " CFAP ,Selects CFA pattern - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " GWDI ,Selects MSB position of Input Data - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8,newEnum9,newEnum10,newEnum11,newEnum12,newEnum13,newEnum14,newEnum15,newEnum16" bitfld.long 0x00 0. " CCDTBL ,On/Off control of A-law table for SDRAM capture - . - ." "newEnum1,newEnum2" group.long 0x84++0x3 line.long 0x00 "ISIF_REC656IF,INPUT CONFIG REGISTER" bitfld.long 0x00 1. " R656ON ,CCIR Rec.656 interface mode - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " ECCFVH ,Error correction of FVH code - . - ." "newEnum1,newEnum2" group.long 0x88++0x3 line.long 0x00 "ISIF_CCDCFG," bitfld.long 0x00 15. " VLDC ,On/off control of CPU registers resynchronize function by VSYNC. All the others are shadowed registers, where register values are updated at V-sync timing by default. If VDLC=1, ISIF register values are updated immediately after register .." "newEnum1,newEnum2" bitfld.long 0x00 13. " MSBINVI ,MSB inverse of CIN port when the data are captured to SDRAM. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BSWD, ISIF_CCDCFG.MSBINV, ISIF_CCDCFG.SDRPACK bit fields control how pixel data are stored to SDRAM.." "newEnum1,newEnum2" bitfld.long 0x00 12. " BSWD ,On/off control of Byte SWAP function when SDRAM capturing. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BSWD, ISIF_CCDCFG.MSBINV, ISIF_CCDCFG.SDRPACK bit fields control how pixel data are stored to SDRAM. - .." "newEnum1,newEnum2" textline " " bitfld.long 0x00 11. " Y8POS ,Selects Y signal position when in 8bit input mode - . - ." "newEnum1,newEnum2" bitfld.long 0x00 10. " EXTRG ,Setting 1 to this register, the SDRAM address is initialized at the rising edge of FID input signal or DWEN register." "0,1" bitfld.long 0x00 9. " TRGSEL ,Select trigger source signal of SDRAM address initializing in case EXTRG=1. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 8. " WENLOG ,Specifies the CCD valid area. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 6.--7. " FIDMD ,Specifies FID detection mode - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 5. " BT656 ,Selects bit width of CCIR656. This bit applies only ifISIF_REC656IF.R656ON = 1. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 4. " YCINSWP ,The ISIF module has a 16-bit interface. When 16-bit YUV data are input, the luma data (YIN7-0) are expected to be on the 8 MS bits and the chroma (CIN7-0) data are expected to be on the LS bits. This bit enables to swap the 8 MS bits with.." "newEnum1,newEnum2" bitfld.long 0x00 0.--1. " SDRPACK ,This bit field selects how the data are stored to SDRAM. There can be 8, 12 or 16 bits per pixel. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BSWD, ISIF_CCDCFG.MSBINV, ISIF_CCDCFG.SDRPACK bit fields contr.." "newEnum1,newEnum2,newEnum3,newEnum4" group.long 0x8C++0x3 line.long 0x00 "ISIF_DFCCTL,VERTICAL LINE DEFCT CTRL REGISTER" bitfld.long 0x00 8.--10. " VDFLSFT ,Vertical line Defect level shift value Defect Level (value to be subtracted from the data) is 8bit width, but can be up-shifted up to 6bits by VDFLSFT. Left shift value = VDFLSFT (Range: 0-6) Setting 7 to VDFLSFT is not allowed." "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. " VDFCUDA ,Vertical line Defect Correction upper pixels disable. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 5.--6. " VDFCSL ,Vertical line Defect Correction mode select. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" textline " " bitfld.long 0x00 4. " VDFCEN ,Vertical line Defect Correction enable. This bit field is latched by VD. - . - ." "newEnum1,newEnum2" group.long 0x90++0x3 line.long 0x00 "ISIF_VDFSATLV,VERTICAL LINE DEFCT CTRL REGISTER" hexmask.long.word 0x00 0.--11. 1. " VDFSLV ,Vertical line Defect Correction saturation level. VDFSLV is U12 (Range: 0 - 4,095)." group.long 0x94++0x3 line.long 0x00 "ISIF_DFCMEMCTL,VERTICAL LINE DEFCT CTRL REGISTER" bitfld.long 0x00 4. " DFCMCLR ,Defect correction. Memory clear. Writing 1 to this bit clears the memory contents to all zero. It will be automatically cleared to `0` when the memory clear is completed." "0,1" bitfld.long 0x00 2. " DFCMARST ,Defect correction. Memory address reset. Setting DFCMWR or DFCMRD with LSCMARST set starts memory access to address offset 0. DFCMARST is automatically cleared if data transfer completes. Setting DFCMWR or DFCMRD with LSCMA.." "newEnum1,newEnum2" bitfld.long 0x00 1. " DFCMRD ,Defect correction. Memory read [for debug purpose] Writing 1 to this bit starts reading from the memory. It will be automatically cleared when the data transfer is completed, and the data can be read from DFCMEM4-0." "0,1" textline " " bitfld.long 0x00 0. " DFCMWR ,Defect correction. Memory write Writing 1 to this bit starts writing to the memory. It will be automatically cleared when the data transfer is completed. DFCMEM4-0 should be set prior to the memory access." "0,1" group.long 0x98++0x3 line.long 0x00 "ISIF_DFCMEM0,Defect correction memory" hexmask.long.word 0x00 0.--12. 1. " DFCMEM0 ,Defect correction memory 0 Sets V position of the defects." group.long 0x9C++0x3 line.long 0x00 "ISIF_DFCMEM1,Defect correction memory" hexmask.long.word 0x00 0.--12. 1. " DFCMEM1 ,Defect correction memory 1 Sets H position of the defects." group.long 0xA0++0x3 line.long 0x00 "ISIF_DFCMEM2,Defect correction memory" hexmask.long.byte 0x00 0.--7. 1. " DFCMEM2 ,Defect correction Memory 2 Set SUB1: Defect level of the Vertical line defect position (V = Vdefect). DFCMEM2 can be up shifted according to VDFLSFT, and subtracted from the data for Vertical line defect correction." group.long 0xA4++0x3 line.long 0x00 "ISIF_DFCMEM3,Defect correction memory" hexmask.long.byte 0x00 0.--7. 1. " DFCMEM3 ,&lt;Defect correction&gt; Memory 3 Set SUB2: Defect level of the pixels upper than the Vertical line defect (V &lt; Vdefect). DFCMEM3 can be up shifted according to VDFLSFT, and subtracted from the data for Vertical line defec.." group.long 0xA8++0x3 line.long 0x00 "ISIF_DFCMEM4,Defect correction memory" hexmask.long.byte 0x00 0.--7. 1. " DFCMEM4 ,Memory 4 Set SUB3: Defect level of the pixels lower than the Vertical line defect (V &gt; Vdefect). DFCMEM4 can be up shifted according to VDFLSFT, and subtracted from the data for Vertical line defect correction." group.long 0xAC++0x3 line.long 0x00 "ISIF_CLAMPCFG,BLACK CLAMP CTRL REGISTER" bitfld.long 0x00 4. " CLMD ,Black clamp mode Clamp value can be calculated regardless of the color or can be calculated separately for each 4 colors. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--2. " CLHMD ,Horizontal Clamp mode - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 0. " CLEN ,Black Clamp Enable Enables clamp value to be subtracted from Image data. - . - ." "newEnum1,newEnum2" group.long 0xB0++0x3 line.long 0x00 "ISIF_CLDCOFST,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0x00 0.--12. 1. " CLDC ,DC offset for black clamp This value is added to the incoming pixels regardless whether optical black clamp is enabled (ISIF_CLAMPCFG.CLEN). This value is in S13Q0 format." group.long 0xB4++0x3 line.long 0x00 "ISIF_CLSV,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0x00 0.--12. 1. " CLSV ,Black Clamp Start position (V). Sets the line number where clamp value subtraction starts. Range: 0 - 8191" group.long 0xB8++0x3 line.long 0x00 "ISIF_CLHWIN0,BLACK CLAMP CTRL REGISTER" bitfld.long 0x00 12.--13. " CLHWN ,Horizontal Black clamp - Vertical dimension of a Window (2). - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 8.--9. " CLHWM ,Horizontal Black clamp - Horizontal dimension of a Window (2). - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 6. " CLHLMT ,Horizontal Black clamp - Pixel value limitation for the Horizontal clamp value calculation. If this bit is set, the maximum pixel value to be used for the clamp value calculation would be limited to 1023. By setting this bit, the pi.." "newEnum1,newEnum2" textline " " bitfld.long 0x00 5. " CLHWBS ,Horizontal Black clamp - Base Window select - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0.--4. " CLHWC ,Horizontal Black clamp - Window count per color Window count = CLHWC+1 Range: 1 - 32" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0xBC++0x3 line.long 0x00 "ISIF_CLHWIN1,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0x00 0.--12. 1. " CLHSH ,Horizontal black clamp. Window Start position (H). Range: 0 - 8191" group.long 0xC0++0x3 line.long 0x00 "ISIF_CLHWIN2,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0x00 0.--12. 1. " CLHSV ,Horizontal black clamp. Window Start position (V). Range: 0 - 8191" group.long 0xC4++0x3 line.long 0x00 "ISIF_CLVRV,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0x00 0.--11. 1. " CLVRV ,Vertical black clamp reset value. (U12) Range: 0 to 4095" group.long 0xC8++0x3 line.long 0x00 "ISIF_CLVWIN0,BLACK CLAMP CTRL REGISTER" hexmask.long.byte 0x00 8.--15. 1. " CLVCOEF ,Vertical Black clamp - Line average coefficient (k). Set a coefficient which is applied to the line average for clamp value calculation. (1-k) is applied to the clamp value of the previous line. Value in the U8Q8 format, the range is 0 to.." bitfld.long 0x00 4.--5. " CLVRVSL ,Vertical Black clamp - reset value selection Select the reset value for the clamp value of the previous line - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 0.--2. " CLVOBH ,Vertical Black clamp - Optical Black H valid (2). - . - . - . - . - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8" group.long 0xCC++0x3 line.long 0x00 "ISIF_CLVWIN1,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0x00 0.--12. 1. " CLVSH ,Vertical black clamp. Window Start position (H). Range: 0 - 8191" group.long 0xD0++0x3 line.long 0x00 "ISIF_CLVWIN2,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0x00 0.--12. 1. " CLVSV ,Vertical black clamp. Window Start position (V). Range: 0 - 8191" group.long 0xD4++0x3 line.long 0x00 "ISIF_CLVWIN3,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0x00 0.--12. 1. " CLVOBV ,Vertical black clamp. Optical black V valid (V). Range: 0 - 8191" group.long 0xD8++0x3 line.long 0x00 "ISIF_LSCHOFST,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--13. 1. " HOFST ,H direction Data offset for Lens Shading Correction. Range: 0-16,383 Not valid if the Formatter is enabled." group.long 0xDC++0x3 line.long 0x00 "ISIF_LSCVOFST,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--13. 1. " VOFST ,V direction Data offset for Lens Shading Correction. Range: 0-16,383" group.long 0xE0++0x3 line.long 0x00 "ISIF_LSCHVAL,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--13. 1. " HVAL ,Number of valid pixels in H direction. HVAL is for LSC. Number of valid pixels = HVAL+ 1" group.long 0xE4++0x3 line.long 0x00 "ISIF_LSCVVAL,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--13. 1. " VVAL ,Number of valid lines in V direction. VVAL is for LSC. Number of valid lines = VVAL+ 1" group.long 0xE8++0x3 line.long 0x00 "ISIF_2DLSCCFG,2D Lens Shading Correction Register" bitfld.long 0x00 12.--14. " GAIN_MODE_M ,Define the horizontal dimension of a paxel. Possible values are listed below. - . - . - . - . - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8" bitfld.long 0x00 8.--10. " GAIN_MODE_N ,Define the vertical dimension of a paxel. Possible values are listed below. - . - . - . - . - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8" bitfld.long 0x00 7. " BUSY ,Busy bit - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 1.--3. " GAIN_FORMAT ,Sets gain table format - . - . - . - . - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8" bitfld.long 0x00 0. " ENABLE ,Enables/disables LSC - . - ." "newEnum1,newEnum2" group.long 0xEC++0x3 line.long 0x00 "ISIF_2DLSCOFST,2D Lens Shading Correction Register" hexmask.long.byte 0x00 8.--15. 1. " OFSTSF ,Scaling factor for Offsets (U8Q7) Range: 0 to 1+127/128" bitfld.long 0x00 4.--6. " OFSTSFT ,Shift up value for Offsets (S8Q0) - . - . - . - . - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8" bitfld.long 0x00 0. " OFSTEN ,Enables/disables Offset control in LSC - . - ." "newEnum1,newEnum2" group.long 0xF0++0x3 line.long 0x00 "ISIF_2DLSCINI,2D Lens Shading Correction Register" hexmask.long.byte 0x00 8.--14. 1. " Y ,Initial Y Y position, in pixels, of the first active pixel in reference to the first active paxel. Must be an even number." hexmask.long.byte 0x00 0.--6. 1. " X ,Initial X X position, in pixels, of the first active pixel in reference to the first active paxel. Must be an even number." group.long 0xF4++0x3 line.long 0x00 "ISIF_2DLSCGRBU,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--15. 1. " BASE31_16 ,Gain Table address base (Upper 16-bits) Table address in bytes. Table is 32-bit aligned so this register must be a multiple of 4. This bit field sets the address of the gain table in memory." group.long 0xF8++0x3 line.long 0x00 "ISIF_2DLSCGRBL,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--15. 1. " BASE15_0 ,Gain Table address base (Lower 16-bits) Table address in bytes. Table is 32-bit aligned so this register must be a multiple of 4. This bit field sets the address of the gain table in memory." group.long 0xFC++0x3 line.long 0x00 "ISIF_2DLSCGROF,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--15. 1. " OFFSET ,Gain Table offset Defines the length, in bytes, of one row of the table. Table is 32-bit aligned, so this value must be a multiple of 4. Note that the row in memory could be longer than what LSC uses." group.long 0x100++0x3 line.long 0x00 "ISIF_2DLSCORBU,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--15. 1. " BASE ,Offset Table address base (Upper 16-bits) Table address in bytes. Table is 32-bit aligned so this register must be a multiple of 4. This bit field sets the address of the gain table in memory." group.long 0x104++0x3 line.long 0x00 "ISIF_2DLSCORBL,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--15. 1. " BASE ,Offset Table address base (Lower 16-bits) Table address in bytes. Table is 32-bit aligned so this register must be a multiple of 4. This bit field sets the address of the gain table in memory." group.long 0x108++0x3 line.long 0x00 "ISIF_2DLSCOROF,2D Lens Shading Correction Register" hexmask.long.word 0x00 0.--15. 1. " OFFSET ,Offset Table offset Defines the length, in bytes, of one row of the table. Table is 32-bit aligned, so this value must be a multiple of 4. Note that the row in memory could be longer than what LSC uses." group.long 0x10C++0x3 line.long 0x00 "ISIF_2DLSCIRQEN," bitfld.long 0x00 3. " SOF ,Interrupt status for LSC SOF Indicates the start of the LSC valid region. LSC configuration registers can be updated after LSC SOF for the next frame. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " PREFETCH_COMPLETED ,Interrupt enable for Prefetch Complete Indicates current state of the prefetch buffer. Could be used to start sending the data once the buffer is full to minimize the risk of an underflow. This event is triggered when the buffer c.." "newEnum1,newEnum2" bitfld.long 0x00 1. " PREFETCH_ERROR ,Interrupt enable for Prefetch Error The prefetch error indicates when the gain table was read to slowly from SDRAM. When this event is pending the module goes into transparent mode (output=input). Normal operation can be resumed at .." "newEnum1,newEnum2" textline " " bitfld.long 0x00 0. " DONE ,Interrupt enable for LSC Done The event is triggered when the internal state of LSC toggles from BUSY to IDLE. - . - ." "newEnum1,newEnum2" group.long 0x110++0x3 line.long 0x00 "ISIF_2DLSCIRQST,2D Lens Shading Correction Register" bitfld.long 0x00 3. " SOF ,Interrupt status for LSC SOF Indicates the start of the LSC valid region. LSC configuration registers can be updated after LSC SOF for the next frame. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " PREFETCH_COMPLETED ,Interrupt status for Prefetch Complete Indicates current state of the prefetch buffer. Could be used to start sending the data once the buffer is full to minimize the risk of an underflow. This event is triggered when the buffer c.." "newEnum1,newEnum2" bitfld.long 0x00 1. " PREFETCH_ERROR ,Interrupt status for Prefetch Error The prefetch error indicates when the gain table was read to slowly from SDRAM. When this event is pending the module goes into transparent mode (output=input). Normal operation can be resumed at .." "newEnum1,newEnum2" textline " " bitfld.long 0x00 0. " DONE ,Interrupt status for LSC Done The event is triggered when the internal state of LSC toggles from BUSY to IDLE. - . - ." "newEnum1,newEnum2" group.long 0x114++0x3 line.long 0x00 "ISIF_FMTCFG,Input Data Formatter Register" bitfld.long 0x00 8.--11. " FMTAINC ,Address increment Address increment = (FMTAINC + 1) Range (1-16) *This bit is latched by VD." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " LNUM ,Split/Combine number of lines *This bit is latched by VD. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 2. " LNALT ,Line alternating *This bit is latched by VD. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 1. " FMTCBL ,Combine Input lines *This bit is latched by VD. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " FMTEN ,CCD Formatter enable *This bit is latched by VD. - . - ." "newEnum1,newEnum2" group.long 0x118++0x3 line.long 0x00 "ISIF_FMTPLEN,Input Data Formatter Register" bitfld.long 0x00 12.--14. " FMTPLEN3 ,Number of program entries for SET3 Number of entries = (FMTPLEN3 + 1) Range: 1-8 Valid only if FMTCBL is set *This bit is latched by VD." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " FMTPLEN2 ,Number of program entries for SET2 Number of entries = (FMTPLEN2 + 1) Range: 1-8 Valid only if FMTCBL is set *This bit is latched by VD." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--7. " FMTPLEN1 ,Number of program entries for SET1 Number of entries = (FMTPLEN1 + 1) Range: 1-16 (FMTCBL = 0) 1-8 (FMTCBL = 1) Setting a value greater than 7 to FMTPLEN1 is not allowed if FMTCBL is set *This bit is latched by VD." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " FMTPLEN0 ,Number of program entries for SET0 Number of entries = (PLEN0 + 1) Range: 1-16 (FMTCBL = 0) 1-8 (FMTCBL = 1) Setting a value greater than 7 to FMTPLEN1 is not allowed if FMTCBL is set *This bit is latched by VD." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x11C++0x3 line.long 0x00 "ISIF_FMTSPH,Input Data Formatter Register" hexmask.long.word 0x00 0.--12. 1. " FMTSPH ,The first pixel in a line fed into the formatter" group.long 0x120++0x3 line.long 0x00 "ISIF_FMTLNH,Input Data Formatter Register" hexmask.long.word 0x00 0.--12. 1. " FMTLNH ,Number of pixels in a line fed to the formatter. Number of pixels = FMTLNH + 1" group.long 0x124++0x3 line.long 0x00 "ISIF_FMTLSV,Input Data Formatter Register" hexmask.long.word 0x00 0.--12. 1. " FMTSLV ,Start line vertical" group.long 0x128++0x3 line.long 0x00 "ISIF_FMTLNV,Input Data Formatter Register" hexmask.long.word 0x00 0.--14. 1. " FMTLNV ,Number of lines in vertical Number of lines = FMTLNV + 1" group.long 0x12C++0x3 line.long 0x00 "ISIF_FMTRLEN,Input Data Formatter Register" hexmask.long.word 0x00 0.--12. 1. " FMTRLEN ,Number of pixels in an output line Maximum value = 4480" group.long 0x130++0x3 line.long 0x00 "ISIF_FMTHCNT,Input Data Formatter Register" hexmask.long.word 0x00 0.--12. 1. " FMTHCNT ,HD interval for output lines Set all 0 to this register if combining multiple lines into a single line" group.long 0x134++0x3 line.long 0x00 "ISIF_FMTAPTR0,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 0 This address can not exceed FMTRLEN - 1" group.long 0x138++0x3 line.long 0x00 "ISIF_FMTAPTR1,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 1 This address can not exceed FMTRLEN - 1" group.long 0x13C++0x3 line.long 0x00 "ISIF_FMTAPTR2,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 2 This address can not exceed FMTRLEN - 1" group.long 0x140++0x3 line.long 0x00 "ISIF_FMTAPTR3,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 3 This address can not exceed FMTRLEN - 1" group.long 0x144++0x3 line.long 0x00 "ISIF_FMTAPTR4,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 4 This address can not exceed FMTRLEN - 1" group.long 0x148++0x3 line.long 0x00 "ISIF_FMTAPTR5,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 5 This address can not exceed FMTRLEN - 1" group.long 0x14C++0x3 line.long 0x00 "ISIF_FMTAPTR6,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 6 This address can not exceed FMTRLEN - 1" group.long 0x150++0x3 line.long 0x00 "ISIF_FMTAPTR7,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 7 This address can not exceed FMTRLEN - 1" group.long 0x154++0x3 line.long 0x00 "ISIF_FMTAPTR8,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 8 This address can not exceed FMTRLEN - 1" group.long 0x158++0x3 line.long 0x00 "ISIF_FMTAPTR9,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 9 This address can not exceed FMTRLEN - 1" group.long 0x15C++0x3 line.long 0x00 "ISIF_FMTAPTR10,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 10 This address can not exceed FMTRLEN - 1" group.long 0x160++0x3 line.long 0x00 "ISIF_FMTAPTR11,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 11 This address can not exceed FMTRLEN - 1" group.long 0x164++0x3 line.long 0x00 "ISIF_FMTAPTR12,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 12 This address can not exceed FMTRLEN - 1" group.long 0x168++0x3 line.long 0x00 "ISIF_FMTAPTR13,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 13 This address can not exceed FMTRLEN - 1" group.long 0x16C++0x3 line.long 0x00 "ISIF_FMTAPTR14,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 14 This address can not exceed FMTRLEN - 1" group.long 0x170++0x3 line.long 0x00 "ISIF_FMTAPTR15,Input Data Formatter Register" bitfld.long 0x00 13.--14. " LINE ,The output line the address belongs to Valid only if FMTCBL is cleared - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" hexmask.long.word 0x00 0.--12. 1. " INIT ,Initial address value for address pointer 15 This address can not exceed FMTRLEN - 1" group.long 0x174++0x3 line.long 0x00 "ISIF_FMTPGMVF0,Input Data Formatter Register" bitfld.long 0x00 15. " PGM15EN ,Program 15 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 14. " PGM14EN ,Program 14 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 13. " PGM13EN ,Program 13 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 12. " PGM12EN ,Program 12 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 11. " PGM11EN ,Program 11 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 10. " PGM10EN ,Program 10 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 9. " PGM09EN ,Program 9 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 8. " PGM08EN ,Program 8 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 7. " PGM07EN ,Program 7 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 6. " PGM06EN ,Program 6 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 5. " PGM05EN ,Program 5 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 4. " PGM04EN ,Program 4 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 3. " PGM03EN ,Program 3 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " PGM02EN ,Program 2 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " PGM01EN ,Program 1 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 0. " PGM00EN ,Program 0 Valid Flag - . - ." "newEnum1,newEnum2" group.long 0x178++0x3 line.long 0x00 "ISIF_FMTPGMVF1,Input Data Formatter Register" bitfld.long 0x00 15. " PGM31EN ,Program 31 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 14. " PGM30EN ,Program 30 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 13. " PGM29EN ,Program 29 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 12. " PGM28EN ,Program 28 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 11. " PGM27EN ,Program 27 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 10. " PGM26EN ,Program 26 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 9. " PGM25EN ,Program 25 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 8. " PGM24EN ,Program 24 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 7. " PGM23EN ,Program 23 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 6. " PGM22EN ,Program 22 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 5. " PGM21EN ,Program 21 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 4. " PGM20EN ,Program 20 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 3. " PGM19EN ,Program 19 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " PGM18EN ,Program 18 Valid Flag - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " PGM17EN ,Program 17 Valid Flag - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 0. " PGM16EN ,Program 16 Valid Flag - . - ." "newEnum1,newEnum2" group.long 0x17C++0x3 line.long 0x00 "ISIF_FMTPGMAPU0,Input Data Formatter Register" bitfld.long 0x00 15. " PGM15UPDT ,Program 15 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 14. " PGM14UPDT ,Program 14 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 13. " PGM13UPDT ,Program 13 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 12. " PGM12UPDT ,Program 12 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 11. " PGM11UPDT ,Program 11 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 10. " PGM10UPDT ,Program 10 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 9. " PGM9UPDT ,Program 9 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 8. " PGM8UPDT ,Program 8 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 7. " PGM7UPDT ,Program 7 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 6. " PGM6UPDT ,Program 6 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 5. " PGM5UPDT ,Program 5 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 4. " PGM4UPDT ,Program 4 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 3. " PGM3UPDT ,Program 3 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " PGM2UPDT ,Program 2 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " PGM1UPDT ,Program 1 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 0. " PGM0UPDT ,Program 0 Address Pointer Update - . - ." "newEnum1,newEnum2" group.long 0x180++0x3 line.long 0x00 "ISIF_FMTPGMAPU1,Input Data Formatter Register" bitfld.long 0x00 15. " PGM31UPDT ,Program 31 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 14. " PGM30UPDT ,Program 30 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 13. " PGM29UPDT ,Program 29 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 12. " PGM28UPDT ,Program 28 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 11. " PGM27UPDT ,Program 27 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 10. " PGM26UPDT ,Program 26 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 9. " PGM25UPDT ,Program 25 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 8. " PGM24UPDT ,Program 24 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 7. " PGM23UPDT ,Program 23 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 6. " PGM22UPDT ,Program 22 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 5. " PGM21UPDT ,Program 21 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 4. " PGM20UPDT ,Program 20 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 3. " PGM19UPDT ,Program 19 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " PGM18UPDT ,Program 18 Address Pointer Update - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " PGM17UPDT ,Program 17 Address Pointer Update - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 0. " PGM16UPDT ,Program 16 Address Pointer Update - . - ." "newEnum1,newEnum2" group.long 0x184++0x3 line.long 0x00 "ISIF_FMTPGMAPS0,Input Data Formatter Register" bitfld.long 0x00 12.--15. " PGM3APTR ,Program 3 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PGM2APTR ,Program 2 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PGM1APTR ,Program 1 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " PGM0APTR ,Program 0 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x188++0x3 line.long 0x00 "ISIF_FMTPGMAPS1,Input Data Formatter Register" bitfld.long 0x00 12.--15. " PGM7APTR ,Program 7 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PGM6APTR ,Program 6 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PGM5APTR ,Program 5 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " PGM4APTR ,Program 0 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18C++0x3 line.long 0x00 "ISIF_FMTPGMAPS2,Input Data Formatter Register" bitfld.long 0x00 12.--15. " PGM11APTR ,Program 11 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PGM10APTR ,Program 10 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PGM9APTR ,Program 9 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " PGM8APTR ,Program 8 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x190++0x3 line.long 0x00 "ISIF_FMTPGMAPS3,Input Data Formatter Register" bitfld.long 0x00 12.--15. " PGM15APTR ,Program 15 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PGM14APTR ,Program 14 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PGM13APTR ,Program 13 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " PGM12APTR ,Program 12 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x194++0x3 line.long 0x00 "ISIF_FMTPGMAPS4,Input Data Formatter Register" bitfld.long 0x00 12.--15. " PGM19APTR ,Program 19 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PGM18APTR ,Program 18 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PGM17APTR ,Program 17 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " PGM16APTR ,Program 16 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x198++0x3 line.long 0x00 "ISIF_FMTPGMAPS5,Input Data Formatter Register" bitfld.long 0x00 12.--15. " PGM23APTR ,Program 23 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PGM22APTR ,Program 22 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PGM21APTR ,Program 21 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " PGM20APTR ,Program 20 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x19C++0x3 line.long 0x00 "ISIF_FMTPGMAPS6,Input Data Formatter Register" bitfld.long 0x00 12.--15. " PGM27APTR ,Program 27 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PGM26APTR ,Program 26 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PGM25APTR ,Program 25 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " PGM24APTR ,Program 24 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1A0++0x3 line.long 0x00 "ISIF_FMTPGMAPS7,Input Data Formatter Register" bitfld.long 0x00 12.--15. " PGM31APTR ,Program 31 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PGM30APTR ,Program 30 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PGM29APTR ,Program 29 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " PGM28APTR ,Program 28 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1A4++0x3 line.long 0x00 "ISIF_CSCCTL,Color Space Converter Register" bitfld.long 0x00 0. " CSCEN ,Controls ON/OFF of Color Space converter. - . - ." "newEnum1,newEnum2" group.long 0x1A8++0x3 line.long 0x00 "ISIF_CSCM0,Color Space Converter Register" hexmask.long.byte 0x00 8.--15. 1. " CSCM01 ,Color Space convert coefficient value M01: This value is signed 8-bit with the 5-bits decimal." hexmask.long.byte 0x00 0.--7. 1. " CSCM00 ,Color Space convert coefficient value M00: This value is signed 8-bit with the 5-bits decimal." group.long 0x1AC++0x3 line.long 0x00 "ISIF_CSCM1,Color Space Converter Register" hexmask.long.byte 0x00 8.--15. 1. " CSCM03 ,Color Space convert coefficient value M03: This value is signed 8-bit with the 5-bits decimal." hexmask.long.byte 0x00 0.--7. 1. " CSCM02 ,Color Space convert coefficient value M02: This value is signed 8-bit with the 5-bits decimal." group.long 0x1B0++0x3 line.long 0x00 "ISIF_CSCM2,Color Space Converter Register" hexmask.long.byte 0x00 8.--15. 1. " CSCM11 ,Color Space convert coefficient value M11: This value is signed 8-bit with the 5-bits decimal." hexmask.long.byte 0x00 0.--7. 1. " CSCM10 ,Color Space convert coefficient value M10: This value is signed 8-bit with the 5-bits decimal." group.long 0x1B4++0x3 line.long 0x00 "ISIF_CSCM3,Color Space Converter Register" hexmask.long.byte 0x00 8.--15. 1. " CSCM13 ,Color Space convert coefficient value M13: This value is signed 8-bit with the 5-bits decimal." hexmask.long.byte 0x00 0.--7. 1. " CSCM12 ,Color Space convert coefficient value M12: This value is signed 8-bit with the 5-bits decimal." group.long 0x1B8++0x3 line.long 0x00 "ISIF_CSCM4,Color Space Converter Register" hexmask.long.byte 0x00 8.--15. 1. " CSCM21 ,Color Space convert coefficient value M21: This value is signed 8-bit with the 5-bits decimal." hexmask.long.byte 0x00 0.--7. 1. " CSCM20 ,Color Space convert coefficient value M20: This value is signed 8-bit with the 5-bits decimal." group.long 0x1BC++0x3 line.long 0x00 "ISIF_CSCM5,Color Space Converter Register" hexmask.long.byte 0x00 8.--15. 1. " CSCM23 ,Color Space convert coefficient value M23: This value is signed 8-bit with the 5-bits decimal." hexmask.long.byte 0x00 0.--7. 1. " CSCM22 ,Color Space convert coefficient value M22: This value is signed 8-bit with the 5-bits decimal." group.long 0x1C0++0x3 line.long 0x00 "ISIF_CSCM6,Color Space Converter Register" hexmask.long.byte 0x00 8.--15. 1. " CSCM31 ,Color Space convert coefficient value M31: This value is signed 8-bit with the 5-bits decimal." hexmask.long.byte 0x00 0.--7. 1. " CSCM30 ,Color Space convert coefficient value M30: This value is signed 8-bit with the 5-bits decimal." group.long 0x1C4++0x3 line.long 0x00 "ISIF_CSCM7,Color Space Converter Register" hexmask.long.byte 0x00 8.--15. 1. " CSCM33 ,Color Space convert coefficient value M33: This value is signed 8-bit with the 5-bits decimal." hexmask.long.byte 0x00 0.--7. 1. " CSCM32 ,Color Space convert coefficient value M32: This value is signed 8-bit with the 5-bits decimal." group.long 0x1F8++0x3 line.long 0x00 "ISIF_CLKCTL," bitfld.long 0x00 1. " CLKEN1 ,Forces isif_clken1 to be active. (Test mode) - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " CLKEN2 ,Forces isif_clken2 to be active. (Test mode) - . - ." "newEnum1,newEnum2" tree.end tree "ISS_RESIZER" base ad:0x52010400 width 18. rgroup.long 0x0++0x3 line.long 0x00 "RSZ_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x4++0x3 line.long 0x00 "RSZ_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is not shadowed. There is no standalone software reset for the resizer module." bitfld.long 0x00 9. " RSZB_CLK_EN ,Resizer B clock enable This bit enable to enable / disable the RESIZER B clock. Note that it is a second level clock enable. This bit has effect only if RSZ_GCK_SDR is set to 1. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 8. " RSZA_CLK_EN ,Resizer A clock enable This bit enable to enable / disable the RESIZER A clock. Note that it is a second level clock enable. This bit has effect only if RSZ_GCK_SDR is set to 1. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " AUTOGATING ,Internal Clock Gating Strategy Enables or disables auto clock gating. - . - ." "newEnum1,newEnum2" group.long 0xC++0x3 line.long 0x00 "RSZ_IN_FIFO_CTRL,INPUT DATA BUFFER CONTROL REGISTER This register is not shadowed" hexmask.long.word 0x00 16.--28. 1. " THRLD_LOW ,WhenRSZ_IN_FIFO_CTRL.THRLD_HIGH = RSZ_IN_FIFO_CTRL.THRLD_LOW, the rsz_stall_input is not asserted. The only purpose of the RSZ_IN_FIFO_CTRL.THRLD_LOW register is to prevent rsz_stall_input signal assertion." hexmask.long.word 0x00 0.--12. 1. " THRLD_HIGH ,High threshold value. The rsz_stall_input signal is asserted if 2 lines of circular buffer are full and the third line has more pixels than RSZ_IN_FIFO_CTRL.THRLD_HIGH. The rsz_stall_input signal stays high as long as one full.." rgroup.long 0x10++0x3 line.long 0x00 "RSZ_GNC,GENERIC PARAMETER REGISTER" hexmask.long.word 0x00 16.--28. 1. " RSZB_MEM_LINE_SIZE ,Resizer #B memory line size (pixels). The output image cannot exceed this size." hexmask.long.word 0x00 0.--12. 1. " RSZA_MEM_LINE_SIZE ,Resizer #A memory line size (pixels). The output image cannot exceed this size." group.long 0x14++0x3 line.long 0x00 "RSZ_FRACDIV,Fractional clock divider settings" hexmask.long.word 0x00 0.--15. 1. " RSZ_FRACDIV ,Fractional clock divider value. The fractional clock divider gates the read requests made to the input data buffer such that the input data buffer is read at an average frequency equal to FFCLK instead of FCLK. The value of FFCLK d.." group.long 0x20++0x3 line.long 0x00 "RSZ_SRC_EN,RESIZER ENABLE REGISTER This register is not shadowed" bitfld.long 0x00 0. " EN ,Resizer module enable The start flag of the RESIZER module. When EN is set to 1, the RESIZER module starts the processing from the next rising edge of the VD pulse. If the processing mode of the RESIZER module is set to 'one shot',.." "newEnum1,newEnum2" group.long 0x24++0x3 line.long 0x00 "RSZ_SRC_MODE,This register is not shadowed" bitfld.long 0x00 1. " WRT ,Video port WEN signal selection This bit selects whether the WEN signal which is present on the IPIPE and IPIPEIF video port is used or not to select the input data. If WRT is 0, the RESIZER module ignores the WEN signal and proces.." "newEnum1,newEnum2" bitfld.long 0x00 0. " OST ,The processing mode selection of the RESIZER module. Value 0 indicates the mode of free run, value 1 indicates the mode of one shot. - . - ." "newEnum1,newEnum2" group.long 0x28++0x3 line.long 0x00 "RSZ_SRC_FMT0,This register is not shadowed" bitfld.long 0x00 1. " BYPASS ,Pass Through This bit enables or disables the RESIZER module pass through mode. The pass through mode can transfer images which are 8K pixel wide. When it is enabled, the input data buffer and the resizer engines are bypassed. - . .." "newEnum1,newEnum2" bitfld.long 0x00 0. " SEL ,Input selection This bit selects which of the two video port is selected to push data through the RESIZER module. - . - ." "newEnum1,SRC" group.long 0x2C++0x3 line.long 0x00 "RSZ_SRC_FMT1," bitfld.long 0x00 2. " COL ,Y/C selection This bit is valid only if the input data is YUV4:2:0 (IN420 = 1). It enables to specify where the data which is input to the RESIZER module is luma or chroma data. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " IN420 ,Chroma Format Selection This bit sets the chroma undersampling when YUV data is input to the RESIZER module. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " RAW ,Pass-through mode input data format selection This bit affects the horizontal reversal (flipping) process. - . - ." "newEnum1,newEnum2" group.long 0x30++0x3 line.long 0x00 "RSZ_SRC_VPS,VERTICAL POSITION REGISTER This register is not shadowed" hexmask.long.word 0x00 0.--15. 1. " VPS ,Vertical Start Position Sets the vertical position of the global frame from the rising edge of the VD. The RSZ module will start the image processing from the VPS'th line. This value can be odd or even whatever the input data forma.." group.long 0x34++0x3 line.long 0x00 "RSZ_SRC_VSZ,VERTICAL SIZER REGISTER" hexmask.long.word 0x00 0.--12. 1. " VSZ ,Vertical Processing Size Sets the vertical size of the processing area. The RSZ module will process (VSZ+1) lines. This value can be odd or even whatever the input data format." group.long 0x38++0x3 line.long 0x00 "RSZ_SRC_HPS,HORIZONTAL POSITION REGISTER This register is not shadowed" hexmask.long.word 0x00 0.--15. 1. " HPS ,Horizontal Start Position The RSZ_SRC_HPS register has two functions: The first function is to compensate for possible delay between the HD pulse and the first valid data. It is possible for this delay to be different than 0 when t.." group.long 0x3C++0x3 line.long 0x00 "RSZ_SRC_HSZ,HORIZONTAL SIZE REGISTER The HSZ value is given by HSZ concatenated with HSZ_LSB" hexmask.long.word 0x00 0.--12. 1. " HSZ ,Horizontal size Sets the horizontal size of the processing area. The RSZ module processes (HSZ+1) pixels. (HSZ+1) must be even for YUV4:2:2 and RAW data. The valid available values for HSZ are 1~xxxx." group.long 0x40++0x3 line.long 0x00 "RSZ_DMA_RZA,RESIZER A - MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x00 0.--15. 1. " RZA ,Sets the minimum interval btw two consecutive memory request for resizer #A. Specified in number of interface clock cycles. Values of 0, 1, and 2 are used as a condition to keep the bandwidth limiter off. When this function is enab.." group.long 0x44++0x3 line.long 0x00 "RSZ_DMA_RZB,RESIZER B - MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x00 0.--15. 1. " RZB ,Sets the minimum interval btw two consecutive memory request for resizer #B. Specified in number of interface clock cycles. Values of 0, 1, and 2 are used as a condition to keep the bandwidth limiter off. When this function is enab.." rgroup.long 0x48++0x3 line.long 0x00 "RSZ_DMA_STA,RESIZER STATUS REGISTER" bitfld.long 0x00 0. " STATUS ,Resizer process status This bit is set in the time window from rsz_int_reg to rsz_int_dma. - . - ." "newEnum1,newEnum2" group.long 0x4C++0x3 line.long 0x00 "RSZ_GCK_MMR,MMR CLOCK CONTROL REGISTER This register is not shadowed" bitfld.long 0x00 0. " MMR ,The on/off selection of the MMR interface clock which is used for MMR register access. - . - ." "newEnum1,newEnum2" group.long 0x54++0x3 line.long 0x00 "RSZ_GCK_SDR,CORE CLOCK CONTROL REGISTER This register is not shadowed" bitfld.long 0x00 0. " CORE ,RSZ Core Clock Enable. This bit enables or disables the resizer core functional clock. When this bit is off, the resizer core (interpolator) is automatically bypassed (resizer-bypass mode of pass-through mode is selected depending .." "newEnum1,newEnum2" group.long 0x58++0x3 line.long 0x00 "RSZ_IRQ_RZA,RESIZER A - CIRCULAR BUFFER INTERRUPT INTERVAL REGISTER" hexmask.long.word 0x00 0.--12. 1. " RZA ,Resizer A circular buffer interval Sets the circular buffer interval for Resizer A. The interrupt is triggered every time (RZA+1) lines are written to the circular buffer (Y buffer). The range goes from 1 to 8192 lines. Usually, th.." group.long 0x5C++0x3 line.long 0x00 "RSZ_IRQ_RZB,RESIZER B - CIRCULAR BUFFER INTERRUPT INTERVAL REGISTER" hexmask.long.word 0x00 0.--12. 1. " RZB ,Resizer B circular buffer interval Sets the circular buffer interval for Resizer B. The interrupt is triggered every time (RZB+1) lines are written to the circular buffer (Y buffer). The range goes from 1 to 8192 lines. Usually, th.." group.long 0x60++0x3 line.long 0x00 "RSZ_YUV_Y_MIN,LUMINANCE SATURATION REGISTER" hexmask.long.byte 0x00 0.--7. 1. " MIN ,The minimum value of Luminance (8bits unsigned). If the value of the Luminance is smaller than VAL, it will be clipped to VAL. This bit field must be set to its default values when the resizer is set in pass-though mode." group.long 0x64++0x3 line.long 0x00 "RSZ_YUV_Y_MAX,LUMINANCE SATURATION REGISTER" hexmask.long.byte 0x00 0.--7. 1. " MAX ,The maximum value of Luminance (8bits unsigned). If the value of the Luminance is larger than VAL, it will be clipped to VAL. This bit field must be set to its default values when the resizer is set in pass-through mode." group.long 0x68++0x3 line.long 0x00 "RSZ_YUV_C_MIN,CHROMINANCE SATURATION REGISTER" hexmask.long.byte 0x00 0.--7. 1. " MIN ,The minimum value of Chrominance (8bits unsigned). If the value of the Chrominance is smaller than VAL, it will be clipped to VAL. This bit field must be set to its default values when the resizer is set in pass-though mode." group.long 0x6C++0x3 line.long 0x00 "RSZ_YUV_C_MAX,CHROMINANCE SATURATION REGISTER" hexmask.long.byte 0x00 0.--7. 1. " MAX ,The maximum value of Chrominance (8bits unsigned). If the value of the Chrominance is larger than VAL, it will be clipped to VAL. This bit field must be set to its default values when the resizer is set in pass-through mode." group.long 0x70++0x3 line.long 0x00 "RSZ_YUV_PHS,The phase position of the output of the Chrominance" bitfld.long 0x00 0. " POS ,The phase position of the output of the chrominance. The RESIZER module does not change the relative position of the chroma samples vs. the luma samples between the input and output and the chroma position at the output of the IPIP.." "newEnum1,newEnum2" group.long 0x74++0x3 line.long 0x00 "RSZ_SEQ," bitfld.long 0x00 4. " CRV ,Chroma sampling point change - . - ." "newEnum1,newEnum2" bitfld.long 0x00 3. " VRVB ,Resizer B - Vertical reversal of output image - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " HRVB ,Resizer B -Horizontal reversal of output image - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 1. " VRVA ,Resizer A - Vertical reversal of output image - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " HRVA ,Resizer A - Horizontal reversal of output image - . - ." "newEnum1,newEnum2" group.long 0x78++0x3 line.long 0x00 "RZA_EN,RESIZER A - ENABLE REGISTER" bitfld.long 0x00 0. " EN ,Enable resizer #A This bit is latched on video port VD input. The reason is that the resizer must only starts the processing on a clean frame boundary. In one-shot mode, this bit is negated on VD. - . - ." "newEnum1,newEnum2" group.long 0x7C++0x3 line.long 0x00 "RZA_MODE,RESIZER #A MODE REGISTER" bitfld.long 0x00 0. " MODE ,Select 'Free Run mode' or 'One Shot Mode' - . - ." "newEnum1,newEnum2" group.long 0x80++0x3 line.long 0x00 "RZA_420,YEN/CEN: 0/0: in = YUV4:2:2 input, out = YUV4:2:2 output 0/1: in = YUV4:2:2 input, out = Chrominance of YUV4:2:0 output 1/0: in = YUV4:2:2 input, out = Luminance of YUV4:2:0 output 1/1: in = YUV4:2:2 input, out = YUV4:2:0 output" bitfld.long 0x00 1. " CEN ,Output Enable for Chrominance This bit is valid in 422 input mode. When CEN=0 and YEN=0, output is 422 - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " YEN ,Output Enable for Luminance This bit is valid in 422 input mode. When CEN=0 and YEN=0, output is 422 - . - ." "newEnum1,newEnum2" group.long 0x84++0x3 line.long 0x00 "RZA_I_VPS,RESIZER A - INPUT VERTICAL START REGISTER" hexmask.long.word 0x00 0.--12. 1. " VPS ,Input Vertical Position Sets the vertical start position of the input image within the global frame. It enables to crop data into the global frame. After SRC_VPS, the Vps'th line is processed as the first line in each image." group.long 0x88++0x3 line.long 0x00 "RZA_I_HPS,RESIZER A - INPUT HORIZONTAL START REGISTER" hexmask.long.word 0x00 0.--12. 1. " HPS ,Input Horizontal Position Sets the horizontal position of the first pixel for each line within the global frame. After SRC_HPS, the pixel at the VAL'th position is processed as the first pixel. This value must be even." group.long 0x8C++0x3 line.long 0x00 "RZA_O_VSZ,RESIZER A - OUTPUT VERTICAL SIZER REGISTER" hexmask.long.word 0x00 0.--12. 1. " VSZ ,The target output size of the resized image. The number of output lines is (VSZ+1). Set 479, when 480 lines of output is required." group.long 0x90++0x3 line.long 0x00 "RZA_O_HSZ,RESIZER A - OUTPUT HORIZONTAL SIZE REGISTER" hexmask.long.word 0x00 1.--12. 1. " HSZ ,The horizontal size of output image. The number of pixel in each line is (HSZ+1). Set 479, when 480 pixels are required. This value must be lower than the max memory line size supported by the resizer engine, except in RAW pass thr.." bitfld.long 0x00 0. " HSZ_LSB ,The least significant bit of HSZ is forced to 1." "0,1" group.long 0x94++0x3 line.long 0x00 "RZA_V_PHS_Y,RESIZER A - INITIAL LUMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV4:2:2 data are output, the phase values for luma and chroma should typically be equal, that is, RZX_V_PHS_Y= RZX_V_PHS_C. The following constraints apply when setting .." hexmask.long.word 0x00 0.--13. 1. " Y ,The initial value for the luma phase in vertical resizing process. This value is in U14Q8 fractional format." group.long 0x98++0x3 line.long 0x00 "RZA_V_PHS_C,RESIZER A - INITIAL CHROMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV4:2:2 data are output, the phase values for luma and chroma should typically be equal, that is, RZX_V_PHS_Y= RZX_V_PHS_C. The following constraints apply when settin.." hexmask.long.word 0x00 0.--13. 1. " C ,The initial value for the chroma phase in vertical resizing process. This value is in U14Q8 fractional format." group.long 0x9C++0x3 line.long 0x00 "RZA_V_DIF,RESIZER A - VERTICAL RESIZER REGISTER" hexmask.long.word 0x00 0.--13. 1. " V ,The parameter for vertical resize. The actual resizing ratio is 256/RZA_V_DIF. In normal mode: 16 &lt;= RZA_V_DIF &lt;= 4096. In down-scale mode: 256 &lt;= RZA_V_DIF &lt;= 4096." group.long 0xA0++0x3 line.long 0x00 "RZA_V_TYP,RESIZER A - INTERPOLATION METHOD FOR VERTICAL RESIZING" bitfld.long 0x00 1. " C ,Selection of resizing method for chrominance: vertical - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " Y ,Selection of resizing method for luminance: vertical - . - ." "newEnum1,newEnum2" group.long 0xA4++0x3 line.long 0x00 "RZA_V_LPF,RESIZER A - VERTICAL LPF INTENSITY REGISTER" bitfld.long 0x00 6.--11. " C ,The intensity parameter for chroma vertical low pass filtering." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " Y ,The intensity parameter for luma vertical low pass filtering." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x3 line.long 0x00 "RZA_H_PHS,RESIZER A - INITIAL PHASE OF HORIZONTAL RESIZING PROCESS" hexmask.long.word 0x00 0.--13. 1. " PHS ,Initial value for the phase in horizontal resizing process, that is, the sampling position is shifted. This value is in U14Q8 fractional format. Example: If RZX_H_PHS = 128, the first output pixel is sampled at the center of the fi.." group.long 0xAC++0x3 line.long 0x00 "RZA_H_PHS_ADJ,RESIZER A - LUMINANCE HORIZONTAL PHASE ADJUSTMENT The register enables to adjust the horizontal phase for the luma component when averaging is enabled (the horizontal averaging disrupts the relative sampling point between luminance and ch.." hexmask.long.word 0x00 0.--8. 1. " ADJ ,Horizontal phase adjustment value. This value is in U9Q8 fractional format. This value is expected to be equal to zero if the averager is disabled or if input chroma is centered." group.long 0xB0++0x3 line.long 0x00 "RZA_H_DIF,RESIZER A - HORIZONTAL RESIZER REGISTER" hexmask.long.word 0x00 0.--13. 1. " H ,The parameter for horizontal resizing process. The actual resizing ratio is 256/VAL. In normal mode 16 &lt;= RSZ_RZA_H_DIF &lt;= 4096 In down-scale mode 256 &lt;= RSZ_RZA_H_DIF &lt;= 4096" group.long 0xB4++0x3 line.long 0x00 "RZA_H_TYP,Resize-A" bitfld.long 0x00 1. " C ,Selection of resizing method for chrominance: horizontal - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " Y ,Selection of resizing method for luminance: horizontal - . - ." "newEnum1,newEnum2" group.long 0xB8++0x3 line.long 0x00 "RZA_H_LPF,RESIZER A - HORIZONTAL LPF INTENSITY REGISTER" bitfld.long 0x00 6.--11. " C ,Horizontal LPF Intensity for Chrominance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " Y ,Selection of resizing method for Luminance in horizontal direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xBC++0x3 line.long 0x00 "RZA_DWN_EN,RESIZER #A - DOWNSCALE ENABLE REGISTER" bitfld.long 0x00 0. " DWN_EN ,Resizer downscale enable - . - ." "newEnum1,newEnum2" group.long 0xC0++0x3 line.long 0x00 "RZA_DWN_AV,Resize-A" bitfld.long 0x00 3.--5. " V ,Vertical averaging size : 1/2 The range goes from 1/2 to 1/256 in power of two. 0:_DIV2 1/2 down scale 1:_DIV4 1/4 down scale 2:_DIV8 1/8 down scale 3:_DIV16 1/16 down scale 4:_DIV32 1/32 down scale 5:_DIV64 1/64 down scale 6:_DIV1.." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " H ,Horizontal averaging size : 1/2 The range goes from 1/2 to 1/256 in power of two. 0:_DIV2 1/2 down scale 1:_DIV4 1/4 down scale 2:_DIV8 1/8 down scale 3:_DIV16 1/16 down scale 4:_DIV32 1/32 down scale 5:_DIV64 1/64 down sca.." "0,1,2,3,4,5,6,7" group.long 0xC4++0x3 line.long 0x00 "RZA_RGB_EN,RESIZER #A - RGB OUTPUT ENABLE" bitfld.long 0x00 0. " RGB_EN ,Enable of RGB output In pass through mode, this register must be 0. This bit can only be set to 1 when YUV4:2:2 data are output. YUV4:2:2 data output is selected when SRC_FMT1.IN420 = 0 and RZA_420.YEN = RZA_420.CEN = 0 - . - ." "newEnum1,newEnum2" group.long 0xC8++0x3 line.long 0x00 "RZA_RGB_TYP,RESIZER A - RGB OUTPUT CONTROL REGISTER" bitfld.long 0x00 2. " MSK1 ,Enables masking of the last 2 pixels This bit is used to mask the 2 last pixels at the image boundary which are affected by the YUV4:2:2 to YUV4:4:4 conversion. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " MSK0 ,Enables masking of the first 2 pixels This bit is used to mask the 2 first pixels at the image boundary which are affected by the YUV4:2:2 to YUV4:4:4 conversion. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " TYP ,16bit/32bit output selection - . - ." "newEnum1,newEnum2" group.long 0xCC++0x3 line.long 0x00 "RZA_RGB_BLD,RESIZER A - RGB BLEND REGISTER" hexmask.long.byte 0x00 0.--7. 1. " BLD ,The alpha value used in 32-bit RGBA output mode" group.long 0xD0++0x3 line.long 0x00 "RZA_SDR_Y_BAD_H,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER (HIGH) This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is writ.." hexmask.long.word 0x00 0.--15. 1. " Y_BAD_H ,Memory Base Address Sets the 16 upper bits of the 32-bit base address of the circular buffer in memory." group.long 0xD4++0x3 line.long 0x00 "RZA_SDR_Y_BAD_L,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER (LOW) This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is writt.." hexmask.long.word 0x00 0.--15. 1. " Y_BAD_L ,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory. It is a byte address. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal.." group.long 0xD8++0x3 line.long 0x00 "RZA_SDR_Y_SAD_H,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER (HIGH) This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is wri.." hexmask.long.word 0x00 0.--15. 1. " Y_SAD_H ,Memory Start Address Sets the 16 upper bits of the 32-bit start address in memory." group.long 0xDC++0x3 line.long 0x00 "RZA_SDR_Y_SAD_L,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER (LOW) This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is writ.." hexmask.long.word 0x00 0.--15. 1. " Y_SAD_L ,Memory Start Address Sets 16 lower bits of the 32-bit start address in memory." group.long 0xE0++0x3 line.long 0x00 "RZA_SDR_Y_OFT,RESIZER A - OUTPUT MEMORY OFFSET REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." hexmask.long.tbyte 0x00 0.--16. 1. " Y_OFT ,Memory Line Offset Sets the size of each line in the circular buffer. It is expressed in bytes and unsigned. Note that OFT does not necessary corresponds to the size of a line in a frame, it can be much bigger. The line offset must.." group.long 0xE4++0x3 line.long 0x00 "RZA_SDR_Y_PTR_S,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." hexmask.long.word 0x00 0.--12. 1. " Y_PTR_S ,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space. This value is expressed in number of lines. The hardware uses it to set up the initial value of the circular buffer. It mu.." group.long 0xE8++0x3 line.long 0x00 "RZA_SDR_Y_PTR_E,RESIZER A - OUTPUT MEMORY END ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." hexmask.long.word 0x00 0.--12. 1. " Y_PTR_E ,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space. This value is expressed in number of lines. When the number of output lines exceeds this value, the address restarts from the firs.." group.long 0xEC++0x3 line.long 0x00 "RZA_SDR_C_BAD_H,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." hexmask.long.word 0x00 0.--15. 1. " C_BAD_H ,Memory Base Address Sets the 16 higher bits of the 32-bit base address of the circular buffer in memory." group.long 0xF0++0x3 line.long 0x00 "RZA_SDR_C_BAD_L,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." hexmask.long.word 0x00 0.--15. 1. " C_BAD_L ,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory. It is a byte address. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal.." group.long 0xF4++0x3 line.long 0x00 "RZA_SDR_C_SAD_H,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." hexmask.long.word 0x00 0.--15. 1. " C_SAD_H ,Memory Base Address Sets the 16 higher bits of the 32-bit start address in memory." group.long 0xF8++0x3 line.long 0x00 "RZA_SDR_C_SAD_L,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." hexmask.long.word 0x00 0.--15. 1. " C_SAD_L ,Memory Base Address Sets the 16 lower bits of the 32-bit start address in memory. It is a byte address. For every frame, the first line of data will be written to this address. We have: SAD = BAD + (PTR_S x OFT) and PTR_S &lt; .." group.long 0xFC++0x3 line.long 0x00 "RZA_SDR_C_OFT,RESIZER A - OUTPUT MEMORY OFFSET REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" hexmask.long.tbyte 0x00 0.--16. 1. " C_OFT ,Memory Line Offset Sets the size of each line in the circular buffer. It is expressed in bytes and unsigned. Note that OFT does not necessary corresponds to the size of a line in a frame, it can be much bigger. The line offset must.." group.long 0x100++0x3 line.long 0x00 "RZA_SDR_C_PTR_S,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" hexmask.long.word 0x00 0.--12. 1. " C_PTR_S ,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space. This value is expressed in number of lines. The hardware uses it to set up the initial value of the circular buffer. It mu.." group.long 0x104++0x3 line.long 0x00 "RZA_SDR_C_PTR_E,RESIZER A - OUTPUT MEMORY END ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" hexmask.long.word 0x00 0.--12. 1. " C_PTR_E ,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space. This value is expressed in number of lines. When the number of output lines exceeds this value, the address restarts from the firs.." group.long 0x108++0x3 line.long 0x00 "RZB_EN,RESIZER B - ENABLE REGISTER" bitfld.long 0x00 0. " EN ,Enable resizer #A This bit is latched on the video port VD input signal. The reason is that the resizer must only starts the processing on a clean frame boundary. In one-shot mode, this bit is negated on VD. - . - ." "newEnum1,newEnum2" group.long 0x10C++0x3 line.long 0x00 "RZB_MODE,RESIZER B MODE REGISTER" bitfld.long 0x00 0. " MODE ,Select 'Free Run mode' or 'One Shot Mode' - . - ." "newEnum1,newEnum2" group.long 0x110++0x3 line.long 0x00 "RZB_420,YEN/CEN: 0/0: in = YUV4:2:2 input, out = YUV4:2:2 output 0/1: in = YUV4:2:2 input, out = Chrominance of YUV4:2:0 output 1/0: in = YUV4:2:2 input, out = Luminance of YUV4:2:0 output 1/1: in = YUV4:2:2 input, out = YUV4:2:0 output" bitfld.long 0x00 1. " CEN ,Output Enable for Chrominance This bit is valid in 422 input mode. When CEN=0 and YEN=0, output is 422 - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " YEN ,Output Enable for Luminance This bit is valid in 422 input mode. When CEN=0 and YEN=0, output is 422 - . - ." "newEnum1,newEnum2" group.long 0x114++0x3 line.long 0x00 "RZB_I_VPS,RESIZER B - INPUT VERTICAL START REGISTER" hexmask.long.word 0x00 0.--12. 1. " VPS ,Input Vertical Position Sets the vertical start position of the input image within the global frame. It enables to crop data into the global frame. After SRC_VPS, the Vps'th line is processed as the first line in each image." group.long 0x118++0x3 line.long 0x00 "RZB_I_HPS,RESIZER B - INPUT HORIZONTAL START REGISTER" hexmask.long.word 0x00 0.--12. 1. " HPS ,Input Horizontal Position Sets the horizontal position of the first pixel for each line within the global frame. After SRC_HPS, the pixel at the VAL'th position is processed as the first pixel. This value must be even." group.long 0x11C++0x3 line.long 0x00 "RZB_O_VSZ,RESIZER B - OUTPUT VERTICAL SIZER REGISTER" hexmask.long.word 0x00 0.--12. 1. " VSZ ,The target output size of the resized image. The number of output lines is (VSZ+1). Set 479, when 480 lines of output is required." group.long 0x120++0x3 line.long 0x00 "RZB_O_HSZ,RESIZER B - OUTPUT HORIZONTAL SIZE REGISTER" hexmask.long.word 0x00 1.--12. 1. " HSZ ,The horizontal size of output image. The number of pixel in each line is (HSZ+1). Set 479, when 480 pixels are required. This value must be lower than the max memory line size supported by the resizer engine, except in RAW pass thr.." bitfld.long 0x00 0. " HSZ_LSB ,The least significant bit of HSZ is forced to 1." "0,1" group.long 0x124++0x3 line.long 0x00 "RZB_V_PHS_Y,RESIZER B - INITIAL LUMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV4:2:2 data are output, the phase values for luma and chroma should typically be equal, that is, RZX_V_PHS_Y= RZX_V_PHS_C. The following constraints apply when setting .." hexmask.long.word 0x00 0.--13. 1. " Y ,The initial value for the luma phase in vertical resizing process. This value is in U14Q8 fractional format." group.long 0x128++0x3 line.long 0x00 "RZB_V_PHS_C,RESIZER B - INITIAL CHROMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV4:2:2 data are output, the phase values for luma and chroma should typically be equal, that is, RZX_V_PHS_Y= RZX_V_PHS_C. The following constraints apply when settin.." hexmask.long.word 0x00 0.--13. 1. " C ,The initial value for the chroma phase in vertical resizing process. This value is in U14Q8 fractional format." group.long 0x12C++0x3 line.long 0x00 "RZB_V_DIF,RESIZER B - VERTICAL RESIZER REGISTERR" hexmask.long.word 0x00 0.--13. 1. " V ,The parameter for vertical resize. The actual resizing ratio is 256/RZB_V_DIF. In normal mode: 16 &lt;= RZB_V_DIF &lt;= 4096. In down-scale mode: 256 &lt;= RZB_V_DIF &lt;= 4096." group.long 0x130++0x3 line.long 0x00 "RZB_V_TYP,RESIZER B - INTERPOLATION METHOD FOR VERTICAL RESIZING" bitfld.long 0x00 1. " C ,Selection of resizing method for chrominance: vertical - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " Y ,Selection of resizing method for luminance: vertical - . - ." "newEnum1,newEnum2" group.long 0x134++0x3 line.long 0x00 "RZB_V_LPF,RESIZER B - VERTICAL LPF INTENSITY REGISTER" bitfld.long 0x00 6.--11. " C ,The intensity parameter for chroma vertical low pass filtering." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " Y ,The intensity parameter for luma vertical low pass filtering." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x138++0x3 line.long 0x00 "RZB_H_PHS,RESIZER B - INITIAL PHASE OF HORIZONTAL RESIZING PROCESS" hexmask.long.word 0x00 0.--13. 1. " PHS ,Initial value for the phase in horizontal resizing process, that is, the sampling position is shifted. This value is in U14Q8 fractional format. Example: If RZX_H_PHS = 128, the first output pixel is sampled at the center of the fi.." group.long 0x13C++0x3 line.long 0x00 "RZB_H_PHS_ADJ,RESIZER B - LUMINANCE HORIZONTAL PHASE ADJUSTMENT The register enables to adjust the horizontal phase for the luma component when averaging is enabled (the horizontal averaging disrupts the relative sampling point between luminance and ch.." hexmask.long.word 0x00 0.--8. 1. " ADJ ,Horizontal phase adjustment value. This value is in U9Q8 fractional format. This value is expected to be equal to zero if the averager is disabled or if input chroma is centered." group.long 0x140++0x3 line.long 0x00 "RZB_H_DIF,RESIZER B - HORIZONTAL RESIZER REGISTER" hexmask.long.word 0x00 0.--13. 1. " H ,The parameter for horizontal resizing process. The actual resizing ratio is 256/VAL. In normal mode 16 &lt;= RSZ_RZA_H_DIF &lt;= 4096 In down-scale mode 256 &lt;= RSZ_RZA_H_DIF &lt;= 4096" group.long 0x144++0x3 line.long 0x00 "RZB_H_TYP,RESIZER B" bitfld.long 0x00 1. " C ,Selection of resizing method for chrominance: horizontal - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " Y ,Selection of resizing method for luminance: horizontal - . - ." "newEnum1,newEnum2" group.long 0x148++0x3 line.long 0x00 "RZB_H_LPF,RESIZER B - HORIZONTAL LPF INTENSITY REGISTER" bitfld.long 0x00 6.--11. " C ,Horizontal LPF Intensity for Chrominance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " Y ,Selection of resizing method for Luminance in horizontal direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x14C++0x3 line.long 0x00 "RZB_DWN_EN,RESIZER B - DOWNSCALE ENABLE REGISTER" bitfld.long 0x00 0. " DWN_EN ,Resizer downscale enable - . - ." "newEnum1,newEnum2" group.long 0x150++0x3 line.long 0x00 "RZB_DWN_AV,RESIZER B" bitfld.long 0x00 3.--5. " V ,Vertical averaging size : 1/2 The range goes from 1/2 to 1/256 in power of two. 0:_DIV2 1/2 down scale 1:_DIV4 1/4 down scale 2:_DIV8 1/8 down scale 3:_DIV16 1/16 down scale 4:_DIV32 1/32 down scale 5:_DIV64 1/64 down scale 6:_DIV1.." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " H ,Horizontal averaging size : 1/2 The range goes from 1/2 to 1/256 in power of two. 0:_DIV2 1/2 down scale 1:_DIV4 1/4 down scale 2:_DIV8 1/8 down scale 3:_DIV16 1/16 down scale 4:_DIV32 1/32 down scale 5:_DIV64 1/64 down sca.." "0,1,2,3,4,5,6,7" group.long 0x154++0x3 line.long 0x00 "RZB_RGB_EN,RESIZER B - RGB OUTPUT ENABLE" bitfld.long 0x00 0. " RGB_EN ,Enable of RGB output In pass through mode, this register must be 0. This bit can only be set to 1 when YUV4:2:2 data are output. YUV4:2:2 data output is selected when SRC_FMT1.IN420 = 0 and RZB_420.YEN = RZB_420.CEN = 0 - . - ." "newEnum1,newEnum2" group.long 0x158++0x3 line.long 0x00 "RZB_RGB_TYP,RESIZER B - RGB OUTPUT CONTROL REGISTER" bitfld.long 0x00 2. " MSK1 ,Enables masking of the last 2 pixels This bit is used to mask the 2 last pixels at the image boundary which are affected by the YUV4:2:2 to YUV4:4:4 conversion. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " MSK0 ,Enables masking of the first 2 pixels This bit is used to mask the 2 first pixels at the image boundary which are affected by the YUV4:2:2 to YUV4:4:4 conversion. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " TYP ,16bit/32bit output selection - . - ." "newEnum1,newEnum2" group.long 0x15C++0x3 line.long 0x00 "RZB_RGB_BLD,RESIZER B - RGB BLEND REGISTER" hexmask.long.byte 0x00 0.--7. 1. " BLD ,The alpha value used in 32-bit RGBA output mode" group.long 0x160++0x3 line.long 0x00 "RZB_SDR_Y_BAD_H,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to .." hexmask.long.word 0x00 0.--15. 1. " Y_BAD_H ,Memory Base Address Sets 16 upper bits of the 32-bit base address of the circular buffer in memory." group.long 0x164++0x3 line.long 0x00 "RZB_SDR_Y_BAD_L,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to .." hexmask.long.word 0x00 0.--15. 1. " Y_BAD_L ,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory. It is a byte address. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal.." group.long 0x168++0x3 line.long 0x00 "RZB_SDR_Y_SAD_H,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to.." hexmask.long.word 0x00 0.--15. 1. " Y_SAD_H ,Memory Start Address Sets 16 upper bits of the 32-bit start address in memory." group.long 0x16C++0x3 line.long 0x00 "RZB_SDR_Y_SAD_L,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to.." hexmask.long.word 0x00 0.--15. 1. " Y_SAD_L ,Memory Start Address Sets the 16 lower bits of the 32-bit start address in memory." group.long 0x170++0x3 line.long 0x00 "RZB_SDR_Y_OFT,RESIZER B - OUTPUT MEMORY OFFSET REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." hexmask.long.tbyte 0x00 0.--16. 1. " Y_OFT ,Memory Line Offset Sets the size of each line in the circular buffer. It is expressed in bytes and unsigned. Note that OFT does not necessary corresponds to the size of a line in a frame, it can be much bigger. The line offset must.." group.long 0x174++0x3 line.long 0x00 "RZB_SDR_Y_PTR_S,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4;2:2, YUV4:2:0 or RGBA." hexmask.long.word 0x00 0.--12. 1. " Y_PTR_S ,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space. This value is expressed in number of lines. The hardware uses it to set up the initial value of the circular buffer. It mu.." group.long 0x178++0x3 line.long 0x00 "RZB_SDR_Y_PTR_E,RESIZER B - OUTPUT MEMORY END ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." hexmask.long.word 0x00 0.--12. 1. " Y_PTR_E ,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space. This value is expressed in number of lines. When the number of output lines exceeds this value, the address restarts from the firs.." group.long 0x17C++0x3 line.long 0x00 "RZB_SDR_C_BAD_H,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." hexmask.long.word 0x00 0.--15. 1. " C_BAD_H ,Memory Base Address Sets the 16 upper bits of the 32-bit base address of the circular buffer in memory." group.long 0x180++0x3 line.long 0x00 "RZB_SDR_C_BAD_L,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." hexmask.long.word 0x00 0.--15. 1. " C_BAD_L ,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory. It is a byte address. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal.." group.long 0x184++0x3 line.long 0x00 "RZB_SDR_C_SAD_H,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." hexmask.long.word 0x00 0.--15. 1. " C_SAD_H ,Memory Base Address Sets the 16 upper bits of the 32-bit start address in memory." group.long 0x188++0x3 line.long 0x00 "RZB_SDR_C_SAD_L,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." hexmask.long.word 0x00 0.--15. 1. " C_SAD_L ,Memory Base Address Sets the 16 lower bits of the 32-bit start address in memory. It is a byte address. For every frame, the first line of data will be written to this address (C_SAD_H/C_SAD_L). We have: SAD = BAD + (PTR_S x OFT) a.." group.long 0x18C++0x3 line.long 0x00 "RZB_SDR_C_OFT,RESIZER B - OUTPUT MEMORY OFFSET REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" hexmask.long.tbyte 0x00 0.--16. 1. " C_OFT ,Memory Line Offset Sets the size of each line in the circular buffer. It is expressed in bytes and unsigned. Note that OFT does not necessary corresponds to the size of a line in a frame, it can be much bigger. The line offset must.." group.long 0x190++0x3 line.long 0x00 "RZB_SDR_C_PTR_S,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" hexmask.long.word 0x00 0.--12. 1. " C_PTR_S ,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space. This value is expressed in number of lines. The hardware uses it to set up the initial value of the circular buffer. It mu.." group.long 0x194++0x3 line.long 0x00 "RZB_SDR_C_PTR_E,RESIZER B - OUTPUT MEMORY END ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" hexmask.long.word 0x00 0.--12. 1. " C_PTR_E ,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space. This value is expressed in number of lines. When the number of output lines exceeds this value, the address restarts from the firs.." tree.end tree "ISS_ISP5_SYS2" base ad:0x520100A0 tree "IRQ_Line_0" width 25. group.long 0x24++0x3 line.long 0x00 "ISP5_IRQENABLE_CLR2_i_0,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. .." eventfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA. - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow - . - . - . - ." "No_action,Disable_Interrupt" textline " " eventfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Disable_Interrupt" group.long 0x20++0x3 line.long 0x00 "ISP5_IRQENABLE_SET2_i_0,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The.." bitfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA." "0,1" bitfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow" "0,1" bitfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow" "0,1" textline " " bitfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt" "0,1" bitfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Enable_interrupt" group.long 0x1C++0x3 line.long 0x00 "ISP5_IRQSTATUS2_i_0,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Overflow / underf.." eventfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA. - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow Overflow errors are not recoverable at ISP level, a software reset is required at ISS level. - . - . - . - ." "No_action,Clear_(raw)_event" textline " " eventfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. Overflow errors are not recoverable at ISP level, a software reset is required at ISS level. - . - . - . - ." "No_action,Clear_(raw)_event" group.long 0x18++0x3 line.long 0x00 "ISP5_IRQSTATUS_RAW2_i_0,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. Overflow / underflow errors are not recoverable at ISP level, a software reset is required.." bitfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by the MPU or the DMA. When the data is read with the MPU, one need to pay attention to clear the ISP5_CTRL[26] HST_RD_CHK bit imme.." "No_action,Set_event_(debug)" bitfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Set_event_(debug)" bitfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow - . - . - . - ." "No_action,Set_event_(debug)" textline " " bitfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Set_event_(debug)" bitfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Set_event_(debug)" tree.end tree "IRQ_Line_1" width 25. group.long 0x34++0x3 line.long 0x00 "ISP5_IRQENABLE_CLR2_i_1,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. .." eventfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA. - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow - . - . - . - ." "No_action,Disable_Interrupt" textline " " eventfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Disable_Interrupt" group.long 0x30++0x3 line.long 0x00 "ISP5_IRQENABLE_SET2_i_1,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The.." bitfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA." "0,1" bitfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow" "0,1" bitfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow" "0,1" textline " " bitfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt" "0,1" bitfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Enable_interrupt" group.long 0x2C++0x3 line.long 0x00 "ISP5_IRQSTATUS2_i_1,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Overflow / underf.." eventfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA. - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow Overflow errors are not recoverable at ISP level, a software reset is required at ISS level. - . - . - . - ." "No_action,Clear_(raw)_event" textline " " eventfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. Overflow errors are not recoverable at ISP level, a software reset is required at ISS level. - . - . - . - ." "No_action,Clear_(raw)_event" group.long 0x28++0x3 line.long 0x00 "ISP5_IRQSTATUS_RAW2_i_1,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. Overflow / underflow errors are not recoverable at ISP level, a software reset is required.." bitfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by the MPU or the DMA. When the data is read with the MPU, one need to pay attention to clear the ISP5_CTRL[26] HST_RD_CHK bit imme.." "No_action,Set_event_(debug)" bitfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Set_event_(debug)" bitfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow - . - . - . - ." "No_action,Set_event_(debug)" textline " " bitfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Set_event_(debug)" bitfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Set_event_(debug)" tree.end tree "IRQ_Line_2" width 25. group.long 0x44++0x3 line.long 0x00 "ISP5_IRQENABLE_CLR2_i_2,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. .." eventfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA. - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow - . - . - . - ." "No_action,Disable_Interrupt" textline " " eventfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Disable_Interrupt" group.long 0x40++0x3 line.long 0x00 "ISP5_IRQENABLE_SET2_i_2,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The.." bitfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA." "0,1" bitfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow" "0,1" bitfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow" "0,1" textline " " bitfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt" "0,1" bitfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Enable_interrupt" group.long 0x3C++0x3 line.long 0x00 "ISP5_IRQSTATUS2_i_2,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Overflow / underf.." eventfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA. - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow Overflow errors are not recoverable at ISP level, a software reset is required at ISS level. - . - . - . - ." "No_action,Clear_(raw)_event" textline " " eventfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. Overflow errors are not recoverable at ISP level, a software reset is required at ISS level. - . - . - . - ." "No_action,Clear_(raw)_event" group.long 0x38++0x3 line.long 0x00 "ISP5_IRQSTATUS_RAW2_i_2,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. Overflow / underflow errors are not recoverable at ISP level, a software reset is required.." bitfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by the MPU or the DMA. When the data is read with the MPU, one need to pay attention to clear the ISP5_CTRL[26] HST_RD_CHK bit imme.." "No_action,Set_event_(debug)" bitfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Set_event_(debug)" bitfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow - . - . - . - ." "No_action,Set_event_(debug)" textline " " bitfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Set_event_(debug)" bitfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Set_event_(debug)" tree.end tree "IRQ_Line_3" width 25. group.long 0x54++0x3 line.long 0x00 "ISP5_IRQENABLE_CLR2_i_3,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. .." eventfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA. - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow - . - . - . - ." "No_action,Disable_Interrupt" textline " " eventfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Disable_Interrupt" eventfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Disable_Interrupt" group.long 0x50++0x3 line.long 0x00 "ISP5_IRQENABLE_SET2_i_3,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The.." bitfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA." "0,1" bitfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow" "0,1" bitfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow" "0,1" textline " " bitfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt" "0,1" bitfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Enable_interrupt" group.long 0x4C++0x3 line.long 0x00 "ISP5_IRQSTATUS2_i_3,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Overflow / underf.." eventfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA. - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow Overflow errors are not recoverable at ISP level, a software reset is required at ISS level. - . - . - . - ." "No_action,Clear_(raw)_event" textline " " eventfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. Overflow errors are not recoverable at ISP level, a software reset is required at ISS level. - . - . - . - ." "No_action,Clear_(raw)_event" group.long 0x48++0x3 line.long 0x00 "ISP5_IRQSTATUS_RAW2_i_3,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. Overflow / underflow errors are not recoverable at ISP level, a software reset is required.." bitfld.long 0x00 4. " IPIPE_HST_ERR ,IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by the MPU or the DMA. When the data is read with the MPU, one need to pay attention to clear the ISP5_CTRL[26] HST_RD_CHK bit imme.." "No_action,Set_event_(debug)" bitfld.long 0x00 3. " ISIF_OVF ,ISIF module overflow - . - . - . - ." "No_action,Set_event_(debug)" bitfld.long 0x00 2. " IPIPE_BOXCAR_OVF ,IPIPE BOXCAR module overflow - . - . - . - ." "No_action,Set_event_(debug)" textline " " bitfld.long 0x00 1. " IPIPEIF_UDF ,IPIPEIF module underflow interrupt - . - . - . - ." "No_action,Set_event_(debug)" bitfld.long 0x00 0. " H3A_OVF ,H3A module overflow interrupt. - . - . - . - ." "No_action,Set_event_(debug)" tree.end textline "" width 14. rgroup.long 0x0++0x3 line.long 0x00 "ISP5_KEY_EN1,IPIPE eFuse enable." bitfld.long 0x00 0. " KEY1_EN ,eFuse enable Equals 1 when ISP5_EFUSE3_EN = 1 or 0 otherwise. - . - ." "newEnum1,newEnum2" rgroup.long 0x4++0x3 line.long 0x00 "ISP5_KEY_EN2,ISIF eFuse enable." bitfld.long 0x00 0. " KEY1_EN ,eFuse enable Equals 1 when ISP5_EFUSE1_EN = 1 or 0 otherwise. - . - ." "newEnum1,newEnum2" rgroup.long 0x8++0x3 line.long 0x00 "ISP5_KEY_EN3,ISIF eFuse enable." bitfld.long 0x00 0. " KEY_EN ,eFuse enable Equals 1 when ISP5_EFUSE3_EN = 1 or 0 otherwise. - . - ." "newEnum1,newEnum2" rgroup.long 0xC++0x3 line.long 0x00 "ISP5_KEY_EN4,IPIPEIF eFuse enable." bitfld.long 0x00 1. " KEY2_EN ,eFuse enable Equals 1 when ISP5_EFUSE4_EN = 1 or 0 otherwise. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " KEY1_EN ,eFuse enable Equals 1 when ISP5_EFUSE1_EN = 1 or 0 otherwise. - . - ." "newEnum1,newEnum2" rgroup.long 0x10++0x3 line.long 0x00 "ISP5_KEY_EN5,H3A eFuse enable." bitfld.long 0x00 0. " KEY_EN ,eFuse enable Equals 1 when ISP5_EFUSE2_EN = 1 or 0 otherwise. - . - ." "newEnum1,newEnum2" rgroup.long 0x14++0x3 line.long 0x00 "ISP5_KEY_EN6,H3A eFuse enable." bitfld.long 0x00 0. " KEY_EN ,eFuse enable Equals 1 when ISP5_EFUSE3_EN = 1 or 0 otherwise. - . - ." "newEnum1,newEnum2" tree.end tree "ISS_H3A" base ad:0x52011400 width 16. rgroup.long 0x0++0x3 line.long 0x00 "H3A_PID,Peripheral Revision and Class Information" bitfld.long 0x00 30.--31. " SCHEME ," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ," bitfld.long 0x00 11.--15. " RTL ," "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" textline " " bitfld.long 0x00 8.--10. " MAJOR ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--5. " MINOR ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4++0x3 line.long 0x00 "H3A_PCR,Peripheral Control Register" hexmask.long.word 0x00 22.--31. 1. " AVE2LMT ,AE/AWB Saturation Limit This is the value that all sub sampled pixels in the AE/AWB engine are compared to. If the data is greater or equal to this data then the block is considered saturated." bitfld.long 0x00 21. " OVF ,H3A module overflow status bit. If the H3A module overflows it will keep sending data. The software can read this status bit during vertical blanking period to ensure that no overflow happened while writing out the data to SDRAM. Ther.." "newEnum1,newEnum2" bitfld.long 0x00 20. " AF_VF_EN ,AF Vertical Focus Enable - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 19. " AEW_MED_EN ,AE/AWB Median filter Enable If the median filter is enabled, then the 1st 2 and last 2 pixels in the frame are not filtered. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 18. " BUSYAEAWB ,Busy bit for AE/AWB" "0,1" bitfld.long 0x00 17. " AEW_ALAW_EN ,AE/AWB A-law Enable - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 16. " AEW_EN ,AE/AWB enable - . - ." "newEnum1,newEnum2" bitfld.long 0x00 15. " BUSYAF ,Busy bit for AF." "0,1" bitfld.long 0x00 14. " FVMODE ,Focus Value Accumulation Mode - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 11.--13. " RGBPOS ,Red, Green, and blue pixel location in the AF windows RGBPOS(0): GR and GB as Bayer pattern RGBPOS(1): RG and GB as Bayer pattern RGBPOS(2): GR and BG as Bayer pattern RGBPOS(3): RG and BG as Bayer pattern RGBPOS(4): GG and RB as custom pa.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 3.--10. 1. " MED_TH ,Median filter threshold." bitfld.long 0x00 2. " AF_MED_EN ,Auto Focus Median filter Enable If the median filter is enabled, then the 1st 2 and last 2 pixels in the frame are not in the valid region. Therefore the paxel start/end and IIR filter start positions should not be set within th.." "newEnum1,newEnum2" textline " " bitfld.long 0x00 1. " AF_ALAW_EN ,AF A-law table enable - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " AF_EN ,AF enable - . - ." "newEnum1,newEnum2" group.long 0x8++0x3 line.long 0x00 "H3A_AFPAX1,Setup for the AF Engine Paxel Configuration" hexmask.long.byte 0x00 16.--23. 1. " PAXW ,AF Engine Paxel Width The width of the paxel is the value of this register plus 1 multiplied by 2. The minimum width is 16 pixels if the pixel clock is half or less of the ISS_FLCK clock. If the pixel clock is equal to the ISS_FLCK clock, .." hexmask.long.byte 0x00 0.--7. 1. " PAXH ,AF Engine Paxel Height The height of the paxel is the value of this register plus 1 multiplied by 2 with a final value of 2-256 (even) * This value is shadowed and latched on the rising edge of VSYNC." group.long 0xC++0x3 line.long 0x00 "H3A_AFPAX2,Setup for the AF Engine Paxel Configuration" bitfld.long 0x00 17.--20. " AFINCH ,AF Engine Column Increments Number of columns to increment in a paxel plus 1 multiplied by 2. Thus, the number of columns that can be skipped between two processed line pairs is 2-32 (even). The starting two columns in a paxel are first pr.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13.--16. " AFINCV ,AF Engine Line Increments Number of lines to increment in a Paxel plus 1 multiplied by 2. Incrementing the line in a paxel is always done on a line pair due to the fact that the RGB pattern falls in two lines. If all the lines are t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 6.--12. 1. " PAXVC ,AF Engine Vertical Paxel Count The number of paxels in the vertical direction plus 1. The maximum number of vertical paxels in a frame should not exceed 128. The value should be set to ensure that the bandwidth requirements and .." textline " " bitfld.long 0x00 0.--5. " PAXHC ,AF Engine Horizontal Paxel Count The number of paxels in the horizontal direction plus 1. It is illegal to set a number that is greater than 35 (total of 36 paxels in the horizontal direction). The minimum number of paxels should be 2 (val.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x3 line.long 0x00 "H3A_AFPAXSTART,Start Position for AF Engine Paxels" hexmask.long.word 0x00 16.--27. 1. " PAXSH ,AF Engine Paxel Horizontal start position Range: 2-4094 PAXSH must be equal to or greater than (IIRSH + 2) This value must be even if Vertical mode is not enabled. If Vertical mode is enabled then the lower bit of PAXSH and IIRSH must be e.." hexmask.long.word 0x00 0.--11. 1. " PAXSV ,AF Engine Paxel Vertical start position Range: 0-4095 Sets the vertical line for the first paxel. This value must be greater then or equal to 8 if the vertical mode is enabled. * This value is shadowed and latched on the rising edge o.." group.long 0x14++0x3 line.long 0x00 "H3A_AFIIRSH,Start Position for IIRSH" hexmask.long.word 0x00 0.--11. 1. " IIRSH ,AF Engine IIR Horizontal Start Position Range from 0-4094. When the horizontal position of a line equals this value the shift registers are cleared on the next pixel. This value must be even if Vertical mode is not enabled. If vertical mod.." group.long 0x18++0x3 line.long 0x00 "H3A_AFBUFST,SDRAM destination address for AF engine statistics" hexmask.long 0x00 5.--31. 1. " AFBUFST ,SDRAM destination address for AF engine statistics The SDRAM destination address for the AF statistics. The 6 LSBs are ignored, address must be on a 64-byte boundary. This field can be altered even when the AF is busy. Change will take pla.." group.long 0x1C++0x3 line.long 0x00 "H3A_AFCOEF010,IIR filter coefficient data for SET 0." hexmask.long.word 0x00 16.--27. 1. " COEFF1 ,AF Engine IIR filter Coefficient #1 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF0 ,AF Engine IIR filter Coefficient #0 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x20++0x3 line.long 0x00 "H3A_AFCOEF032,IIR filter coefficient data for SET 0." hexmask.long.word 0x00 16.--27. 1. " COEFF3 ,AF Engine IIR filter Coefficient #3 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF2 ,AF Engine IIR filter Coefficient #2 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x24++0x3 line.long 0x00 "H3A_AFCOEF054,IIR filter coefficient data for SET 0." hexmask.long.word 0x00 16.--27. 1. " COEFF5 ,AF Engine IIR filter Coefficient #5 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF4 ,AF Engine IIR filter Coefficient #4 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x28++0x3 line.long 0x00 "H3A_AFCOEF076,IIR filter coefficient data for SET 0." hexmask.long.word 0x00 16.--27. 1. " COEFF7 ,AF Engine IIR filter Coefficient #7 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF6 ,AF Engine IIR filter Coefficient #6 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x2C++0x3 line.long 0x00 "H3A_AFCOEF098,IIR filter coefficient data for SET 0." hexmask.long.word 0x00 16.--27. 1. " COEFF9 ,AF Engine IIR filter Coefficient #9 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF8 ,AF Engine IIR filter Coefficient #8 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x30++0x3 line.long 0x00 "H3A_AFCOEF0010,IIR filter coefficient data for SET 0." hexmask.long.word 0x00 0.--11. 1. " COEFF10 ,AF Engine IIR filter Coefficient #10 (Set 0) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x34++0x3 line.long 0x00 "H3A_AFCOEF110,IIR filter coefficient data for SET 1." hexmask.long.word 0x00 16.--27. 1. " COEFF1 ,AF Engine IIR filter Coefficient #1 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF0 ,AF Engine IIR filter Coefficient #0 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x38++0x3 line.long 0x00 "H3A_AFCOEF132,IIR filter coefficient data for SET 1." hexmask.long.word 0x00 16.--27. 1. " COEFF3 ,AF Engine IIR filter Coefficient #3 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF2 ,AF Engine IIR filter Coefficient #2 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x3C++0x3 line.long 0x00 "H3A_AFCOEF154,IIR filter coefficient data for SET 1." hexmask.long.word 0x00 16.--27. 1. " COEFF5 ,AF Engine IIR filter Coefficient #5 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF4 ,AF Engine IIR filter Coefficient #4 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x40++0x3 line.long 0x00 "H3A_AFCOEF176,IIR filter coefficient data for SET 1." hexmask.long.word 0x00 16.--27. 1. " COEFF7 ,AF Engine IIR filter Coefficient #7 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF6 ,AF Engine IIR filter Coefficient #6 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x44++0x3 line.long 0x00 "H3A_AFCOEF198,IIR filter coefficient data for SET 1." hexmask.long.word 0x00 16.--27. 1. " COEFF9 ,AF Engine IIR filter Coefficient #9 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" hexmask.long.word 0x00 0.--11. 1. " COEFF8 ,AF Engine IIR filter Coefficient #8 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x48++0x3 line.long 0x00 "H3A_AFCOEF1010,IIR filter coefficient data for SET 1." hexmask.long.word 0x00 0.--11. 1. " COEFF10 ,AF Engine IIR filter Coefficient #10 (Set 1) The range is signed -32 &lt;= value &lt;= 31 +63/64" group.long 0x4C++0x3 line.long 0x00 "H3A_AEWWIN1,Configuration for AE/AWB Windows." hexmask.long.byte 0x00 24.--31. 1. " WINH ,AE/AWB Engine Window Height This specifies the window height in an even number of pixels, the window height is the value plus 1 multiplied by 2. The final value can be from 2-512 (even) * This value is shadowed and latched on the rising ed.." hexmask.long.byte 0x00 13.--20. 1. " WINW ,AE/AWB Engine Window Width This specifies the window width in an even number of pixels, the window width is the value plus 1 multiplied by 2. The minimum width is 16 pixels if the pixel clock is half or less of the ISS_FLCK clock. I.." hexmask.long.byte 0x00 6.--12. 1. " WINVC ,AE/AWB Engine Vertical Window Count The number of windows in the vertical direction plus 1. The maximum number of vertical windows in a frame should not exceed 128. The value should be set to ensure that the bandwidth requiremen.." textline " " bitfld.long 0x00 0.--5. " WINHC ,AE/AWB Engine Horizontal Window Count The number of horizontal windows plus 1. The maximum number of horizontal windows is 35 plus 1 (36). The minimum number of windows should be 2 (valid range for the field is 1-35). * This value is shado.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x3 line.long 0x00 "H3A_AEWINSTART,Start position for AE/AWB Windows." hexmask.long.word 0x00 16.--27. 1. " WINSV ,AE/AWB Engine Vertical Window Start Position Sets the first line for the first window. Range 0-4095 * This value is shadowed and latched on the rising edge of VSYNC." hexmask.long.word 0x00 0.--11. 1. " WINSH ,AE/AWB Engine Horizontal Window Start Position Sets the horizontal position for the first window on each line. Range 0-4095 * This value is shadowed and latched on the rising edge of VSYNC." group.long 0x54++0x3 line.long 0x00 "H3A_AEWINBLK,Start position and height for black line of AE/AWB Windows" hexmask.long.word 0x00 16.--27. 1. " WINSV ,AE/AWB Engine Vertical Window Start Position for single black line of windows Sets the first line for the single black line of windows. * This value is shadowed and latched on the rising edge of VSYNC. Range 0-4095 Note that the horizontal.." hexmask.long.byte 0x00 0.--6. 1. " WINH ,AE/AWB Engine Window Height for the single black line of windows This specifies the window height in an even number of pixels, the window height is the value plus 1 multiplied by 2. The final value can be from 2-256 (even) * This valu.." group.long 0x58++0x3 line.long 0x00 "H3A_AEWSUBWIN,Configuration for subsample data in AE/AWB window." bitfld.long 0x00 8.--11. " AEWINCV ,AE/AWB Engine Vertical Sampling Point Increment Sets vertical distance between sub-samples within a window plus 1 multiplied by 2. The final range is 2-32. * This value is shadowed and latched on the rising edge of VSYNC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " AEWINCH ,AE/AWB Engine Horizontal Sampling Point Increment Sets horizontal distance between sub-samples within a window plus 1 multiplied by 2. The final range is 2-32. * This value is shadowed and latched on the rising edge of VSYNC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C++0x3 line.long 0x00 "H3A_AEWBUFST,SDRAM destination address for AE/AWB engine statistics" hexmask.long 0x00 5.--31. 1. " AEWBUFST ,SDRAM destination address for AE/AWB engine statistics The start location in SDRAM for the AE/AWB statistics. The 6 LSB are ignored, address should be on a 64-byte boundary This field can be altered even when the AE/AWB is busy. Change wil.." group.long 0x60++0x3 line.long 0x00 "H3A_AEWCFG,Configuration for AE/AWB" bitfld.long 0x00 8.--9. " AEFMT ,AE/AWB output format 0 = sum of squares 1 = min/max 2 = sum only; no sum of squares or min/max * This value is shadowed and latched on the rising edge of VSYNC" "0,1,2,3" bitfld.long 0x00 0.--3. " SUMSHFT ,AE/AWB engine shift value for the accumulation of pixel values This bit field sets the right shift value which is applied on the result of the pixel accumulation before it is stored in the packet. The accumulation takes place on 26.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x64++0x3 line.long 0x00 "H3A_LINE_START,Line Framing Logic Register In certain cases the number of clock cycles between HD pulses will be greater than the line buffer included in the H3A module. The framing module prior to the line buffer enables to control the data which is i.." hexmask.long.word 0x00 16.--31. 1. " SLV ,Start Line Vertical Specifies how many lines after the VD rising edge the real frame starts." hexmask.long.word 0x00 0.--15. 1. " LINE_START ,Line Start The framing module uses the LINE_START bit field to find the position of the first pixel to place into the line buffer. Range: 0-65535" group.long 0x68++0x3 line.long 0x00 "H3A_VFV_CFG1,Vertical focus value configuration 1." hexmask.long.byte 0x00 24.--31. 1. " VCOEF1_3 ,Vertical FV FIR 1 coefficient 3" hexmask.long.byte 0x00 16.--23. 1. " VCOEF1_2 ,Vertical FV FIR 1 coefficient 2" hexmask.long.byte 0x00 8.--15. 1. " VCOEF1_1 ,Vertical FV FIR 1 coefficient 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " VCOEF1_0 ,Vertical FV FIR 1 coefficient 0" group.long 0x6C++0x3 line.long 0x00 "H3A_VFV_CFG2,Vertical focus value configuration 2." hexmask.long.word 0x00 16.--31. 1. " VTHR1 ,Threshold for vertical FV FIR 1" hexmask.long.byte 0x00 0.--7. 1. " VCOEF1_4 ,Vertical FV FIR 1 coefficient 4" group.long 0x70++0x3 line.long 0x00 "H3A_VFV_CFG3,Vertical focus value configuration 4." hexmask.long.byte 0x00 24.--31. 1. " VCOEF2_3 ,Vertical FV FIR 2 coefficient 3" hexmask.long.byte 0x00 16.--23. 1. " VCOEF2_2 ,Vertical FV FIR 2 coefficient 2" hexmask.long.byte 0x00 8.--15. 1. " VCOEF2_1 ,Vertical FV FIR 2 coefficient 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " VCOEF2_0 ,Vertical FV FIR 2 coefficient 0" group.long 0x74++0x3 line.long 0x00 "H3A_VFV_CFG4,Vertical focus value configuration 4." hexmask.long.word 0x00 16.--31. 1. " VTHR2 ,Threshold for vertical FV FIR 2" hexmask.long.byte 0x00 0.--7. 1. " VCOEF2_4 ,Vertical FV FIR 2 coefficient 4" group.long 0x78++0x3 line.long 0x00 "H3A_HVF_THR,Horizontal Focus Value Threshold" hexmask.long.word 0x00 16.--31. 1. " HTHR2 ,Threshold for horizontal FV IIR 2" hexmask.long.word 0x00 0.--15. 1. " HTHR1 ,Threshold for horizontal FV IIR 1" group.long 0x7C++0x3 line.long 0x00 "H3A_ADVANCED,Normal and Advanced AF stats collection mode" hexmask.long.tbyte 0x00 15.--31. 1. " ID ,- ." bitfld.long 0x00 0. " AF_MODE ,AF engine mode. - . - ." "Normal_Mode,1" tree.end tree "ISS_IPIPE" base ad:0x52010800 width 21. group.long 0x0++0x3 line.long 0x00 "IPIPE_SRC_EN,This register is not shadowed" bitfld.long 0x00 0. " EN ,The start flag of the IPIPE module. When EN is 1, the IPIPE module starts a processing from the next rising edge of the VD. If the processing mode of the IPIPE module is one shot, the EN is cleared to 0 immediately after the processing has s.." "newEnum1,newEnum2" group.long 0x4++0x3 line.long 0x00 "IPIPE_SRC_MODE," bitfld.long 0x00 1. " WRT ,The mode selection of the ipipeif_wrt which is an input port of the IPIPE module. If WRT is 0, the IPIPE module does not use the ipipeif_wrt. Else the IPIPE module uses it. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " OST ,The processing mode selection of the IPIPE module. Value 0 indicates the mode of free run, value 1 indicates the mode of one shot. - . - ." "newEnum1,newEnum2" group.long 0x8++0x3 line.long 0x00 "IPIPE_SRC_FMT," bitfld.long 0x00 0.--1. " FMT ,IPIPE module data path selection - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" group.long 0xC++0x3 line.long 0x00 "IPIPE_SRC_COL," bitfld.long 0x00 6.--7. " OO ,The color pattern of the odd line and odd pixel. This parameter is valid when IPIPE_SRC[FMT] is 0,1,2. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 4.--5. " OE ,The color pattern of the odd line and even pixel. This parameter is valid when IPIPE_SRC[FMT] is 0,1,2. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 2.--3. " EO ,The color pattern of the even line and odd pixel. This parameter is valid when IPIPE_SRC[FMT] is 0,1,2. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" textline " " bitfld.long 0x00 0.--1. " EE ,The color pattern of the even line and even pixel. This parameter is valid when IPIPE_SRC[FMT] is 0,1,2. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" group.long 0x10++0x3 line.long 0x00 "IPIPE_SRC_VPS," hexmask.long.word 0x00 0.--15. 1. " VAL ,The vertical position of the global frame from the rising edge of the VD. The IPIPE module will start an image processing from VAL line." group.long 0x14++0x3 line.long 0x00 "IPIPE_SRC_VSZ," hexmask.long.word 0x00 0.--12. 1. " VAL ,The vertical size of the processing area. The VAL0 can not be written. The IPIPE module will process (VAL+1) lines." group.long 0x18++0x3 line.long 0x00 "IPIPE_SRC_HPS," hexmask.long.word 0x00 0.--15. 1. " VAL ,The horizontal position of the global frame from the rising edge of the HD. The IPIPE module will start an image processing from VAL clock." group.long 0x1C++0x3 line.long 0x00 "IPIPE_SRC_HSZ," hexmask.long.word 0x00 1.--12. 1. " VAL ,The horizontal size of the processing area. The VAL0 is fixed. The IPIPE module processes (VAL+1) clocks." bitfld.long 0x00 0. " VAL_0 ,This is the LSB of the VAL[12:0]. This bit is read only." "0,1" group.long 0x20++0x3 line.long 0x00 "IPIPE_SEL_SBU," bitfld.long 0x00 0. " EDOF ,EDOF port selection This bit must not be enabled since the EDOF module is not implemented. This is a provision for a future revision of the IP. - . - ." "newEnum1,newEnum2" rgroup.long 0x24++0x3 line.long 0x00 "IPIPE_SRC_STA,IPIPE STATUS REGISTER" bitfld.long 0x00 4. " VAL4 ,Status of Histogram Process (busy status)." "0,1" bitfld.long 0x00 3. " VAL3 ,Status of Histogram bank select." "0,1" bitfld.long 0x00 2. " VAL2 ,Status of BSC process (busy status)." "0,1" textline " " bitfld.long 0x00 1. " VAL1 ,Status of Boxcar process (busy status)." "0,1" bitfld.long 0x00 0. " VAL0 ,Status of Boxcar process (error status). This bit will be triggered when an overflow happens while transferring the boxcar data to memory. Instead of polling for this register, it is preferable to use the IPIPE_BOXCAR_OVF interru.." "0,1" group.long 0x28++0x3 line.long 0x00 "IPIPE_GCK_MMR," bitfld.long 0x00 0. " REG ,The on/off selection of the clk_arm_g0 which is used for some ARM register access. - . - ." "newEnum1,newEnum2" group.long 0x2C++0x3 line.long 0x00 "IPIPE_GCK_PIX,This register is not shadowed" bitfld.long 0x00 3. " G3 ,The on/off selection of the clk_pix_g3 which is use for the IPIPE processes of EE and 'CAR'. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " G2 ,The on/off selection of the clk_pix_g2 which is use for the IPIPE processes of CFA to '422', 'Histogram(YCbCr input)', and 'Boundary Signal Calculator'. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " G1 ,The on/off selection of the clk_pix_g1 which is used for the IPIPE processes of 'DefectCorrection' to 'WhiteBalance', and 'Histogram(RAW input)'. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 0. " G0 ,The on/off selection of the clk_pix_g0 which is used for the IPIPE processing of 'Boxcar'. - . - ." "newEnum1,newEnum2" group.long 0x34++0x3 line.long 0x00 "IPIPE_DPC_LUT_EN," bitfld.long 0x00 0. " EN ,Enable of LUT defect pixel correction. - . - ." "newEnum1,newEnum2" group.long 0x38++0x3 line.long 0x00 "IPIPE_DPC_LUT_SEL," bitfld.long 0x00 1. " TBL ,LUT table type selection. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " DOT ,Replace dot selection on processing method 0. - . - ." "newEnum1,newEnum2" group.long 0x3C++0x3 line.long 0x00 "IPIPE_DPC_LUT_ADR," hexmask.long.word 0x00 0.--9. 1. " ADR ,The address of the first valid data in look-up-table" group.long 0x40++0x3 line.long 0x00 "IPIPE_DPC_LUT_SIZ," hexmask.long.word 0x00 0.--9. 1. " SIZ ,The number of valid data in look-up-table. (SIZ+1)" group.long 0x90++0x3 line.long 0x00 "IPIPE_LSC_VOFT,LSC VOFT" hexmask.long.word 0x00 0.--12. 1. " LSC_VOFT ," group.long 0x94++0x3 line.long 0x00 "IPIPE_LSC_VA2," hexmask.long.word 0x00 0.--12. 1. " VAL ,LSC VA2" group.long 0x98++0x3 line.long 0x00 "IPIPE_LSC_VA1," hexmask.long.word 0x00 0.--12. 1. " VAL ,LSC VA1" group.long 0x9C++0x3 line.long 0x00 "IPIPE_LSC_VS," bitfld.long 0x00 4.--7. " VS2 ,LSC VS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " VS1 ,LSC VS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x3 line.long 0x00 "IPIPE_LSC_HOFT," hexmask.long.word 0x00 0.--12. 1. " VAL ,LSC HOFT" group.long 0xA4++0x3 line.long 0x00 "IPIPE_LSC_HA2," hexmask.long.word 0x00 0.--12. 1. " VAL ,LSC HA2" group.long 0xA8++0x3 line.long 0x00 "IPIPE_LSC_HA1," hexmask.long.word 0x00 0.--12. 1. " VAL ,LSC HA1" group.long 0xAC++0x3 line.long 0x00 "IPIPE_LSC_HS," bitfld.long 0x00 4.--7. " HS2 ,LSC HS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HS1 ,LSC HS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x3 line.long 0x00 "IPIPE_LSC_GAN_R," hexmask.long.byte 0x00 0.--7. 1. " VAL ,GAN R" group.long 0xB4++0x3 line.long 0x00 "IPIPE_LSC_GAN_GR," hexmask.long.byte 0x00 0.--7. 1. " VAL ,GAN GR" group.long 0xB8++0x3 line.long 0x00 "IPIPE_LSC_GAN_GB," hexmask.long.byte 0x00 0.--7. 1. " VAL ,GAN GB" group.long 0xBC++0x3 line.long 0x00 "IPIPE_LSC_GAN_B," hexmask.long.byte 0x00 0.--7. 1. " VAL ,GAN B" group.long 0xC0++0x3 line.long 0x00 "IPIPE_LSC_OFT_R," hexmask.long.byte 0x00 0.--7. 1. " VAL ,LSC OFT R" group.long 0xC4++0x3 line.long 0x00 "IPIPE_LSC_OFT_GR," hexmask.long.byte 0x00 0.--7. 1. " VAL ,LSC OFT GR" group.long 0xC8++0x3 line.long 0x00 "IPIPE_LSC_OFT_GB," hexmask.long.byte 0x00 0.--7. 1. " VAL ,LSC OFT GB" group.long 0xCC++0x3 line.long 0x00 "IPIPE_LSC_OFT_B," hexmask.long.byte 0x00 0.--7. 1. " VAL ,LSC OFT B" group.long 0xD0++0x3 line.long 0x00 "IPIPE_LSC_SHF," bitfld.long 0x00 0.--3. " VAL ,LSC SHV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD4++0x3 line.long 0x00 "IPIPE_LSC_MAX," hexmask.long.word 0x00 0.--8. 1. " VAL ,LSC MAX" group.long 0x1D0++0x3 line.long 0x00 "IPIPE_WB2_OFT_R,White Balance Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,Offset before white balance (S12) -2048 to +2047" group.long 0x1D4++0x3 line.long 0x00 "IPIPE_WB2_OFT_GR,White Balance Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,Offset before white balance (S12) -2048 to +2047" group.long 0x1D8++0x3 line.long 0x00 "IPIPE_WB2_OFT_GB,White Balance Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,Offset before white balance (S12) -2048 to +2047" group.long 0x1DC++0x3 line.long 0x00 "IPIPE_WB2_OFT_B,White Balance Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,Offset before white balance (S12) -2048 to +2047" group.long 0x1E0++0x3 line.long 0x00 "IPIPE_WB2_WGN_R,White Balance Register" hexmask.long.word 0x00 0.--12. 1. " VAL ,White balance gain for R in U4.9 format 0 to +15.998" group.long 0x1E4++0x3 line.long 0x00 "IPIPE_WB2_WGN_GR,White Balance Register" hexmask.long.word 0x00 0.--12. 1. " VAL ,White balance gain for Gr in U4.9 format 0 to +15.998" group.long 0x1E8++0x3 line.long 0x00 "IPIPE_WB2_WGN_GB,White Balance Register" hexmask.long.word 0x00 0.--12. 1. " VAL ,White balance gain for Gb in U4.9 format 0 to +15.998" group.long 0x1EC++0x3 line.long 0x00 "IPIPE_WB2_WGN_B,White Balance Register" hexmask.long.word 0x00 0.--12. 1. " VAL ,White balance gain for B in U4.9 format 0 to +15.998" group.long 0x22C++0x3 line.long 0x00 "IPIPE_RGB1_MUL_RR,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient. 011111111111 = 2047/256 = 7.99609375 011111111110 = 2046/256 [...] 000011111111 = 255/256 000100000000 = 256/256 = 1 000100000001 = 257/256 [...] 000000000001 = 1/256 000000000000 = 0/256 = 0 111111111111 = -1/256 = -.." group.long 0x230++0x3 line.long 0x00 "IPIPE_RGB1_MUL_GR,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x234++0x3 line.long 0x00 "IPIPE_RGB1_MUL_BR,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x238++0x3 line.long 0x00 "IPIPE_RGB1_MUL_RG,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x23C++0x3 line.long 0x00 "IPIPE_RGB1_MUL_GG,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x240++0x3 line.long 0x00 "IPIPE_RGB1_MUL_BG,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x244++0x3 line.long 0x00 "IPIPE_RGB1_MUL_RB,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x248++0x3 line.long 0x00 "IPIPE_RGB1_MUL_GB,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x24C++0x3 line.long 0x00 "IPIPE_RGB1_MUL_BB,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x250++0x3 line.long 0x00 "IPIPE_RGB1_OFT_OR,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--12. 1. " VAL ,The output offset value for R. (s13) -4096 to +4095" group.long 0x254++0x3 line.long 0x00 "IPIPE_RGB1_OFT_OG,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--12. 1. " VAL ,The output offset value for G. (s13) -4096 to +4095" group.long 0x258++0x3 line.long 0x00 "IPIPE_RGB1_OFT_OB,RGB to RGB Conversion Register" hexmask.long.word 0x00 0.--12. 1. " VAL ,The output offset value for B. (s13) -4096 to +4095" group.long 0x25C++0x3 line.long 0x00 "IPIPE_GMM_CFG,RGB to RGB Conversion Register" bitfld.long 0x00 5.--6. " SIZ ,The size of the gamma table. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 4. " TBL ,Selection of Gamma table. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " BYPB ,Gamma correction mode for B - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 1. " BYPG ,Gamma correction mode for G - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " BYPR ,Gamma correction mode for R - . - ." "newEnum1,newEnum2" group.long 0x260++0x3 line.long 0x00 "IPIPE_RGB2_MUL_RR,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The matrix coefficient. 011111111111 = 2047/256 = 7.99609375 011111111110 = 2046/256 000011111111 = 255/256 000100000000 = 256/256 = 1 000100000001 = 257/256 000000000001 = 1/256 000000000000 = 0/256 = 0 111111111111 = -1/256 = -0.00390625 1.." group.long 0x264++0x3 line.long 0x00 "IPIPE_RGB2_MUL_GR,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The matrix coefficient." group.long 0x268++0x3 line.long 0x00 "IPIPE_RGB2_MUL_BR,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The matrix coefficient." group.long 0x26C++0x3 line.long 0x00 "IPIPE_RGB2_MUL_RG,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The matrix coefficient." group.long 0x270++0x3 line.long 0x00 "IPIPE_RGB2_MUL_GG,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The matrix coefficient." group.long 0x274++0x3 line.long 0x00 "IPIPE_RGB2_MUL_BG,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The matrix coefficient." group.long 0x278++0x3 line.long 0x00 "IPIPE_RGB2_MUL_RB,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The matrix coefficient." group.long 0x27C++0x3 line.long 0x00 "IPIPE_RGB2_MUL_GB,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The matrix coefficient." group.long 0x280++0x3 line.long 0x00 "IPIPE_RGB2_MUL_BB,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The matrix coefficient." group.long 0x284++0x3 line.long 0x00 "IPIPE_RGB2_OFT_OR,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The output offset value for R S10 number: -1024 to + 1023" group.long 0x288++0x3 line.long 0x00 "IPIPE_RGB2_OFT_OG,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The output offset value for G S10 number: -1024 to + 1023" group.long 0x28C++0x3 line.long 0x00 "IPIPE_RGB2_OFT_OB,RGB to RGB conversion after gamma" hexmask.long.word 0x00 0.--10. 1. " VAL ,The output offset value for B S10 number: -1024 to + 1023" group.long 0x294++0x3 line.long 0x00 "IPIPE_YUV_ADJ,RGB to YUV Conversion Register" hexmask.long.byte 0x00 8.--15. 1. " BRT ,The offset value for brightness control." hexmask.long.byte 0x00 0.--7. 1. " CRT ,The multiplier coefficient value for contrast control. 00000000 = 0/16 = 0 00000001 = 1/16 00001111 = 15/16 00010000 = 16/16 = 1 00010001 = 17/16 11111110 = 254/16 11111111 = 255/16 = 15.9375" group.long 0x298++0x3 line.long 0x00 "IPIPE_YUV_MUL_RY,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,Matrix Coefficient for RY (S4.8 = -8 - +7.996)" group.long 0x29C++0x3 line.long 0x00 "IPIPE_YUV_MUL_GY,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,Matrix Coefficient for GY (S4.8 = -8 - +7.996)" group.long 0x2A0++0x3 line.long 0x00 "IPIPE_YUV_MUL_BY,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,Matrix Coefficient for BY (S4.8 = -8 - +7.996)" group.long 0x2A4++0x3 line.long 0x00 "IPIPE_YUV_MUL_RCB,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x2A8++0x3 line.long 0x00 "IPIPE_YUV_MUL_GCB,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x2AC++0x3 line.long 0x00 "IPIPE_YUV_MUL_BCB,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x2B0++0x3 line.long 0x00 "IPIPE_YUV_MUL_RCR,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x2B4++0x3 line.long 0x00 "IPIPE_YUV_MUL_GCR,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x2B8++0x3 line.long 0x00 "IPIPE_YUV_MUL_BCR,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,The matrix coefficient." group.long 0x2BC++0x3 line.long 0x00 "IPIPE_YUV_OFT_Y,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--10. 1. " VAL ,The output offset value for Y" group.long 0x2C0++0x3 line.long 0x00 "IPIPE_YUV_OFT_CB,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--10. 1. " VAL ,The output offset value for Cb For Cb/Cr, set (0x80 + offset value) here. (0x80 for zero offset.)" group.long 0x2C4++0x3 line.long 0x00 "IPIPE_YUV_OFT_CR,RGB to YUV Conversion Register" hexmask.long.word 0x00 0.--10. 1. " VAL ,The output offset value for Cr For Cb/Cr, set (0x80 + offset value) here. (0x80 for zero offset.)" group.long 0x2C8++0x3 line.long 0x00 "IPIPE_YUV_PHS,YUV4:2:2 down sampling register. This register controls the YUV4:4:4 to YUV4:2:2 chroma downsampling. This register is valid if .FMT = 0 (RAW input and YUV output). = 0 leads to pure subsampling, no filtering, cosited chroma output. = 1 l.." bitfld.long 0x00 1. " LPF ,121-LPF enable for chrominance samples. This register is valid if IPIPE_SRC_FMT.FMT = 0 (RAW input and YUV output). - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " POS ,This bit sets the output position of the chrominance sample with regards to the luma sample positions. One can choose between centered and cosited. This register is valid if IPIPE_SRC_FMT.FMT = 0 (RAW input and YUV output). The RESIZER .." "newEnum1,newEnum2" group.long 0x2D4++0x3 line.long 0x00 "IPIPE_YEE_EN,Edge Enhancer Register" bitfld.long 0x00 0. " EN ,The on/off selection of the Edge enhancer. - . - ." "newEnum1,newEnum2" group.long 0x2D8++0x3 line.long 0x00 "IPIPE_YEE_TYP,Edge Enhancer Register" bitfld.long 0x00 1. " HAL ,Halo reduction in Edge Sharpener module" "0,1" bitfld.long 0x00 0. " SEL ,Merging method between Edge Enhancer and Edge Sharpener - . - ." "newEnum1,newEnum2" group.long 0x2DC++0x3 line.long 0x00 "IPIPE_YEE_SHF,Edge Enhancer Register" bitfld.long 0x00 0.--3. " SHF ,Down shift length of high pass filter (HPF) in edge enhancer." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2E0++0x3 line.long 0x00 "IPIPE_YEE_MUL_00,Edge Enhancer Register" hexmask.long.word 0x00 0.--9. 1. " VAL ,Multiplier coefficient in HPF. 0111111111 = 511 0111111110 = 510 0000000001 = 1 0000000000 = 0 1111111111 = -1 1000000001 = -511 1000000000 = -512" group.long 0x2E4++0x3 line.long 0x00 "IPIPE_YEE_MUL_01,Edge Enhancer Register" hexmask.long.word 0x00 0.--9. 1. " VAL ,Multiplier coefficient in HPF." group.long 0x2E8++0x3 line.long 0x00 "IPIPE_YEE_MUL_02,Edge Enhancer Register" hexmask.long.word 0x00 0.--9. 1. " VAL ,Multiplier coefficient in HPF." group.long 0x2EC++0x3 line.long 0x00 "IPIPE_YEE_MUL_10,Edge Enhancer Register" hexmask.long.word 0x00 0.--9. 1. " VAL ,Multiplier coefficient in HPF." group.long 0x2F0++0x3 line.long 0x00 "IPIPE_YEE_MUL_11,Edge Enhancer Register" hexmask.long.word 0x00 0.--9. 1. " VAL ,Multiplier coefficient in HPF." group.long 0x2F4++0x3 line.long 0x00 "IPIPE_YEE_MUL_12,Edge Enhancer Register" hexmask.long.word 0x00 0.--9. 1. " VAL ,Multiplier coefficient in HPF." group.long 0x2F8++0x3 line.long 0x00 "IPIPE_YEE_MUL_20,Edge Enhancer Register" hexmask.long.word 0x00 0.--9. 1. " VAL ,Multiplier coefficient in HPF." group.long 0x2FC++0x3 line.long 0x00 "IPIPE_YEE_MUL_21,Edge Enhancer Register" hexmask.long.word 0x00 0.--9. 1. " VAL ,Multiplier coefficient in HPF." group.long 0x300++0x3 line.long 0x00 "IPIPE_YEE_MUL_22,Edge Enhancer Register" hexmask.long.word 0x00 0.--9. 1. " VAL ,Multiplier coefficient in HPF." group.long 0x304++0x3 line.long 0x00 "IPIPE_YEE_THR,Edge Enhancer Register" bitfld.long 0x00 0.--5. " VAL ,Edge Enhancer lower threshold before referring to LUT. If HPF &lt;IPIPE_YEE_THR -&gt; output is HPF + IPIPE_YEE_THR If HPF &gt; IPIPE_YEE_THR -&gt; output is HPF - IPIPE_YEE_THR Otherwise, output is zero." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x308++0x3 line.long 0x00 "IPIPE_YEE_E_GAN,Edge Enhancer Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,Edge sharpener gain" group.long 0x30C++0x3 line.long 0x00 "IPIPE_YEE_E_THR_1,Edge Enhancer Register" hexmask.long.word 0x00 0.--11. 1. " VAL ,Edge sharpener HPF value lower limit" group.long 0x310++0x3 line.long 0x00 "IPIPE_YEE_E_THR_2,Edge Enhancer Register" bitfld.long 0x00 0.--5. " VAL ,Edge sharpener HPF value upper limit (after 6 bit right shift)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x314++0x3 line.long 0x00 "IPIPE_YEE_G_GAN,Edge Enhancer Register" hexmask.long.byte 0x00 0.--7. 1. " VAL ,Edge sharpener, gain value on gradient" group.long 0x318++0x3 line.long 0x00 "IPIPE_YEE_G_OFT,Edge Enhancer Register" bitfld.long 0x00 0.--5. " VAL ,Edge sharpener, offset value on gradient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x380++0x3 line.long 0x00 "IPIPE_BOX_EN,Boxcar Register" bitfld.long 0x00 0. " EN ,This bit enables or disables the BOXCAR functionality. The BOXCAR output is written to SDRAM. One need to set the IPIPE_BOX_SDR_SAD_H and IPIPE_BOX_SDR_SAD_L registers with the appropriate address. - . - ." "newEnum1,newEnum2" group.long 0x384++0x3 line.long 0x00 "IPIPE_BOX_MODE,Boxcar Register" bitfld.long 0x00 0. " OST ,The processing mode selection of the Boxcar function. A 0 indicates the mode of the free run, a 1 indicates the mode of the one shot. - . - ." "newEnum1,newEnum2" group.long 0x388++0x3 line.long 0x00 "IPIPE_BOX_TYP,Boxcar Register" bitfld.long 0x00 0. " SEL ,Block size in boxcar sampling - . - ." "newEnum1,newEnum2" group.long 0x38C++0x3 line.long 0x00 "IPIPE_BOX_SHF,Boxcar Register" bitfld.long 0x00 0.--2. " VAL ,The down shift value applied to the boxcar computation result. R out = SUM (Rij) &gt;&gt; SHF G out = (SUM (Gr ij)/2 + SUM (Gr ij)/2) &gt;&gt; SHF B out = SUM (Gij) &gt;&gt; SHF" "0,1,2,3,4,5,6,7" group.long 0x390++0x3 line.long 0x00 "IPIPE_BOX_SDR_SAD_H,Boxcar Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,The higher 11 bits of the first address of output in memory." group.long 0x394++0x3 line.long 0x00 "IPIPE_BOX_SDR_SAD_L,Boxcar Register" hexmask.long.word 0x00 5.--15. 1. " VAL ,The lower 16 bits of the first address of output in memory." bitfld.long 0x00 0.--4. " VAL_RESERVED ,Ensures 32-byte alignment." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x39C++0x3 line.long 0x00 "IPIPE_HST_EN,Histogram" bitfld.long 0x00 0. " EN ,This bit enables or disables the HISTOGRAM functionality. When enabled, the HISTOGRAM computation will start the processing from the next rising edge of the VD pulse. If the processing mode of the HISTOGRAM is one shot, the enable bit will b.." "newEnum1,newEnum2" group.long 0x3A0++0x3 line.long 0x00 "IPIPE_HST_MODE,Histogram" bitfld.long 0x00 0. " OST ,The processing mode selection of the Histogram module. A 0 indicates the mode of the free run, a 1 indicates the mode of the one shot. - . - ." "newEnum1,newEnum2" group.long 0x3A4++0x3 line.long 0x00 "IPIPE_HST_SEL,Histogram" bitfld.long 0x00 2. " SEL ,Input selection. When SEL0=0, RGBY are sampled from the output of the line buffer in noise filter-2. When SEL0=1, YCbCr are sampled at the output of RGB2YCbCr module. Y is sampled twice. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0.--1. " TYP ,G selection in Bayer mode (SEL0=0) - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" group.long 0x3A8++0x3 line.long 0x00 "IPIPE_HST_PARA,Histogram COL0, COL1, COL2, and COL3 should be set to 1." bitfld.long 0x00 12.--13. " BIN ,The number of the bins. - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 8.--11. " SHF ,The shift length of the input data. data = (INPUT &gt;&gt; SHF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " COL3 ,The on/off selection of the color pattern 3 (Y). - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 6. " COL2 ,The on/off selection of the color pattern 2 (B). - . - ." "newEnum1,newEnum2" bitfld.long 0x00 5. " COL1 ,The on/off selection of the color pattern 1 (G). - . - ." "newEnum1,newEnum2" bitfld.long 0x00 4. " COL0 ,The on/off selection of the color pattern 0 (R). - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 3. " RGN3 ,The on/off selection of the region 3. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " RGN2 ,The on/off selection of the region 2. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " RGN1 ,The on/off selection of the region 1. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 0. " RGN0 ,The on/off selection of the region 0. - . - ." "newEnum1,newEnum2" group.long 0x3AC++0x3 line.long 0x00 "IPIPE_HST_0_VPS,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 0 will start the Histogram processing from VAL line. VAL[0] can not be written." bitfld.long 0x00 0. " VAL_RESERVED ,The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 0 will start the Histogram processing from VAL line. VAL[0] can not be written." "0,1" group.long 0x3B0++0x3 line.long 0x00 "IPIPE_HST_0_VSZ,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The vertical size of the region 0. The Histogram processing of the region 0 will process (VAL+1) lines." bitfld.long 0x00 0. " VAL_RESERVED ,The vertical size of the region 0. The Histogram processing of the region 0 will process (VAL+1) lines. VAL[0] cannot be written." "0,1" group.long 0x3B4++0x3 line.long 0x00 "IPIPE_HST_0_HPS,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 0 will start the Histogram processing from VAL clocks. VAL[0] can not be written." bitfld.long 0x00 0. " VAL_RESERVED ,The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 0 will start the Histogram processing from VAL clocks. VAL[0] can not be written." "0,1" group.long 0x3B8++0x3 line.long 0x00 "IPIPE_HST_0_HSZ,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The horizontal size of the region 0. The Histogram processing of the region 0 will process (VAL+1) clocks. VAL[0] cannot be written." bitfld.long 0x00 0. " VAL_RESERVED ,The horizontal size of the region 0. The Histogram processing of the region 0 will process (VAL+1) clocks. VAL[0] cannot be written." "0,1" group.long 0x3BC++0x3 line.long 0x00 "IPIPE_HST_1_VPS,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 1 will start the Histogram processing from VAL line. VAL[0] can not be written." bitfld.long 0x00 0. " VAL_RESERVED ,The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 1 will start the Histogram processing from VAL line. VAL[0] can not be written." "0,1" group.long 0x3C0++0x3 line.long 0x00 "IPIPE_HST_1_VSZ,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The vertical size of the region 1. The Histogram processing of the region 1 will process (VAL+1) lines. VAL[0] cannot be written." bitfld.long 0x00 0. " VAL_RESERVED ,The vertical size of the region 1. The Histogram processing of the region 1 will process (VAL+1) lines. VAL[0] cannot be written." "0,1" group.long 0x3C4++0x3 line.long 0x00 "IPIPE_HST_1_HPS,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 1 will start the Histogram processing from VAL clocks. VAL[0] can not be written." bitfld.long 0x00 0. " VAL_RESERVED ,The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 1 will start the Histogram processing from VAL clocks. VAL[0] can not be written." "0,1" group.long 0x3C8++0x3 line.long 0x00 "IPIPE_HST_1_HSZ,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The horizontal size of the region 1. The Histogram processing of the region 1 will process (VAL+1) clocks. VAL[0] cannot be written." bitfld.long 0x00 0. " VAL_RESERVED ,The horizontal size of the region 1. The Histogram processing of the region 1 will process (VAL+1) clocks. VAL[0] cannot be written." "0,1" group.long 0x3CC++0x3 line.long 0x00 "IPIPE_HST_2_VPS,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 2 will start the Histogram processing from VAL line. VAL[0] can not be written." bitfld.long 0x00 0. " VAL_RESERVED ,The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 2 will start the Histogram processing from VAL line. VAL[0] can not be written." "0,1" group.long 0x3D0++0x3 line.long 0x00 "IPIPE_HST_2_VSZ,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The vertical size of the region 2. The Histogram processing of the region 2 will process (VAL+1) lines. VAL[0] cannot be written." bitfld.long 0x00 0. " VAL_RESERVED ,The vertical size of the region 2. The Histogram processing of the region 2 will process (VAL+1) lines. VAL[0] cannot be written." "0,1" group.long 0x3D4++0x3 line.long 0x00 "IPIPE_HST_2_HPS,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 2 will start the Histogram processing from VAL clocks. VAL[0] can not be written." bitfld.long 0x00 0. " VAL_RESERVED ,The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 2 will start the Histogram processing from VAL clocks. VAL[0] can not be written." "0,1" group.long 0x3D8++0x3 line.long 0x00 "IPIPE_HST_2_HSZ,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The horizontal size of the region 2. The Histogram processing of the region 2 will process (VAL+1) clocks. VAL[0] cannot be written." bitfld.long 0x00 0. " VAL_RESERVED ,The horizontal size of the region 2. The Histogram processing of the region 2 will process (VAL+1) clocks. VAL[0] cannot be written." "0,1" group.long 0x3DC++0x3 line.long 0x00 "IPIPE_HST_3_VPS,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 3 will start the Histogram processing from VAL line. VAL[0] can not be written." bitfld.long 0x00 0. " VAL_RESERVED ,The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 3 will start the Histogram processing from VAL line. VAL[0] can not be written." "0,1" group.long 0x3E0++0x3 line.long 0x00 "IPIPE_HST_3_VSZ,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The vertical size of the region 3. The Histogram processing of the region 3 will process (VAL+1) lines. VAL[0] cannot be written." bitfld.long 0x00 0. " VAL_RESERVED ,The vertical size of the region 3. The Histogram processing of the region 3 will process (VAL+1) lines. VAL[0] cannot be written." "0,1" group.long 0x3E4++0x3 line.long 0x00 "IPIPE_HST_3_HPS,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 3 will start the Histogram processing from VAL clocks. VAL[0] can not be written." bitfld.long 0x00 0. " VAL_RESERVED ,The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 3 will start the Histogram processing from VAL clocks. VAL[0] can not be written." "0,1" group.long 0x3E8++0x3 line.long 0x00 "IPIPE_HST_3_HSZ,Histogram" hexmask.long.word 0x00 1.--12. 1. " VAL ,The horizontal size of the region 3. The Histogram processing of the region 3 will process (VAL+1) clocks. VAL[0] cannot be written." bitfld.long 0x00 0. " VAL_RESERVED ,The horizontal size of the region 3. The Histogram processing of the region 3 will process (VAL+1) clocks. VAL[0] cannot be written." "0,1" group.long 0x3EC++0x3 line.long 0x00 "IPIPE_HST_TBL,Histogram" bitfld.long 0x00 1. " CLR ,Histogram memory clear. The histogram can be cleared before the start of operations. However, the clear takes 512 cycles and therefore: + if line size &gt; 512, the first line must not be used for histogram computation. + if line size &a.." "newEnum1,newEnum2" bitfld.long 0x00 0. " SEL ,This bit must be used to select which memory is used to store the histogram data. By selecting alternatively one or the other bit, one can double buffer the histogram output buffer. The 4 KB memory can either be read by the CPU or a DMA.." "newEnum1,newEnum2" group.long 0x3F0++0x3 line.long 0x00 "IPIPE_HST_MUL_R,Histogram" hexmask.long.byte 0x00 0.--7. 1. " GAIN ,Gain" group.long 0x3F4++0x3 line.long 0x00 "IPIPE_HST_MUL_GR,Histogram" hexmask.long.byte 0x00 0.--7. 1. " GAIN ,Gain" group.long 0x3F8++0x3 line.long 0x00 "IPIPE_HST_MUL_GB,Histogram" hexmask.long.byte 0x00 0.--7. 1. " GAIN ,Gain" group.long 0x3FC++0x3 line.long 0x00 "IPIPE_HST_MUL_B,Histogram" hexmask.long.byte 0x00 0.--7. 1. " GAIN ,Gain" tree.end tree "ISS_ISP5_SYS1" base ad:0x52010000 tree "IRQ_Line_0" width 24. group.long 0x30++0x3 line.long 0x00 "ISP5_IRQENABLE_CLR_i_0,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be merged on the fo.." eventfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additio.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the .." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 18. " RSZ_FIFO_OVF ,RESIZER module event: This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface.. This event would typically happen because the video port pixel clock is too high. - . - . - . - ..." "No_action,Disable_interrupt" eventfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. U.." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 15. " RSZ_INT_DMA ,RESIZER module event: This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for t.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 14. " RSZ_INT_LAST_PIX ,RESIZER module event: This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " RSZ_INT_REG ,RESIZER module event: This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 3. " ISIF_INT_3 ,Set this bit to disable the LSC interrupt issued by the 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Set this bit to disable the interrupt mapped to the INT_2 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Set this bit to disable the interrupt mapped to the INT_1 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see.." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Set this bit to disable the interrupt mapped to the INT_0 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see, -.." "noaction_/_disabled,disable_/_enabled" group.long 0x2C++0x3 line.long 0x00 "ISP5_IRQENABLE_SET_i_0,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be merged on the four .." bitfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additio.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the .." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware .." "No_action,Enable_interrupt" bitfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. U.." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 3. " ISIF_INT_3 ,LSC interrupt issued by the 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Set this bit to enable the interrupt and map it to the INT_2 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, .." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Set this bit to enable the interrupt and map it to the INT_1 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, .." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Set this bit to enable the interrupt mapped to INT_0 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see, - . - .." "noaction_/_disabled,enable_/_enabled" group.long 0x24++0x3 line.long 0x00 "ISP5_IRQSTATUS_RAW_i_0,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be m.." bitfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additi.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the.." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware must take care to use a lower p.." "No_action,Set_event_(debug)" bitfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. .." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 3. " ISIF_INT_3 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 2. " ISIF_INT_2 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 1. " ISIF_INT_1 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 0. " ISIF_INT_0 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x28++0x3 line.long 0x00 "ISP5_IRQSTATUS_i_0,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). The ISP outputs fo.." eventfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additi.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the.." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware .." "No_action,Clear_(raw)_event" eventfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. .." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 3. " ISIF_INT_3 ,LSC interrupt issued by 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Read this bit to check the interrupt mapped to the INT_2 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Read this bit to check the interrupt mapped to the INT_1 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information.." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Read this bit to check the interrupt mapped to the INT_0 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, se.." "noaction_/_noevent,clear_/_pending" tree.end tree "IRQ_Line_1" width 24. group.long 0x40++0x3 line.long 0x00 "ISP5_IRQENABLE_CLR_i_1,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be merged on the fo.." eventfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additio.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the .." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 18. " RSZ_FIFO_OVF ,RESIZER module event: This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface.. This event would typically happen because the video port pixel clock is too high. - . - . - . - ..." "No_action,Disable_interrupt" eventfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. U.." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 15. " RSZ_INT_DMA ,RESIZER module event: This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for t.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 14. " RSZ_INT_LAST_PIX ,RESIZER module event: This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " RSZ_INT_REG ,RESIZER module event: This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 3. " ISIF_INT_3 ,Set this bit to disable the LSC interrupt issued by the 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Set this bit to disable the interrupt mapped to the INT_2 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Set this bit to disable the interrupt mapped to the INT_1 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see.." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Set this bit to disable the interrupt mapped to the INT_0 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see, -.." "noaction_/_disabled,disable_/_enabled" group.long 0x3C++0x3 line.long 0x00 "ISP5_IRQENABLE_SET_i_1,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be merged on the four .." bitfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additio.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the .." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware .." "No_action,Enable_interrupt" bitfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. U.." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 3. " ISIF_INT_3 ,LSC interrupt issued by the 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Set this bit to enable the interrupt and map it to the INT_2 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, .." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Set this bit to enable the interrupt and map it to the INT_1 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, .." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Set this bit to enable the interrupt mapped to INT_0 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see, - . - .." "noaction_/_disabled,enable_/_enabled" group.long 0x34++0x3 line.long 0x00 "ISP5_IRQSTATUS_RAW_i_1,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be m.." bitfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additi.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the.." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware must take care to use a lower p.." "No_action,Set_event_(debug)" bitfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. .." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 3. " ISIF_INT_3 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 2. " ISIF_INT_2 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 1. " ISIF_INT_1 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 0. " ISIF_INT_0 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x38++0x3 line.long 0x00 "ISP5_IRQSTATUS_i_1,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). The ISP outputs fo.." eventfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additi.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the.." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware .." "No_action,Clear_(raw)_event" eventfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. .." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 3. " ISIF_INT_3 ,LSC interrupt issued by 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Read this bit to check the interrupt mapped to the INT_2 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Read this bit to check the interrupt mapped to the INT_1 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information.." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Read this bit to check the interrupt mapped to the INT_0 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, se.." "noaction_/_noevent,clear_/_pending" tree.end tree "IRQ_Line_2" width 24. group.long 0x50++0x3 line.long 0x00 "ISP5_IRQENABLE_CLR_i_2,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be merged on the fo.." eventfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additio.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the .." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 18. " RSZ_FIFO_OVF ,RESIZER module event: This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface.. This event would typically happen because the video port pixel clock is too high. - . - . - . - ..." "No_action,Disable_interrupt" eventfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. U.." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 15. " RSZ_INT_DMA ,RESIZER module event: This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for t.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 14. " RSZ_INT_LAST_PIX ,RESIZER module event: This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " RSZ_INT_REG ,RESIZER module event: This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 3. " ISIF_INT_3 ,Set this bit to disable the LSC interrupt issued by the 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Set this bit to disable the interrupt mapped to the INT_2 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Set this bit to disable the interrupt mapped to the INT_1 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see.." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Set this bit to disable the interrupt mapped to the INT_0 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see, -.." "noaction_/_disabled,disable_/_enabled" group.long 0x4C++0x3 line.long 0x00 "ISP5_IRQENABLE_SET_i_2,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be merged on the four .." bitfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additio.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the .." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware .." "No_action,Enable_interrupt" bitfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. U.." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 3. " ISIF_INT_3 ,LSC interrupt issued by the 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Set this bit to enable the interrupt and map it to the INT_2 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, .." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Set this bit to enable the interrupt and map it to the INT_1 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, .." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Set this bit to enable the interrupt mapped to INT_0 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see, - . - .." "noaction_/_disabled,enable_/_enabled" group.long 0x44++0x3 line.long 0x00 "ISP5_IRQSTATUS_RAW_i_2,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be m.." bitfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additi.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the.." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware must take care to use a lower p.." "No_action,Set_event_(debug)" bitfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. .." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 3. " ISIF_INT_3 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 2. " ISIF_INT_2 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 1. " ISIF_INT_1 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 0. " ISIF_INT_0 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x48++0x3 line.long 0x00 "ISP5_IRQSTATUS_i_2,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). The ISP outputs fo.." eventfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additi.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the.." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware .." "No_action,Clear_(raw)_event" eventfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. .." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 3. " ISIF_INT_3 ,LSC interrupt issued by 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Read this bit to check the interrupt mapped to the INT_2 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Read this bit to check the interrupt mapped to the INT_1 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information.." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Read this bit to check the interrupt mapped to the INT_0 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, se.." "noaction_/_noevent,clear_/_pending" tree.end tree "IRQ_Line_3" width 24. group.long 0x60++0x3 line.long 0x00 "ISP5_IRQENABLE_CLR_i_3,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be merged on the fo.." eventfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_disabled,disable_/_enabled" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additio.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the .." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 18. " RSZ_FIFO_OVF ,RESIZER module event: This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface.. This event would typically happen because the video port pixel clock is too high. - . - . - . - ..." "No_action,Disable_interrupt" eventfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. U.." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 15. " RSZ_INT_DMA ,RESIZER module event: This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for t.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 14. " RSZ_INT_LAST_PIX ,RESIZER module event: This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 13. " RSZ_INT_REG ,RESIZER module event: This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 3. " ISIF_INT_3 ,Set this bit to disable the LSC interrupt issued by the 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Set this bit to disable the interrupt mapped to the INT_2 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see.." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Set this bit to disable the interrupt mapped to the INT_1 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see.." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Set this bit to disable the interrupt mapped to the INT_0 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see, -.." "noaction_/_disabled,disable_/_enabled" group.long 0x5C++0x3 line.long 0x00 "ISP5_IRQENABLE_SET_i_3,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be merged on the four .." bitfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additio.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the .." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware .." "No_action,Enable_interrupt" bitfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. U.." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 3. " ISIF_INT_3 ,LSC interrupt issued by the 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Set this bit to enable the interrupt and map it to the INT_2 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, .." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Set this bit to enable the interrupt and map it to the INT_1 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, .." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Set this bit to enable the interrupt mapped to INT_0 line. This interrupt is set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, see, - . - .." "noaction_/_disabled,enable_/_enabled" group.long 0x54++0x3 line.long 0x00 "ISP5_IRQSTATUS_RAW_i_3,Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. The ISP outputs four interrupt lines, ISP_IRQ0 to ISP_IRQ3. Any internal ISP event can be m.." bitfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additi.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the.." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware must take care to use a lower p.." "No_action,Set_event_(debug)" bitfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. .." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 3. " ISIF_INT_3 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 2. " ISIF_INT_2 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 1. " ISIF_INT_1 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 0. " ISIF_INT_0 ,- . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x58++0x3 line.long 0x00 "ISP5_IRQSTATUS_i_3,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). The ISP outputs fo.." eventfld.long 0x00 31. " OCP_ERR_IRQ ,An OCP error has been received on the ISP master port. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 29. " IPIPE_INT_DPC_RNEW1 ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 28. " IPIPE_INT_DPC_RNEW0 ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 27. " IPIPE_INT_DPC_INI ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 25. " IPIPE_INT_EOF ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 24. " H3A_INT_EOF ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 23. " RSZ_INT_EOF1 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer B engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additional.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 22. " RSZ_INT_EOF0 ,RESIZER module event: This event signals that the BL has received the EOF signal from the resizer A engine which happens one the last transfer in the frame has happened. Note that because the BL has FIFOs it may take some additi.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 19. " RSZ_FIFO_IN_BLK_ERR ,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the.." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 18. " RSZ_FIFO_OVF ,This event signals that overflow happened in the input data buffering submodule or in the RSZ output interface. This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware .." "No_action,Clear_(raw)_event" eventfld.long 0x00 17. " RSZ_INT_CYC_RZB ,RESIZER module event: This event is the circular interrupt for RESIZER #B. An event can be triggered every time that RSZ_IRQ_RZB output lines have been written out to the RZB_SDR_Y buffer. The range can go from 1 to 8192 lines..." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 16. " RSZ_INT_CYC_RZA ,RESIZER module event: This event is the circular interrupt for RESIZER #A. An event can be triggered every time that RSZ_IRQ_RZA output lines have been written out to the RZA_SDR_Y buffer. The range can go from 1 to 8192 lines. .." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 15. " RSZ_INT_DMA ,This event is triggered when the last EOF (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle. rsz_int_dma is a true indication that all processing is finished for the particular frame on.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 14. " RSZ_INT_LAST_PIX ,This event is triggered when the last pixel of the valid area is received. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 13. " RSZ_INT_REG ,This event is triggered when the first pixel of the valid area is received. Shadowed registers can be updated at any time but the new value will take effect on the next rsz_int_reg event. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 12. " H3A_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " AF_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 10. " AEW_INT ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 9. " IPIPEIF_IRQ ,IPIPEIF module interrupt - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 8. " IPIPE_INT_HST ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 7. " IPIPE_INT_BSC ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 6. " IPIPE_INT_DMA ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 5. " IPIPE_INT_LAST_PIX ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 4. " IPIPE_INT_REG ,- . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 3. " ISIF_INT_3 ,LSC interrupt issued by 2D-LSC block. Four types of 2D-LSC can be generated and mapped to the INT_3 line. For more information, see, - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 2. " ISIF_INT_2 ,VD interrupt 2 event. Read this bit to check the interrupt mapped to the INT_2 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information.." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 1. " ISIF_INT_1 ,VD interrupt 1 event. Read this bit to check the interrupt mapped to the INT_1 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information.." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 0. " ISIF_INT_0 ,VD interrupt 0 event. Read this bit to check the interrupt mapped to the INT_0 line. This interrupt is also set based on the VD pulse position after receiving a configured number of horizontal pulse signals. For more information, se.." "noaction_/_noevent,clear_/_pending" tree.end textline "" width 20. rgroup.long 0x0++0x3 line.long 0x00 "ISP5_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "ISP5_HWINFO1,GENERIC PARAMETER REGISTER Information about the hardware configuration of the IP module." hexmask.long.word 0x00 16.--28. 1. " ISIF_RFM_LINE_SIZE ,Memory line size for the data reformatter in the ISIF module." hexmask.long.word 0x00 0.--12. 1. " IPIPE_LINE_SIZE ,Memory line size for the IPIPE module" rgroup.long 0x8++0x3 line.long 0x00 "ISP5_HWINFO2,GENERIC PARAMETER REGISTER Information about the hardware configuration of the IP module." hexmask.long.word 0x00 0.--12. 1. " H3A_LINE_SIZE ,Memory line size for the H3A module" group.long 0x10++0x3 line.long 0x00 "ISP5_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. - . - . - . - ." "force,no,smart,?..." bitfld.long 0x00 1. " SOFTRESET ,Software reset. The soft reset will cause the MStandby to be asserted as the reset value of the ISP5_CTRL.MSTANDBY bit is 1. After a soft reset, the software must ensure not to perform any access for 16 clock cycles (OC.." bitfld.long 0x00 0. " AUTO_IDLE ,Auto clock gating. Always enabled." "0,1" group.long 0x64++0x3 line.long 0x00 "ISP5_DMAENABLE_SET,Per-line DMA enable bit vector Write 1 to set (enable DMA request generation). Readout equal to corresponding _CLR register." bitfld.long 0x00 4. " IPIPE_INT_DPC_RNEW1 ,Enable for ISP DMA request generation on line #2 This DMA request must be set to transfer the DPC data from memory to the IPIPE internal RAM. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 3. " IPIPE_INT_LAST_PIX ,Enable for ISP DMA request generation on line #3 This DMA request must be set to transfer the GAMMA data from memory to the IPIPE internal RAM or to initialize the DPC table. One must set the ISP5_CTRL.DMA3_CFG register before ena.." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 2. " IPIPE_INT_DPC_RNEW0 ,Enable for ISP DMA request generation on line #2 This DMA request must be set to transfer the DPC data from memory to the IPIPE internal RAM. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 1. " IPIPE_INT_HST ,Enable for ISP DMA request generation on line #1 This DMA request must be set to transfer the HIST data from the IPIPE internal RAM to memory. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " IPIPE_INT_BSC ,Enable for ISP DMA request generation on line #0 This DMA request must be set to transfer the BSC data from the IPIPE internal RAM to memory. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x68++0x3 line.long 0x00 "ISP5_DMAENABLE_CLR,Per-line DMA clear bit vector Write 1 to clear (disable DMA request generation). Readout equal to corresponding _SET register." eventfld.long 0x00 4. " IPIPE_INT_DPC_RNEW1 ,Clear for ISP DMA request generation on line ISS_DMA2. This DMA request must be set to transfer the DPC data from memory to the IPIPE internal RAM. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 3. " IPIPE_INT_LAST_PIX ,Clear for ISP DMA request generation on ISS_DMA3. This DMA request must be set to transfer the GAMMA data from memory to the IPIPE internal RAM. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 2. " IPIPE_INT_DPC_RNEW0 ,Clear for ISP DMA request generation on ISS_DMA2. This DMA request must be set to transfer the DPC data from memory to the IPIPE internal RAM. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 1. " IPIPE_INT_HST ,Clear for ISP DMA request generation on ISS_DMA1. This DMA request must be set to transfer the HIST data from the IPIPE internal RAM to memory. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " IPIPE_INT_BSC ,Clear for ISP DMA request generation on ISS_DMA0. This DMA request must be set to transfer the BSC data from the IPIPE internal RAM to memory. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x6C++0x3 line.long 0x00 "ISP5_CTRL,ISP5 CONTROL REGISTER" bitfld.long 0x00 30.--31. " DMA3_CFG ,This bit field selects the DMA transfer configuration which is used with the ISS_DMA3 DMA request signal. This DMA request is generated from IPIPE_INT_LAST_PIXEL event. One can choose to use this DMA request to transfer the DPC i.." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 26. " HST_RD_CHK ,When the HISTOGRAM computation is enabled and the HST DMA request is not used to read out the data, this register ensures that the data is read fast enough, else an interruptISP5_IRQSTATUS2_i[5] IPIPE_HST_ERR is trigger.." "0,?..." bitfld.long 0x00 25. " DPC_EVT_INI ,Select the IPIPE module event to be used to generate the DMA requests for the DPC submodule. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 24. " MSTANDBY ,MStandby signal assertion and de-assertion control for power management transitions. After software reset, this bit is asserted. Write '1' to transition from normal mode to idle mode. The firmware needs to ensure that no more ISP.." "newEnum1,newEnum2" bitfld.long 0x00 23. " VD_PULSE_EXT ,VD pulse extension enable This bit enables or disables the VD extension bridge. By default, the bridge is enabled. At ISS level, it is expected that ISP5_CTRL.VD_PULSE_EXT = 1 when the VPORT gets data from the CSI2 RX m.." "newEnum1,newEnum2" bitfld.long 0x00 22. " PCLK_INV ,Pixel clock inversion This bit enables or disables pixel clock inversion. The ISP always samples the data on the rising edge of the pixel clock. Enabling the inversion shifts the resampling period by 1/2 a pixel clock .." "newEnum1,newEnum2" textline " " bitfld.long 0x00 21. " MFLAG ,MFlag signal generation control This bit controls how the OCP MFlag signal is generated on the ISS NOC. 0x0: The MFlag value is dynamic. 0x1: The MFlag value is static. The value is set with the ISP5_CTRL[3:1] VBUSM_CPRIORITY." "0,1" bitfld.long 0x00 20. " MSTANDDBY_WAIT ,MStandby / Wait power management status bit. The power management framework of the ISP is based on the handshaking of the MStandby and Wait signals. The software is not supposed to write inside the ISP slave port.." "newEnum1,newEnum2" bitfld.long 0x00 15. " BL_CLK_ENABLE ,BL clock enable - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 14. " ISIF_CLK_ENABLE ,ISIF clock enable The ISP will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled. There must be at least three clock cycles between the time this bit is modified and the HD/VD pulse for .." "newEnum1,newEnum2" bitfld.long 0x00 13. " H3A_CLK_ENABLE ,H3A clock enable The ISP will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 12. " RSZ_CLK_ENABLE ,RESIZER clock enable The ISP will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 11. " IPIPE_CLK_ENABLE ,IPIPE clock enable The ISP will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 10. " IPIPEIF_CLK_ENABLE ,IPIPEIF clock enable The ISP will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 9. " SYNC_ENABLE ,PCLK Sync module enable. This bit may only be modified when the video port is not receiving data such as when data is read from the IPIPEIF module memory read port. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 8. " PSYNC_CLK_SEL ,PCLK Sync clock select. This bit selects the clock which is used to resynchronize the input pixel clock. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 4.--7. " VBUSM_CIDS ,BL MAX VBUSM CIDs The BL module supports up to 16 CIDs/tags. This bit field sets up the maximum number of CISs/tags that the BL can use. The actual number of CIDs/tags is setup by VBUSM_CIDS + 1. Tag number 0 to VBUSM_C.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--3. " VBUSM_CPRIORITY ,BL VBUSM priority setting - . - . - . - . - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4,newEnum5,newEnum6,newEnum7,newEnum8" textline " " bitfld.long 0x00 0. " OCP_WRNP ,ISP OCP master port non-posted write control. - . - ." "newEnum1,newEnum2" group.long 0x70++0x3 line.long 0x00 "ISP5_PG,PATTERN GENERATOR REGISTER" bitfld.long 0x00 4.--5. " SRC_SEL ,Input mux selection - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 3. " EN ,- . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " WEN ,- . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 1. " HDPOL ,- . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " VDPOL ,- . - ." "newEnum1,newEnum2" group.long 0x74++0x3 line.long 0x00 "ISP5_PG_PULSE_CTRL,PATTERN GENERATOR REGISTER" hexmask.long.word 0x00 16.--27. 1. " VDW ,Pattern generator VD width Width = VDW+1" hexmask.long.word 0x00 0.--12. 1. " HDW ,Pattern generator HD width Width = HDW+1" group.long 0x78++0x3 line.long 0x00 "ISP5_PG_FRAME_SIZE,PATTERN GENERATOR REGISTER" hexmask.long.word 0x00 16.--31. 1. " PPLN ,Pattern Generator: pixels per line, PPLN+1" hexmask.long.word 0x00 0.--15. 1. " HLPFR ,Pattern Generator: half lines per frame, HLPFR+1" group.long 0x7C++0x3 line.long 0x00 "ISP5_MPSR,ISP memory access register. One need to pay attention when setting the bit fields in this register such that there is no conflict between the CPU and module accesses. Usually, the ISP modules must have access to the memories and it is only wh.." bitfld.long 0x00 24. " IPIPE_GAMMA_RGB_COPY ,GAMMA table RGB Copy This bit must be enable when one wants to use the same Gamma table for the R, G and B color components. When the CPU writes the R table, it is automatically copied to the G and B tables if this bit is set. - .." "newEnum1,newEnum2" bitfld.long 0x00 20. " IPIPE_BSC_TB1 ,IPIPE BSC TB1 memory access priority This memory is expected to be read by the CPU or the DMA to get BSC information during vertical blanking period. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 19. " IPIPE_BSC_TB0 ,IPIPE BSC TB0 memory access priority This memory is expected to be read by the CPU or the DMA to get BSC information during vertical blanking period. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 18. " IPIPE_HST_TB3 ,IPIPE histogram memory #3 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 17. " IPIPE_HST_TB2 ,IPIPE histogram memory #2 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 16. " IPIPE_HST_TB1 ,IPIPE histogram memory #1 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 15. " IPIPE_HST_TB0 ,IPIPE histogram memory #0 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 14. " IPIPE_D3L_TB3 ,D3L TB3 memory access priority This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 13. " IPIPE_D3L_TB2 ,D3L TB2 memory access priority This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 12. " IPIPE_D3L_TB1 ,D3L TB1 memory access priority This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 11. " IPIPE_D3L_TB0 ,D3L TB0 memory access priority This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 10. " IPIPE_GBC_TB ,IPIPE GBC TB memory access priority This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 9. " IPIPE_YEE_TB ,YEE TB memory access priority This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 8. " IPIPE_GMM_TBR ,IPIPE Gamma LUT R memory arbitration This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 7. " IPIPE_GMM_TBG ,IPIPE Gamma LUT G memory arbitration This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 6. " IPIPE_GMM_TBB ,IPIPE Gamma LUT B memory arbitration This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 5. " IPIPE_DPC_TB ,IPIPE defect pixel memory arbitration This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 4. " ISIF_DCLAMP ,ISIF DC accumulation memory arbitration This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" textline " " bitfld.long 0x00 3. " ISIF_LSC_TB1 ,ISIF LSC memory 1 access This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 2. " ISIF_LSC_TB0 ,ISIF LSC memory 0 access This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " ISIF_LIN_TB ,ISIF linearity compensation memory arbitration This memory is expected to be written during ISP initialization and potentially updated during vertical blanking periods. - . - ." "newEnum1,newEnum2" group.long 0x80++0x3 line.long 0x00 "ISP5_BL_MTC_1,MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x00 16.--31. 1. " ISIF_R ,Sets the minimum interval btw two consecutive memory requests for the ISIF-Read port. Specified in number of interface clock cycles." hexmask.long.word 0x00 0.--15. 1. " IPIPEIF_R ,Sets the minimum interval btw two consecutive memory requests for the IPIPEIF-Read port. Specified in number of interface clock cycles." group.long 0x84++0x3 line.long 0x00 "ISP5_BL_MTC_2,MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x00 16.--31. 1. " H3A_W ,Sets the minimum interval btw two consecutive memory requests for the H3A-Write port. Specified in number of interface clock cycles." group.long 0x88++0x3 line.long 0x00 "ISP5_BL_VBUSM,BL VBUSM TUNING REGISTER The settings in the register are static and not expected to be modified dynamically." bitfld.long 0x00 5. " MFLAG_THRES ,MFLAG Threshold value The value of this bit field is a threshold which is compared to the MFlag output of the ISP5. If the BL MFlag signal is greater or equal to this threshold the last beat of the VBUSM command is delayed by ISP.." "Thres_=_1,Thres_=_3" bitfld.long 0x00 0.--4. " LASTCMD_DLY ,The value of this bit field represents a delay expressed in cycles (L3 clock). This value is used to delay the last beat of the VBUSM command such that the ISP does not loose arbitration at the ISS level because the BL d.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree.open "ISS_SIMCOP_Overview" tree "SIMCOP_CONTROL_L3Interconnect" base ad:0x52020000 tree "IRQ_Line_0" width 29. group.long 0x2C++0x3 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_0,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Interrupt_enabled" textline " " eventfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Interrupt_enabled" eventfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x28++0x3 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_0,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Interrupt_enabled" textline " " bitfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Interrupt_enabled" bitfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x20++0x3 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_0,Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" bitfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Event_pending" textline " " bitfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Event_pending" bitfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" group.long 0x24++0x3 line.long 0x00 "SIMCOP_HL_IRQSTATUS_i_0,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" eventfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Event_pending" textline " " eventfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Event_pending" eventfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: -The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" tree.end tree "IRQ_Line_1" width 29. group.long 0x3C++0x3 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_1,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Interrupt_enabled" textline " " eventfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Interrupt_enabled" eventfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x38++0x3 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_1,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Interrupt_enabled" textline " " bitfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Interrupt_enabled" bitfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x30++0x3 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_1,Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" bitfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Event_pending" textline " " bitfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Event_pending" bitfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" group.long 0x34++0x3 line.long 0x00 "SIMCOP_HL_IRQSTATUS_i_1,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" eventfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Event_pending" textline " " eventfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Event_pending" eventfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: -The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" tree.end tree "IRQ_Line_2" width 29. group.long 0x4C++0x3 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_2,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Interrupt_enabled" textline " " eventfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Interrupt_enabled" eventfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x48++0x3 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_2,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Interrupt_enabled" textline " " bitfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Interrupt_enabled" bitfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x40++0x3 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_2,Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" bitfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Event_pending" textline " " bitfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Event_pending" bitfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" group.long 0x44++0x3 line.long 0x00 "SIMCOP_HL_IRQSTATUS_i_2,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" eventfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Event_pending" textline " " eventfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Event_pending" eventfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: -The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" tree.end tree "IRQ_Line_3" width 29. group.long 0x5C++0x3 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_3,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Interrupt_enabled" textline " " eventfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Interrupt_enabled" eventfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x58++0x3 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_3,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Interrupt_enabled" textline " " bitfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Interrupt_enabled" bitfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x50++0x3 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_3,Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" bitfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Event_pending" textline " " bitfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Event_pending" bitfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" group.long 0x54++0x3 line.long 0x00 "SIMCOP_HL_IRQSTATUS_i_3,Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 19. " CPU_PROC_START_IRQ ,Event triggered by the hardware sequencer to instruct the CPU to process a macroblock - . - . - . - ." "noaction_/_noevent,clear_/_pending" bitfld.long 0x00 18. " SIMCOP_DMA_IRQ1 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" eventfld.long 0x00 17. " LDC2BRIDGE_ERR_IRQ ,The LDC2 bridge has generated an error. - . - . - . - ." "No_action,Event_pending" textline " " eventfld.long 0x00 16. " ICNT_ERR_IRQ ,An error has been received on the SIMCOP master port. - . - . - . - ." "No_action,Event_pending" eventfld.long 0x00 15. " VLCDJ_DECODE_ERR_IRQ ,A decode error has been signaled by the VLCDJ module - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 14. " DONE_IRQ ,Event triggered when the hardware sequencer finishes the sequence: -The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 13. " STEP3_IRQ ,Event triggered when Step 3 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 12. " STEP2_IRQ ,Event triggered when Step 2 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 11. " STEP1_IRQ ,Event triggered when Step 1 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 10. " STEP0_IRQ ,Event triggered when Step 0 is activated by the hardware sequencer - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 9. " LDC_BLOCK_IRQ ,This event is triggered by LDC when a macroblock has been processed - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 7. " ROT_A ,Event triggered by the ROT a engine - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 6. " IMX_B_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 5. " IMX_A_IRQ ,Event triggered when iMX has executed a SLEEP instruction. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 4. " NSF_IRQ_IRQ ,Event triggered by the NSF2 imaging accelerator when processing of a block is done. - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 3. " VLCDJ_BLOC_IRQ ,This event is triggered by VLCDJ when a macroblock has been processed (encode/decode) - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 2. " DCT_IRQ ,Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 1. " LDC_FRAME_IRQ ,This event is triggered by LDC when a full frame has been processed - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " bitfld.long 0x00 0. " SIMCOP_DMA_IRQ0 ,Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers. - . - ." "noevent,pending" tree.end textline "" width 21. rgroup.long 0x0++0x3 line.long 0x00 "SIMCOP_HL_REVISION,MODULE REVISION This register contains the IP revision code in binary coded digital. For example, we have: 0x01 = revision 0.1 and 0x21 = revision 2.1" hexmask.long 0x00 0.--31. 1. " REV ,Revision ID" rgroup.long 0x4++0x3 line.long 0x00 "SIMCOP_HL_HWINFO,Information about the IP module's hardware configuration. It provides information about the generic parameters." bitfld.long 0x00 10.--12. " LDCR_RESP_FIFO ,Defines the size of the LDC read master response FIFO in words of 128-bits. - . - . - . - . - . - ." "0,1,S2,S3,S4,S5,S6,S7" bitfld.long 0x00 8.--9. " IMAGE_BUFFERS ,This parameter defines the image buffer count. - . - ." "IM4,IM8,2,3" bitfld.long 0x00 6. " ROT_A_ENABLE ,The ROT a is present when this parameter is set. - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 5. " IMX_B_ENABLE ,The iMX B module and the CMD b, COEFF b memories are present when this parameter is set. - . - ." "DISABLE,ENABLE" bitfld.long 0x00 4. " IMX_A_ENABLE ,The iMX A module and the CMD a, COEFF a memories are present when this parameter is set. - . - ." "DISABLE,ENABLE" bitfld.long 0x00 3. " NSF_ENABLE ,The NSF2 is present when this parameter is set. - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 2. " VLCDJ_ENABLE ,The VLCD module and the QUANT, HUFFMAN, BITSTREAM memories are present when this parameter is set. - . - ." "DISABLE,ENABLE" bitfld.long 0x00 1. " DCT_ENABLE ,The DCT module is present when this parameter is set. - . - ." "DISABLE,ENABLE" bitfld.long 0x00 0. " LDC_ENABLE ,The LDC module and the LDC LUT are present when this parameter is set. - . - ." "DISABLE,ENABLE" group.long 0x10++0x3 line.long 0x00 "SIMCOP_HL_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. - . - . - ." "force,no,smart,3" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - . - . - ." "done_/_noaction,pending_/_reset" group.long 0x60++0x3 line.long 0x00 "SIMCOP_CTRL,SIMCOP control register" bitfld.long 0x00 28. " LDC_R_BURST_BREAK ,Controls if bursts issued by the LDC2 bridge could cross burst length boundaries. When this register is set, the LDC2 bridge only issues aligned bursts. Register can only be used when LDC_R_MAX_BURST_LENGHT is 32, 64, or 128 bytes. .." "YES,NO" bitfld.long 0x00 26.--27. " LDC_R_MAX_BURST_LENGHT ,Limits the maximum burst length that could be used by the LDC2 bridge - . - . - . - ." "8_x_128,6_x_128,4_x_128,2_x_128" bitfld.long 0x00 21.--24. " LDC_R_TAG_CNT ,Limits the maximum number of outstanding requests to LDC_R_TAG_CNT+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " LDC_R_TAG_OFST ,First OCP tag ID that can be used by LDC reads.Software must prevent overlap with tags generated by the SIMCOP DMA.Typically this value should be equal to SIMCP_DMA_CTRL.TAG_CNT+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14. " IMX_B_CMD ,Switch for iMX # command memory - . - ." "COPR,IMXB" bitfld.long 0x00 12.--13. " IMX_A_CMD ,Switch for iMX A command memory - . - . - ." "COPR,IMXA,IMXB,3" textline " " bitfld.long 0x00 11. " HUFF ,Switch for Huffman table - . - ." "COPR,VLCDJ" bitfld.long 0x00 10. " QUANT ,Switch for quantization table - . - ." "COPR,VLCDJ" bitfld.long 0x00 8. " LDC_LUT ,Switch for LDC LUT - . - ." "COPR,LDC" textline " " bitfld.long 0x00 6.--7. " LDC_INPUT ,Selects input data buffer for LDC. Memories attached to LDC as working memories cannot be used by any other accelerators. HWSEQ or HWSEQ software override settings are ignored for those memories. - . - . - . - ." "NONE,IMBUF2,IMBUF4,LDC_PRIVATE" bitfld.long 0x00 4.--5. " NSF_WMEM ,Selects working memory for NSF. Memories attached to NSF as working memories cannot be used by any other accelerators. HWSEQ or HWSEQ software override settings are ignored for those memories. - . - . - . - ." "NONE,COEFF_A,IMBUFF_2,IMBUFF_4" bitfld.long 0x00 3. " IRQ3_MODE ,Interrupt generation method - . - ." "OR,AND" textline " " bitfld.long 0x00 2. " IRQ2_MODE ,Interrupt generation method - . - ." "OR,AND" bitfld.long 0x00 1. " IRQ1_MODE ,Interrupt generation method - . - ." "OR,AND" bitfld.long 0x00 0. " IRQ0_MODE ,Interrupt generation method - . - ." "OR,AND" group.long 0x64++0x3 line.long 0x00 "SIMCOP_CLKCTRL,SIMCOP clock control register. Use to enable/disable the interface and functional clock of SIMCOP submodules. Disabled modules cannot be accessed" bitfld.long 0x00 7. " ROT_A ,ROT A - . - . - . - ." "WOFF_/_ROFF,WON_/_RON" bitfld.long 0x00 6. " IMX_B ,iMX B - . - . - . - ." "WOFF_/_ROFF,WON_/_RON" bitfld.long 0x00 5. " IMX_A ,iMX A - . - . - . - ." "WOFF_/_ROFF,WON_/_RON" textline " " bitfld.long 0x00 4. " NSF2 ,NSF2 - . - . - . - ." "WOFF_/_ROFF,WON_/_RON" bitfld.long 0x00 3. " VLCDJ ,VLCDJ - . - . - . - ." "WOFF_/_ROFF,WON_/_RON" bitfld.long 0x00 2. " DCT ,DCT - . - . - . - ." "WOFF_/_ROFF,WON_/_RON" textline " " bitfld.long 0x00 1. " LDC ,LDC - . - . - . - ." "WOFF_/_ROFF,WON_/_RON" bitfld.long 0x00 0. " DMA ,DMA - . - . - . - ." "WOFF_/_ROFF,WON_/_RON" tree.end tree.end tree.open "ISS_SIMCOP_Hardware_Sequencer_and_Buffers" tree "HWSEQ_L3Interconnect" base ad:0x52020000 tree "Channel_0" width 32. group.long 0x8C++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_0,Hardware sequencer step control register" bitfld.long 0x00 10.--11. " NSF2_IO_OFST ,Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,E2,E3" bitfld.long 0x00 8.--9. " LDC_O_OFST ,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "E0,E1,E2,E3" bitfld.long 0x00 4.--6. " COEFF_B ,Coefficient buffer b switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_O,RSV" textline " " bitfld.long 0x00 0.--2. " COEFF_A ,Coefficient buffer a switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" group.long 0x80++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_0,Hardware sequencer step control register" bitfld.long 0x00 31. " CPU_SYNC ,Enable hardware synchronization with the CPU so that it can be used for some processing on in the macroblock pipeline. - . - ." "Disabled,Enabled" bitfld.long 0x00 28.--30. " DMA_OFST ,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 - . - . - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,SIX,SEVEN" bitfld.long 0x00 26.--27. " ROT_O_OFST ,Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 24.--25. " ROT_I_OFST ,Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 20.--22. " DCT_F_OFST ,Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" bitfld.long 0x00 18.--19. " DCT_S_OFST ,Controls DCT.S bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 15.--17. " VLCDJ_IO_OFST ,Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" bitfld.long 0x00 13.--14. " IMX_B_D_OFST ,Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 11.--12. " IMX_A_D_OFST ,Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 9.--10. " NEXT ,Next channel in the sync chain - . - . - . - ." "STEP0,STEP1,STEP2,STEP3" bitfld.long 0x00 5.--7. " DMA_SYNC ,Enable hardware synchronization with the SIMCOP DMA - . - . - . - . - . - . - . - ." "Disabled,CHAN0_1,CHAN0_2,CHAN0_3,CHAN0,CHAN1,CHAN2,CHAN3" bitfld.long 0x00 4. " ROT_A_SYNC ,Enable hardware synchronization with the ROT #a module - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 3. " NSF_SYNC ,Enable hardware synchronization with the NSF module - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " VLCDJ_SYNC ,Enable hardware synchronization with the VLCDJ module - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " DCT_SYNC ,Enable hardware synchronization with the DCT module - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LDC_SYNC ,Enable hardware synchronization with the LDC module - . - ." "Disabled,Enabled" group.long 0x88++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_IMX_CTRL_i_0,Hardware sequencer step control register The configuration of step #0 is used when hardware sequencer is idle." bitfld.long 0x00 31. " IMX_B_SYNC ,Enable hardware synchronization with the iMX B module - . - ." "Disabled,Enabled" hexmask.long.word 0x00 16.--28. 1. " IMX_B_START ,This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[31] IMX_B_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started." bitfld.long 0x00 15. " IMX_A_SYNC ,Enable hardware synchronization with the iMX A module - . - ." "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--12. 1. " IMX_A_START ,This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[15] IMX_A_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started." group.long 0x84++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_SWITCH_i_0,Image buffer switch control. The configuration of step #0 is used when hardware sequencer is idle." bitfld.long 0x00 28.--31. " IMBUFF_H ,Switch for image buffer h - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " IMBUFF_G ,Switch for image buffer g - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 20.--22. " IMBUFF_F ,Switch for image buffer f - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" textline " " bitfld.long 0x00 16.--18. " IMBUFF_E ,Switch for image buffer e - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" bitfld.long 0x00 12.--14. " IMBUFF_D ,Switch for image buffer d - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 8.--10. " IMBUFF_C ,Switch for image buffer c. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" textline " " bitfld.long 0x00 4.--6. " IMBUFF_B ,Switch for image buffer b. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 0.--2. " IMBUFF_A ,Switch for image buffer a - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" tree.end tree "Channel_1" width 32. group.long 0x9C++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_1,Hardware sequencer step control register" bitfld.long 0x00 10.--11. " NSF2_IO_OFST ,Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,E2,E3" bitfld.long 0x00 8.--9. " LDC_O_OFST ,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "E0,E1,E2,E3" bitfld.long 0x00 4.--6. " COEFF_B ,Coefficient buffer b switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_O,RSV" textline " " bitfld.long 0x00 0.--2. " COEFF_A ,Coefficient buffer a switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" group.long 0x90++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_1,Hardware sequencer step control register" bitfld.long 0x00 31. " CPU_SYNC ,Enable hardware synchronization with the CPU so that it can be used for some processing on in the macroblock pipeline. - . - ." "Disabled,Enabled" bitfld.long 0x00 28.--30. " DMA_OFST ,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 - . - . - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,SIX,SEVEN" bitfld.long 0x00 26.--27. " ROT_O_OFST ,Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 24.--25. " ROT_I_OFST ,Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 20.--22. " DCT_F_OFST ,Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" bitfld.long 0x00 18.--19. " DCT_S_OFST ,Controls DCT.S bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 15.--17. " VLCDJ_IO_OFST ,Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" bitfld.long 0x00 13.--14. " IMX_B_D_OFST ,Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 11.--12. " IMX_A_D_OFST ,Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 9.--10. " NEXT ,Next channel in the sync chain - . - . - . - ." "STEP0,STEP1,STEP2,STEP3" bitfld.long 0x00 5.--7. " DMA_SYNC ,Enable hardware synchronization with the SIMCOP DMA - . - . - . - . - . - . - . - ." "Disabled,CHAN0_1,CHAN0_2,CHAN0_3,CHAN0,CHAN1,CHAN2,CHAN3" bitfld.long 0x00 4. " ROT_A_SYNC ,Enable hardware synchronization with the ROT #a module - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 3. " NSF_SYNC ,Enable hardware synchronization with the NSF module - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " VLCDJ_SYNC ,Enable hardware synchronization with the VLCDJ module - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " DCT_SYNC ,Enable hardware synchronization with the DCT module - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LDC_SYNC ,Enable hardware synchronization with the LDC module - . - ." "Disabled,Enabled" group.long 0x98++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_IMX_CTRL_i_1,Hardware sequencer step control register The configuration of step #0 is used when hardware sequencer is idle." bitfld.long 0x00 31. " IMX_B_SYNC ,Enable hardware synchronization with the iMX B module - . - ." "Disabled,Enabled" hexmask.long.word 0x00 16.--28. 1. " IMX_B_START ,This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[31] IMX_B_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started." bitfld.long 0x00 15. " IMX_A_SYNC ,Enable hardware synchronization with the iMX A module - . - ." "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--12. 1. " IMX_A_START ,This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[15] IMX_A_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started." group.long 0x94++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_SWITCH_i_1,Image buffer switch control. The configuration of step #0 is used when hardware sequencer is idle." bitfld.long 0x00 28.--31. " IMBUFF_H ,Switch for image buffer h - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " IMBUFF_G ,Switch for image buffer g - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 20.--22. " IMBUFF_F ,Switch for image buffer f - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" textline " " bitfld.long 0x00 16.--18. " IMBUFF_E ,Switch for image buffer e - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" bitfld.long 0x00 12.--14. " IMBUFF_D ,Switch for image buffer d - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 8.--10. " IMBUFF_C ,Switch for image buffer c. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" textline " " bitfld.long 0x00 4.--6. " IMBUFF_B ,Switch for image buffer b. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 0.--2. " IMBUFF_A ,Switch for image buffer a - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" tree.end tree "Channel_2" width 32. group.long 0xAC++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_2,Hardware sequencer step control register" bitfld.long 0x00 10.--11. " NSF2_IO_OFST ,Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,E2,E3" bitfld.long 0x00 8.--9. " LDC_O_OFST ,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "E0,E1,E2,E3" bitfld.long 0x00 4.--6. " COEFF_B ,Coefficient buffer b switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_O,RSV" textline " " bitfld.long 0x00 0.--2. " COEFF_A ,Coefficient buffer a switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" group.long 0xA0++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_2,Hardware sequencer step control register" bitfld.long 0x00 31. " CPU_SYNC ,Enable hardware synchronization with the CPU so that it can be used for some processing on in the macroblock pipeline. - . - ." "Disabled,Enabled" bitfld.long 0x00 28.--30. " DMA_OFST ,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 - . - . - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,SIX,SEVEN" bitfld.long 0x00 26.--27. " ROT_O_OFST ,Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 24.--25. " ROT_I_OFST ,Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 20.--22. " DCT_F_OFST ,Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" bitfld.long 0x00 18.--19. " DCT_S_OFST ,Controls DCT.S bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 15.--17. " VLCDJ_IO_OFST ,Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" bitfld.long 0x00 13.--14. " IMX_B_D_OFST ,Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 11.--12. " IMX_A_D_OFST ,Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 9.--10. " NEXT ,Next channel in the sync chain - . - . - . - ." "STEP0,STEP1,STEP2,STEP3" bitfld.long 0x00 5.--7. " DMA_SYNC ,Enable hardware synchronization with the SIMCOP DMA - . - . - . - . - . - . - . - ." "Disabled,CHAN0_1,CHAN0_2,CHAN0_3,CHAN0,CHAN1,CHAN2,CHAN3" bitfld.long 0x00 4. " ROT_A_SYNC ,Enable hardware synchronization with the ROT #a module - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 3. " NSF_SYNC ,Enable hardware synchronization with the NSF module - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " VLCDJ_SYNC ,Enable hardware synchronization with the VLCDJ module - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " DCT_SYNC ,Enable hardware synchronization with the DCT module - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LDC_SYNC ,Enable hardware synchronization with the LDC module - . - ." "Disabled,Enabled" group.long 0xA8++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_IMX_CTRL_i_2,Hardware sequencer step control register The configuration of step #0 is used when hardware sequencer is idle." bitfld.long 0x00 31. " IMX_B_SYNC ,Enable hardware synchronization with the iMX B module - . - ." "Disabled,Enabled" hexmask.long.word 0x00 16.--28. 1. " IMX_B_START ,This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[31] IMX_B_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started." bitfld.long 0x00 15. " IMX_A_SYNC ,Enable hardware synchronization with the iMX A module - . - ." "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--12. 1. " IMX_A_START ,This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[15] IMX_A_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started." group.long 0xA4++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_SWITCH_i_2,Image buffer switch control. The configuration of step #0 is used when hardware sequencer is idle." bitfld.long 0x00 28.--31. " IMBUFF_H ,Switch for image buffer h - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " IMBUFF_G ,Switch for image buffer g - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 20.--22. " IMBUFF_F ,Switch for image buffer f - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" textline " " bitfld.long 0x00 16.--18. " IMBUFF_E ,Switch for image buffer e - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" bitfld.long 0x00 12.--14. " IMBUFF_D ,Switch for image buffer d - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 8.--10. " IMBUFF_C ,Switch for image buffer c. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" textline " " bitfld.long 0x00 4.--6. " IMBUFF_B ,Switch for image buffer b. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 0.--2. " IMBUFF_A ,Switch for image buffer a - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" tree.end tree "Channel_3" width 32. group.long 0xBC++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_3,Hardware sequencer step control register" bitfld.long 0x00 10.--11. " NSF2_IO_OFST ,Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,E2,E3" bitfld.long 0x00 8.--9. " LDC_O_OFST ,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "E0,E1,E2,E3" bitfld.long 0x00 4.--6. " COEFF_B ,Coefficient buffer b switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_O,RSV" textline " " bitfld.long 0x00 0.--2. " COEFF_A ,Coefficient buffer a switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" group.long 0xB0++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_3,Hardware sequencer step control register" bitfld.long 0x00 31. " CPU_SYNC ,Enable hardware synchronization with the CPU so that it can be used for some processing on in the macroblock pipeline. - . - ." "Disabled,Enabled" bitfld.long 0x00 28.--30. " DMA_OFST ,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 - . - . - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,SIX,SEVEN" bitfld.long 0x00 26.--27. " ROT_O_OFST ,Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 24.--25. " ROT_I_OFST ,Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 20.--22. " DCT_F_OFST ,Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" bitfld.long 0x00 18.--19. " DCT_S_OFST ,Controls DCT.S bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 15.--17. " VLCDJ_IO_OFST ,Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" bitfld.long 0x00 13.--14. " IMX_B_D_OFST ,Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 11.--12. " IMX_A_D_OFST ,Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 9.--10. " NEXT ,Next channel in the sync chain - . - . - . - ." "STEP0,STEP1,STEP2,STEP3" bitfld.long 0x00 5.--7. " DMA_SYNC ,Enable hardware synchronization with the SIMCOP DMA - . - . - . - . - . - . - . - ." "Disabled,CHAN0_1,CHAN0_2,CHAN0_3,CHAN0,CHAN1,CHAN2,CHAN3" bitfld.long 0x00 4. " ROT_A_SYNC ,Enable hardware synchronization with the ROT #a module - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 3. " NSF_SYNC ,Enable hardware synchronization with the NSF module - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " VLCDJ_SYNC ,Enable hardware synchronization with the VLCDJ module - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " DCT_SYNC ,Enable hardware synchronization with the DCT module - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LDC_SYNC ,Enable hardware synchronization with the LDC module - . - ." "Disabled,Enabled" group.long 0xB8++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_IMX_CTRL_i_3,Hardware sequencer step control register The configuration of step #0 is used when hardware sequencer is idle." bitfld.long 0x00 31. " IMX_B_SYNC ,Enable hardware synchronization with the iMX B module - . - ." "Disabled,Enabled" hexmask.long.word 0x00 16.--28. 1. " IMX_B_START ,This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[31] IMX_B_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started." bitfld.long 0x00 15. " IMX_A_SYNC ,Enable hardware synchronization with the iMX A module - . - ." "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--12. 1. " IMX_A_START ,This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[15] IMX_A_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started." group.long 0xB4++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_SWITCH_i_3,Image buffer switch control. The configuration of step #0 is used when hardware sequencer is idle." bitfld.long 0x00 28.--31. " IMBUFF_H ,Switch for image buffer h - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " IMBUFF_G ,Switch for image buffer g - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 20.--22. " IMBUFF_F ,Switch for image buffer f - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" textline " " bitfld.long 0x00 16.--18. " IMBUFF_E ,Switch for image buffer e - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" bitfld.long 0x00 12.--14. " IMBUFF_D ,Switch for image buffer d - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 8.--10. " IMBUFF_C ,Switch for image buffer c. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" textline " " bitfld.long 0x00 4.--6. " IMBUFF_B ,Switch for image buffer b. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 0.--2. " IMBUFF_A ,Switch for image buffer a - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" tree.end textline "" width 35. group.long 0x68++0x3 line.long 0x00 "SIMCOP_HWSEQ_CTRL,SIMCOP hardware sequencer control register" hexmask.long.word 0x00 16.--31. 1. " HW_SEQ_STEP_COUNTER ,Number of steps executed by the hardware sequencer. HW_SEQ_STEP_COUNTER=0 corresponds to manual sequencing." bitfld.long 0x00 11.--12. " STEP ,This register is automatically updated by the hardware sequencer when it is active. Otherwise, software can use it to activate the content of a given set of step registers (SIMCOP_HWSEQ_STEP_i) or to choose the first step .." "0,1,2,3" bitfld.long 0x00 10. " CPU_PROC_DONE ,Used by the CPU to tell that it has completed data processing. This feature should be used together with the CPU_PROC_START_IRQ event Read's always return 0. - . - ." "ZERO,ONE" textline " " bitfld.long 0x00 8.--9. " BBM_SYNC_CHAN ,Defines the SIMCOP DMA hardware synchronization channel to be used for BBM. This register is only used when BITSTREAM=ENCODE or DECODE. Software must ensure that the same DMA hardware synchronization channel is not used by the har.." "0,1,2,3" bitfld.long 0x00 7. " BBM_STATUS ,Status of the Bitstream buffer management hardware.Used only during automatic mode [BITSTREAM=5 or 6]. Equals 0 (IDLE) in manual mode [BITSTREAM=0..4].Set when automatic mode is entered. Automatic encode mode: used to d.." "IDLE,BUSY" bitfld.long 0x00 4.--6. " BITSTREAM ,Bitstream buffer access control - . - . - . - . - . - . - ." "COPR,DMA_DMA,VLCDJ_VLCDJ,DMA_VLCDJ,VLCDJ_DMA,PINGPONG_ENCODE,PINGPONG_DECODE,7" textline " " bitfld.long 0x00 2.--3. " BITSTR_XFER_SIZE ,Defines the amount of data to be transferred per hardware request to the SIMCOP DMA. Bigger sizes lead to better SDRAM efficiency but prevents fine grained DMA transfer arbitration. This register is only used by hardware when BITS.." "B2046,B1024,B512,B256" bitfld.long 0x00 1. " HW_SEQ_STOP ,Stop the hardware sequencer. This feature is typically used to recover from an error condition. Read's always return 0. - . - ." "NOEFFECT,STOP" bitfld.long 0x00 0. " HW_SEQ_START ,Start the hardware sequencer. Read's always return 0. - . - ." "NOCHANGE,START" rgroup.long 0x6C++0x3 line.long 0x00 "SIMCOP_HWSEQ_STATUS,Hardware sequencer status register" hexmask.long.word 0x00 16.--31. 1. " HW_SEQ_STEP_COUNTER ,Current step number" bitfld.long 0x00 0. " STATE ,Current state - . - ." "IDLE,RUNNING" group.long 0x70++0x3 line.long 0x00 "SIMCOP_HWSEQ_OVERRIDE,Hardware sequencer override control register. Bits in this register select what configuration register control a resource. 0: Resource controlled by hardware sequencer. Hardware uses the value from SIMCOP_HWSEQ_STEP_xx registers f.." bitfld.long 0x00 18. " COEFF_B ,See register description" "0,1" bitfld.long 0x00 17. " COEFF_A ,See register description" "0,1" bitfld.long 0x00 16. " IMBUFF_H ,See register description" "0,1" textline " " bitfld.long 0x00 15. " IMBUFF_G ,See register description" "0,1" bitfld.long 0x00 14. " IMBUFF_F ,See register description" "0,1" bitfld.long 0x00 13. " IMBUFF_E ,See register description" "0,1" textline " " bitfld.long 0x00 12. " IMBUFF_D ,See register description" "0,1" bitfld.long 0x00 11. " IMBUFF_C ,See register description" "0,1" bitfld.long 0x00 10. " IMBUFF_B ,See register description" "0,1" textline " " bitfld.long 0x00 9. " IMBUFF_A ,See register description" "0,1" bitfld.long 0x00 8. " LDC_O_OFST_OVR ,See register description" "0,1" bitfld.long 0x00 7. " ROT_O_OFST_OVR ,See register description" "0,1" textline " " bitfld.long 0x00 6. " ROT_I_OFST_OVR ,See register description" "0,1" bitfld.long 0x00 5. " NSF_IO_OFST_OVR ,See register description" "0,1" bitfld.long 0x00 4. " DCT_F_OFST_OVR ,See register description" "0,1" textline " " bitfld.long 0x00 3. " DCT_S_OFST_OVR ,See register description" "0,1" bitfld.long 0x00 2. " VLCDJ_IO_OFST_OVR ,See register description" "0,1" bitfld.long 0x00 1. " IMX_B_D_OFST_OVR ,See register description" "0,1" textline " " bitfld.long 0x00 0. " IMX_A_D_OFST_OVR ,See register description" "0,1" group.long 0x74++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_OVERRIDE,Hardware sequencer override register. Used to execute software sequences in parallel to hardware sequencing steps" bitfld.long 0x00 26.--27. " ROT_O_OFST ,Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 24.--25. " ROT_I_OFST ,Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 20.--22. " DCT_F_OFST ,Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" textline " " bitfld.long 0x00 18.--19. " DCT_S_OFST ,Controls DCT.S bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 15.--17. " VLCDJ_IO_OFST ,Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - . - . - ." "ZERO,ONE,TWO,THREE,FOUR,FIVE,6,7" bitfld.long 0x00 13.--14. " IMX_B_D_OFST ,Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" textline " " bitfld.long 0x00 11.--12. " IMX_A_D_OFST ,Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "ZERO,ONE,TWO,THREE" bitfld.long 0x00 5.--7. " DMA_TRIGGER ,Software controlled START/DONE synchronization - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "NE_/_RZERO,CHAN0_1_/_RCHAN0_1,CHAN0_2_/_RCHAN0_2,CHAN0_3_/_RCHAN0_3,CHAN0_/_RCHAN0,CHAN1_/_RCHAN1,CHAN2_/_RCHAN2,CHAN3_/_RCHAN3" bitfld.long 0x00 4. " ROT_A_TRIGGER ,Software controlled START/DONE synchronization - . - . - . - ." "WZERO_/_RZERO,WONE_/_RONE" textline " " bitfld.long 0x00 3. " NSF_TRIGGER ,Software controlled START/DONE synchronization - . - . - . - ." "WZERO_/_RZERO,WONE_/_RONE" bitfld.long 0x00 2. " VLCDJ_TRIGGER ,Software controlled START/DONE synchronization - . - . - . - ." "WZERO_/_RZERO,WONE_/_RONE" bitfld.long 0x00 1. " DCT_TRIGGER ,Software controlled START/DONE synchronization - . - . - . - ." "WZERO_/_RZERO,WONE_/_RONE" textline " " bitfld.long 0x00 0. " LDC_TRIGGER ,Software controlled START/DONE synchronization - . - . - . - ." "WZERO_/_RZERO,WONE_/_RONE" group.long 0x78++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_SWITCH_OVERRIDE,Hardware sequencer override register. Used to execute software sequences in parallel to hardware sequencing steps" bitfld.long 0x00 28.--31. " IMBUFF_H ,Switch for image buffer h - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " IMBUFF_G ,Switch for image buffer g - . - . - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_S,DCT_F,ROT_A_O,NSF_IO,LDC_O,10,11,12,13,14,15" bitfld.long 0x00 20.--22. " IMBUFF_F ,Switch for image buffer f - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" textline " " bitfld.long 0x00 16.--18. " IMBUFF_E ,Switch for image buffer e - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,DCT_S,NSF_IO,LDC_O,ROT_A_O" bitfld.long 0x00 12.--14. " IMBUFF_D ,Switch for image buffer d - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 8.--10. " IMBUFF_C ,Switch for image buffer c. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" textline " " bitfld.long 0x00 4.--6. " IMBUFF_B ,Switch for image buffer b. - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" bitfld.long 0x00 0.--2. " IMBUFF_A ,Switch for image buffer a - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" group.long 0x7C++0x3 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_OVERRIDE,Hardware sequencer override register. Used to execute software sequences in parallel to hardware sequencing steps" bitfld.long 0x00 10.--11. " NSF2_IO_OFST ,Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000 - . - . - . - ." "ZERO,ONE,E2,E3" bitfld.long 0x00 8.--9. " LDC_O_OFST ,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 - . - . - . - ." "E0,E1,E2,E3" bitfld.long 0x00 4.--6. " COEFF_B ,Coefficient buffer b switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_O,RSV" textline " " bitfld.long 0x00 0.--2. " COEFF_A ,Coefficient buffer a switch - . - . - . - . - . - . - . - ." "COPR,DMA,IMX_A,IMX_B,VLCDJ_IO,DCT_F,ROT_A_I,RSV" tree.end tree.end tree.open "ISS_SIMCOP_DMA_Module" tree "DMA_L3Interconnect" base ad:0x52020200 tree "DMA_Channel_0" width 35. group.long 0x94++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_0,2D block size" hexmask.long.word 0x00 16.--28. 1. " YNUM ,Height, in lines, per 2D block Valid values are 1- 8191." hexmask.long.word 0x00 4.--13. 1. " XNUM ,Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB." group.long 0xA4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_0,Offset between 2D blocks." hexmask.long.word 0x00 16.--29. 1. " YSTEP ,Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191." hexmask.long.word 0x00 4.--14. 1. " XSTEP ,Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB." group.long 0x90++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_0,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. " ADDR ,Address in 128-bit words." group.long 0x8C++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_0,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. " OFST ,Line offset. In 128-bit words." group.long 0x80++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_0,Logical channel control register" bitfld.long 0x00 20.--22. " HWSTOP ,DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 17.--19. " HWSTART ,DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 12.--16. " LINKED ,DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - . - . - . - . - ." "DISABLED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,CHAN0,CHAN1,CHAN2,CHAN3,CHAN4,CHAN5,CHAN6,CHAN7,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 6. " TILERMODE ,Selects OCP transaction breakdown algorithm - . - ." "REGULAR,TILER" bitfld.long 0x00 5. " DIR ,Transfer direction - . - ." "SDR2BUF,BUF2SDR" bitfld.long 0x00 3.--4. " STATUS ,SW could poll this bit to know the state of the channel - . - . - . - ." "Idle,Active,Pending,Running" textline " " bitfld.long 0x00 2. " SWTRIGGER ,Software trigger of the DMA channel. Read of this register always returns 0. - . - ." "ZERO,ONE" bitfld.long 0x00 1. " DISABLE ,Disable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,DISABLE" bitfld.long 0x00 0. " ENABLE ,Enable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,ENABLE" rgroup.long 0xA0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_0,SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." hexmask.long.word 0x00 16.--25. 1. " BY ,Vertical position of the last transferred 2D block in the frame." hexmask.long.word 0x00 0.--9. 1. " BX ,Horizontal position of the last transferred 2D block in the frame." group.long 0x98++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_0,Defines a frame. A frame is composed of 2D blocks." hexmask.long.word 0x00 16.--25. 1. " YCNT ,Vertical count of 2D blocks per frame. Valid values are 1-1023" hexmask.long.word 0x00 0.--9. 1. " XCNT ,Horizontal count of 2D blocks per frame. Valid values are 1-1023" group.long 0x84++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_0,System memory address" hexmask.long 0x00 4.--31. 1. " ADDR ,Address in 128-bit words" group.long 0x88++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_0,System memory line offset in 128-bit words. Maximum stride = 1MB" hexmask.long.word 0x00 4.--19. 1. " OFST ,Line offset. In 128-bit words." group.long 0x2C++0x3 line.long 0x00 "SIMCOP_DMA_IRQENABLE_CLR_j_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 31. " CHAN7_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 30. " CHAN6_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 29. " CHAN5_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 28. " CHAN4_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 27. " CHAN3_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 26. " CHAN2_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 25. " CHAN1_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 24. " CHAN0_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 23. " CHAN7_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 22. " CHAN6_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 21. " CHAN5_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 20. " CHAN4_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 19. " CHAN3_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 18. " CHAN2_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 17. " CHAN1_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 16. " CHAN0_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " OCP_ERR ,OCP error - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x28++0x3 line.long 0x00 "SIMCOP_DMA_IRQENABLE_SET_j_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 31. " CHAN7_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 30. " CHAN6_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 29. " CHAN5_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 28. " CHAN4_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 27. " CHAN3_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 26. " CHAN2_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 25. " CHAN1_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 24. " CHAN0_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 23. " CHAN7_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 22. " CHAN6_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 21. " CHAN5_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 20. " CHAN4_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 19. " CHAN3_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 18. " CHAN2_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 17. " CHAN1_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 16. " CHAN0_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " OCP_ERR ,OCP error - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x20++0x3 line.long 0x00 "SIMCOP_DMA_IRQSTATUS_RAW_j_0,Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 31. " CHAN7_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 30. " CHAN6_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 29. " CHAN5_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 28. " CHAN4_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 27. " CHAN3_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 26. " CHAN2_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 25. " CHAN1_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 24. " CHAN0_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 23. " CHAN7_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 22. " CHAN6_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 21. " CHAN5_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 20. " CHAN4_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 19. " CHAN3_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 18. " CHAN2_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 17. " CHAN1_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 16. " CHAN0_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 0. " OCP_ERR ,OCP error - . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x24++0x3 line.long 0x00 "SIMCOP_DMA_IRQSTATUS_j_0,Per-event 'enabled' interrupt status vector Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 31. " CHAN7_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 30. " CHAN6_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 29. " CHAN5_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 28. " CHAN4_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 27. " CHAN3_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 26. " CHAN2_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 25. " CHAN1_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 24. " CHAN0_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 23. " CHAN7_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 22. " CHAN6_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 21. " CHAN5_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 20. " CHAN4_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 19. " CHAN3_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 18. " CHAN2_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 17. " CHAN1_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 16. " CHAN0_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 0. " BUS_ERR ,BUS error - . - . - . - ." "No_action,Event_pending" tree.end tree "DMA_Channel_1" width 35. group.long 0xC4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_1,2D block size" hexmask.long.word 0x00 16.--28. 1. " YNUM ,Height, in lines, per 2D block Valid values are 1- 8191." hexmask.long.word 0x00 4.--13. 1. " XNUM ,Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB." group.long 0xD4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_1,Offset between 2D blocks." hexmask.long.word 0x00 16.--29. 1. " YSTEP ,Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191." hexmask.long.word 0x00 4.--14. 1. " XSTEP ,Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB." group.long 0xC0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_1,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. " ADDR ,Address in 128-bit words." group.long 0xBC++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_1,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. " OFST ,Line offset. In 128-bit words." group.long 0xB0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_1,Logical channel control register" bitfld.long 0x00 20.--22. " HWSTOP ,DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 17.--19. " HWSTART ,DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 12.--16. " LINKED ,DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - . - . - . - . - ." "DISABLED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,CHAN0,CHAN1,CHAN2,CHAN3,CHAN4,CHAN5,CHAN6,CHAN7,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 6. " TILERMODE ,Selects OCP transaction breakdown algorithm - . - ." "REGULAR,TILER" bitfld.long 0x00 5. " DIR ,Transfer direction - . - ." "SDR2BUF,BUF2SDR" bitfld.long 0x00 3.--4. " STATUS ,SW could poll this bit to know the state of the channel - . - . - . - ." "Idle,Active,Pending,Running" textline " " bitfld.long 0x00 2. " SWTRIGGER ,Software trigger of the DMA channel. Read of this register always returns 0. - . - ." "ZERO,ONE" bitfld.long 0x00 1. " DISABLE ,Disable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,DISABLE" bitfld.long 0x00 0. " ENABLE ,Enable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,ENABLE" rgroup.long 0xD0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_1,SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." hexmask.long.word 0x00 16.--25. 1. " BY ,Vertical position of the last transferred 2D block in the frame." hexmask.long.word 0x00 0.--9. 1. " BX ,Horizontal position of the last transferred 2D block in the frame." group.long 0xC8++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_1,Defines a frame. A frame is composed of 2D blocks." hexmask.long.word 0x00 16.--25. 1. " YCNT ,Vertical count of 2D blocks per frame. Valid values are 1-1023" hexmask.long.word 0x00 0.--9. 1. " XCNT ,Horizontal count of 2D blocks per frame. Valid values are 1-1023" group.long 0xB4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_1,System memory address" hexmask.long 0x00 4.--31. 1. " ADDR ,Address in 128-bit words" group.long 0xB8++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_1,System memory line offset in 128-bit words. Maximum stride = 1MB" hexmask.long.word 0x00 4.--19. 1. " OFST ,Line offset. In 128-bit words." group.long 0x3C++0x3 line.long 0x00 "SIMCOP_DMA_IRQENABLE_CLR_j_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 31. " CHAN7_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 30. " CHAN6_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 29. " CHAN5_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 28. " CHAN4_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 27. " CHAN3_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 26. " CHAN2_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 25. " CHAN1_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 24. " CHAN0_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 23. " CHAN7_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 22. " CHAN6_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 21. " CHAN5_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 20. " CHAN4_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 19. " CHAN3_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 18. " CHAN2_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 17. " CHAN1_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" textline " " eventfld.long 0x00 16. " CHAN0_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " OCP_ERR ,OCP error - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x38++0x3 line.long 0x00 "SIMCOP_DMA_IRQENABLE_SET_j_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 31. " CHAN7_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 30. " CHAN6_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 29. " CHAN5_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 28. " CHAN4_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 27. " CHAN3_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 26. " CHAN2_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 25. " CHAN1_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 24. " CHAN0_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 23. " CHAN7_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 22. " CHAN6_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 21. " CHAN5_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 20. " CHAN4_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 19. " CHAN3_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 18. " CHAN2_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 17. " CHAN1_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" textline " " bitfld.long 0x00 16. " CHAN0_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " OCP_ERR ,OCP error - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x30++0x3 line.long 0x00 "SIMCOP_DMA_IRQSTATUS_RAW_j_1,Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 31. " CHAN7_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 30. " CHAN6_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 29. " CHAN5_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 28. " CHAN4_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 27. " CHAN3_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 26. " CHAN2_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 25. " CHAN1_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 24. " CHAN0_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 23. " CHAN7_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 22. " CHAN6_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 21. " CHAN5_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 20. " CHAN4_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 19. " CHAN3_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 18. " CHAN2_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 17. " CHAN1_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" textline " " bitfld.long 0x00 16. " CHAN0_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 0. " OCP_ERR ,OCP error - . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x34++0x3 line.long 0x00 "SIMCOP_DMA_IRQSTATUS_j_1,Per-event 'enabled' interrupt status vector Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 31. " CHAN7_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 30. " CHAN6_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 29. " CHAN5_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 28. " CHAN4_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 27. " CHAN3_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 26. " CHAN2_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 25. " CHAN1_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 24. " CHAN0_FRAME_DONE_IRQ ,Channel has completed transfer of the full frame - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 23. " CHAN7_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 22. " CHAN6_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 21. " CHAN5_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 20. " CHAN4_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 19. " CHAN3_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 18. " CHAN2_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 17. " CHAN1_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" textline " " eventfld.long 0x00 16. " CHAN0_BLOCK_DONE_IRQ ,Channel has completed transfer of one 2D block - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 0. " BUS_ERR ,BUS error - . - . - . - ." "No_action,Event_pending" tree.end tree "DMA_Channel_2" width 35. group.long 0xF4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_2,2D block size" hexmask.long.word 0x00 16.--28. 1. " YNUM ,Height, in lines, per 2D block Valid values are 1- 8191." hexmask.long.word 0x00 4.--13. 1. " XNUM ,Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB." group.long 0x104++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_2,Offset between 2D blocks." hexmask.long.word 0x00 16.--29. 1. " YSTEP ,Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191." hexmask.long.word 0x00 4.--14. 1. " XSTEP ,Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB." group.long 0xF0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_2,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. " ADDR ,Address in 128-bit words." group.long 0xEC++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_2,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. " OFST ,Line offset. In 128-bit words." group.long 0xE0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_2,Logical channel control register" bitfld.long 0x00 20.--22. " HWSTOP ,DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 17.--19. " HWSTART ,DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 12.--16. " LINKED ,DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - . - . - . - . - ." "DISABLED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,CHAN0,CHAN1,CHAN2,CHAN3,CHAN4,CHAN5,CHAN6,CHAN7,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 6. " TILERMODE ,Selects OCP transaction breakdown algorithm - . - ." "REGULAR,TILER" bitfld.long 0x00 5. " DIR ,Transfer direction - . - ." "SDR2BUF,BUF2SDR" bitfld.long 0x00 3.--4. " STATUS ,SW could poll this bit to know the state of the channel - . - . - . - ." "Idle,Active,Pending,Running" textline " " bitfld.long 0x00 2. " SWTRIGGER ,Software trigger of the DMA channel. Read of this register always returns 0. - . - ." "ZERO,ONE" bitfld.long 0x00 1. " DISABLE ,Disable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,DISABLE" bitfld.long 0x00 0. " ENABLE ,Enable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,ENABLE" rgroup.long 0x100++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_2,SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." hexmask.long.word 0x00 16.--25. 1. " BY ,Vertical position of the last transferred 2D block in the frame." hexmask.long.word 0x00 0.--9. 1. " BX ,Horizontal position of the last transferred 2D block in the frame." group.long 0xF8++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_2,Defines a frame. A frame is composed of 2D blocks." hexmask.long.word 0x00 16.--25. 1. " YCNT ,Vertical count of 2D blocks per frame. Valid values are 1-1023" hexmask.long.word 0x00 0.--9. 1. " XCNT ,Horizontal count of 2D blocks per frame. Valid values are 1-1023" group.long 0xE4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_2,System memory address" hexmask.long 0x00 4.--31. 1. " ADDR ,Address in 128-bit words" group.long 0xE8++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_2,System memory line offset in 128-bit words. Maximum stride = 1MB" hexmask.long.word 0x00 4.--19. 1. " OFST ,Line offset. In 128-bit words." tree.end tree "DMA_Channel_3" width 35. group.long 0x124++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_3,2D block size" hexmask.long.word 0x00 16.--28. 1. " YNUM ,Height, in lines, per 2D block Valid values are 1- 8191." hexmask.long.word 0x00 4.--13. 1. " XNUM ,Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB." group.long 0x134++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_3,Offset between 2D blocks." hexmask.long.word 0x00 16.--29. 1. " YSTEP ,Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191." hexmask.long.word 0x00 4.--14. 1. " XSTEP ,Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB." group.long 0x120++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_3,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. " ADDR ,Address in 128-bit words." group.long 0x11C++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_3,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. " OFST ,Line offset. In 128-bit words." group.long 0x110++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_3,Logical channel control register" bitfld.long 0x00 20.--22. " HWSTOP ,DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 17.--19. " HWSTART ,DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 12.--16. " LINKED ,DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - . - . - . - . - ." "DISABLED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,CHAN0,CHAN1,CHAN2,CHAN3,CHAN4,CHAN5,CHAN6,CHAN7,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 6. " TILERMODE ,Selects OCP transaction breakdown algorithm - . - ." "REGULAR,TILER" bitfld.long 0x00 5. " DIR ,Transfer direction - . - ." "SDR2BUF,BUF2SDR" bitfld.long 0x00 3.--4. " STATUS ,SW could poll this bit to know the state of the channel - . - . - . - ." "Idle,Active,Pending,Running" textline " " bitfld.long 0x00 2. " SWTRIGGER ,Software trigger of the DMA channel. Read of this register always returns 0. - . - ." "ZERO,ONE" bitfld.long 0x00 1. " DISABLE ,Disable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,DISABLE" bitfld.long 0x00 0. " ENABLE ,Enable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,ENABLE" rgroup.long 0x130++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_3,SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." hexmask.long.word 0x00 16.--25. 1. " BY ,Vertical position of the last transferred 2D block in the frame." hexmask.long.word 0x00 0.--9. 1. " BX ,Horizontal position of the last transferred 2D block in the frame." group.long 0x128++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_3,Defines a frame. A frame is composed of 2D blocks." hexmask.long.word 0x00 16.--25. 1. " YCNT ,Vertical count of 2D blocks per frame. Valid values are 1-1023" hexmask.long.word 0x00 0.--9. 1. " XCNT ,Horizontal count of 2D blocks per frame. Valid values are 1-1023" group.long 0x114++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_3,System memory address" hexmask.long 0x00 4.--31. 1. " ADDR ,Address in 128-bit words" group.long 0x118++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_3,System memory line offset in 128-bit words. Maximum stride = 1MB" hexmask.long.word 0x00 4.--19. 1. " OFST ,Line offset. In 128-bit words." tree.end tree "DMA_Channel_4" width 35. group.long 0x154++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_4,2D block size" hexmask.long.word 0x00 16.--28. 1. " YNUM ,Height, in lines, per 2D block Valid values are 1- 8191." hexmask.long.word 0x00 4.--13. 1. " XNUM ,Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB." group.long 0x164++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_4,Offset between 2D blocks." hexmask.long.word 0x00 16.--29. 1. " YSTEP ,Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191." hexmask.long.word 0x00 4.--14. 1. " XSTEP ,Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB." group.long 0x150++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_4,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. " ADDR ,Address in 128-bit words." group.long 0x14C++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_4,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. " OFST ,Line offset. In 128-bit words." group.long 0x140++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_4,Logical channel control register" bitfld.long 0x00 20.--22. " HWSTOP ,DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 17.--19. " HWSTART ,DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 12.--16. " LINKED ,DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - . - . - . - . - ." "DISABLED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,CHAN0,CHAN1,CHAN2,CHAN3,CHAN4,CHAN5,CHAN6,CHAN7,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 6. " TILERMODE ,Selects OCP transaction breakdown algorithm - . - ." "REGULAR,TILER" bitfld.long 0x00 5. " DIR ,Transfer direction - . - ." "SDR2BUF,BUF2SDR" bitfld.long 0x00 3.--4. " STATUS ,SW could poll this bit to know the state of the channel - . - . - . - ." "Idle,Active,Pending,Running" textline " " bitfld.long 0x00 2. " SWTRIGGER ,Software trigger of the DMA channel. Read of this register always returns 0. - . - ." "ZERO,ONE" bitfld.long 0x00 1. " DISABLE ,Disable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,DISABLE" bitfld.long 0x00 0. " ENABLE ,Enable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,ENABLE" rgroup.long 0x160++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_4,SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." hexmask.long.word 0x00 16.--25. 1. " BY ,Vertical position of the last transferred 2D block in the frame." hexmask.long.word 0x00 0.--9. 1. " BX ,Horizontal position of the last transferred 2D block in the frame." group.long 0x158++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_4,Defines a frame. A frame is composed of 2D blocks." hexmask.long.word 0x00 16.--25. 1. " YCNT ,Vertical count of 2D blocks per frame. Valid values are 1-1023" hexmask.long.word 0x00 0.--9. 1. " XCNT ,Horizontal count of 2D blocks per frame. Valid values are 1-1023" group.long 0x144++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_4,System memory address" hexmask.long 0x00 4.--31. 1. " ADDR ,Address in 128-bit words" group.long 0x148++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_4,System memory line offset in 128-bit words. Maximum stride = 1MB" hexmask.long.word 0x00 4.--19. 1. " OFST ,Line offset. In 128-bit words." tree.end tree "DMA_Channel_5" width 35. group.long 0x184++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_5,2D block size" hexmask.long.word 0x00 16.--28. 1. " YNUM ,Height, in lines, per 2D block Valid values are 1- 8191." hexmask.long.word 0x00 4.--13. 1. " XNUM ,Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB." group.long 0x194++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_5,Offset between 2D blocks." hexmask.long.word 0x00 16.--29. 1. " YSTEP ,Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191." hexmask.long.word 0x00 4.--14. 1. " XSTEP ,Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB." group.long 0x180++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_5,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. " ADDR ,Address in 128-bit words." group.long 0x17C++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_5,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. " OFST ,Line offset. In 128-bit words." group.long 0x170++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_5,Logical channel control register" bitfld.long 0x00 20.--22. " HWSTOP ,DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 17.--19. " HWSTART ,DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 12.--16. " LINKED ,DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - . - . - . - . - ." "DISABLED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,CHAN0,CHAN1,CHAN2,CHAN3,CHAN4,CHAN5,CHAN6,CHAN7,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 6. " TILERMODE ,Selects OCP transaction breakdown algorithm - . - ." "REGULAR,TILER" bitfld.long 0x00 5. " DIR ,Transfer direction - . - ." "SDR2BUF,BUF2SDR" bitfld.long 0x00 3.--4. " STATUS ,SW could poll this bit to know the state of the channel - . - . - . - ." "Idle,Active,Pending,Running" textline " " bitfld.long 0x00 2. " SWTRIGGER ,Software trigger of the DMA channel. Read of this register always returns 0. - . - ." "ZERO,ONE" bitfld.long 0x00 1. " DISABLE ,Disable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,DISABLE" bitfld.long 0x00 0. " ENABLE ,Enable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,ENABLE" rgroup.long 0x190++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_5,SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." hexmask.long.word 0x00 16.--25. 1. " BY ,Vertical position of the last transferred 2D block in the frame." hexmask.long.word 0x00 0.--9. 1. " BX ,Horizontal position of the last transferred 2D block in the frame." group.long 0x188++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_5,Defines a frame. A frame is composed of 2D blocks." hexmask.long.word 0x00 16.--25. 1. " YCNT ,Vertical count of 2D blocks per frame. Valid values are 1-1023" hexmask.long.word 0x00 0.--9. 1. " XCNT ,Horizontal count of 2D blocks per frame. Valid values are 1-1023" group.long 0x174++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_5,System memory address" hexmask.long 0x00 4.--31. 1. " ADDR ,Address in 128-bit words" group.long 0x178++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_5,System memory line offset in 128-bit words. Maximum stride = 1MB" hexmask.long.word 0x00 4.--19. 1. " OFST ,Line offset. In 128-bit words." tree.end tree "DMA_Channel_6" width 35. group.long 0x1B4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_6,2D block size" hexmask.long.word 0x00 16.--28. 1. " YNUM ,Height, in lines, per 2D block Valid values are 1- 8191." hexmask.long.word 0x00 4.--13. 1. " XNUM ,Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB." group.long 0x1C4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_6,Offset between 2D blocks." hexmask.long.word 0x00 16.--29. 1. " YSTEP ,Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191." hexmask.long.word 0x00 4.--14. 1. " XSTEP ,Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB." group.long 0x1B0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_6,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. " ADDR ,Address in 128-bit words." group.long 0x1AC++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_6,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. " OFST ,Line offset. In 128-bit words." group.long 0x1A0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_6,Logical channel control register" bitfld.long 0x00 20.--22. " HWSTOP ,DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 17.--19. " HWSTART ,DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 12.--16. " LINKED ,DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - . - . - . - . - ." "DISABLED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,CHAN0,CHAN1,CHAN2,CHAN3,CHAN4,CHAN5,CHAN6,CHAN7,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 6. " TILERMODE ,Selects OCP transaction breakdown algorithm - . - ." "REGULAR,TILER" bitfld.long 0x00 5. " DIR ,Transfer direction - . - ." "SDR2BUF,BUF2SDR" bitfld.long 0x00 3.--4. " STATUS ,SW could poll this bit to know the state of the channel - . - . - . - ." "Idle,Active,Pending,Running" textline " " bitfld.long 0x00 2. " SWTRIGGER ,Software trigger of the DMA channel. Read of this register always returns 0. - . - ." "ZERO,ONE" bitfld.long 0x00 1. " DISABLE ,Disable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,DISABLE" bitfld.long 0x00 0. " ENABLE ,Enable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,ENABLE" rgroup.long 0x1C0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_6,SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." hexmask.long.word 0x00 16.--25. 1. " BY ,Vertical position of the last transferred 2D block in the frame." hexmask.long.word 0x00 0.--9. 1. " BX ,Horizontal position of the last transferred 2D block in the frame." group.long 0x1B8++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_6,Defines a frame. A frame is composed of 2D blocks." hexmask.long.word 0x00 16.--25. 1. " YCNT ,Vertical count of 2D blocks per frame. Valid values are 1-1023" hexmask.long.word 0x00 0.--9. 1. " XCNT ,Horizontal count of 2D blocks per frame. Valid values are 1-1023" group.long 0x1A4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_6,System memory address" hexmask.long 0x00 4.--31. 1. " ADDR ,Address in 128-bit words" group.long 0x1A8++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_6,System memory line offset in 128-bit words. Maximum stride = 1MB" hexmask.long.word 0x00 4.--19. 1. " OFST ,Line offset. In 128-bit words." tree.end tree "DMA_Channel_7" width 35. group.long 0x1E4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_7,2D block size" hexmask.long.word 0x00 16.--28. 1. " YNUM ,Height, in lines, per 2D block Valid values are 1- 8191." hexmask.long.word 0x00 4.--13. 1. " XNUM ,Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB." group.long 0x1F4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_7,Offset between 2D blocks." hexmask.long.word 0x00 16.--29. 1. " YSTEP ,Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191." hexmask.long.word 0x00 4.--14. 1. " XSTEP ,Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB." group.long 0x1E0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_7,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. " ADDR ,Address in 128-bit words." group.long 0x1DC++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_7,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. " OFST ,Line offset. In 128-bit words." group.long 0x1D0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_7,Logical channel control register" bitfld.long 0x00 20.--22. " HWSTOP ,DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 17.--19. " HWSTART ,DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - ." "DISABLED,1,2,3,HW0,HW1,HW2,HW3" bitfld.long 0x00 12.--16. " LINKED ,DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior. - . - . - . - . - . - . - . - . - ." "DISABLED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,CHAN0,CHAN1,CHAN2,CHAN3,CHAN4,CHAN5,CHAN6,CHAN7,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 6. " TILERMODE ,Selects OCP transaction breakdown algorithm - . - ." "REGULAR,TILER" bitfld.long 0x00 5. " DIR ,Transfer direction - . - ." "SDR2BUF,BUF2SDR" bitfld.long 0x00 3.--4. " STATUS ,SW could poll this bit to know the state of the channel - . - . - . - ." "Idle,Active,Pending,Running" textline " " bitfld.long 0x00 2. " SWTRIGGER ,Software trigger of the DMA channel. Read of this register always returns 0. - . - ." "ZERO,ONE" bitfld.long 0x00 1. " DISABLE ,Disable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,DISABLE" bitfld.long 0x00 0. " ENABLE ,Enable control of the logical channel. Read of this register always returns 0. - . - ." "ZERO,ENABLE" rgroup.long 0x1F0++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_7,SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." hexmask.long.word 0x00 16.--25. 1. " BY ,Vertical position of the last transferred 2D block in the frame." hexmask.long.word 0x00 0.--9. 1. " BX ,Horizontal position of the last transferred 2D block in the frame." group.long 0x1E8++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_7,Defines a frame. A frame is composed of 2D blocks." hexmask.long.word 0x00 16.--25. 1. " YCNT ,Vertical count of 2D blocks per frame. Valid values are 1-1023" hexmask.long.word 0x00 0.--9. 1. " XCNT ,Horizontal count of 2D blocks per frame. Valid values are 1-1023" group.long 0x1D4++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_7,System memory address" hexmask.long 0x00 4.--31. 1. " ADDR ,Address in 128-bit words" group.long 0x1D8++0x3 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_7,System memory line offset in 128-bit words. Maximum stride = 1MB" hexmask.long.word 0x00 4.--19. 1. " OFST ,Line offset. In 128-bit words." tree.end textline "" width 22. rgroup.long 0x0++0x3 line.long 0x00 "SIMCOP_DMA_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REV ,Revision ID" rgroup.long 0x4++0x3 line.long 0x00 "SIMCOP_DMA_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics." bitfld.long 0x00 2. " CHAN ,Logical channels - . - ." "FOUR,EIGHT" bitfld.long 0x00 0.--1. " CONTEXT ,Maximum outstanding OCP transactions - . - . - ." "FOUR,EIGHT,SIXTEEN,3" group.long 0x10++0x3 line.long 0x00 "SIMCOP_DMA_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. - . - . - . - ." "force,no,smart1,smart2" group.long 0x1C++0x3 line.long 0x00 "SIMCOP_DMA_CTRL," hexmask.long.word 0x00 16.--31. 1. " BW_LIMITER ,SIMCOP DMA guarantees that there are at least BW_LIMITER functional clock cycles between two OCP requests. No IDLE cycles are inserted during an OCP transaction. This parameter could be used to reduce traffic generated by the SIMCOP DM.." bitfld.long 0x00 4.--7. " TAG_CNT ,Limits the outstanding transactions count. Only tags 0 - TAG_CNT will be used by SIMCOP DMA The maximum allowed value is 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " POSTED_WRITES ,Select write type. Setting depend on the used interconnect - . - ." "NON_POSTED,POSTED" textline " " bitfld.long 0x00 0.--1. " MAX_BURST_SIZE ,Defines the maximum burst length for INCR bursts. In case of 2D bursts, length x height is less or equal to this value. - . - . - . - ." "ONE,TWO,FOUR,EIGHT" tree.end tree.end tree.open "ISS_SIMCOP_Discrete_Cosine_Transform_Module" tree "DCT_L3Interconnect" base ad:0x52020800 width 13. rgroup.long 0x0++0x3 line.long 0x00 "DCT_VERSION,IP Revision" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x4++0x3 line.long 0x00 "DCT_CTRL,DCT control register" bitfld.long 0x00 15. " BUSY ,IDCT/busy status 0: Idle 1: Busy" "0,1" bitfld.long 0x00 0. " EN ,Write 1 whenDCT_CFG[4] TRIG_SRC = 0 to start module operation. Read returns 0." "0,1" group.long 0x8++0x3 line.long 0x00 "DCT_CFG,DCT configuration register" bitfld.long 0x00 8.--13. " NMCUS ,Number of MCUs (for FMT = 0, 1) or blocks (for FMT = 2) 0 = 1 MCU or block 1 = 2 MCUs or blocks ... 63 = 64 MCUs or blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5. " AUTOGATING ,Internal clock gating on interface and functional clocks 0: Clocks are free-running 1: Clocks are gated off in subblocks that are not required for operation." "0,1" bitfld.long 0x00 4. " TRIG_SRC ,Trigger source 0: Memory mapper register 1: Hardware start signal" "0,1" textline " " bitfld.long 0x00 3. " INTEN ,0: Interrupt disabled 1: Interrupt enabled" "0,1" bitfld.long 0x00 1.--2. " FMT ,Data format 0: YUV4:2:0 format 1: YUV4:2:2 format 2: Sequential blocks format 3: Reserved" "0,1,2,3" bitfld.long 0x00 0. " MODE ,0: DCT 1: IDCT" "0,1" group.long 0xC++0x3 line.long 0x00 "DCT_SPTR,Spatial-domain data pointer, byte address" hexmask.long.byte 0x00 5.--12. 1. " ADDR ,Address in 256-bit words Intention is that software write a byte address into the register. Hardware ignores the lowest 5 bits and bits 12..5 specifies the 256-bit/word memory address.." group.long 0x10++0x3 line.long 0x00 "DCT_FPTR,Frequency-domain data pointer, byte address" hexmask.long.word 0x00 4.--13. 1. " ADDR ,Address in 128-bit words. Intention is that software write a byte address into the register. Hardware ignores the lowest 4 bits and bits 13..4 specifies the 128-bit/word memory address." tree.end tree.end tree.open "ISS_SIMCOP_Variable_Length_Coder_Decoder_for_JPEG_Module" tree "VLCDJ_L3Interconnect" base ad:0x52020600 width 17. rgroup.long 0x0++0x3 line.long 0x00 "VLCDJ_REVISION,IP revision" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x4++0x3 line.long 0x00 "VLCDJ_CTRL,Controls common to encoding and decoding" bitfld.long 0x00 16. " BUSY ,Idle/busy status 0: Idle 1: Busy" "0,1" bitfld.long 0x00 7. " CLRRB ,Write only; read returns 0." "0,1" bitfld.long 0x00 6. " RBEN ,Enable RB signaling." "0,1" textline " " bitfld.long 0x00 5. " INTEN_ERR ,Interrupt enable for decode error 0: No interrupt generated on decode error 1: Interrupt generated on decode error" "0,1" bitfld.long 0x00 4. " INTEN_DONE ,Interrupt enable for task completion. DONE_VLCD is not gated by this and is always asserted at task completion. 0: No interrupt generated on task completion 1: Interrupt generated on task completion" "0,1" bitfld.long 0x00 3. " AUTOGATING ,Internal clock gating on OCP clock and functional clock 0: Clocks are free-running. 1: Clocks are gated off in sub-blocks that are not required for operation." "0,1" textline " " bitfld.long 0x00 2. " TRIG_SRC ,Which mechanism starts VLCDJ operation 0: MMR write to VLCDJ_CTRL.EN 1: Hardware start signal" "0,1" bitfld.long 0x00 1. " MODE ,0: Encode 1: Decode" "0,1" bitfld.long 0x00 0. " EN ,Module enable by software (write-only, read returns 0). When TRIG_SRC = 0 and BUSY = 0, set this field to 1 to start VLCDJ. When TRIG_SRC = 1, writes to this field are ignored. Setting TRIG_SRC = 0 and EN = 1 on the same register write.." "0,1" group.long 0x8++0x3 line.long 0x00 "VLCDJE_CFG,Encode configuration" bitfld.long 0x00 8.--13. " NMCUS ,Number of MCUs (FMT = 0, 1) or blocks (FMT = 2) to encode 0: 1 MCU 1: 2 MCUs, etc." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 3. " RLOCEN ,Restart marker location recording enable 0: Restart marker location recording disabled 1: Restart marker location recording enabled" "0,1" bitfld.long 0x00 2. " RSTEN ,Restart marker insertion enable 0: Restart marker insertion disabled 1: Restart marker insertion enabled" "0,1" textline " " bitfld.long 0x00 0.--1. " FMT ,0: YUV4:2:0 1: YUV4:2:2 2 : Sequential blocks" "0,1,2,3" group.long 0xC++0x3 line.long 0x00 "VLCDJE_DCPREDY,Encode DC predictor for Y" hexmask.long.word 0x00 0.--11. 1. " PREDY ,DC predictor for Y" group.long 0x10++0x3 line.long 0x00 "VLCDJE_DCPREDUV,Encode DC predictor for U and V" hexmask.long.word 0x00 16.--27. 1. " PREDV ,DC predictor for V" hexmask.long.word 0x00 0.--11. 1. " PREDU ,DC predictor for U" group.long 0x14++0x3 line.long 0x00 "VLCDJE_BSPTR,Encode bitstream pointer" bitfld.long 0x00 16.--19. " BITPTR ,Bit pointer, 1..8, indicates number of available bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " BYTEPTR ,Byte pointer (to BSMEM)" group.long 0x18++0x3 line.long 0x00 "VLCDJE_CBUF,Encode bitstream circular buffer" bitfld.long 0x00 26.--27. " END ,Ending quarter (1KB each unit) of bitstream buffer. Software can write a byte address into the upper 16 bits of the register." "0,1,2,3" bitfld.long 0x00 10.--11. " START ,Starting quarter (1KB each unit) of bitstream buffer. Software can write a byte address to the lower 16 bits of the register." "0,1,2,3" group.long 0x1C++0x3 line.long 0x00 "VLCDJE_RSTCFG,Encode restart marker configuration" bitfld.long 0x00 28.--30. " INC ,Restart count increment value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " INIT ,Restart marker initial count" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 12.--21. 1. " PHASE ,MCU count within the interval" textline " " hexmask.long.word 0x00 0.--9. 1. " INTRVL ,Restart interval (in MCUs)" group.long 0x20++0x3 line.long 0x00 "VLCDJE_DCTQM,Encode DCT coefficient and quantizer matrix pointers" bitfld.long 0x00 23.--24. " QMR ,Quarter (128 bytes/unit) of quantization matrix reciprocal. Software can write a byte address to the upper 16 bits of the register." "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. " DCT ,128-bit/word address of DCT coefficients. Software can write a byte address to the lower 16 bits of the register." group.long 0x24++0x3 line.long 0x00 "VLCDJE_VLCTBL,Encode Huffman table pointer" hexmask.long.word 0x00 2.--11. 1. " ADDR ,Encode Huffman table pointer, 32-bit word address. Software can write a byte address into the entire register." group.long 0x28++0x3 line.long 0x00 "VLCDJE_RSTPTR,Encode restart marker locations" hexmask.long.word 0x00 4.--13. 1. " ADDR ,Pointer to restart marker locations in image buffer, 128-bit/word address Software can write a byte address into the entire register." group.long 0x2C++0x3 line.long 0x00 "VLCDJE_RSTOFST,SDRAM address to add to encode restart marker locations" hexmask.long 0x00 0.--31. 1. " OFFSET ,SDRAM address of bitstream buffer, to be added to the restart marker locations" group.long 0x40++0x3 line.long 0x00 "VLCDJD_CFG,Decode configuration" bitfld.long 0x00 8.--13. " NMCUS ,Number of MCUs (FMT = 0, 1) or blocks (FMT = 2) to decode 0: 1 MCU 1: 2 MCUs, etc." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 2. " RSTEN ,Restart marker detection/processing enable 0: Restart marker detection/processing disabled 1: Restart marker detection/processing enabled" "0,1" bitfld.long 0x00 0.--1. " FMT ,0: YUV4:2:0 1: YUV4:2:2 2: Sequential blocks" "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "VLCDJD_DCPREDY,Decode DC predictor for Y" hexmask.long.word 0x00 0.--11. 1. " PREDY ,DC predictor for Y" group.long 0x48++0x3 line.long 0x00 "VLCDJD_DCPREDUV,Decode DC predictor for U and V" hexmask.long.word 0x00 16.--27. 1. " PREDV ,DC predictor for V" hexmask.long.word 0x00 0.--11. 1. " PREDU ,DC predictor for U" group.long 0x4C++0x3 line.long 0x00 "VLCDJD_BSPTR,Decode bitstream pointer" bitfld.long 0x00 16.--19. " BITPTR ,Bit pointer, 1..8, indicates number of available bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " BYTEPTR ,Byte pointer (to BSMEM)" group.long 0x50++0x3 line.long 0x00 "VLCDJD_CBUF,Decode bitstream circular buffer" bitfld.long 0x00 26.--27. " END ,Ending quarter (1KB each unit) of bitstream buffer. Software can write a byte address into the upper 16 bits of the register." "0,1,2,3" bitfld.long 0x00 10.--11. " START ,Starting quarter (1KB each unit) of bitstream buffer. Software can write a byte address to the lower 16 bits of the register." "0,1,2,3" group.long 0x54++0x3 line.long 0x00 "VLCDJD_DCTQM,Decode DCT coefficient and quantizer matrix pointers" bitfld.long 0x00 23.--24. " QM ,Quarter (128 bytes/unit) of quantization matrix. Software can write a byte address to the upper 16 bits of the register." "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. " DCT ,128-bit/word address of DCT coefficients. Software can write a byte address to the lower 16 bits of the register." group.long 0x58++0x3 line.long 0x00 "VLCDJD_CTRLTBL,Decode control table base" hexmask.long.word 0x00 2.--11. 1. " ADDR ,Starting address of decode control table, 32-bit word. Software can write a byte address into the entire register." group.long 0x5C++0x3 line.long 0x00 "VLCDJD_DCDTBL01,Decode Huffman tables 0 and 1" hexmask.long.word 0x00 18.--27. 1. " DCDTBL1 ,Starting byte address of decode table 1, 32-bit word. Software can write a byte address into the lower 16 bits of the register. This is for Luma AC." hexmask.long.word 0x00 2.--11. 1. " DCDTBL0 ,Starting byte address of decode table 0, 32-bit word. Software can write a byte address into the lower 16 bits of the register. This is for Luma DC." group.long 0x60++0x3 line.long 0x00 "VLCDJD_DCDTBL23,Decode Huffman tables 2 and 3" hexmask.long.word 0x00 18.--27. 1. " DCDTBL3 ,Starting byte address of decode table 3, 32-bit word. Software can write a byte address into the lower 16 bits of the register. This is for Chroma AC." hexmask.long.word 0x00 2.--11. 1. " DCDTBL2 ,Starting byte address of decode table 2, 32-bit word. Software can write a byte address into the lower 16 bits of the register. This is for Chroma DC." rgroup.long 0x64++0x3 line.long 0x00 "VLCDJD_DCTERR," hexmask.long.word 0x00 0.--13. 1. " ERRPTR ,Byte address pointer to DCT coefficients, near where decode error occurs (read-only)" tree.end tree.end tree.open "ISS_SIMCOP_Rotation_Accelerator_Module" tree "ROT_L3Interconnect" base ad:0x52020700 width 16. group.long 0x0++0x3 line.long 0x00 "ROT_REVISION,Module revision" group.long 0x4++0x3 line.long 0x00 "ROT_CTRL,Control" bitfld.long 0x00 15. " BUSY ,Idle/busy status (read-only) 0 = Idle, 1 = Busy" "0,1" bitfld.long 0x00 0. " EN ,Module enable, writing 1 starts the module; always reads as 0." "0,1" group.long 0x8++0x3 line.long 0x00 "ROT_CFG,Configuration" bitfld.long 0x00 12.--15. " NBLKS ,Number of blocks minus 1 0: 1 block, 1: 2 blocks, etc." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. " AUTOGATING ,Internal interconnect and functional clock gating 0: Interconnect and functional clocks are free-running. 1: Automatic clock gating is applied, based on the interface activity for the interface clock, and on the functional activity for .." "0,1" bitfld.long 0x00 8. " TRIG_SRC ,Trigger source 0 = MMR write 1 = Hardware start signal" "0,1" textline " " bitfld.long 0x00 4.--6. " FMT ,Data format 0 = 8-bit data 1 = 16-bit data 2 = 32-bit data 3 = YUV4:2:2 data 4 = YUV4:2:0 data" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " OP ,Operation 0 = Rotate 0 degree 1 = Rotate 90 degrees 2 = Rotate 180 degrees 3 = Rotate 270 degrees 4 = Data shift (FMT = 0) 5 = Horizontal circular (FMT = 0) shift" "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x00 "ROT_BLKSZ,Block size" hexmask.long.word 0x00 16.--27. 1. " BLKH ,Block height, in pixels (YUV4:2:0/4:2:2) or number of rows (8-/16-/32-bit). Should be a multiple of 8, and at least 8, for rotation. Should be at least 1 for data shifting." hexmask.long.word 0x00 0.--11. 1. " BLKW ,Block width, in pixels (YUV4:2:0/4:2:2) or data units (8-/16-/32-bit). Should be a multiple of 8, and at least 8, for rotation. Should be at least 4 for data shifting." group.long 0x10++0x3 line.long 0x00 "ROT_SRC_START1,Source starting address" hexmask.long.word 0x00 0.--13. 1. " ADDR ,Byte address Should be a multiple of 8 for rotation. No constraint for data shifting." group.long 0x14++0x3 line.long 0x00 "ROT_SRC_LOFST,Source line offset" hexmask.long.word 0x00 0.--15. 1. " LOFST ,Line offset in bytes Should be a multiple of 8 for rotation and normal data shifting. Should be a power of 2 and at least 32 for horizontal circular shifting." group.long 0x18++0x3 line.long 0x00 "ROT_DST_START1,Destination starting address" hexmask.long.word 0x00 0.--13. 1. " ADDR ,Byte address Should be a multiple of 8 for rotation. No constraint for data shifting." group.long 0x1C++0x3 line.long 0x00 "ROT_DST_LOFST,Destination line offset" hexmask.long.word 0x00 0.--15. 1. " LOFST ,Line offset in bytes Should be a multiple of 8 for rotation and normal data shifting. Should be a power of 2 and at least 32 for horizontal circular shifting." group.long 0x20++0x3 line.long 0x00 "ROT_SRC_START2,Source starting address 2 (only form YUV4:2:0 FMT = 2)" hexmask.long.word 0x00 0.--13. 1. " ADDR ,Byte address, should be a multiple of 8." group.long 0x24++0x3 line.long 0x00 "ROT_DST_START2,Destination starting address 2 (only form YUV4:2:0 FMT = 2)" hexmask.long.word 0x00 0.--13. 1. " ADDR ,Byte address, should be a multiple of 8." tree.end tree.end tree.open "Face_Detect" tree "FDIF" base ad:0x4A10A000 tree "IRQ_Line_0" width 24. group.long 0x30++0x3 line.long 0x00 "FDIF_IRQENABLE_CLR_j_0,Per-event interrupt enable bit vector, line #n. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Interrupt_enabled" group.long 0x2C++0x3 line.long 0x00 "FDIF_IRQENABLE_SET_j_0,Per-event interrupt enable bit vector, line #n. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Interrupt_enabled" group.long 0x24++0x3 line.long 0x00 "FDIF_IRQSTATUS_RAW_j_0,Per-event raw interrupt status vector, line #n. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Event_pending" group.long 0x28++0x3 line.long 0x00 "FDIF_IRQSTATUS_j_0,Per-event 'enabled' interrupt status vector, line #n. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Event_pending" rgroup.long 0x16C++0x3 line.long 0x00 "FD_ANGLE_i_0,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x160++0x3 line.long 0x00 "FD_CENTERX_i_0,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x164++0x3 line.long 0x00 "FD_CENTERY_i_0,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x168++0x3 line.long 0x00 "FD_CONFSIZE_i_0,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "IRQ_Line_1" width 24. group.long 0x40++0x3 line.long 0x00 "FDIF_IRQENABLE_CLR_j_1,Per-event interrupt enable bit vector, line #n. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Interrupt_enabled" group.long 0x3C++0x3 line.long 0x00 "FDIF_IRQENABLE_SET_j_1,Per-event interrupt enable bit vector, line #n. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Interrupt_enabled" group.long 0x34++0x3 line.long 0x00 "FDIF_IRQSTATUS_RAW_j_1,Per-event raw interrupt status vector, line #n. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Event_pending" group.long 0x38++0x3 line.long 0x00 "FDIF_IRQSTATUS_j_1,Per-event 'enabled' interrupt status vector, line #n. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Event_pending" rgroup.long 0x17C++0x3 line.long 0x00 "FD_ANGLE_i_1,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x170++0x3 line.long 0x00 "FD_CENTERX_i_1,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x174++0x3 line.long 0x00 "FD_CENTERY_i_1,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x178++0x3 line.long 0x00 "FD_CONFSIZE_i_1,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "IRQ_Line_2" width 24. group.long 0x50++0x3 line.long 0x00 "FDIF_IRQENABLE_CLR_j_2,Per-event interrupt enable bit vector, line #n. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_disabled,disable_/_enabled" eventfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Interrupt_enabled" group.long 0x4C++0x3 line.long 0x00 "FDIF_IRQENABLE_SET_j_2,Per-event interrupt enable bit vector, line #n. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_disabled,enable_/_enabled" bitfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Interrupt_enabled" group.long 0x44++0x3 line.long 0x00 "FDIF_IRQSTATUS_RAW_j_2,Per-event raw interrupt status vector, line #n. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_noevent,set_/_pending" bitfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Event_pending" group.long 0x48++0x3 line.long 0x00 "FDIF_IRQSTATUS_j_2,Per-event 'enabled' interrupt status vector, line #n. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." eventfld.long 0x00 8. " FINISH_IRQ ,Face detection processing done. - . - . - . - ." "noaction_/_noevent,clear_/_pending" eventfld.long 0x00 0. " ERR_IRQ ,Error received by the L3 port. - . - . - . - ." "No_action,Event_pending" rgroup.long 0x18C++0x3 line.long 0x00 "FD_ANGLE_i_2,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x180++0x3 line.long 0x00 "FD_CENTERX_i_2,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x184++0x3 line.long 0x00 "FD_CENTERY_i_2,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x188++0x3 line.long 0x00 "FD_CONFSIZE_i_2,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_3" width 17. rgroup.long 0x19C++0x3 line.long 0x00 "FD_ANGLE_i_3,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x190++0x3 line.long 0x00 "FD_CENTERX_i_3,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x194++0x3 line.long 0x00 "FD_CENTERY_i_3,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x198++0x3 line.long 0x00 "FD_CONFSIZE_i_3,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_4" width 17. rgroup.long 0x1AC++0x3 line.long 0x00 "FD_ANGLE_i_4,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x1A0++0x3 line.long 0x00 "FD_CENTERX_i_4,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x1A4++0x3 line.long 0x00 "FD_CENTERY_i_4,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x1A8++0x3 line.long 0x00 "FD_CONFSIZE_i_4,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_5" width 17. rgroup.long 0x1BC++0x3 line.long 0x00 "FD_ANGLE_i_5,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x1B0++0x3 line.long 0x00 "FD_CENTERX_i_5,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x1B4++0x3 line.long 0x00 "FD_CENTERY_i_5,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x1B8++0x3 line.long 0x00 "FD_CONFSIZE_i_5,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_6" width 17. rgroup.long 0x1CC++0x3 line.long 0x00 "FD_ANGLE_i_6,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x1C0++0x3 line.long 0x00 "FD_CENTERX_i_6,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x1C4++0x3 line.long 0x00 "FD_CENTERY_i_6,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x1C8++0x3 line.long 0x00 "FD_CONFSIZE_i_6,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_7" width 17. rgroup.long 0x1DC++0x3 line.long 0x00 "FD_ANGLE_i_7,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x1D0++0x3 line.long 0x00 "FD_CENTERX_i_7,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x1D4++0x3 line.long 0x00 "FD_CENTERY_i_7,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x1D8++0x3 line.long 0x00 "FD_CONFSIZE_i_7,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_8" width 17. rgroup.long 0x1EC++0x3 line.long 0x00 "FD_ANGLE_i_8,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x1E0++0x3 line.long 0x00 "FD_CENTERX_i_8,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x1E4++0x3 line.long 0x00 "FD_CENTERY_i_8,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x1E8++0x3 line.long 0x00 "FD_CONFSIZE_i_8,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_9" width 17. rgroup.long 0x1FC++0x3 line.long 0x00 "FD_ANGLE_i_9,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x1F0++0x3 line.long 0x00 "FD_CENTERX_i_9,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x1F4++0x3 line.long 0x00 "FD_CENTERY_i_9,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x1F8++0x3 line.long 0x00 "FD_CONFSIZE_i_9,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_10" width 18. rgroup.long 0x20C++0x3 line.long 0x00 "FD_ANGLE_i_10,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x200++0x3 line.long 0x00 "FD_CENTERX_i_10,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x204++0x3 line.long 0x00 "FD_CENTERY_i_10,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x208++0x3 line.long 0x00 "FD_CONFSIZE_i_10,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_11" width 18. rgroup.long 0x21C++0x3 line.long 0x00 "FD_ANGLE_i_11,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x210++0x3 line.long 0x00 "FD_CENTERX_i_11,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x214++0x3 line.long 0x00 "FD_CENTERY_i_11,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x218++0x3 line.long 0x00 "FD_CONFSIZE_i_11,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_12" width 18. rgroup.long 0x22C++0x3 line.long 0x00 "FD_ANGLE_i_12,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x220++0x3 line.long 0x00 "FD_CENTERX_i_12,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x224++0x3 line.long 0x00 "FD_CENTERY_i_12,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x228++0x3 line.long 0x00 "FD_CONFSIZE_i_12,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_13" width 18. rgroup.long 0x23C++0x3 line.long 0x00 "FD_ANGLE_i_13,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x230++0x3 line.long 0x00 "FD_CENTERX_i_13,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x234++0x3 line.long 0x00 "FD_CENTERY_i_13,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x238++0x3 line.long 0x00 "FD_CONFSIZE_i_13,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_14" width 18. rgroup.long 0x24C++0x3 line.long 0x00 "FD_ANGLE_i_14,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x240++0x3 line.long 0x00 "FD_CENTERX_i_14,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x244++0x3 line.long 0x00 "FD_CENTERY_i_14,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x248++0x3 line.long 0x00 "FD_CONFSIZE_i_14,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_15" width 18. rgroup.long 0x25C++0x3 line.long 0x00 "FD_ANGLE_i_15,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x250++0x3 line.long 0x00 "FD_CENTERX_i_15,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x254++0x3 line.long 0x00 "FD_CENTERY_i_15,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x258++0x3 line.long 0x00 "FD_CONFSIZE_i_15,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_16" width 18. rgroup.long 0x26C++0x3 line.long 0x00 "FD_ANGLE_i_16,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x260++0x3 line.long 0x00 "FD_CENTERX_i_16,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x264++0x3 line.long 0x00 "FD_CENTERY_i_16,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x268++0x3 line.long 0x00 "FD_CONFSIZE_i_16,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_17" width 18. rgroup.long 0x27C++0x3 line.long 0x00 "FD_ANGLE_i_17,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x270++0x3 line.long 0x00 "FD_CENTERX_i_17,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x274++0x3 line.long 0x00 "FD_CENTERY_i_17,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x278++0x3 line.long 0x00 "FD_CONFSIZE_i_17,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_18" width 18. rgroup.long 0x28C++0x3 line.long 0x00 "FD_ANGLE_i_18,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x280++0x3 line.long 0x00 "FD_CENTERX_i_18,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x284++0x3 line.long 0x00 "FD_CENTERY_i_18,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x288++0x3 line.long 0x00 "FD_CONFSIZE_i_18,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_19" width 18. rgroup.long 0x29C++0x3 line.long 0x00 "FD_ANGLE_i_19,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x290++0x3 line.long 0x00 "FD_CENTERX_i_19,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x294++0x3 line.long 0x00 "FD_CENTERY_i_19,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x298++0x3 line.long 0x00 "FD_CONFSIZE_i_19,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_20" width 18. rgroup.long 0x2AC++0x3 line.long 0x00 "FD_ANGLE_i_20,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x2A0++0x3 line.long 0x00 "FD_CENTERX_i_20,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x2A4++0x3 line.long 0x00 "FD_CENTERY_i_20,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x2A8++0x3 line.long 0x00 "FD_CONFSIZE_i_20,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_21" width 18. rgroup.long 0x2BC++0x3 line.long 0x00 "FD_ANGLE_i_21,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x2B0++0x3 line.long 0x00 "FD_CENTERX_i_21,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x2B4++0x3 line.long 0x00 "FD_CENTERY_i_21,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x2B8++0x3 line.long 0x00 "FD_CONFSIZE_i_21,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_22" width 18. rgroup.long 0x2CC++0x3 line.long 0x00 "FD_ANGLE_i_22,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x2C0++0x3 line.long 0x00 "FD_CENTERX_i_22,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x2C4++0x3 line.long 0x00 "FD_CENTERY_i_22,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x2C8++0x3 line.long 0x00 "FD_CONFSIZE_i_22,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_23" width 18. rgroup.long 0x2DC++0x3 line.long 0x00 "FD_ANGLE_i_23,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x2D0++0x3 line.long 0x00 "FD_CENTERX_i_23,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x2D4++0x3 line.long 0x00 "FD_CENTERY_i_23,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x2D8++0x3 line.long 0x00 "FD_CONFSIZE_i_23,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_24" width 18. rgroup.long 0x2EC++0x3 line.long 0x00 "FD_ANGLE_i_24,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x2E0++0x3 line.long 0x00 "FD_CENTERX_i_24,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x2E4++0x3 line.long 0x00 "FD_CENTERY_i_24,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x2E8++0x3 line.long 0x00 "FD_CONFSIZE_i_24,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_25" width 18. rgroup.long 0x2FC++0x3 line.long 0x00 "FD_ANGLE_i_25,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x2F0++0x3 line.long 0x00 "FD_CENTERX_i_25,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x2F4++0x3 line.long 0x00 "FD_CENTERY_i_25,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x2F8++0x3 line.long 0x00 "FD_CONFSIZE_i_25,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_26" width 18. rgroup.long 0x30C++0x3 line.long 0x00 "FD_ANGLE_i_26,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x300++0x3 line.long 0x00 "FD_CENTERX_i_26,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x304++0x3 line.long 0x00 "FD_CENTERY_i_26,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x308++0x3 line.long 0x00 "FD_CONFSIZE_i_26,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_27" width 18. rgroup.long 0x31C++0x3 line.long 0x00 "FD_ANGLE_i_27,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x310++0x3 line.long 0x00 "FD_CENTERX_i_27,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x314++0x3 line.long 0x00 "FD_CENTERY_i_27,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x318++0x3 line.long 0x00 "FD_CONFSIZE_i_27,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_28" width 18. rgroup.long 0x32C++0x3 line.long 0x00 "FD_ANGLE_i_28,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x320++0x3 line.long 0x00 "FD_CENTERX_i_28,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x324++0x3 line.long 0x00 "FD_CENTERY_i_28,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x328++0x3 line.long 0x00 "FD_CONFSIZE_i_28,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_29" width 18. rgroup.long 0x33C++0x3 line.long 0x00 "FD_ANGLE_i_29,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x330++0x3 line.long 0x00 "FD_CENTERX_i_29,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x334++0x3 line.long 0x00 "FD_CENTERY_i_29,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x338++0x3 line.long 0x00 "FD_CONFSIZE_i_29,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_30" width 18. rgroup.long 0x34C++0x3 line.long 0x00 "FD_ANGLE_i_30,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x340++0x3 line.long 0x00 "FD_CENTERX_i_30,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x344++0x3 line.long 0x00 "FD_CENTERY_i_30,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x348++0x3 line.long 0x00 "FD_CONFSIZE_i_30,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_31" width 18. rgroup.long 0x35C++0x3 line.long 0x00 "FD_ANGLE_i_31,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x350++0x3 line.long 0x00 "FD_CENTERX_i_31,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x354++0x3 line.long 0x00 "FD_CENTERY_i_31,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x358++0x3 line.long 0x00 "FD_CONFSIZE_i_31,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_32" width 18. rgroup.long 0x36C++0x3 line.long 0x00 "FD_ANGLE_i_32,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x360++0x3 line.long 0x00 "FD_CENTERX_i_32,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x364++0x3 line.long 0x00 "FD_CENTERY_i_32,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x368++0x3 line.long 0x00 "FD_CONFSIZE_i_32,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_33" width 18. rgroup.long 0x37C++0x3 line.long 0x00 "FD_ANGLE_i_33,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x370++0x3 line.long 0x00 "FD_CENTERX_i_33,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x374++0x3 line.long 0x00 "FD_CENTERY_i_33,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x378++0x3 line.long 0x00 "FD_CONFSIZE_i_33,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end tree "Channel_34" width 18. rgroup.long 0x38C++0x3 line.long 0x00 "FD_ANGLE_i_34,Detection Result: Angle. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " ANGLE ,Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)" rgroup.long 0x380++0x3 line.long 0x00 "FD_CENTERX_i_34,Detection Result: X Coordinate. Its value is undefined after reset." hexmask.long.word 0x00 0.--8. 1. " CENTERX ,Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F" rgroup.long 0x384++0x3 line.long 0x00 "FD_CENTERY_i_34,Detection Result: Y Coordinate. Its value is undefined after reset." hexmask.long.byte 0x00 0.--7. 1. " CENTERY ,Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF" rgroup.long 0x388++0x3 line.long 0x00 "FD_CONFSIZE_i_34,Detection Result: Confidence Level and Size. Its value is undefined after reset." bitfld.long 0x00 8.--11. " CONF ,Confidence level Permitted values are 0x0 (high) to 0x9 (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Detection result face size Permitted values 0x14 to 0xF0" tree.end textline "" width 16. rgroup.long 0x0++0x3 line.long 0x00 "FDIF_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision number" rgroup.long 0x4++0x3 line.long 0x00 "FDIF_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." bitfld.long 0x00 0.--3. " FDIF_TAGS ,Hardware design value. This bit field reflects the value of the FDIF_TAG generic parameter. 0x0: 1 tag supported 0x1: 2 tags supported [...] 0xF: 16 tags supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "FDIF_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. - . - . - . - ." "force,no,smart,?..." bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "force,no,smart,?..." bitfld.long 0x00 0. " SOFTRESET ,Software reset. - . - . - . - ." "done_/_noaction,pending_/_reset" group.long 0x60++0x3 line.long 0x00 "FDIF_PICADDR,Picture data store address" hexmask.long 0x00 5.--31. 1. " ADDR ,Picture data store address. The 5 least significant bits are forced to 0." group.long 0x64++0x3 line.long 0x00 "FDIF_CTRL," bitfld.long 0x00 6. " MSTANDBY_HDSHK ,MStandby / Wait power management handshaking status bit The power management framework of the FDIF module is based on the handshaking of the MSTANDBY and WAIT signals. When going from a idle to normal power management transition, the s.." "0,1" bitfld.long 0x00 5. " MSTANDBY ,MStandby signal generation. This bit shall be set to initiate a power management transition from NORMAL to IDLE or IDLE to NORMAL. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " MAX_TAGS ,Max interconnect tags. This bit field sets the maximum number of interconnect tags that the module shall use. This number is programmable between 1 (MAX_TAGS = 0) and FDIF_TAGS (MAX_TAGS = FDIF_TAGS - 1). The value of MAX_TAGS is reflected.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " WRNP ,L3 port non-posted write control. Dynamic usage of this feature is not supported. This bit shall be set at initialization and not modified hereafter until the processing is completed. When non-posted writes are used, tags shall be used.." "0,1" group.long 0x68++0x3 line.long 0x00 "FDIF_WKADDR," hexmask.long 0x00 5.--31. 1. " ADDR ,Work area address The 5 least significant bits are forced to 0." group.long 0x80++0x3 line.long 0x00 "FD_CTRL,Control register Don't set more than 2 bits to '1' at the same time. Otherwise, operations cannot be guaranteed." bitfld.long 0x00 2. " FINISH ,Process Completion Flag Clear - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1. " RUN ,Process Start Request - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " SRST ,Software Reset This bit shall not be used to reset the FDIF module. Instead, the FDIF_SYSCONFIG[0] SOFTRESET bit shall be used for complete soft reset. - . - ." "newEnum1,newEnum2" rgroup.long 0x84++0x3 line.long 0x00 "FD_DNUM,Face Detection Result Count Register" bitfld.long 0x00 0.--5. " DNUM ,Face detection result count. Up to 35 faces can be detected. Number of face(s) detected: 0x0: 0 face detected 0x1: 1 face detected 0x2: 2 faces detected [...] 0x23: 35 faces detected 0x24 to 0x3F: unused" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x88++0x3 line.long 0x00 "FD_DCOND,Detection Condition Setting Register" bitfld.long 0x00 2.--3. " DIR ,Detection direction setting - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" bitfld.long 0x00 0.--1. " MIN ,Reserved - . - . - . - ." "newEnum1,newEnum2,newEnum3,newEnum4" group.long 0x8C++0x3 line.long 0x00 "FD_STARTX,Detection Area Setting Register: X Start Coordinate." hexmask.long.byte 0x00 0.--7. 1. " STARTX ,Starting X coordinates Permitted values are 0&lt;=STARTX&lt;=160" group.long 0x90++0x3 line.long 0x00 "FD_STARTY,Detection Area Setting Register: Y Start Coordinate." hexmask.long.byte 0x00 0.--6. 1. " STARTY ,Starting Y coordinates Permitted values are 0&lt;=STARTY&lt;=120" group.long 0x94++0x3 line.long 0x00 "FD_SIZEX,Detection Area Setting Register: X Direction Size" hexmask.long.word 0x00 0.--8. 1. " SIZEX ,X Direction Size" group.long 0x98++0x3 line.long 0x00 "FD_SIZEY,Detection Area Setting Register: Y Direction Size" hexmask.long.byte 0x00 0.--7. 1. " SIZEY ,Y Direction Size" group.long 0x9C++0x3 line.long 0x00 "FD_LHIT,Threshold Setting Register" bitfld.long 0x00 0.--3. " LHIT ,Threshold Permitted values are 0x0 to 0x9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.end tree.open "Display_Subsystem_Overview" tree.open "DSS_L4_PER" tree "DSS_L4_PER" base ad:0x48040000 width 15. rgroup.long 0x0++0x3 line.long 0x00 "DSS_REVISION,This register contains the DSS revision number." hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" rgroup.long 0x14++0x3 line.long 0x00 "DSS_SYSSTATUS,This register provides status information about the module." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "rstact,rstcomp" group.long 0x40++0x3 line.long 0x00 "DSS_CTRL,This register contains the DSS control bits." bitfld.long 0x00 17. " LCD2_TV_SEL ,Selection between LCD2 and TV channel out on the LCD2 parallel output (multiplexer 13) 0x0: Select LCD2 channel output (default selection) 0x1: Select TV channel output" "0,1" bitfld.long 0x00 15. " VENC_HDMI_SWITCH ,Selects HDMI sync and associated clock or VENC and its associated TV_CLK - . - ." "VENC_Sel,HDMI_Sel" bitfld.long 0x00 14. " RFBI_SWITCH ,Selects the video port from DISPC between video port 1 and video port 2 (multiplexer 11). - . - ." "VP1_Sel,VP2_Sel" textline " " bitfld.long 0x00 13. " SYNC_SWITCH ,Selects the sync generator for SD video (DSS VENC IP, or component VENC IP connected at the top) - . - ." "VENC_INT_Sel,VENC_EXT_Sel" bitfld.long 0x00 12. " LCD2_CLK_SWITCH ,DSS_CLK/PLL2_CLK1 clock switch (multiplexer 3) Selects the clock source for the DISPC LCD2_CLK clock - . - ." "DSS_CLK_Sel,PLL2_CLK1_Sel" bitfld.long 0x00 11. " TV_CLK_SWITCH ,DSS_TV_CLK/PLL3_CLK clock switch Selects the clock source for the VENC/HDMI functional clock - . - ." "DSS_TV_CLK_sel,PLL3_CLK1_Sel" textline " " bitfld.long 0x00 10. " DSI2_CLK_SWITCH ,DSS_CLK/PLL2_CLK2 clock switch Selects the clock source for the DSI2 functional clock DSI2_CLK - . - ." "DSS_CLK_Sel,PLL2_CLK2_Sel" bitfld.long 0x00 8.--9. " FCK_CLK_SWITCH ,Selects the clock source for the DISPC functional clock DISPC_FCLK - . - . - . - ." "DSS_CLK,PLL1_CLK1,PLL2_CLK1,PLL3_CLK1" bitfld.long 0x00 6. " VENC_OUT_SEL ,VENC mode selection for VENC output multiplexer - . - ." "Compoite,S_Video" textline " " bitfld.long 0x00 5. " DAC_POWERDN_BGZ ,DAC Power-down band gap control - . - ." "Disable,Enable" bitfld.long 0x00 4. " DAC_DEMEN ,DAC Dynamic Element Matching Enable - . - ." "Disable,Enable" bitfld.long 0x00 3. " VENC_CLOCK_4X_ENABLE ,VENC clock CLK4X enable This bit is used to control the CLK4X clock gating. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " VENC_CLOCK_MODE ,VENC clock mode. See, . - . - ." "Mode0,Mode1" bitfld.long 0x00 1. " DSI1_CLK_SWITCH ,DSS_CLK/PLL1_CLK2 clock switch Selects the clock source for the DSI1 functional clock DSI1_CLK - . - ." "DSS_CLK_Sel,PLL1_CLK2_Sel" bitfld.long 0x00 0. " LCD1_CLK_SWITCH ,DSS_CLK/PLL1_CLK1 clock switch (multiplexer 2) Selects the clock source for the DISPC LCD1_CLK clock - . - ." "DSS_CLK_Sel,PLL1_CLK1_Sel" rgroup.long 0x5C++0x3 line.long 0x00 "DSS_STATUS,This register contains the DSS status." bitfld.long 0x00 21. " RFBI_STATUS ,Video port selection status (multiplexer 11) Indicates if video port 1 or video 2 from DISPC is used to provide data to the RFBI - . - ." "VP1_Sel,VP2_Sel" bitfld.long 0x00 19.--20. " SYNC_STATUS ,Sync generator selection status (multiplexer 9) Indicates if DSS VENC IP or external component VENC IP is selected as syncs generator (master mode) - . - . - ." "VENC_INT_Sel,VENC_EXT_Sel,HDMI,3" bitfld.long 0x00 15.--18. " FCK_CLK_STATUS ,DISPC_FCLK clock selection status (multiplexer 1), indicates which clock is used by the glitch-free multiplexer selecting the source of DISPC_FCLK. The current and the new-selected clocks must be running to be able to sw.." "DSS_CLK_TRANSITION,DSS_CLK_Sel,PLL1_CLK1_Sel,3,PLL2_CLK1_Sel,5,6,7,TV_CLK_Sel,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--14. " TV_CLK_STATUS ,TV_CLK clock selection status (multiplexer 7), indicates which clock is used by the multiplexer selecting the source of TV_CLK. The current and the new-selected clocks must be running to be able to switch. Both clocks are used at the .." "0,TV_CLK1_sel,PLL3_CLK_sel,3" bitfld.long 0x00 11.--12. " LCD2_CLK_STATUS ,LCD2_CLK clock selection status (multiplexer 3), indicates which clock is used by the glitch-free multiplexer selecting the source of LCD2_CLK. The current and the new-selected clocks must be running to be able to switch. Bo.." "LCD2_CLK_TRANSITION,DSS_CLK_Sel,PLL2_CLK1_Sel,3" bitfld.long 0x00 9.--10. " DSI2_CLK_STATUS ,DSI2_CLK clock selection status (multiplexer 5), indicates which clock is used by the glitch-free multiplexer selecting the source of DSI2_CLK. The current and the new-selected clocks must be running to be able to switch. Both .." "DSI2_CLK_TRANSITION,DSS_CLK_Sel,PLL2_CLK2_Sel,3" textline " " bitfld.long 0x00 7.--8. " DSI1_CLK_STATUS ,DSI1_CLK clock selection status (multiplexer 4), indicates which clock is used by the glitch-free multiplexer selecting the source of DSI1_CLK. The current and the new-selected clocks must be running to be able to switch. Both clocks .." "DSI1_CLK_TRANSITION,DSS_CLK_Sel,PLL1_CLK2_Sel,3" bitfld.long 0x00 5.--6. " TV_CLK_OUT_STATUS ,TV_CLK_OUT selection status (multiplexer 12) indicates which clock is used by the multiplexer selecting the TV_CLK_OUT of the DISPC. The current and the new-selected clocks must be running to be able to switch. Both clocks are used.." "0,DSS_TV_PLL3_CLK1_CLK,HDMI_PCLK,3" bitfld.long 0x00 0.--1. " LCD1_CLK_STATUS ,LCD1_CLK clock selection status (multiplexer 2), indicates which clock is used by the glitch-free multiplexer selecting the source of LCD1_CLK. The current and the new-selected clocks must be running to be able to switch. Both c.." "LCD1_CLK_TRANSITION,DSS_CLK_Sel,PLL1_CLK1_Sel,3" tree.end tree "DSS_L3" base ad:0x58000000 width 15. rgroup.long 0x0++0x3 line.long 0x00 "DSS_REVISION,This register contains the DSS revision number." hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" rgroup.long 0x14++0x3 line.long 0x00 "DSS_SYSSTATUS,This register provides status information about the module." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "rstact,rstcomp" group.long 0x40++0x3 line.long 0x00 "DSS_CTRL,This register contains the DSS control bits." bitfld.long 0x00 17. " LCD2_TV_SEL ,Selection between LCD2 and TV channel out on the LCD2 parallel output (multiplexer 13) 0x0: Select LCD2 channel output (default selection) 0x1: Select TV channel output" "0,1" bitfld.long 0x00 15. " VENC_HDMI_SWITCH ,Selects HDMI sync and associated clock or VENC and its associated TV_CLK - . - ." "VENC_Sel,HDMI_Sel" bitfld.long 0x00 14. " RFBI_SWITCH ,Selects the video port from DISPC between video port 1 and video port 2 (multiplexer 11). - . - ." "VP1_Sel,VP2_Sel" textline " " bitfld.long 0x00 13. " SYNC_SWITCH ,Selects the sync generator for SD video (DSS VENC IP, or component VENC IP connected at the top) - . - ." "VENC_INT_Sel,VENC_EXT_Sel" bitfld.long 0x00 12. " LCD2_CLK_SWITCH ,DSS_CLK/PLL2_CLK1 clock switch (multiplexer 3) Selects the clock source for the DISPC LCD2_CLK clock - . - ." "DSS_CLK_Sel,PLL2_CLK1_Sel" bitfld.long 0x00 11. " TV_CLK_SWITCH ,DSS_TV_CLK/PLL3_CLK clock switch Selects the clock source for the VENC/HDMI functional clock - . - ." "DSS_TV_CLK_sel,PLL3_CLK1_Sel" textline " " bitfld.long 0x00 10. " DSI2_CLK_SWITCH ,DSS_CLK/PLL2_CLK2 clock switch Selects the clock source for the DSI2 functional clock DSI2_CLK - . - ." "DSS_CLK_Sel,PLL2_CLK2_Sel" bitfld.long 0x00 8.--9. " FCK_CLK_SWITCH ,Selects the clock source for the DISPC functional clock DISPC_FCLK - . - . - . - ." "DSS_CLK,PLL1_CLK1,PLL2_CLK1,PLL3_CLK1" bitfld.long 0x00 6. " VENC_OUT_SEL ,VENC mode selection for VENC output multiplexer - . - ." "Compoite,S_Video" textline " " bitfld.long 0x00 5. " DAC_POWERDN_BGZ ,DAC Power-down band gap control - . - ." "Disable,Enable" bitfld.long 0x00 4. " DAC_DEMEN ,DAC Dynamic Element Matching Enable - . - ." "Disable,Enable" bitfld.long 0x00 3. " VENC_CLOCK_4X_ENABLE ,VENC clock CLK4X enable This bit is used to control the CLK4X clock gating. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " VENC_CLOCK_MODE ,VENC clock mode. See, . - . - ." "Mode0,Mode1" bitfld.long 0x00 1. " DSI1_CLK_SWITCH ,DSS_CLK/PLL1_CLK2 clock switch Selects the clock source for the DSI1 functional clock DSI1_CLK - . - ." "DSS_CLK_Sel,PLL1_CLK2_Sel" bitfld.long 0x00 0. " LCD1_CLK_SWITCH ,DSS_CLK/PLL1_CLK1 clock switch (multiplexer 2) Selects the clock source for the DISPC LCD1_CLK clock - . - ." "DSS_CLK_Sel,PLL1_CLK1_Sel" rgroup.long 0x5C++0x3 line.long 0x00 "DSS_STATUS,This register contains the DSS status." bitfld.long 0x00 21. " RFBI_STATUS ,Video port selection status (multiplexer 11) Indicates if video port 1 or video 2 from DISPC is used to provide data to the RFBI - . - ." "VP1_Sel,VP2_Sel" bitfld.long 0x00 19.--20. " SYNC_STATUS ,Sync generator selection status (multiplexer 9) Indicates if DSS VENC IP or external component VENC IP is selected as syncs generator (master mode) - . - . - ." "VENC_INT_Sel,VENC_EXT_Sel,HDMI,3" bitfld.long 0x00 15.--18. " FCK_CLK_STATUS ,DISPC_FCLK clock selection status (multiplexer 1), indicates which clock is used by the glitch-free multiplexer selecting the source of DISPC_FCLK. The current and the new-selected clocks must be running to be able to sw.." "DSS_CLK_TRANSITION,DSS_CLK_Sel,PLL1_CLK1_Sel,3,PLL2_CLK1_Sel,5,6,7,TV_CLK_Sel,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--14. " TV_CLK_STATUS ,TV_CLK clock selection status (multiplexer 7), indicates which clock is used by the multiplexer selecting the source of TV_CLK. The current and the new-selected clocks must be running to be able to switch. Both clocks are used at the .." "0,TV_CLK1_sel,PLL3_CLK_sel,3" bitfld.long 0x00 11.--12. " LCD2_CLK_STATUS ,LCD2_CLK clock selection status (multiplexer 3), indicates which clock is used by the glitch-free multiplexer selecting the source of LCD2_CLK. The current and the new-selected clocks must be running to be able to switch. Bo.." "LCD2_CLK_TRANSITION,DSS_CLK_Sel,PLL2_CLK1_Sel,3" bitfld.long 0x00 9.--10. " DSI2_CLK_STATUS ,DSI2_CLK clock selection status (multiplexer 5), indicates which clock is used by the glitch-free multiplexer selecting the source of DSI2_CLK. The current and the new-selected clocks must be running to be able to switch. Both .." "DSI2_CLK_TRANSITION,DSS_CLK_Sel,PLL2_CLK2_Sel,3" textline " " bitfld.long 0x00 7.--8. " DSI1_CLK_STATUS ,DSI1_CLK clock selection status (multiplexer 4), indicates which clock is used by the glitch-free multiplexer selecting the source of DSI1_CLK. The current and the new-selected clocks must be running to be able to switch. Both clocks .." "DSI1_CLK_TRANSITION,DSS_CLK_Sel,PLL1_CLK2_Sel,3" bitfld.long 0x00 5.--6. " TV_CLK_OUT_STATUS ,TV_CLK_OUT selection status (multiplexer 12) indicates which clock is used by the multiplexer selecting the TV_CLK_OUT of the DISPC. The current and the new-selected clocks must be running to be able to switch. Both clocks are used.." "0,DSS_TV_PLL3_CLK1_CLK,HDMI_PCLK,3" bitfld.long 0x00 0.--1. " LCD1_CLK_STATUS ,LCD1_CLK clock selection status (multiplexer 2), indicates which clock is used by the glitch-free multiplexer selecting the source of LCD1_CLK. The current and the new-selected clocks must be running to be able to switch. Both c.." "LCD1_CLK_TRANSITION,DSS_CLK_Sel,PLL1_CLK1_Sel,3" tree.end tree.end tree.end tree.open "Display_Controller" tree.open "DISPC_L4_PER" tree "DISPC_L4_PER" base ad:0x48041000 tree "Channel_0" width 29. group.long 0x80++0x3 line.long 0x00 "DISPC_GFX_BA_j_0,The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output.." hexmask.long 0x00 0.--31. 1. " BA ,Graphics base address Base address of the graphics buffer (aligned on pixel size boundary) (in case 1-, 2-, and 4-bpp, byte alignment is required, in case of RGB24 packed format, 4-pixel alignment is required) When the TILER is addressed.." group.long 0x640++0x3 line.long 0x00 "DISPC_VID1_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0xE8++0x3 line.long 0x00 "DISPC_VID1_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x600++0x3 line.long 0x00 "DISPC_VID1_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0xBC++0x3 line.long 0x00 "DISPC_VID1_BA_j_0,The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x648++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x64C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF4++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF0++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x688++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E0++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6AC++0x3 line.long 0x00 "DISPC_VID2_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x178++0x3 line.long 0x00 "DISPC_VID2_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x608++0x3 line.long 0x00 "DISPC_VID2_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x14C++0x3 line.long 0x00 "DISPC_VID2_BA_j_0,The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x6B4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6B8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x184++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x180++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6F4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x200++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x728++0x3 line.long 0x00 "DISPC_VID3_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x300++0x3 line.long 0x00 "DISPC_VID3_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x610++0x3 line.long 0x00 "DISPC_VID3_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x308++0x3 line.long 0x00 "DISPC_VID3_BA_j_0,The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x730++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x734++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x314++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x310++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x770++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x350++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x794++0x3 line.long 0x00 "DISPC_WB_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the fiel.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x500++0x3 line.long 0x00 "DISPC_WB_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field p.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x618++0x3 line.long 0x00 "DISPC_WB_BA_UV_j_0,The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 .." hexmask.long 0x00 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x508++0x3 line.long 0x00 "DISPC_WB_BA_j_0,The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.G.." hexmask.long 0x00 0.--31. 1. " BA ,Write-back base address Base address of the WB buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2;0, byte alignment .." group.long 0x7A0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7A4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x514++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x510++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x550++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_1" width 29. group.long 0x84++0x3 line.long 0x00 "DISPC_GFX_BA_j_1,The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output.." hexmask.long 0x00 0.--31. 1. " BA ,Graphics base address Base address of the graphics buffer (aligned on pixel size boundary) (in case 1-, 2-, and 4-bpp, byte alignment is required, in case of RGB24 packed format, 4-pixel alignment is required) When the TILER is addressed.." group.long 0x644++0x3 line.long 0x00 "DISPC_VID1_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0xEC++0x3 line.long 0x00 "DISPC_VID1_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x604++0x3 line.long 0x00 "DISPC_VID1_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0xC0++0x3 line.long 0x00 "DISPC_VID1_BA_j_1,The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x650++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x654++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xFC++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF8++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x68C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E4++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6B0++0x3 line.long 0x00 "DISPC_VID2_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x17C++0x3 line.long 0x00 "DISPC_VID2_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x60C++0x3 line.long 0x00 "DISPC_VID2_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x150++0x3 line.long 0x00 "DISPC_VID2_BA_j_1,The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x6BC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6C0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x18C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x188++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6F8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x204++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x72C++0x3 line.long 0x00 "DISPC_VID3_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x304++0x3 line.long 0x00 "DISPC_VID3_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x614++0x3 line.long 0x00 "DISPC_VID3_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x30C++0x3 line.long 0x00 "DISPC_VID3_BA_j_1,The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x738++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x73C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x31C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x318++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x774++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x354++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x798++0x3 line.long 0x00 "DISPC_WB_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the fiel.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x504++0x3 line.long 0x00 "DISPC_WB_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field p.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x61C++0x3 line.long 0x00 "DISPC_WB_BA_UV_j_1,The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 .." hexmask.long 0x00 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x50C++0x3 line.long 0x00 "DISPC_WB_BA_j_1,The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.G.." hexmask.long 0x00 0.--31. 1. " BA ,Write-back base address Base address of the WB buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2;0, byte alignment .." group.long 0x7A8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7AC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x51C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x518++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x554++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_2" width 29. group.long 0x658++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x65C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x104++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x100++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x690++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E8++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6C4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6C8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x194++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x190++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6FC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x208++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x740++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x744++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x324++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x320++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x778++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x358++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7B0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7B4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x524++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x520++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x558++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_3" width 29. group.long 0x660++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x664++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x10C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x108++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x694++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1EC++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6CC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6D0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x19C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x198++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x700++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x20C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x748++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x74C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x32C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x328++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x77C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x35C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7B8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7BC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x52C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x528++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7EC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x55C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_4" width 29. group.long 0x668++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x66C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x114++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x110++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x698++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1F0++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6D4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6D8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1A4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1A0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x704++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x210++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x750++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x754++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x334++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x330++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x780++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x360++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7C0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7C4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x534++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x530++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7F0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x560++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_5" width 29. group.long 0x670++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x674++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x11C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x118++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x69C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1F4++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6DC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6E0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1AC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1A8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x708++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x214++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x758++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x75C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x33C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x338++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x784++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x364++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7C8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7CC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x53C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x538++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7F4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x564++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_6" width 29. group.long 0x678++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x67C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x124++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x120++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6A0++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1F8++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6E4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6E8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1B4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1B0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x70C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x218++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x760++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x764++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x344++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x340++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x788++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x368++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7D0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7D4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x544++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x540++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7F8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x568++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_7" width 29. group.long 0x680++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x684++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x12C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x128++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6A4++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1FC++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6EC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6F0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1BC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1B8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x710++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x21C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x768++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x76C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x34C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x348++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x78C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x36C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7D8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7DC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x54C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x548++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7FC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x56C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end textline "" width 28. rgroup.long 0x0++0x3 line.long 0x00 "DISPC_REVISION,IP Revision" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "DISPC_SYSCONFIG,This register allows to control various parameters of the OCP interface." bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management, standby/wait control - . - . - . - ." "fStandBy,nStandBy,Sstandby,Res" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period - . - . - . - ." "OCPFuncOff,FuncOff,OCPOff,OCPFuncOn" bitfld.long 0x00 5. " WARMRESET ,Warm reset. Set this bit to 1 triggers a module warm reset. The bit is automatically reset by the hardware. During reads, it always returns 0. The warm reset keep the configuration registers unchanged. - . - ." "Normal,warmreset" textline " " bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, Idle req/ack control - . - . - . - ." "fIdle,nIdle,sIdle,Res" bitfld.long 0x00 2. " ENWAKEUP ,WakeUp feature control - . - ." "WakeUpDis,WakeUpEnb" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "nMode,Rst" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy - . - ." "ClkFree,ClkGated" rgroup.long 0x14++0x3 line.long 0x00 "DISPC_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "rstongoing,rstcomp" group.long 0x18++0x3 line.long 0x00 "DISPC_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt. Write 1 to a given bit resets this bit" eventfld.long 0x00 26. " WBUNCOMPLETEERROR_IRQ ,Write-back DMA buffer is flushed before it is completely drained. In WB capture mode, if the new frame starts before the WB DMA buffers are fully drained (onto external memory), then the contents of the WB DMA buffers .." "false,True" eventfld.long 0x00 25. " WBBUFFER_OVERFLOW_IRQ ,Write-back DMA Buffer Overflow. The DMA buffer is full. - . - ." "0,1" eventfld.long 0x00 24. " FRAME_DONETV_IRQ ,Frame Done for the TV. The TV output has been disabled by user. All the data have been sent. - . - ." "0,1" textline " " eventfld.long 0x00 23. " FRAME_DONEWB_IRQ ,Frame Done for the write-back channel. The write-back channel has output the frame. All the data of the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to b.." "0,1" eventfld.long 0x00 22. " FRAME_DONE2_IRQ ,Frame Done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent. - . - ." "0,1" eventfld.long 0x00 21. " ACBIASCOUNT_STATUS2_IRQ ,AC Bias Count Status for the secondary LCD - . - ." "0,1" textline " " eventfld.long 0x00 20. " VID3BUFFER_UNDERFLOW_IRQ ,Video 3 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" eventfld.long 0x00 19. " VID3END_WINDOW_IRQ ,The end of the video 3 Window has been reached. It is detected by the overlay manager when the full video 3 has been displayed. - . - ." "0,1" eventfld.long 0x00 18. " VSYNC2_IRQ ,Vertical Synchronization for the secondary LCD - . - ." "False,True" textline " " eventfld.long 0x00 17. " SYNC_LOST2_IRQ ,Synchronization Lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output. - . .." "0,1" eventfld.long 0x00 16. " WAKEUP_IRQ ,Wake-up - . - ." "False,True" eventfld.long 0x00 15. " SYNCLOST_TV_IRQ ,Synchronization Lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output. - . - ." "0,1" textline " " eventfld.long 0x00 14. " SYNC_LOST1_IRQ ,Synchronization Lost on the primary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the primary LCD output. - . - ." "0,1" eventfld.long 0x00 13. " VID2END_WINDOW_IRQ ,The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed. - . - ." "0,1" eventfld.long 0x00 12. " VID2BUFFER_UNDERFLOW_IRQ ,Video 2 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" textline " " eventfld.long 0x00 11. " VID1END_WINDOW_IRQ ,The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed. - . - ." "0,1" eventfld.long 0x00 10. " VID1BUFFER_UNDERFLOW_IRQ ,Video 1 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" eventfld.long 0x00 9. " OCPERROR_IRQ ,OCP Error. L3 Interconnect has sent SResp=ERR. - . - ." "False,True" textline " " eventfld.long 0x00 8. " PALETTEGAMMA_LOADING_IRQ ,Palette Gamma Loading status. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded su.." "0,1" eventfld.long 0x00 7. " GFXEND_WINDOW_IRQ ,The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed. - . - ." "0,1" eventfld.long 0x00 6. " GFXBUFFER_UNDERFLOW_IRQ ,Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" textline " " eventfld.long 0x00 5. " PROGRAMMED_LINENUMBER_IRQ ,Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number. - . - ." "0,1" eventfld.long 0x00 4. " ACBIASCOUNT_STATUS1_IRQ ,AC Bias Count Status for the primary LCD - . - ." "0,1" eventfld.long 0x00 3. " EVSYNC__ODD_IRQ ,VSYNC for odd field from the TV encoder (VENC or HDMI) - . - ." "0,1" textline " " eventfld.long 0x00 2. " EVSYNC__EVEN_IRQ ,VSYNC for even field from the TV encoder (VENC or HDMI) - . - ." "0,1" eventfld.long 0x00 1. " VSYNC1_IRQ ,Vertical Synchronization for the primary LCD. - . - ." "False,True" eventfld.long 0x00 0. " FRAME_DONE1_IRQ ,Frame Done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent. - . - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "DISPC_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt, on an event-by-event basis" bitfld.long 0x00 26. " WBUNCOMPLETEERROR_EN ,The write back buffer has been flushed before it has been fully drained. Enable. - . - ." "masked,genint" bitfld.long 0x00 25. " WBBUFFER_OVERFLOW_EN ,Write-back DMA Buffer Overflow. The DMA buffer is full - . - ." "0,1" bitfld.long 0x00 24. " FRAME_DONETV_EN ,Frame Done for the TV. The TV output has been disabled by user. All the data have been sent. - . - ." "0,1" textline " " bitfld.long 0x00 23. " FRAME_DONEWB_EN ,Frame Done for the write-back channel. The write-back channel has output the frame. All the data have been sent for the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-b.." "0,1" bitfld.long 0x00 22. " FRAME_DONE2_EN ,Frame Done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent. - . - ." "0,1" bitfld.long 0x00 21. " ACBIASCOUNT_STATUS2_EN ,AC Bias Count Status for the secondary LCD - . - ." "0,1" textline " " bitfld.long 0x00 20. " VID3BUFFER_UNDERFLOW_EN ,Video 3 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" bitfld.long 0x00 19. " VID3END_WINDOW_EN ,The end of the video 3 Window has been reached. It is detected by the overlay manager when the full video 3 has been displayed. - . - ." "Vid3EndWindow_is_masked,1" bitfld.long 0x00 18. " VSYNC2_EN ,Vertical Synchronization for the secondary LCD - . - ." "masked,genint" textline " " bitfld.long 0x00 17. " SYNC_LOST2_EN ,Synchronization Lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output. - . .." "0,1" bitfld.long 0x00 16. " WAKEUP_EN ,Wake Up Mask - . - ." "masked,genint" bitfld.long 0x00 15. " SYNC_LOSTTV_EN ,Synchronization Lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output. - . - ." "0,1" textline " " bitfld.long 0x00 14. " SYNC_LOST1_EN ,Synchronization Lost for the primary LCD - . - ." "0,1" bitfld.long 0x00 13. " VID2END_WINDOW_EN ,The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed. - . - ." "Vid2EndWindow_is_masked,1" bitfld.long 0x00 12. " VID2BUFFER_UNDERFLOW_EN ,Video 2 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" textline " " bitfld.long 0x00 11. " ENDVID1_WINDOW_EN ,The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed. - . - ." "EndVid1Window_is_masked,1" bitfld.long 0x00 10. " VID1BUFFER_UNDERFLOW_EN ,Video 1 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" bitfld.long 0x00 9. " OCPERROR_EN ,OCP Error. L3 Interconnect has sent SResp=ERR. - . - ." "masked,genint" textline " " bitfld.long 0x00 8. " PALETTE_GAMMA_EN ,Palette Gamma Loading mask. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded succ.." "PaletteGamma_is_masked,1" bitfld.long 0x00 7. " GFXEND_WINDOW_EN ,The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed. - . - ." "GfxEndWindow_is_masked,1" bitfld.long 0x00 6. " GFXBUFFER_UNDERFLOW_EN ,Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" textline " " bitfld.long 0x00 5. " PROGRAMMED_LINENUMBER_EN ,Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number. - . - ." "0,1" bitfld.long 0x00 4. " ACBIASCOUNT_STATUS1_EN ,AC Bias Count Status for the primary LCD - . - ." "0,1" bitfld.long 0x00 3. " EVSYNC_ODD_EN ,VSYNC for odd field from the TV encoder (VENC or HDMI) - . - ." "masked,genint" textline " " bitfld.long 0x00 2. " EVSYNC_EVEN_EN ,VSYNC for even field from the TV encoder (VENC or HDMI) - . - ." "masked,genint" bitfld.long 0x00 1. " VSYNC1_EN ,Vertical Synchronization for the primary LCD. - . - ." "masked,genint" bitfld.long 0x00 0. " FRAMEDONE_EN ,Frame Done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent. - . - ." "masked,genint" group.long 0x40++0x3 line.long 0x00 "DISPC_CONTROL1,The control register configures the Display Controller module for the primary LCD and TV outputs." bitfld.long 0x00 30.--31. " SPATIALTEMPORAL_DITHERINGFRAMES ,Spatial/Temporal dithering number of frames for the primary LCD output wr: VFP start period of primary LCD - . - . - . - ." "Spatial_only,1,2,?..." bitfld.long 0x00 29. " LCDENABLEPOL ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 28. " LCDENABLESIGNAL ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x00 27. " PCKFREEENABLE ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 25.--26. " TDMUNUSEDBITS ,State of unused bits (TDM mode only) for the primary LCD output. wr: VFP start period of primary LCD - . - . - . - ." "LowLevel,HighLevel,Unchanged,Res" bitfld.long 0x00 23.--24. " TDMCYCLEFORMAT ,Cycle format (TDM mode only) for the primary LCD output wr: VFP start period of primary LCD - . - . - . - ." "1CycPerPix,2CycPerPix,3CycPerPix,3CycPer2Pix" textline " " bitfld.long 0x00 21.--22. " TDMPARALLELMODE ,Output Interface width (TDM mode only) for the primary LCD output wr: VFP start period of primary LCD - . - . - . - ." "8bParaInt,9bParaInt,12bParaInt,16bParaInt" bitfld.long 0x00 20. " TDMENABLE ,Enable the multiple cycle format (TDM mode only used for TFT mode with the RFBI enable bit off) for the primary LCD output. wr: VFP start period of primary LCD - . - ." "TDMDis,TDMEnb" bitfld.long 0x00 17.--19. " HT ,Hold Time for TV output wr: EVSYNC Encoded value (from 1 to 8) to specify the number of external digital clock periods to hold the data (programmed value = value minus 1)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16. " GPOUT1 ,General Purpose Output Signal wr:immediate - . - ." "reset,set" bitfld.long 0x00 15. " GPOUT0 ,General Purpose Output Signal wr:immediate - . - ." "reset,set" bitfld.long 0x00 14. " GPIN1 ,General Purpose Input Signal wr: immediately - . - ." "reset,set" textline " " bitfld.long 0x00 13. " GPIN0 ,General Purpose Input Signal wr: immediately - . - ." "GPin0Rst,GPin0Set" bitfld.long 0x00 12. " OVERLAYOPTI_MIZATION ,Overlay Optimization for the primary LCD output wr: VFP start period of the primary LCD - . - ." "0,1" bitfld.long 0x00 11. " STALLMODE ,STALL Mode for the primary LCD output wr: VFP start period of primary LCD - . - ." "nMode,RFBIMode" textline " " bitfld.long 0x00 8.--9. " TFTDATALINES ,Number of lines of the primary LCD interface wr: VFP start period of primary LCD - . - . - . - ." "OaLSB12b,OaLSB16b,OaLSB18b,OaLSB24b" bitfld.long 0x00 7. " STDITHERENABLE ,Spatial Temporal dithering enable for the primary LCD output wr: VFP start period of primary LCD - . - ." "STDithDis,STDithEnb" bitfld.long 0x00 6. " GOTV ,GO Command for the TV output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the TV output. wr: immediate - . - ." "HfUISR,UfPSR" textline " " bitfld.long 0x00 5. " GOLCD ,GO Command for the primary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the primary LCD output. wr: immediate - . - ." "HfUISR,UfPSR" bitfld.long 0x00 4. " M8B ,Mono 8-bit mode of the primary LCD wr: VFP start period of primary LCD output - . - ." "4PixtoPanel,8PixtoPanel" bitfld.long 0x00 3. " STNTFT ,LCD Display type of the primary LCD wr: VFP start period of primary LCD output - . - ." "STNdispEnb,ATFTDisEnb" textline " " bitfld.long 0x00 2. " MONOCOLOR ,Monochrome/Color selection for the primary LCD wr: VFP start period of primary LCD output - . - ." "ColOpEnb,MonOpEnb" bitfld.long 0x00 1. " TVENABLE ,Enable the TV output wr: immediate effect only occurs at the end of the current frame. - . - ." "DigOpDis,DigOpEnb" bitfld.long 0x00 0. " LCDENABLE ,Enable the primary LCD outputs wr: immediate Effect only occurs at the end of the current frame - . - ." "LCDOpDis,LCDOpEnb" group.long 0x44++0x3 line.long 0x00 "DISPC_CONFIG1,The control register configures the Display Controller module for the primary LCD output and TV output. Shadow register, updated on VFP start period of primary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is fin.." bitfld.long 0x00 25. " FULLRANGE ,Color Space Conversion full range setting. wr: VFP start of primary LCD - . - ." "Limrange,FullRange" bitfld.long 0x00 24. " COLORCONV_ENABLE ,Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1. wr: VFP start of primary LCD - . - ." "0,1" bitfld.long 0x00 23. " FIDFIRST ,Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. wr: VFP start of primary LCD - . - ." "Even,Odd" textline " " bitfld.long 0x00 22. " OUTPUTMODE_ENABLE ,Selects between progressive and interlace mode for the primary LCD output. wr: VFP start of primary LCD - . - ." "0,Interlace_mode_selected." bitfld.long 0x00 19. " TVALPHABLENDER_ENABLE ,Selects the alpha blender overlay manager for the TV output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-.." "0,1" bitfld.long 0x00 18. " LCDALPHABLENDER_ENABLE ,Selects the alpha blender overlay manager for the primary LCD output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility o.." "0,1" textline " " bitfld.long 0x00 17. " BUFFERFILLING ,Controls if the DMA buffers are refilled only when the LOW threshold is reached or if all DMA buffers are refilled when at least one of them reaches the LOW threshold. wr: immediate - . - ." "FIFOfillingDis,FIFOfillingEnb" bitfld.long 0x00 16. " BUFFERHAND_CHECK ,Controls the handcheck between DMA buffer and STALL signal in order to prevent from underflow. The bit shall be set to 0 when the module is not in STALL mode. (primary LCD output) wr: VFP start of primary LCD - . -.." "0,1" bitfld.long 0x00 15. " CPR ,Color Phase Rotation Control (primary LCD output). It shall be reset when ColorConvEnable bit field is set to 1 wr: VFP start period of primary LCD output - . - ." "CPRDis,CPREnb" textline " " bitfld.long 0x00 14. " BUFFERMERGE ,Buffer merge control wr: EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output us.." "MergeDis,MergeEnb" bitfld.long 0x00 13. " TCKTV_SELECTION ,Transparency Color Key Selection (TV output) wr: EVSYNC - . - ." "0,1" bitfld.long 0x00 12. " TCKTVENABLE ,Transparency Color Key Enabled (TV output) wr: EVSYNC - . - ." "DisTCK,EnbTCK" textline " " bitfld.long 0x00 11. " TCKLCD_SELECTION ,Transparency Color Key Selection (primary LCD output) wr: VFP start period of primary LCD output - . - ." "0,1" bitfld.long 0x00 10. " TCKLCDENABLE ,Transparency Color Key Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "DisTCK,EnbTCK" bitfld.long 0x00 9. " GAMATABLE_ENABLE ,For backward compatibility, an enable bit has been added on the 2 additional gamma tables (secondary display and TV). Gamma table of LCD1 is always enabled. - . - ." "0,1" textline " " bitfld.long 0x00 8. " ACBIASGATED ,ACBias Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "ACBGDis,ACBGEnb" bitfld.long 0x00 7. " VSYNCGATED ,VSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "VGDis,VGEnb" bitfld.long 0x00 6. " HSYNCGATED ,HSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "HGDis,HGEnb" textline " " bitfld.long 0x00 5. " PIXELCLOCK_GATED ,Pixel Clock Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "0,1" bitfld.long 0x00 4. " PIXELDATAGATED ,Pixel Data Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "PDGDis,PDGEnb" bitfld.long 0x00 3. " PALETTEGAMMA_TABLE ,Palette/Gamma Table selection wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finis.." "0,1" textline " " bitfld.long 0x00 1.--2. " LOADMODE ,Loading Mode for the Palette/Gamma Table wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finis.." "PgTabLeFr,PgTabUsetb,FrDatLeFr,DLoFrSw" bitfld.long 0x00 0. " PIXELGATED ,Pixel Gated Enable (only for TFT) (primary LCD output) wr: VFP start period of primary LCD output - . - ." "PclkTogA,PclkTogV" group.long 0x4C++0x3 line.long 0x00 "DISPC_DEFAULT_COLOR0,The control register allows to configure the default solid background color for the primary LCD. Shadow register, updated on VFP start period of the primary LCD" hexmask.long.tbyte 0x00 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays." group.long 0x50++0x3 line.long 0x00 "DISPC_DEFAULT_COLOR1,The control register allows to configure the default solid background color for the TV output. Shadow register, updated on EVSYNC" hexmask.long.tbyte 0x00 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays." group.long 0x54++0x3 line.long 0x00 "DISPC_TRANS_COLOR0,The register sets the transparency color value for the video/graphics overlays for the primary LCD output. Shadow register, updated on VFP start period of the primary LCD" hexmask.long.tbyte 0x00 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [2.." group.long 0x58++0x3 line.long 0x00 "DISPC_TRANS_COLOR1,The register sets the transparency color value for the video/graphics overlays for the TV output. Shadow register, updated on EVSYNC" hexmask.long.tbyte 0x00 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [2.." rgroup.long 0x5C++0x3 line.long 0x00 "DISPC_LINE_STATUS,The control register indicates the current primary LCD panel display line number." hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,Current LCD panel line number Current display line number. The first active line has the value 0. During blanking lines the line number is not incremented." group.long 0x60++0x3 line.long 0x00 "DISPC_LINE_NUMBER,The control register indicates the primary LCD panel display line number for the interrupt and the DMA request. Shadow register, updated on VFP start period of primary LCD." hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs." group.long 0x64++0x3 line.long 0x00 "DISPC_TIMING_H1,The register configures the timing logic for the HSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 20.--31. 1. " HBP ,Horizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to valu.." hexmask.long.word 0x00 8.--19. 1. " HFP ,Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1). When .." hexmask.long.byte 0x00 0.--7. 1. " HSW ,Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1). When in BT mode.." group.long 0x68++0x3 line.long 0x00 "DISPC_TIMING_V1,The register configures the timing logic for the VSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 20.--31. 1. " VBP ,Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame." hexmask.long.word 0x00 8.--19. 1. " VFP ,Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame." hexmask.long.byte 0x00 0.--7. 1. " VSW ,Vertical synchronization pulse width In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of .." group.long 0x6C++0x3 line.long 0x00 "DISPC_POL_FREQ1,The register configures the signal configuration. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD." bitfld.long 0x00 18. " ALIGN ,Defines the alignment between HSYNC and VSYNC assertion. - . - ." "notAligned,Aligned" bitfld.long 0x00 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/Off - . - ." "DOpEdPCk,DBit16" bitfld.long 0x00 16. " RF ,Program HSYNC/VSYNC Rise or Fall - . - ." "DFEdPCk,DRiEdPCk" textline " " bitfld.long 0x00 15. " IEO ,Invert output enable - . - ." "ACBaHigh,ACBaLow" bitfld.long 0x00 14. " IPC ,Invert pixel clock - . - ." "DrPCk,DfPCk" bitfld.long 0x00 13. " IHS ,Invert HSYNC - . - ." "LCkpinAh,LCkpinAl" textline " " bitfld.long 0x00 12. " IVS ,Invert VSYNC - . - ." "FCkpinAh,FCkpinAl" bitfld.long 0x00 8.--11. " ACBI ,AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " ACB ,AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supp.." group.long 0x70++0x3 line.long 0x00 "DISPC_DIVISOR1,The register configures the divisors. It is used for the primary LCD output Shadow register, updated on VFP start period of primary LCD" hexmask.long.byte 0x00 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD1_CLK. The value 0 is invalid." hexmask.long.byte 0x00 0.--7. 1. " PCD ,Pixel Clock Divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD1_CLK divided byDISPC_DIVISOR1.LCD value. The values 0 is invalid." group.long 0x74++0x3 line.long 0x00 "DISPC_GLOBAL_ALPHA,The register defines the global alpha value for the graphics and three video pipelines. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by softwa.." hexmask.long.byte 0x00 24.--31. 1. " VID3GLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." hexmask.long.byte 0x00 16.--23. 1. " VID2GLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." hexmask.long.byte 0x00 8.--15. 1. " VID1GLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." textline " " hexmask.long.byte 0x00 0.--7. 1. " GFXGLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." group.long 0x78++0x3 line.long 0x00 "DISPC_SIZE_TV,The register configures the size of the TV output field (interlace), frame (progressive) (horizontal and vertical). Shadow register, updated on EVSYNC. A delta value is used to indicate if the odd field has same vertical size as the even .." hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel (LPP). Encoded value (from 1 to 2048) to specify the number of LPP." bitfld.long 0x00 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field - . - . - ." "same,PlusOne,MinusOne,3" hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display." group.long 0x7C++0x3 line.long 0x00 "DISPC_SIZE_LCD1,The register configures the panel size (horizontal and vertical). Shadow register, updated on VFP start period of primary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel Encoded value (from 1 to 2048) to specify the number of lines per panel (program to value minus 1)." bitfld.long 0x00 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field - . - . - ." "Same,PlusOne,MinusOne,3" hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only va.." group.long 0x88++0x3 line.long 0x00 "DISPC_GFX_POSITION,The register configures the position of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is .." hexmask.long.word 0x00 16.--26. 1. " POSY ,Y position of the graphics window. Encoded value (from 0 to 2047) to specify the Y position of the graphics window on the screen. The line at the top has the Y-position 0." hexmask.long.word 0x00 0.--10. 1. " POSX ,X position of the graphics window. Encoded value (from 0 to 2047) to specify the X position of the graphics window on the screen. The first pixel on the left of the screen has the X-position 0." group.long 0x8C++0x3 line.long 0x00 "DISPC_GFX_SIZE,The register configures the size of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished.." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the graphics window. Encoded value (from 1 to 2048) to specify the number of lines of the graphics window (program to value minus 1)." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the graphics window. Encoded value (from 1 to 2048) to specify the number of pixels per line of the graphics window (program to value minus 1)." group.long 0xA0++0x3 line.long 0x00 "DISPC_GFX_ATTRIBUTES,The register configures the graphics attributes. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (.." bitfld.long 0x00 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero) wr: immediate - . - . - ." "PrimaryLCDSel,SecondaryLCDSel,2,WriteBacksel1" bitfld.long 0x00 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. (It does not apply to the palette loading OCP requests using INCR burst only) - .." "INC,BLCK" bitfld.long 0x00 28. " PREMULTIPLYALPHA ,The field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data. - . - ." "0,1" textline " " bitfld.long 0x00 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is s.." "zorder0,zorder1,zorder2,zorder3" bitfld.long 0x00 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled. - . - ." "ZorderDis,ZorderEnb" bitfld.long 0x00 24. " ANTIFLICKER ,Antiflicker filtering using a 3-tap filter with hardcoded coefficients (1/4, 1/2, 1/4) - . - ." "AFDis,AFEnb" textline " " bitfld.long 0x00 17. " SELFREFRESHAUTO ,Automatic self-refresh mode - . - ." "SelfRefreshAutoDis,SelfRefreshAutoEn" bitfld.long 0x00 15. " SELFREFRESH ,Enables the self refresh of the graphics window from its own DMA buffer. This bit should be set only after having set the GO bit of the channel and read back a zero in its field. - . - ." "SelfRefreshDis,SelfRefreshEnb" bitfld.long 0x00 14. " ARBITRATION ,Determines the priority of the graphics pipeline. When the graphics pipeline is one of the high priority pipelines. The arbitration wheel gives always the priority first to the high priority pipelines using round-ro.." "NormalPrio,HighPrio" textline " " bitfld.long 0x00 12.--13. " ROTATION ,Graphics Rotation Flag - . - . - . - ." "NoRot,Rot90,Rot180,Rot270" bitfld.long 0x00 11. " BUFPRELOAD ,Graphics Preload Value - . - ." "DefVal,HighThres" bitfld.long 0x00 9. " NIBBLEMODE ,Graphics Nibble Mode (only for 1-, 2- and 4-bpp) - . - ." "NibMDis,NibMEnb" textline " " bitfld.long 0x00 8. " CHANNELOUT ,Graphics Channel Out configuration: LCD, WB or TV. wr: immediate - . - ." "LCDOpSel,TVOpSel" bitfld.long 0x00 6.--7. " BURSTSIZE ,Graphics DMA Burst Size - . - . - . - ." "Burst2x128,Burst4x128,Burst8x128,Res" bitfld.long 0x00 5. " REPLICATIONENABLE ,Graphics Replication Enabled: RGB . ARGB, and RGBA formats are converted into ARGB32-8888 using replication of the MSBs or '0s - . - ." "GRLogEnb,GRLogDis" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Graphics format. It defines the pixel format when fetching the graphics picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "BitMap1,BitMap2,BitMap4,BitMap8,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24p,RGBx12,RGBA12,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,Graphics Enable - . - ." "GraphicsDis,GraphicsEnb" group.long 0xA4++0x3 line.long 0x00 "DISPC_GFX_BUF_THRESHOLD,The register configures the graphics buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (n.." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer Low Threshold Number of 128-bits defining the threshold value. The value put is this register should always be greater than zero." rgroup.long 0xA8++0x3 line.long 0x00 "DISPC_GFX_BUF_SIZE_STATUS,The register defines the Graphics buffer size" hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,DMA buffer Size in number of 128-bits" group.long 0xAC++0x3 line.long 0x00 "DISPC_GFX_ROW_INC,The register configures the number of bytes to increment at the end of the row. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and cu.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded unsigned value to specify the number of bytes to increment at the end of the row in the graphics buffer. The value 0 is invalid. The value 1 means next pixel. .." group.long 0xB0++0x3 line.long 0x00 "DISPC_GFX_PIXEL_INC,The register configures the number of bytes to increment between two pixels. For more information, see, Predecimation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the graphics buffer. The value 0 is invalid. The value 1 means next pixel. Th.." group.long 0xB8++0x3 line.long 0x00 "DISPC_GFX_TABLE_BA,The register configures the base address of the palette buffer or the gamma table buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by soft.." hexmask.long 0x00 0.--31. 1. " TABLEBA ,Base address of the palette/gamma table buffer (24-bit entries in 32-bit containers, aligned on 32-bit boundary)." group.long 0xC4++0x3 line.long 0x00 "DISPC_VID1_POSITION,The register configures the position of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is .." hexmask.long.word 0x00 16.--26. 1. " POSY ,Y position of the video window 1 Encoded value (from 0 to 2047) to specify the Y position of the video window 1 .The line at the top has the Y-position 0." hexmask.long.word 0x00 0.--10. 1. " POSX ,X position of the video window 1 Encoded value (from 0 to 2047) to specify the X position of the video window 1. The first pixel on the left of the display screen has the X-position 0." group.long 0xC8++0x3 line.long 0x00 "DISPC_VID1_SIZE,The register configures the size of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished.." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the video 1 Encoded value (from 1 to 2048) to specify the number of lines of the video window 1. Program to value minus 1." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the video window 1 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 1. Program to value minus 1." group.long 0xCC++0x3 line.long 0x00 "DISPC_VID1_ATTRIBUTES,The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame.." bitfld.long 0x00 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate - . - . - ." "PrimaryLCDSel,SecondaryLCDSel,2,WriteBacksel1" bitfld.long 0x00 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. - . - ." "INC,BLCK" bitfld.long 0x00 28. " PREMULTIPHYALPHA ,The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data. - . - ." "0,1" textline " " bitfld.long 0x00 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is s.." "zorder0,zorder1,zorder2,zorder3" bitfld.long 0x00 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled. - . - ." "ZorderDis,ZorderEnb" bitfld.long 0x00 24. " SELFREFRESH ,Enables the self refresh of the video window from its own DMA buffer only. - . - ." "SelfRefreshDis,SelfRefreshEnb" textline " " bitfld.long 0x00 23. " ARBITRATION ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. Whe.." "NormalPrio,HighPrio" bitfld.long 0x00 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0. - . - ." "Initial,Double" bitfld.long 0x00 21. " VERTICALTAPS ,Video Vertical Resize Tap Number. The vertical polyphase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps, the maximum input picture width is double while using 3-tap .." "taps3,taps5" textline " " bitfld.long 0x00 20. " DMAOPTIMIZATION ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 19. " BUFPRELOAD ,Video Preload Value - . - ." "DefVal,HighThres" bitfld.long 0x00 17. " SELFREFRESHAUTO ,Automatic self-refresh mode - . - ." "SelfRefreshAutoDis,SelfRefreshAutoEn" textline " " bitfld.long 0x00 16. " CHANNELOUT ,Video Channel Out configuration: LCD, WB or TV. wr: immediate - . - ." "LCDOp,TVOp" bitfld.long 0x00 14.--15. " BURSTSIZE ,Video DMA Burst Size - . - . - . - ." "Burst2x128b,Burst4x128b,Burst8x128b,Res" bitfld.long 0x00 12.--13. " ROTATION ,Video Rotation Flag - . - . - . - ." "NoRot,Rot90,Rot180,Rot270" textline " " bitfld.long 0x00 11. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 10. " REPLICATIONENABLE ,Replication Enable - . - ." "VRepLDis,VRepLEnb" bitfld.long 0x00 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV. - . - ." "ColSpCDis,ColSpCEnb" textline " " bitfld.long 0x00 8. " VRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 7. " HRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 5.--6. " RESIZEENABLE ,Video Resize Enable - . - . - . - ." "ReSizeProc,HReSize,2,3" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Video Format. It defines the pixel format when fetching the video 1 picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "NV12,RGBx12,RGBA12,3,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24p,YUV2,UYVY,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,Video Enable - . - ." "VideoDis,VideoEnb" group.long 0xD0++0x3 line.long 0x00 "DISPC_VID1_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software .." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,Video DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." rgroup.long 0xD4++0x3 line.long 0x00 "DISPC_VID1_BUF_SIZE_STATUS,The register defines the Video buffer size for the video pipeline 1." hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,Video 1 DMA buffer Size in number of 128-bits" group.long 0xD8++0x3 line.long 0x00 "DISPC_VID1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means ne.." group.long 0xDC++0x3 line.long 0x00 "DISPC_VID1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation. The register is used only when the TILER is not present in the.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The v.." group.long 0xE0++0x3 line.long 0x00 "DISPC_VID1_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secon.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0xE4++0x3 line.long 0x00 "DISPC_VID1_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 1 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or wh.." hexmask.long.word 0x00 16.--26. 1. " ORGSIZEY ,Number of lines of the video picture. Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of.." hexmask.long.word 0x00 0.--10. 1. " ORGSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line .." group.long 0x130++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x134++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GY ,GY Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RCB ,RCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x138++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GCB ,GCb Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " GCR ,GCr Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x13C++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " BCR ,BCr coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " BY ,BY coefficient Encoded signed value (from -1024 to 1023)." group.long 0x140++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 0.--10. 1. " BCB ,BCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x154++0x3 line.long 0x00 "DISPC_VID2_POSITION,The register configures the position of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is .." hexmask.long.word 0x00 16.--26. 1. " POSY ,Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0." hexmask.long.word 0x00 0.--10. 1. " POSX ,X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0." group.long 0x158++0x3 line.long 0x00 "DISPC_VID2_SIZE,The register configures the size of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished.." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the video 2 Encoded value (from 1 to 2048) to specify the number of lines of the video window 2. Program to value minus 1." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the video window 2 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 2. Program to value minus 1." group.long 0x15C++0x3 line.long 0x00 "DISPC_VID2_ATTRIBUTES,The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame.." bitfld.long 0x00 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero) - . - . - ." "PrimaryLCDSel,SecondaryLCDSel,2,WriteBacksel1" bitfld.long 0x00 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. - . - ." "INC,BLCK" bitfld.long 0x00 28. " PREMULTIPLYALPHA ,The field configures the DISPC VID2 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data. - . - ." "0,1" textline " " bitfld.long 0x00 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is s.." "zorder0,zorder1,zorder2,zorder3" bitfld.long 0x00 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled. - . - ." "ZorderDis,ZorderEnb" bitfld.long 0x00 24. " SELFREFRESH ,Enables the self refresh of the video window from its own DMA buffer only. - . - ." "SelfRefreshDis,SelfRefreshEnb" textline " " bitfld.long 0x00 23. " ARBITRATION ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. Whe.." "NormalPrio,HighPrio" bitfld.long 0x00 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0. - . - ." "Initial,Double" bitfld.long 0x00 21. " VERTICALTAPS ,Video Vertical Resize Tap Number - . - ." "taps3,taps5" textline " " bitfld.long 0x00 20. " DMAOPTIMIZATION ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 19. " BUFPRELOAD ,Video Preload Value - . - ." "DefVal,HighThres" bitfld.long 0x00 17. " SELFREFRESHAUTO ,Automatic self-refresh mode - . - ." "SelfRefreshAutoDis,SelfRefreshAutoEn" textline " " bitfld.long 0x00 16. " CHANNELOUT ,Video Channel Out configuration: LCD, WB or TV. wr: immediate - . - ." "LCDOp,TVOp" bitfld.long 0x00 14.--15. " BURSTSIZE ,Video DMA Burst Size - . - . - . - ." "Burst2x128b,Burst4x128b,Burst8x128b,Res" bitfld.long 0x00 12.--13. " ROTATION ,Video Rotation Flag - . - . - . - ." "NoRot,Rot90,Rot180,Rot270" textline " " bitfld.long 0x00 11. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 10. " REPLICATIONENABLE ,Replication Enable - . - ." "VRepLDis,VRepLEnb" bitfld.long 0x00 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV. - . - ." "ColSpCDis,ColSpCEnb" textline " " bitfld.long 0x00 8. " VRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 7. " HRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 5.--6. " RESIZEENABLE ,Video Resize Enable - . - . - . - ." "ReSizeProc,HReSize,2,3" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Video Format. It defines the pixel format when fetching the video 2 picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "NV12,RGBx12,RGBA12,3,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24,YUV2,UYVY,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,VidEnable - . - ." "VideoDis,VideoEnb" group.long 0x160++0x3 line.long 0x00 "DISPC_VID2_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software an.." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." rgroup.long 0x164++0x3 line.long 0x00 "DISPC_VID2_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 2." hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,DMA buffer size in number of 128 bits" group.long 0x168++0x3 line.long 0x00 "DISPC_VID2_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means ne.." group.long 0x16C++0x3 line.long 0x00 "DISPC_VID2_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation. The register is used only when the TILER is not present in the.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The v.." group.long 0x170++0x3 line.long 0x00 "DISPC_VID2_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secon.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x174++0x3 line.long 0x00 "DISPC_VID2_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 2 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or wh.." hexmask.long.word 0x00 16.--26. 1. " ORGSIZEY ,Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of .." hexmask.long.word 0x00 0.--10. 1. " ORGSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line .." group.long 0x1C0++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1C4++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GY ,GY Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RCB ,RCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1C8++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GCB ,GCb Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " GCR ,GCr Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1CC++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " BCR ,BCr coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " BY ,BY coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1D0++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 0.--10. 1. " BCB ,BCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1D4++0x3 line.long 0x00 "DISPC_DATA1_CYCLE1,The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of primary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x1D8++0x3 line.long 0x00 "DISPC_DATA1_CYCLE2,The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of primary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x1DC++0x3 line.long 0x00 "DISPC_DATA1_CYCLE3,The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of primary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x220++0x3 line.long 0x00 "DISPC_CPR1_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 22.--31. 1. " RR ,RR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " RG ,RG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " RB ,RB Coefficient Encoded signed value (from -512 to 511)." group.long 0x224++0x3 line.long 0x00 "DISPC_CPR1_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 22.--31. 1. " GR ,GR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " GG ,GG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " GB ,GB Coefficient Encoded signed value (from -512 to 511)." group.long 0x228++0x3 line.long 0x00 "DISPC_CPR1_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 22.--31. 1. " BR ,BR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " BG ,BG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " BB ,BB Coefficient Encoded signed value (from -512 to 511)." group.long 0x22C++0x3 line.long 0x00 "DISPC_GFX_PRELOAD,The register configures the graphics DMA buffer Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no m.." hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." group.long 0x230++0x3 line.long 0x00 "DISPC_VID1_PRELOAD,The register configures the DMA buffer of the video 1 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame .." hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." group.long 0x234++0x3 line.long 0x00 "DISPC_VID2_PRELOAD,The register configures the DMA buffer of the video 2 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame .." hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." group.long 0x238++0x3 line.long 0x00 "DISPC_CONTROL2,The control register configures the Display Controller module for the secondary LCD output. Shadow registers are updated during the VFP start period of the secondary LCD, EVSYNC, or when.GOWB is set to 1 by software and the current WB fr.." bitfld.long 0x00 30.--31. " SPATIALTEMPORAL_DITHERINGFRAMES ,Spatial/Temporal dithering number of frames for the secondary LCD output wr: VFP start period of secondary LCD output - . - . - . - ." "Spatial_only,1,2,?..." bitfld.long 0x00 25.--26. " TDMUNUSED_BITS ,State of unused bits (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - . - . - . - ." "low_level_(0),high_level_(1),2,?..." bitfld.long 0x00 23.--24. " TDMCYCLE_FORMAT ,Cycle format (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 21.--22. " TDMPARALLEL_MODE ,Output Interface width (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " TDMENABLE ,Enable the multiple cycle format (TDM mode only used for Active Matrix mode with the RFBI enable bit off) for the secondary LCD output wr: VFP start period of secondary LCD output - . - ." "TDMDis,TDMEnb" bitfld.long 0x00 13. " TVOVERLAY_OPTIMIZATION ,Overlay Optimization for the TV output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization eve.." "0,1" textline " " bitfld.long 0x00 12. " OVERLAY_OPTIMIZATION ,Overlay Optimization for the secondary LCD output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization eve.." "0,1" bitfld.long 0x00 11. " STALLMODE ,STALL Mode for the secondary LCD output wr: VFP start period of secondary LCD output - . - ." "nMode,RFBIMode" bitfld.long 0x00 8.--9. " TFTDATALINES ,Number of lines of the secondary LCD interface wr: VFP start period of secondary LCD output - . - . - . - ." "OaLSB12b,OaLSB16b,OaLSB18b,OaLSB24b" textline " " bitfld.long 0x00 7. " STDITHER_ENABLE ,Spatial Temporal dithering enable for the secondary LCD output wr: VFP start period of secondary LCD output - . - ." "0,1" bitfld.long 0x00 6. " GOWB ,GO Command for the write-back output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the write-back output to the memory. wr:immediate - . - ." "HfUISR,UfPSR" bitfld.long 0x00 5. " GOLCD ,GO Command for the secondary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the secondary LCD output. wr:immediate - . - ." "HfUISR,UfPSR" textline " " bitfld.long 0x00 4. " M8B ,Mono 8-bit mode of the secondary LCD wr: VFP start period of secondary LCD output - . - ." "4PixtoPanel,8PixtoPanel" bitfld.long 0x00 3. " STNTFT ,LCD Display type of the secondary LCD wr: VFP start period of secondary LCD output - . - ." "STNdispEnb,ATFTDisEnb" bitfld.long 0x00 2. " MONOCOLOR ,Monochrome/Color selection for the secondary LCD wr: VFP start period of secondary LCD output - . - ." "ColOpEnb,MonOpEnb" textline " " bitfld.long 0x00 0. " LCDENABLE ,Enable the secondary LCD output wr:immediate - . - ." "LCDOpDis,LCDOpEnb" group.long 0x370++0x3 line.long 0x00 "DISPC_VID3_ATTRIBUTES,The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame.." bitfld.long 0x00 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate - . - . - ." "PrimaryLCDSel,SecondaryLCDSel,2,WriteBacksel1" bitfld.long 0x00 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. - . - ." "INC,BLCK" bitfld.long 0x00 28. " PREMULTIPLYALPHA ,The field configures the DISPC VID3 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data. - . - ." "0,1" textline " " bitfld.long 0x00 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is s.." "zorder0,zorder1,zorder2,zorder3" bitfld.long 0x00 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled. - . - ." "ZorderDis,ZorderEnb" bitfld.long 0x00 24. " SELFREFRESH ,Enables the self refresh of the video window from its own DMA buffer only. - . - ." "SelfRefreshDis,SelfRefreshEnb" textline " " bitfld.long 0x00 23. " ARBITRATION ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. Whe.." "NormalPrio,HighPrio" bitfld.long 0x00 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0. - . - ." "Initial,Double" bitfld.long 0x00 21. " VERTICALTAPS ,Video Vertical Resize Tap Number - . - ." "taps3,taps5" textline " " bitfld.long 0x00 20. " DMAOPTIMIZATION ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 19. " BUFPRELOAD ,Video Preload Value - . - ." "DefVal,HighThres" bitfld.long 0x00 17. " SELFREFRESHAUTO ,Automatic self-refresh mode - . - ." "SelfRefreshAutoDis,SelfrefreshAutoEn" textline " " bitfld.long 0x00 16. " CHANNELOUT ,Video Channel Out configuration: LCD, WB or TV. wr: immediate - . - ." "LCDOp,TVOp" bitfld.long 0x00 14.--15. " BURSTSIZE ,Video DMA Burst Size - . - . - . - ." "Burst2x128b,Burst4x128b,Burst8x128b,Res" bitfld.long 0x00 12.--13. " ROTATION ,Video Rotation Flag - . - . - . - ." "NoRot,Rot90,Rot180,Rot270" textline " " bitfld.long 0x00 11. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 10. " REPLICATIONENABLE ,Replication Enable - . - ." "VRepLDis,VRepLEnb" bitfld.long 0x00 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV. - . - ." "ColSpCDis,ColSpCEnb" textline " " bitfld.long 0x00 8. " VRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 7. " HRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 5.--6. " RESIZEENABLE ,Video Resize Enable - . - . - . - ." "ReSizeProc,HReSize,2,3" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Video Format. It defines the pixel format when fetching the video 3 picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "NV12,RGBx12,RGBA12,3,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24,YUV2,UYVY,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,Video Enable - . - ." "VideoDis,VideoEnb" group.long 0x374++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x378++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GY ,GY Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RCB ,RCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x37C++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GCB ,GCb Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " GCR ,GCr Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x380++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " BCR ,BCr coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " BY ,BY coefficient Encoded signed value (from -1024 to 1023)." group.long 0x384++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 0.--10. 1. " BCB ,BCb Coefficient Encoded signed value (from -1024 to 1023)." rgroup.long 0x388++0x3 line.long 0x00 "DISPC_VID3_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 3." hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,DMA buffer Size in number of 128-bits." group.long 0x38C++0x3 line.long 0x00 "DISPC_VID3_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software an.." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." group.long 0x390++0x3 line.long 0x00 "DISPC_VID3_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secon.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x394++0x3 line.long 0x00 "DISPC_VID3_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 3 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or wh.." hexmask.long.word 0x00 16.--26. 1. " ORGSIZEY ,Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of .." hexmask.long.word 0x00 0.--10. 1. " ORGSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line .." group.long 0x398++0x3 line.long 0x00 "DISPC_VID3_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 3. For more information, see, Predecimation. The register is used only when the TILER is not present in the.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The v.." group.long 0x39C++0x3 line.long 0x00 "DISPC_VID3_POSITION,The register configures the position of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is .." hexmask.long.word 0x00 16.--26. 1. " POSY ,Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0." hexmask.long.word 0x00 0.--10. 1. " POSX ,X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0." group.long 0x3A0++0x3 line.long 0x00 "DISPC_VID3_PRELOAD,The register configures the DMA buffer of the video 3 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame .." hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." group.long 0x3A4++0x3 line.long 0x00 "DISPC_VID3_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means ne.." group.long 0x3A8++0x3 line.long 0x00 "DISPC_VID3_SIZE,The register configures the size of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished.." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the video 3 Encoded value (from 1 to 2048) to specify the number of lines of the video window 3. Program to value minus 1." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the video window 3 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 3. Program to value minus 1." group.long 0x3AC++0x3 line.long 0x00 "DISPC_DEFAULT_COLOR2,The control register allows to configure the default solid background color for the secondary LCD Shadow register, updated on VFP start period of secondary LCD" hexmask.long.tbyte 0x00 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays." group.long 0x3B0++0x3 line.long 0x00 "DISPC_TRANS_COLOR2,The register sets the transparency color value for the video/graphics overlays for the secondary LCD output. Shadow register, updated on VFP start period of the secondary LCD" hexmask.long.tbyte 0x00 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [2.." group.long 0x3B4++0x3 line.long 0x00 "DISPC_CPR2_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 22.--31. 1. " BR ,BR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " BG ,BG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " BB ,BB Coefficient Encoded signed value (from -512 to 511)." group.long 0x3B8++0x3 line.long 0x00 "DISPC_CPR2_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 22.--31. 1. " GR ,GR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " GG ,GG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " GB ,GB Coefficient Encoded signed value (from -512 to 511)." group.long 0x3BC++0x3 line.long 0x00 "DISPC_CPR2_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 22.--31. 1. " RR ,RR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " RG ,RG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " RB ,RB Coefficient Encoded signed value (from -512 to 511)." group.long 0x3C0++0x3 line.long 0x00 "DISPC_DATA2_CYCLE1,The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x3C4++0x3 line.long 0x00 "DISPC_DATA2_CYCLE2,The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x3C8++0x3 line.long 0x00 "DISPC_DATA2_CYCLE3,The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x3CC++0x3 line.long 0x00 "DISPC_SIZE_LCD2,The register configures the panel size (horizontal and vertical). It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD. A delta value is used to indicate if the odd field has same vertic.." hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel Encoded value (from 1 to 2048) to specify the number of lines per panel (program to value minus 1)." bitfld.long 0x00 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field - . - . - ." "Same,PlusOne,MinusOne,3" hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only va.." group.long 0x400++0x3 line.long 0x00 "DISPC_TIMING_H2,The register configures the timing logic for the HSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 20.--31. 1. " HBP ,Horizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to valu.." hexmask.long.word 0x00 8.--19. 1. " HFP ,Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1)." hexmask.long.byte 0x00 0.--7. 1. " HSW ,Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1)." group.long 0x404++0x3 line.long 0x00 "DISPC_TIMING_V2,The register configures the timing logic for the VSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 20.--31. 1. " VBP ,Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display." hexmask.long.word 0x00 8.--19. 1. " VFP ,Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame." hexmask.long.byte 0x00 0.--7. 1. " VSW ,Vertical synchronization pulse width In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of .." group.long 0x408++0x3 line.long 0x00 "DISPC_POL_FREQ2,The register configures the signal configuration. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x00 18. " ALIGN ,Defines the alignment between HSYNC and VSYNC assertion. - . - ." "notAligned,Aligned" bitfld.long 0x00 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/Off - . - ." "DOpEdPCk,DBit16" bitfld.long 0x00 16. " RF ,Program HSYNC/VSYNC Rise or Fall - . - ." "DFEdPCk,DRiEdPCk" textline " " bitfld.long 0x00 15. " IEO ,Invert output enable - . - ." "ACBaHigh,ACBaLow" bitfld.long 0x00 14. " IPC ,Invert pixel clock - . - ." "DrPCk,DfPCk" bitfld.long 0x00 13. " IHS ,Invert HSYNC - . - ." "LCkpinAh,LCkpinAl" textline " " bitfld.long 0x00 12. " IVS ,Invert VSYNC - . - ." "FCkpinAh,FCkpinAl" bitfld.long 0x00 8.--11. " ACBI ,AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " ACB ,AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supp.." group.long 0x40C++0x3 line.long 0x00 "DISPC_DIVISOR2,The register configures the divisors. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.byte 0x00 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD2_CLK. The value 0 is invalid." hexmask.long.byte 0x00 0.--7. 1. " PCD ,Pixel Clock Divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD2_CLK divided byDISPC_DIVISOR2.LCD value. The values 0 is invalid." group.long 0x570++0x3 line.long 0x00 "DISPC_WB_ATTRIBUTES,The register configures the attributes of the viwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is direc.." bitfld.long 0x00 28.--31. " IDLENUMBER ,Determines the number of idles between requests on the L3 interconnect. It is only used when the write-back pipeline does data transfer from memory to memory. When the output of an overlay is stored in memory through t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " IDLESIZE ,Determines if the IDLENUMBER corresponds to a number of bursts or singles. - . - ." "IdleSingle,IdleBurst" bitfld.long 0x00 24.--26. " CAPTUREMODE ,Defines the frame rate capture. - . - . - . - . - . - . - . - ." "All,Only1,Only1_2,Only1_3,Only1_4,Only1_5,Only1_6,Only1_7" textline " " bitfld.long 0x00 23. " ARBITRATION ,Determines the priority of the write-back pipeline. The write-back pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between.." "NormalPrio,HighPrio" bitfld.long 0x00 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0. - . - ." "Initial,Double" bitfld.long 0x00 21. " VERTICALTAPS ,Video Vertical Resize Tap Number - . - ." "taps3,taps5" textline " " bitfld.long 0x00 19. " WRITEBACKMODE ,When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel. 0x0: Capture mode (default mode) 0x1: Memory-to-memo.." "0,1" bitfld.long 0x00 16.--18. " CHANNELIN ,Video Channel In configuration wr: immediate - . - . - . - . - . - . - ." "LCD1,LCD2,TV,Gfx,Vid1,Vid2,Vid3,7" bitfld.long 0x00 14.--15. " BURSTSIZE ,Write-back DMA Burst Size - . - . - . - ." "Burst2x128b,Burst4x128b,Burst8x128b,Res" textline " " bitfld.long 0x00 11. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 10. " TRUNCATIONENABLE ,It applies only when the input format to the write-back pipeline from the overlay or directly from one of the pipelines is ARGB32. If the format is one of the YUV supported formats, the bit field is ignored. -.." "WBTruncDis,WBTruncEnb" bitfld.long 0x00 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV. - . - ." "ColSpCDis,ColSpCEnb" textline " " bitfld.long 0x00 8. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. - . - ." "1D_burst,2D_burst" bitfld.long 0x00 7. " ALPHAENABLE ,Premultiplied alpha enable Read 0x1: Enabled Read 0x0: Disabled. This bit also disable the logic present in the associated channel out that compute the alpha component sent to the WB pipe. When the WB is conf.." "0,1" bitfld.long 0x00 5.--6. " RESIZEENABLE ,Resize Enable - . - . - . - ." "ReSizeProc,HReSize,2,3" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Write-back Format. It defines the pixel format when storing the write-back picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "NV12,RGBx12,RGBA12,3,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24,YUV2,UYVY,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,Write-back Enable. wr: immediate - . - ." "WBDis,WBEnb" group.long 0x574++0x3 line.long 0x00 "DISPC_WB_CONV_COEF0,The register configures the color space conversion matrix coefficients for the write back pipeline (YUV4:4:4 to RGB24) Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the .." hexmask.long.word 0x00 16.--26. 1. " YG ,YG Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " YR ,YR Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x578++0x3 line.long 0x00 "DISPC_WB_CONV_COEF1,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline.." hexmask.long.word 0x00 16.--26. 1. " CRR ,CrR Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " YB ,YB Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x57C++0x3 line.long 0x00 "DISPC_WB_CONV_COEF2,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline.." hexmask.long.word 0x00 16.--26. 1. " CRB ,CrB Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " CRG ,CrG Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x580++0x3 line.long 0x00 "DISPC_WB_CONV_COEF3,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline.." hexmask.long.word 0x00 16.--26. 1. " CBG ,CbG coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " CBR ,CbR coefficient Encoded signed value (from -1024 to 1023)." group.long 0x584++0x3 line.long 0x00 "DISPC_WB_CONV_COEF4,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline.." hexmask.long.word 0x00 0.--10. 1. " CBB ,CbB Coefficient Encoded signed value (from -1024 to 1023)." rgroup.long 0x588++0x3 line.long 0x00 "DISPC_WB_BUF_SIZE_STATUS,The register defines the DMA buffer size for the write back pipeline." hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,DMA buffer Size in number of 128-bits." group.long 0x58C++0x3 line.long 0x00 "DISPC_WB_BUF_THRESHOLD,The register configures the DMA buffer associated with the write-back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pip.." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." group.long 0x590++0x3 line.long 0x00 "DISPC_WB_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the write back pipeline. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finish.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x594++0x3 line.long 0x00 "DISPC_WB_PICTURE_SIZE,The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in.." hexmask.long.word 0x00 16.--26. 1. " ORGSIZEY ,Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1)." hexmask.long.word 0x00 0.--10. 1. " ORGSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line .." group.long 0x598++0x3 line.long 0x00 "DISPC_WB_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the write back pipeline. The register is used only when the TILER is not present in the system in order to perform low perform.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Values other than 1 are invalid" group.long 0x5A4++0x3 line.long 0x00 "DISPC_WB_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the vwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no mor.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means ne.." group.long 0x5A8++0x3 line.long 0x00 "DISPC_WB_SIZE,The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline. When the overlay is output on the primary LCD or secondary LCD or TV outputs, .." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the Write-back picture Encoded value (from 1 to 2048) to specify the number of lines of the write-back picture. Program to value minus 1." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the Write-back picture Encoded value (from 1 to 2048) to specify the number of pixels of the write-back picture. Program to value minus 1." group.long 0x620++0x3 line.long 0x00 "DISPC_CONFIG2,The control register configures the Display Controller module for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD or EVSYNC" bitfld.long 0x00 25. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 24. " COLORCONV_ENABLE ,Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1. - . - ." "0,1" bitfld.long 0x00 23. " FIDFIRST ,Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. - . - ." "Even,Odd" textline " " bitfld.long 0x00 22. " OUTPUTMODE_ENABLE ,Selects between progressive and interlace mode for the secondary LCD output. - . - ." "0,Interlace_mode_selected." bitfld.long 0x00 16. " BUFFERHAND_CHECK ,Controls the handcheck between DMA buffer and STALL signal in order to prevent from underflow. The bit shall be set to 0 when the module is not in STALL mode. (secondary LCD output) - . - ." "0,1" bitfld.long 0x00 15. " CPR ,Color Phase Rotation Control secondary LCD output). It shall be reset when ColorConvEnable bit field is set to 1. wr: VFP start period of secondary LCD output - . - ." "CPRDis,CPREnb" textline " " bitfld.long 0x00 11. " TCKLCD_SELECTION ,Transparency Color Key Selection (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "0,1" bitfld.long 0x00 10. " TCKLCDENABLE ,Transparency Color Key Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "DisTCK,EnbTCK" bitfld.long 0x00 8. " ACBIASGATED ,ACBias Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "ACBGDis,ACBGEnb" textline " " bitfld.long 0x00 7. " VSYNCGATED ,VSYNC Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "VGDis,VGEnb" bitfld.long 0x00 6. " HSYNCGATED ,HSYNC Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "HGDis,HGEnb" bitfld.long 0x00 5. " PIXELCLOCK_GATED ,Pixel Clock Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "0,1" textline " " bitfld.long 0x00 4. " PIXELDATA_GATED ,Pixel Data Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "0,1" bitfld.long 0x00 0. " PIXELGATED ,Pixel Gated Enable (only for Active Matrix) (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "PclkTogA,PclkTogV" group.long 0x624++0x3 line.long 0x00 "DISPC_VID1_ATTRIBUTES2,The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB fram.." bitfld.long 0x00 8. " YUVCHROMARE_SAMPLING ,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphas.." "0,1" bitfld.long 0x00 4.--6. " VC1_RANGE__CBCR ,Defines the VC-1 range value for the CbCr component from 0 to 7." "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " VC1_RANGE_Y ,Defines the VC-1 range value for the Y component from 0 to 7." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " VC1ENABLE ,Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats. - . - ." "VC1Dis,VC1Enb" group.long 0x628++0x3 line.long 0x00 "DISPC_VID2_ATTRIBUTES2,The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB fram.." bitfld.long 0x00 8. " YUVCHROMARE_SAMPLING ,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphas.." "0,1" bitfld.long 0x00 4.--6. " VC1_RANGE__CBCR ,Defines the VC-1 range value for the CbCr component from 0 to 7." "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " VC1_RANGE_Y ,Defines the VC-1 range value for the Y component from 0 to 7." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " VC1ENABLE ,Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats. - . - ." "VC1Dis,VC1Enb" group.long 0x62C++0x3 line.long 0x00 "DISPC_VID3_ATTRIBUTES2,The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB fram.." bitfld.long 0x00 8. " YUVCHROMARE_SAMPLING ,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphas.." "0,1" bitfld.long 0x00 4.--6. " VC1_RANGE__CBCR ,Defines the VC-1 range value for the CbCr component from 0 to 7." "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " VC1_RANGE_Y ,Defines the VC-1 range value for the Y component from 0 to 7." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " VC1ENABLE ,Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats. - . - ." "VC1Dis,VC1Enb" wgroup.long 0x630++0x3 line.long 0x00 "DISPC_GAMMA_TABLE0,The register configures the look up table used as color look up table for BITMAP formats (1-, 2-, 4, and 8-bpp) on the graphics pipeline or as gamma table on the primary LCD output." hexmask.long.byte 0x00 24.--31. 1. " INDEX ,Defines the location in the table where the bit field VALUE is stored." hexmask.long.byte 0x00 16.--23. 1. " VALUE_R ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." hexmask.long.byte 0x00 8.--15. 1. " VALUE_G ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." textline " " hexmask.long.byte 0x00 0.--7. 1. " VALUE_B ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." wgroup.long 0x634++0x3 line.long 0x00 "DISPC_GAMMA_TABLE1,The register configures the gamma table on the secondary LCD output." hexmask.long.byte 0x00 24.--31. 1. " INDEX ,Defines the location in the table where the bit field VALUE is stored." hexmask.long.byte 0x00 16.--23. 1. " VALUE_R ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." hexmask.long.byte 0x00 8.--15. 1. " VALUE_G ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." textline " " hexmask.long.byte 0x00 0.--7. 1. " VALUE_B ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." wgroup.long 0x638++0x3 line.long 0x00 "DISPC_GAMMA_TABLE2,The register configures the gamma table on the TV output." bitfld.long 0x00 31. " INDEX ,Setting this bit to 1 resets the internal index counter to zero. Each subsequent access to the register (with the INDEX bit kept at 0) increments the address for the next storage location into the table memory." "0,1" hexmask.long.word 0x00 20.--29. 1. " VALUE_R ,10-bit color component value to store in the table." hexmask.long.word 0x00 10.--19. 1. " VALUE_G ,10-bit color component value to store in the table." textline " " hexmask.long.word 0x00 0.--9. 1. " VALUE_B ,10-bit color component value to store in the table." group.long 0x63C++0x3 line.long 0x00 "DISPC_VID1_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats..." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x6A8++0x3 line.long 0x00 "DISPC_VID2_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats..." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x724++0x3 line.long 0x00 "DISPC_VID3_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats..." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x790++0x3 line.long 0x00 "DISPC_WB_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the write-back pipeline. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV forma.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x800++0x3 line.long 0x00 "DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipeline (graphics, video1, video2, video3 and write-back). Both TOP and BOTTOM must be allocated to the same pipeline." bitfld.long 0x00 27.--29. " WB_BOTTOM__BUFFER ,Write-back DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to write-back pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " WB_TOP__BUFFER ,Write-back DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to write-back pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. " VID3_BOTTOM__BUFFER ,Video3 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video3 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18.--20. " VID3_TOP__BUFFER ,Video3 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video3 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " VID2_BOTTOM__BUFFER ,Video2 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video2 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " VID2_TOP__BUFFER ,Video2 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video2 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " VID1_BOTTOM__BUFFER ,Video1 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video1 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " VID1_TOP__BUFFER ,Video1 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video 1 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " GFX_BOTTOM__BUFFER ,Graphics DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to graphics pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " GFX_TOP__BUFFER ,Graphics DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to graphics pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" group.long 0x804++0x3 line.long 0x00 "DISPC_DIVISOR,The register configures the divisor value for generating the core functional clock. There is a backward compatibility mode enabled by default in order to use.LCD value instead of .LCD bit field for generating the core functional clock." hexmask.long.byte 0x00 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the frequency of the Display Controller logic clock based on the function clock. The value 0 is invalid." bitfld.long 0x00 0. " ENABLE ,When the bit field is set to 1, the bit field LCD is used to generated the core functional clock from the input clock. When the bit field is set to 0, the valueDISPC_DIVISOR1.LCD is used instead. - . - .." "Disable,Enable" group.long 0x810++0x3 line.long 0x00 "DISPC_WB_ATTRIBUTES2,The register set the counter to control the delay to flush the WB pipe after the end of the frame in capture mode. Shadow register, updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending.." hexmask.long.byte 0x00 0.--7. 1. " WBDELAYCOUNT ,Delays the WB pipe flush after the end of the frame.delay = n x (1/F_clk) n = 0:255" tree.end tree "DISPC_L3" base ad:0x58001000 tree "Channel_0" width 29. group.long 0x80++0x3 line.long 0x00 "DISPC_GFX_BA_j_0,The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output.." hexmask.long 0x00 0.--31. 1. " BA ,Graphics base address Base address of the graphics buffer (aligned on pixel size boundary) (in case 1-, 2-, and 4-bpp, byte alignment is required, in case of RGB24 packed format, 4-pixel alignment is required) When the TILER is addressed.." group.long 0x640++0x3 line.long 0x00 "DISPC_VID1_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0xE8++0x3 line.long 0x00 "DISPC_VID1_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x600++0x3 line.long 0x00 "DISPC_VID1_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0xBC++0x3 line.long 0x00 "DISPC_VID1_BA_j_0,The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x648++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x64C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF4++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF0++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x688++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E0++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6AC++0x3 line.long 0x00 "DISPC_VID2_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x178++0x3 line.long 0x00 "DISPC_VID2_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x608++0x3 line.long 0x00 "DISPC_VID2_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x14C++0x3 line.long 0x00 "DISPC_VID2_BA_j_0,The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x6B4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6B8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x184++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x180++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6F4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x200++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x728++0x3 line.long 0x00 "DISPC_VID3_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x300++0x3 line.long 0x00 "DISPC_VID3_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x610++0x3 line.long 0x00 "DISPC_VID3_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x308++0x3 line.long 0x00 "DISPC_VID3_BA_j_0,The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x730++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x734++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x314++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x310++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x770++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x350++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x794++0x3 line.long 0x00 "DISPC_WB_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the fiel.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x500++0x3 line.long 0x00 "DISPC_WB_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field p.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x618++0x3 line.long 0x00 "DISPC_WB_BA_UV_j_0,The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 .." hexmask.long 0x00 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x508++0x3 line.long 0x00 "DISPC_WB_BA_j_0,The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.G.." hexmask.long 0x00 0.--31. 1. " BA ,Write-back base address Base address of the WB buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2;0, byte alignment .." group.long 0x7A0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7A4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x514++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x510++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x550++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_1" width 29. group.long 0x84++0x3 line.long 0x00 "DISPC_GFX_BA_j_1,The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output.." hexmask.long 0x00 0.--31. 1. " BA ,Graphics base address Base address of the graphics buffer (aligned on pixel size boundary) (in case 1-, 2-, and 4-bpp, byte alignment is required, in case of RGB24 packed format, 4-pixel alignment is required) When the TILER is addressed.." group.long 0x644++0x3 line.long 0x00 "DISPC_VID1_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0xEC++0x3 line.long 0x00 "DISPC_VID1_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x604++0x3 line.long 0x00 "DISPC_VID1_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0xC0++0x3 line.long 0x00 "DISPC_VID1_BA_j_1,The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x650++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x654++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xFC++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF8++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x68C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E4++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6B0++0x3 line.long 0x00 "DISPC_VID2_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x17C++0x3 line.long 0x00 "DISPC_VID2_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x60C++0x3 line.long 0x00 "DISPC_VID2_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x150++0x3 line.long 0x00 "DISPC_VID2_BA_j_1,The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x6BC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6C0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x18C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x188++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6F8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x204++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x72C++0x3 line.long 0x00 "DISPC_VID3_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the fie.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x304++0x3 line.long 0x00 "DISPC_VID3_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field .." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x614++0x3 line.long 0x00 "DISPC_VID3_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x30C++0x3 line.long 0x00 "DISPC_VID3_BA_j_1,The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used.." hexmask.long 0x00 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is.." group.long 0x738++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x73C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x31C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x318++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x774++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x354++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x798++0x3 line.long 0x00 "DISPC_WB_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the fiel.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x504++0x3 line.long 0x00 "DISPC_WB_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field p.." hexmask.long.word 0x00 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from -1024 to 1023)." group.long 0x61C++0x3 line.long 0x00 "DISPC_WB_BA_UV_j_1,The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 .." hexmask.long 0x00 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32.." group.long 0x50C++0x3 line.long 0x00 "DISPC_WB_BA_j_1,The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.G.." hexmask.long 0x00 0.--31. 1. " BA ,Write-back base address Base address of the WB buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2;0, byte alignment .." group.long 0x7A8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7AC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x51C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x518++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x554++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_2" width 29. group.long 0x658++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x65C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x104++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x100++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x690++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E8++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6C4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6C8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x194++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x190++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6FC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x208++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x740++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x744++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x324++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x320++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x778++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x358++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7B0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7B4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x524++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x520++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x558++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_3" width 29. group.long 0x660++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x664++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x10C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x108++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x694++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1EC++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6CC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6D0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x19C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x198++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x700++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x20C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x748++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x74C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x32C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x328++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x77C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x35C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7B8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7BC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x52C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x528++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7EC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x55C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_4" width 29. group.long 0x668++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x66C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x114++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x110++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x698++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1F0++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6D4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6D8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1A4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1A0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x704++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x210++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x750++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x754++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x334++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x330++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x780++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x360++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7C0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7C4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x534++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x530++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7F0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x560++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_5" width 29. group.long 0x670++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x674++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x11C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x118++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x69C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1F4++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6DC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6E0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1AC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1A8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x708++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x214++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x758++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x75C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x33C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x338++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x784++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x364++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7C8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7CC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x53C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x538++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7F4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x564++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_6" width 29. group.long 0x678++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x67C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x124++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x120++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6A0++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1F8++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6E4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6E8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1B4++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1B0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x70C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x218++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x760++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x764++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x344++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x340++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x788++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x368++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7D0++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7D4++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x544++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x540++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7F8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x568++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_7" width 29. group.long 0x680++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x684++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x12C++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x128++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6A4++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1FC++0x3 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6EC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6F0++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setti.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1BC++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1B8++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x710++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used o.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x21C++0x3 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x768++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x76C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x34C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y settin.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x348++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register,.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x78C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x36C++0x3 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7D8++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7DC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x54C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y set.." hexmask.long.byte 0x00 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x548++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow regist.." hexmask.long.byte 0x00 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x00 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7FC++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x56C++0x3 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow reg.." hexmask.long.byte 0x00 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end textline "" width 28. rgroup.long 0x0++0x3 line.long 0x00 "DISPC_REVISION,IP Revision" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "DISPC_SYSCONFIG,This register allows to control various parameters of the OCP interface." bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management, standby/wait control - . - . - . - ." "fStandBy,nStandBy,Sstandby,Res" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period - . - . - . - ." "OCPFuncOff,FuncOff,OCPOff,OCPFuncOn" bitfld.long 0x00 5. " WARMRESET ,Warm reset. Set this bit to 1 triggers a module warm reset. The bit is automatically reset by the hardware. During reads, it always returns 0. The warm reset keep the configuration registers unchanged. - . - ." "Normal,warmreset" textline " " bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, Idle req/ack control - . - . - . - ." "fIdle,nIdle,sIdle,Res" bitfld.long 0x00 2. " ENWAKEUP ,WakeUp feature control - . - ." "WakeUpDis,WakeUpEnb" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "nMode,Rst" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy - . - ." "ClkFree,ClkGated" rgroup.long 0x14++0x3 line.long 0x00 "DISPC_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "rstongoing,rstcomp" group.long 0x18++0x3 line.long 0x00 "DISPC_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt. Write 1 to a given bit resets this bit" eventfld.long 0x00 26. " WBUNCOMPLETEERROR_IRQ ,Write-back DMA buffer is flushed before it is completely drained. In WB capture mode, if the new frame starts before the WB DMA buffers are fully drained (onto external memory), then the contents of the WB DMA buffers .." "false,True" eventfld.long 0x00 25. " WBBUFFER_OVERFLOW_IRQ ,Write-back DMA Buffer Overflow. The DMA buffer is full. - . - ." "0,1" eventfld.long 0x00 24. " FRAME_DONETV_IRQ ,Frame Done for the TV. The TV output has been disabled by user. All the data have been sent. - . - ." "0,1" textline " " eventfld.long 0x00 23. " FRAME_DONEWB_IRQ ,Frame Done for the write-back channel. The write-back channel has output the frame. All the data of the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to b.." "0,1" eventfld.long 0x00 22. " FRAME_DONE2_IRQ ,Frame Done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent. - . - ." "0,1" eventfld.long 0x00 21. " ACBIASCOUNT_STATUS2_IRQ ,AC Bias Count Status for the secondary LCD - . - ." "0,1" textline " " eventfld.long 0x00 20. " VID3BUFFER_UNDERFLOW_IRQ ,Video 3 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" eventfld.long 0x00 19. " VID3END_WINDOW_IRQ ,The end of the video 3 Window has been reached. It is detected by the overlay manager when the full video 3 has been displayed. - . - ." "0,1" eventfld.long 0x00 18. " VSYNC2_IRQ ,Vertical Synchronization for the secondary LCD - . - ." "False,True" textline " " eventfld.long 0x00 17. " SYNC_LOST2_IRQ ,Synchronization Lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output. - . .." "0,1" eventfld.long 0x00 16. " WAKEUP_IRQ ,Wake-up - . - ." "False,True" eventfld.long 0x00 15. " SYNCLOST_TV_IRQ ,Synchronization Lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output. - . - ." "0,1" textline " " eventfld.long 0x00 14. " SYNC_LOST1_IRQ ,Synchronization Lost on the primary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the primary LCD output. - . - ." "0,1" eventfld.long 0x00 13. " VID2END_WINDOW_IRQ ,The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed. - . - ." "0,1" eventfld.long 0x00 12. " VID2BUFFER_UNDERFLOW_IRQ ,Video 2 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" textline " " eventfld.long 0x00 11. " VID1END_WINDOW_IRQ ,The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed. - . - ." "0,1" eventfld.long 0x00 10. " VID1BUFFER_UNDERFLOW_IRQ ,Video 1 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" eventfld.long 0x00 9. " OCPERROR_IRQ ,OCP Error. L3 Interconnect has sent SResp=ERR. - . - ." "False,True" textline " " eventfld.long 0x00 8. " PALETTEGAMMA_LOADING_IRQ ,Palette Gamma Loading status. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded su.." "0,1" eventfld.long 0x00 7. " GFXEND_WINDOW_IRQ ,The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed. - . - ." "0,1" eventfld.long 0x00 6. " GFXBUFFER_UNDERFLOW_IRQ ,Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" textline " " eventfld.long 0x00 5. " PROGRAMMED_LINENUMBER_IRQ ,Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number. - . - ." "0,1" eventfld.long 0x00 4. " ACBIASCOUNT_STATUS1_IRQ ,AC Bias Count Status for the primary LCD - . - ." "0,1" eventfld.long 0x00 3. " EVSYNC__ODD_IRQ ,VSYNC for odd field from the TV encoder (VENC or HDMI) - . - ." "0,1" textline " " eventfld.long 0x00 2. " EVSYNC__EVEN_IRQ ,VSYNC for even field from the TV encoder (VENC or HDMI) - . - ." "0,1" eventfld.long 0x00 1. " VSYNC1_IRQ ,Vertical Synchronization for the primary LCD. - . - ." "False,True" eventfld.long 0x00 0. " FRAME_DONE1_IRQ ,Frame Done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent. - . - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "DISPC_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt, on an event-by-event basis" bitfld.long 0x00 26. " WBUNCOMPLETEERROR_EN ,The write back buffer has been flushed before it has been fully drained. Enable. - . - ." "masked,genint" bitfld.long 0x00 25. " WBBUFFER_OVERFLOW_EN ,Write-back DMA Buffer Overflow. The DMA buffer is full - . - ." "0,1" bitfld.long 0x00 24. " FRAME_DONETV_EN ,Frame Done for the TV. The TV output has been disabled by user. All the data have been sent. - . - ." "0,1" textline " " bitfld.long 0x00 23. " FRAME_DONEWB_EN ,Frame Done for the write-back channel. The write-back channel has output the frame. All the data have been sent for the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-b.." "0,1" bitfld.long 0x00 22. " FRAME_DONE2_EN ,Frame Done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent. - . - ." "0,1" bitfld.long 0x00 21. " ACBIASCOUNT_STATUS2_EN ,AC Bias Count Status for the secondary LCD - . - ." "0,1" textline " " bitfld.long 0x00 20. " VID3BUFFER_UNDERFLOW_EN ,Video 3 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" bitfld.long 0x00 19. " VID3END_WINDOW_EN ,The end of the video 3 Window has been reached. It is detected by the overlay manager when the full video 3 has been displayed. - . - ." "Vid3EndWindow_is_masked,1" bitfld.long 0x00 18. " VSYNC2_EN ,Vertical Synchronization for the secondary LCD - . - ." "masked,genint" textline " " bitfld.long 0x00 17. " SYNC_LOST2_EN ,Synchronization Lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output. - . .." "0,1" bitfld.long 0x00 16. " WAKEUP_EN ,Wake Up Mask - . - ." "masked,genint" bitfld.long 0x00 15. " SYNC_LOSTTV_EN ,Synchronization Lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output. - . - ." "0,1" textline " " bitfld.long 0x00 14. " SYNC_LOST1_EN ,Synchronization Lost for the primary LCD - . - ." "0,1" bitfld.long 0x00 13. " VID2END_WINDOW_EN ,The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed. - . - ." "Vid2EndWindow_is_masked,1" bitfld.long 0x00 12. " VID2BUFFER_UNDERFLOW_EN ,Video 2 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" textline " " bitfld.long 0x00 11. " ENDVID1_WINDOW_EN ,The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed. - . - ." "EndVid1Window_is_masked,1" bitfld.long 0x00 10. " VID1BUFFER_UNDERFLOW_EN ,Video 1 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" bitfld.long 0x00 9. " OCPERROR_EN ,OCP Error. L3 Interconnect has sent SResp=ERR. - . - ." "masked,genint" textline " " bitfld.long 0x00 8. " PALETTE_GAMMA_EN ,Palette Gamma Loading mask. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded succ.." "PaletteGamma_is_masked,1" bitfld.long 0x00 7. " GFXEND_WINDOW_EN ,The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed. - . - ." "GfxEndWindow_is_masked,1" bitfld.long 0x00 6. " GFXBUFFER_UNDERFLOW_EN ,Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses) - . - ." "0,1" textline " " bitfld.long 0x00 5. " PROGRAMMED_LINENUMBER_EN ,Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number. - . - ." "0,1" bitfld.long 0x00 4. " ACBIASCOUNT_STATUS1_EN ,AC Bias Count Status for the primary LCD - . - ." "0,1" bitfld.long 0x00 3. " EVSYNC_ODD_EN ,VSYNC for odd field from the TV encoder (VENC or HDMI) - . - ." "masked,genint" textline " " bitfld.long 0x00 2. " EVSYNC_EVEN_EN ,VSYNC for even field from the TV encoder (VENC or HDMI) - . - ." "masked,genint" bitfld.long 0x00 1. " VSYNC1_EN ,Vertical Synchronization for the primary LCD. - . - ." "masked,genint" bitfld.long 0x00 0. " FRAMEDONE_EN ,Frame Done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent. - . - ." "masked,genint" group.long 0x40++0x3 line.long 0x00 "DISPC_CONTROL1,The control register configures the Display Controller module for the primary LCD and TV outputs." bitfld.long 0x00 30.--31. " SPATIALTEMPORAL_DITHERINGFRAMES ,Spatial/Temporal dithering number of frames for the primary LCD output wr: VFP start period of primary LCD - . - . - . - ." "Spatial_only,1,2,?..." bitfld.long 0x00 29. " LCDENABLEPOL ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 28. " LCDENABLESIGNAL ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x00 27. " PCKFREEENABLE ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 25.--26. " TDMUNUSEDBITS ,State of unused bits (TDM mode only) for the primary LCD output. wr: VFP start period of primary LCD - . - . - . - ." "LowLevel,HighLevel,Unchanged,Res" bitfld.long 0x00 23.--24. " TDMCYCLEFORMAT ,Cycle format (TDM mode only) for the primary LCD output wr: VFP start period of primary LCD - . - . - . - ." "1CycPerPix,2CycPerPix,3CycPerPix,3CycPer2Pix" textline " " bitfld.long 0x00 21.--22. " TDMPARALLELMODE ,Output Interface width (TDM mode only) for the primary LCD output wr: VFP start period of primary LCD - . - . - . - ." "8bParaInt,9bParaInt,12bParaInt,16bParaInt" bitfld.long 0x00 20. " TDMENABLE ,Enable the multiple cycle format (TDM mode only used for TFT mode with the RFBI enable bit off) for the primary LCD output. wr: VFP start period of primary LCD - . - ." "TDMDis,TDMEnb" bitfld.long 0x00 17.--19. " HT ,Hold Time for TV output wr: EVSYNC Encoded value (from 1 to 8) to specify the number of external digital clock periods to hold the data (programmed value = value minus 1)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16. " GPOUT1 ,General Purpose Output Signal wr:immediate - . - ." "reset,set" bitfld.long 0x00 15. " GPOUT0 ,General Purpose Output Signal wr:immediate - . - ." "reset,set" bitfld.long 0x00 14. " GPIN1 ,General Purpose Input Signal wr: immediately - . - ." "reset,set" textline " " bitfld.long 0x00 13. " GPIN0 ,General Purpose Input Signal wr: immediately - . - ." "GPin0Rst,GPin0Set" bitfld.long 0x00 12. " OVERLAYOPTI_MIZATION ,Overlay Optimization for the primary LCD output wr: VFP start period of the primary LCD - . - ." "0,1" bitfld.long 0x00 11. " STALLMODE ,STALL Mode for the primary LCD output wr: VFP start period of primary LCD - . - ." "nMode,RFBIMode" textline " " bitfld.long 0x00 8.--9. " TFTDATALINES ,Number of lines of the primary LCD interface wr: VFP start period of primary LCD - . - . - . - ." "OaLSB12b,OaLSB16b,OaLSB18b,OaLSB24b" bitfld.long 0x00 7. " STDITHERENABLE ,Spatial Temporal dithering enable for the primary LCD output wr: VFP start period of primary LCD - . - ." "STDithDis,STDithEnb" bitfld.long 0x00 6. " GOTV ,GO Command for the TV output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the TV output. wr: immediate - . - ." "HfUISR,UfPSR" textline " " bitfld.long 0x00 5. " GOLCD ,GO Command for the primary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the primary LCD output. wr: immediate - . - ." "HfUISR,UfPSR" bitfld.long 0x00 4. " M8B ,Mono 8-bit mode of the primary LCD wr: VFP start period of primary LCD output - . - ." "4PixtoPanel,8PixtoPanel" bitfld.long 0x00 3. " STNTFT ,LCD Display type of the primary LCD wr: VFP start period of primary LCD output - . - ." "STNdispEnb,ATFTDisEnb" textline " " bitfld.long 0x00 2. " MONOCOLOR ,Monochrome/Color selection for the primary LCD wr: VFP start period of primary LCD output - . - ." "ColOpEnb,MonOpEnb" bitfld.long 0x00 1. " TVENABLE ,Enable the TV output wr: immediate effect only occurs at the end of the current frame. - . - ." "DigOpDis,DigOpEnb" bitfld.long 0x00 0. " LCDENABLE ,Enable the primary LCD outputs wr: immediate Effect only occurs at the end of the current frame - . - ." "LCDOpDis,LCDOpEnb" group.long 0x44++0x3 line.long 0x00 "DISPC_CONFIG1,The control register configures the Display Controller module for the primary LCD output and TV output. Shadow register, updated on VFP start period of primary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is fin.." bitfld.long 0x00 25. " FULLRANGE ,Color Space Conversion full range setting. wr: VFP start of primary LCD - . - ." "Limrange,FullRange" bitfld.long 0x00 24. " COLORCONV_ENABLE ,Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1. wr: VFP start of primary LCD - . - ." "0,1" bitfld.long 0x00 23. " FIDFIRST ,Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. wr: VFP start of primary LCD - . - ." "Even,Odd" textline " " bitfld.long 0x00 22. " OUTPUTMODE_ENABLE ,Selects between progressive and interlace mode for the primary LCD output. wr: VFP start of primary LCD - . - ." "0,Interlace_mode_selected." bitfld.long 0x00 19. " TVALPHABLENDER_ENABLE ,Selects the alpha blender overlay manager for the TV output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-.." "0,1" bitfld.long 0x00 18. " LCDALPHABLENDER_ENABLE ,Selects the alpha blender overlay manager for the primary LCD output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility o.." "0,1" textline " " bitfld.long 0x00 17. " BUFFERFILLING ,Controls if the DMA buffers are refilled only when the LOW threshold is reached or if all DMA buffers are refilled when at least one of them reaches the LOW threshold. wr: immediate - . - ." "FIFOfillingDis,FIFOfillingEnb" bitfld.long 0x00 16. " BUFFERHAND_CHECK ,Controls the handcheck between DMA buffer and STALL signal in order to prevent from underflow. The bit shall be set to 0 when the module is not in STALL mode. (primary LCD output) wr: VFP start of primary LCD - . -.." "0,1" bitfld.long 0x00 15. " CPR ,Color Phase Rotation Control (primary LCD output). It shall be reset when ColorConvEnable bit field is set to 1 wr: VFP start period of primary LCD output - . - ." "CPRDis,CPREnb" textline " " bitfld.long 0x00 14. " BUFFERMERGE ,Buffer merge control wr: EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output us.." "MergeDis,MergeEnb" bitfld.long 0x00 13. " TCKTV_SELECTION ,Transparency Color Key Selection (TV output) wr: EVSYNC - . - ." "0,1" bitfld.long 0x00 12. " TCKTVENABLE ,Transparency Color Key Enabled (TV output) wr: EVSYNC - . - ." "DisTCK,EnbTCK" textline " " bitfld.long 0x00 11. " TCKLCD_SELECTION ,Transparency Color Key Selection (primary LCD output) wr: VFP start period of primary LCD output - . - ." "0,1" bitfld.long 0x00 10. " TCKLCDENABLE ,Transparency Color Key Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "DisTCK,EnbTCK" bitfld.long 0x00 9. " GAMATABLE_ENABLE ,For backward compatibility, an enable bit has been added on the 2 additional gamma tables (secondary display and TV). Gamma table of LCD1 is always enabled. - . - ." "0,1" textline " " bitfld.long 0x00 8. " ACBIASGATED ,ACBias Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "ACBGDis,ACBGEnb" bitfld.long 0x00 7. " VSYNCGATED ,VSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "VGDis,VGEnb" bitfld.long 0x00 6. " HSYNCGATED ,HSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "HGDis,HGEnb" textline " " bitfld.long 0x00 5. " PIXELCLOCK_GATED ,Pixel Clock Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "0,1" bitfld.long 0x00 4. " PIXELDATAGATED ,Pixel Data Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - . - ." "PDGDis,PDGEnb" bitfld.long 0x00 3. " PALETTEGAMMA_TABLE ,Palette/Gamma Table selection wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finis.." "0,1" textline " " bitfld.long 0x00 1.--2. " LOADMODE ,Loading Mode for the Palette/Gamma Table wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finis.." "PgTabLeFr,PgTabUsetb,FrDatLeFr,DLoFrSw" bitfld.long 0x00 0. " PIXELGATED ,Pixel Gated Enable (only for TFT) (primary LCD output) wr: VFP start period of primary LCD output - . - ." "PclkTogA,PclkTogV" group.long 0x4C++0x3 line.long 0x00 "DISPC_DEFAULT_COLOR0,The control register allows to configure the default solid background color for the primary LCD. Shadow register, updated on VFP start period of the primary LCD" hexmask.long.tbyte 0x00 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays." group.long 0x50++0x3 line.long 0x00 "DISPC_DEFAULT_COLOR1,The control register allows to configure the default solid background color for the TV output. Shadow register, updated on EVSYNC" hexmask.long.tbyte 0x00 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays." group.long 0x54++0x3 line.long 0x00 "DISPC_TRANS_COLOR0,The register sets the transparency color value for the video/graphics overlays for the primary LCD output. Shadow register, updated on VFP start period of the primary LCD" hexmask.long.tbyte 0x00 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [2.." group.long 0x58++0x3 line.long 0x00 "DISPC_TRANS_COLOR1,The register sets the transparency color value for the video/graphics overlays for the TV output. Shadow register, updated on EVSYNC" hexmask.long.tbyte 0x00 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [2.." rgroup.long 0x5C++0x3 line.long 0x00 "DISPC_LINE_STATUS,The control register indicates the current primary LCD panel display line number." hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,Current LCD panel line number Current display line number. The first active line has the value 0. During blanking lines the line number is not incremented." group.long 0x60++0x3 line.long 0x00 "DISPC_LINE_NUMBER,The control register indicates the primary LCD panel display line number for the interrupt and the DMA request. Shadow register, updated on VFP start period of primary LCD." hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs." group.long 0x64++0x3 line.long 0x00 "DISPC_TIMING_H1,The register configures the timing logic for the HSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 20.--31. 1. " HBP ,Horizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to valu.." hexmask.long.word 0x00 8.--19. 1. " HFP ,Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1). When .." hexmask.long.byte 0x00 0.--7. 1. " HSW ,Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1). When in BT mode.." group.long 0x68++0x3 line.long 0x00 "DISPC_TIMING_V1,The register configures the timing logic for the VSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 20.--31. 1. " VBP ,Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame." hexmask.long.word 0x00 8.--19. 1. " VFP ,Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame." hexmask.long.byte 0x00 0.--7. 1. " VSW ,Vertical synchronization pulse width In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of .." group.long 0x6C++0x3 line.long 0x00 "DISPC_POL_FREQ1,The register configures the signal configuration. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD." bitfld.long 0x00 18. " ALIGN ,Defines the alignment between HSYNC and VSYNC assertion. - . - ." "notAligned,Aligned" bitfld.long 0x00 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/Off - . - ." "DOpEdPCk,DBit16" bitfld.long 0x00 16. " RF ,Program HSYNC/VSYNC Rise or Fall - . - ." "DFEdPCk,DRiEdPCk" textline " " bitfld.long 0x00 15. " IEO ,Invert output enable - . - ." "ACBaHigh,ACBaLow" bitfld.long 0x00 14. " IPC ,Invert pixel clock - . - ." "DrPCk,DfPCk" bitfld.long 0x00 13. " IHS ,Invert HSYNC - . - ." "LCkpinAh,LCkpinAl" textline " " bitfld.long 0x00 12. " IVS ,Invert VSYNC - . - ." "FCkpinAh,FCkpinAl" bitfld.long 0x00 8.--11. " ACBI ,AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " ACB ,AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supp.." group.long 0x70++0x3 line.long 0x00 "DISPC_DIVISOR1,The register configures the divisors. It is used for the primary LCD output Shadow register, updated on VFP start period of primary LCD" hexmask.long.byte 0x00 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD1_CLK. The value 0 is invalid." hexmask.long.byte 0x00 0.--7. 1. " PCD ,Pixel Clock Divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD1_CLK divided byDISPC_DIVISOR1.LCD value. The values 0 is invalid." group.long 0x74++0x3 line.long 0x00 "DISPC_GLOBAL_ALPHA,The register defines the global alpha value for the graphics and three video pipelines. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by softwa.." hexmask.long.byte 0x00 24.--31. 1. " VID3GLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." hexmask.long.byte 0x00 16.--23. 1. " VID2GLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." hexmask.long.byte 0x00 8.--15. 1. " VID1GLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." textline " " hexmask.long.byte 0x00 0.--7. 1. " GFXGLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." group.long 0x78++0x3 line.long 0x00 "DISPC_SIZE_TV,The register configures the size of the TV output field (interlace), frame (progressive) (horizontal and vertical). Shadow register, updated on EVSYNC. A delta value is used to indicate if the odd field has same vertical size as the even .." hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel (LPP). Encoded value (from 1 to 2048) to specify the number of LPP." bitfld.long 0x00 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field - . - . - ." "same,PlusOne,MinusOne,3" hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display." group.long 0x7C++0x3 line.long 0x00 "DISPC_SIZE_LCD1,The register configures the panel size (horizontal and vertical). Shadow register, updated on VFP start period of primary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel Encoded value (from 1 to 2048) to specify the number of lines per panel (program to value minus 1)." bitfld.long 0x00 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field - . - . - ." "Same,PlusOne,MinusOne,3" hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only va.." group.long 0x88++0x3 line.long 0x00 "DISPC_GFX_POSITION,The register configures the position of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is .." hexmask.long.word 0x00 16.--26. 1. " POSY ,Y position of the graphics window. Encoded value (from 0 to 2047) to specify the Y position of the graphics window on the screen. The line at the top has the Y-position 0." hexmask.long.word 0x00 0.--10. 1. " POSX ,X position of the graphics window. Encoded value (from 0 to 2047) to specify the X position of the graphics window on the screen. The first pixel on the left of the screen has the X-position 0." group.long 0x8C++0x3 line.long 0x00 "DISPC_GFX_SIZE,The register configures the size of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished.." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the graphics window. Encoded value (from 1 to 2048) to specify the number of lines of the graphics window (program to value minus 1)." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the graphics window. Encoded value (from 1 to 2048) to specify the number of pixels per line of the graphics window (program to value minus 1)." group.long 0xA0++0x3 line.long 0x00 "DISPC_GFX_ATTRIBUTES,The register configures the graphics attributes. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (.." bitfld.long 0x00 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero) wr: immediate - . - . - ." "PrimaryLCDSel,SecondaryLCDSel,2,WriteBacksel1" bitfld.long 0x00 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. (It does not apply to the palette loading OCP requests using INCR burst only) - .." "INC,BLCK" bitfld.long 0x00 28. " PREMULTIPLYALPHA ,The field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data. - . - ." "0,1" textline " " bitfld.long 0x00 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is s.." "zorder0,zorder1,zorder2,zorder3" bitfld.long 0x00 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled. - . - ." "ZorderDis,ZorderEnb" bitfld.long 0x00 24. " ANTIFLICKER ,Antiflicker filtering using a 3-tap filter with hardcoded coefficients (1/4, 1/2, 1/4) - . - ." "AFDis,AFEnb" textline " " bitfld.long 0x00 17. " SELFREFRESHAUTO ,Automatic self-refresh mode - . - ." "SelfRefreshAutoDis,SelfRefreshAutoEn" bitfld.long 0x00 15. " SELFREFRESH ,Enables the self refresh of the graphics window from its own DMA buffer. This bit should be set only after having set the GO bit of the channel and read back a zero in its field. - . - ." "SelfRefreshDis,SelfRefreshEnb" bitfld.long 0x00 14. " ARBITRATION ,Determines the priority of the graphics pipeline. When the graphics pipeline is one of the high priority pipelines. The arbitration wheel gives always the priority first to the high priority pipelines using round-ro.." "NormalPrio,HighPrio" textline " " bitfld.long 0x00 12.--13. " ROTATION ,Graphics Rotation Flag - . - . - . - ." "NoRot,Rot90,Rot180,Rot270" bitfld.long 0x00 11. " BUFPRELOAD ,Graphics Preload Value - . - ." "DefVal,HighThres" bitfld.long 0x00 9. " NIBBLEMODE ,Graphics Nibble Mode (only for 1-, 2- and 4-bpp) - . - ." "NibMDis,NibMEnb" textline " " bitfld.long 0x00 8. " CHANNELOUT ,Graphics Channel Out configuration: LCD, WB or TV. wr: immediate - . - ." "LCDOpSel,TVOpSel" bitfld.long 0x00 6.--7. " BURSTSIZE ,Graphics DMA Burst Size - . - . - . - ." "Burst2x128,Burst4x128,Burst8x128,Res" bitfld.long 0x00 5. " REPLICATIONENABLE ,Graphics Replication Enabled: RGB . ARGB, and RGBA formats are converted into ARGB32-8888 using replication of the MSBs or '0s - . - ." "GRLogEnb,GRLogDis" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Graphics format. It defines the pixel format when fetching the graphics picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "BitMap1,BitMap2,BitMap4,BitMap8,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24p,RGBx12,RGBA12,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,Graphics Enable - . - ." "GraphicsDis,GraphicsEnb" group.long 0xA4++0x3 line.long 0x00 "DISPC_GFX_BUF_THRESHOLD,The register configures the graphics buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (n.." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer Low Threshold Number of 128-bits defining the threshold value. The value put is this register should always be greater than zero." rgroup.long 0xA8++0x3 line.long 0x00 "DISPC_GFX_BUF_SIZE_STATUS,The register defines the Graphics buffer size" hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,DMA buffer Size in number of 128-bits" group.long 0xAC++0x3 line.long 0x00 "DISPC_GFX_ROW_INC,The register configures the number of bytes to increment at the end of the row. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and cu.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded unsigned value to specify the number of bytes to increment at the end of the row in the graphics buffer. The value 0 is invalid. The value 1 means next pixel. .." group.long 0xB0++0x3 line.long 0x00 "DISPC_GFX_PIXEL_INC,The register configures the number of bytes to increment between two pixels. For more information, see, Predecimation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the graphics buffer. The value 0 is invalid. The value 1 means next pixel. Th.." group.long 0xB8++0x3 line.long 0x00 "DISPC_GFX_TABLE_BA,The register configures the base address of the palette buffer or the gamma table buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by soft.." hexmask.long 0x00 0.--31. 1. " TABLEBA ,Base address of the palette/gamma table buffer (24-bit entries in 32-bit containers, aligned on 32-bit boundary)." group.long 0xC4++0x3 line.long 0x00 "DISPC_VID1_POSITION,The register configures the position of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is .." hexmask.long.word 0x00 16.--26. 1. " POSY ,Y position of the video window 1 Encoded value (from 0 to 2047) to specify the Y position of the video window 1 .The line at the top has the Y-position 0." hexmask.long.word 0x00 0.--10. 1. " POSX ,X position of the video window 1 Encoded value (from 0 to 2047) to specify the X position of the video window 1. The first pixel on the left of the display screen has the X-position 0." group.long 0xC8++0x3 line.long 0x00 "DISPC_VID1_SIZE,The register configures the size of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished.." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the video 1 Encoded value (from 1 to 2048) to specify the number of lines of the video window 1. Program to value minus 1." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the video window 1 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 1. Program to value minus 1." group.long 0xCC++0x3 line.long 0x00 "DISPC_VID1_ATTRIBUTES,The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame.." bitfld.long 0x00 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate - . - . - ." "PrimaryLCDSel,SecondaryLCDSel,2,WriteBacksel1" bitfld.long 0x00 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. - . - ." "INC,BLCK" bitfld.long 0x00 28. " PREMULTIPHYALPHA ,The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data. - . - ." "0,1" textline " " bitfld.long 0x00 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is s.." "zorder0,zorder1,zorder2,zorder3" bitfld.long 0x00 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled. - . - ." "ZorderDis,ZorderEnb" bitfld.long 0x00 24. " SELFREFRESH ,Enables the self refresh of the video window from its own DMA buffer only. - . - ." "SelfRefreshDis,SelfRefreshEnb" textline " " bitfld.long 0x00 23. " ARBITRATION ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. Whe.." "NormalPrio,HighPrio" bitfld.long 0x00 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0. - . - ." "Initial,Double" bitfld.long 0x00 21. " VERTICALTAPS ,Video Vertical Resize Tap Number. The vertical polyphase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps, the maximum input picture width is double while using 3-tap .." "taps3,taps5" textline " " bitfld.long 0x00 20. " DMAOPTIMIZATION ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 19. " BUFPRELOAD ,Video Preload Value - . - ." "DefVal,HighThres" bitfld.long 0x00 17. " SELFREFRESHAUTO ,Automatic self-refresh mode - . - ." "SelfRefreshAutoDis,SelfRefreshAutoEn" textline " " bitfld.long 0x00 16. " CHANNELOUT ,Video Channel Out configuration: LCD, WB or TV. wr: immediate - . - ." "LCDOp,TVOp" bitfld.long 0x00 14.--15. " BURSTSIZE ,Video DMA Burst Size - . - . - . - ." "Burst2x128b,Burst4x128b,Burst8x128b,Res" bitfld.long 0x00 12.--13. " ROTATION ,Video Rotation Flag - . - . - . - ." "NoRot,Rot90,Rot180,Rot270" textline " " bitfld.long 0x00 11. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 10. " REPLICATIONENABLE ,Replication Enable - . - ." "VRepLDis,VRepLEnb" bitfld.long 0x00 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV. - . - ." "ColSpCDis,ColSpCEnb" textline " " bitfld.long 0x00 8. " VRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 7. " HRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 5.--6. " RESIZEENABLE ,Video Resize Enable - . - . - . - ." "ReSizeProc,HReSize,2,3" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Video Format. It defines the pixel format when fetching the video 1 picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "NV12,RGBx12,RGBA12,3,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24p,YUV2,UYVY,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,Video Enable - . - ." "VideoDis,VideoEnb" group.long 0xD0++0x3 line.long 0x00 "DISPC_VID1_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software .." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,Video DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." rgroup.long 0xD4++0x3 line.long 0x00 "DISPC_VID1_BUF_SIZE_STATUS,The register defines the Video buffer size for the video pipeline 1." hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,Video 1 DMA buffer Size in number of 128-bits" group.long 0xD8++0x3 line.long 0x00 "DISPC_VID1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means ne.." group.long 0xDC++0x3 line.long 0x00 "DISPC_VID1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation. The register is used only when the TILER is not present in the.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The v.." group.long 0xE0++0x3 line.long 0x00 "DISPC_VID1_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secon.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0xE4++0x3 line.long 0x00 "DISPC_VID1_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 1 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or wh.." hexmask.long.word 0x00 16.--26. 1. " ORGSIZEY ,Number of lines of the video picture. Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of.." hexmask.long.word 0x00 0.--10. 1. " ORGSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line .." group.long 0x130++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x134++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GY ,GY Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RCB ,RCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x138++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GCB ,GCb Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " GCR ,GCr Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x13C++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " BCR ,BCr coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " BY ,BY coefficient Encoded signed value (from -1024 to 1023)." group.long 0x140++0x3 line.long 0x00 "DISPC_VID1_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 0.--10. 1. " BCB ,BCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x154++0x3 line.long 0x00 "DISPC_VID2_POSITION,The register configures the position of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is .." hexmask.long.word 0x00 16.--26. 1. " POSY ,Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0." hexmask.long.word 0x00 0.--10. 1. " POSX ,X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0." group.long 0x158++0x3 line.long 0x00 "DISPC_VID2_SIZE,The register configures the size of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished.." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the video 2 Encoded value (from 1 to 2048) to specify the number of lines of the video window 2. Program to value minus 1." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the video window 2 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 2. Program to value minus 1." group.long 0x15C++0x3 line.long 0x00 "DISPC_VID2_ATTRIBUTES,The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame.." bitfld.long 0x00 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero) - . - . - ." "PrimaryLCDSel,SecondaryLCDSel,2,WriteBacksel1" bitfld.long 0x00 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. - . - ." "INC,BLCK" bitfld.long 0x00 28. " PREMULTIPLYALPHA ,The field configures the DISPC VID2 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data. - . - ." "0,1" textline " " bitfld.long 0x00 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is s.." "zorder0,zorder1,zorder2,zorder3" bitfld.long 0x00 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled. - . - ." "ZorderDis,ZorderEnb" bitfld.long 0x00 24. " SELFREFRESH ,Enables the self refresh of the video window from its own DMA buffer only. - . - ." "SelfRefreshDis,SelfRefreshEnb" textline " " bitfld.long 0x00 23. " ARBITRATION ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. Whe.." "NormalPrio,HighPrio" bitfld.long 0x00 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0. - . - ." "Initial,Double" bitfld.long 0x00 21. " VERTICALTAPS ,Video Vertical Resize Tap Number - . - ." "taps3,taps5" textline " " bitfld.long 0x00 20. " DMAOPTIMIZATION ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 19. " BUFPRELOAD ,Video Preload Value - . - ." "DefVal,HighThres" bitfld.long 0x00 17. " SELFREFRESHAUTO ,Automatic self-refresh mode - . - ." "SelfRefreshAutoDis,SelfRefreshAutoEn" textline " " bitfld.long 0x00 16. " CHANNELOUT ,Video Channel Out configuration: LCD, WB or TV. wr: immediate - . - ." "LCDOp,TVOp" bitfld.long 0x00 14.--15. " BURSTSIZE ,Video DMA Burst Size - . - . - . - ." "Burst2x128b,Burst4x128b,Burst8x128b,Res" bitfld.long 0x00 12.--13. " ROTATION ,Video Rotation Flag - . - . - . - ." "NoRot,Rot90,Rot180,Rot270" textline " " bitfld.long 0x00 11. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 10. " REPLICATIONENABLE ,Replication Enable - . - ." "VRepLDis,VRepLEnb" bitfld.long 0x00 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV. - . - ." "ColSpCDis,ColSpCEnb" textline " " bitfld.long 0x00 8. " VRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 7. " HRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 5.--6. " RESIZEENABLE ,Video Resize Enable - . - . - . - ." "ReSizeProc,HReSize,2,3" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Video Format. It defines the pixel format when fetching the video 2 picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "NV12,RGBx12,RGBA12,3,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24,YUV2,UYVY,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,VidEnable - . - ." "VideoDis,VideoEnb" group.long 0x160++0x3 line.long 0x00 "DISPC_VID2_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software an.." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." rgroup.long 0x164++0x3 line.long 0x00 "DISPC_VID2_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 2." hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,DMA buffer size in number of 128 bits" group.long 0x168++0x3 line.long 0x00 "DISPC_VID2_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means ne.." group.long 0x16C++0x3 line.long 0x00 "DISPC_VID2_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation. The register is used only when the TILER is not present in the.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The v.." group.long 0x170++0x3 line.long 0x00 "DISPC_VID2_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secon.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x174++0x3 line.long 0x00 "DISPC_VID2_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 2 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or wh.." hexmask.long.word 0x00 16.--26. 1. " ORGSIZEY ,Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of .." hexmask.long.word 0x00 0.--10. 1. " ORGSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line .." group.long 0x1C0++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1C4++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GY ,GY Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RCB ,RCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1C8++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GCB ,GCb Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " GCR ,GCr Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1CC++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " BCR ,BCr coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " BY ,BY coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1D0++0x3 line.long 0x00 "DISPC_VID2_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 0.--10. 1. " BCB ,BCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x1D4++0x3 line.long 0x00 "DISPC_DATA1_CYCLE1,The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of primary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x1D8++0x3 line.long 0x00 "DISPC_DATA1_CYCLE2,The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of primary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x1DC++0x3 line.long 0x00 "DISPC_DATA1_CYCLE3,The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of primary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x220++0x3 line.long 0x00 "DISPC_CPR1_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 22.--31. 1. " RR ,RR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " RG ,RG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " RB ,RB Coefficient Encoded signed value (from -512 to 511)." group.long 0x224++0x3 line.long 0x00 "DISPC_CPR1_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 22.--31. 1. " GR ,GR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " GG ,GG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " GB ,GB Coefficient Encoded signed value (from -512 to 511)." group.long 0x228++0x3 line.long 0x00 "DISPC_CPR1_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x00 22.--31. 1. " BR ,BR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " BG ,BG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " BB ,BB Coefficient Encoded signed value (from -512 to 511)." group.long 0x22C++0x3 line.long 0x00 "DISPC_GFX_PRELOAD,The register configures the graphics DMA buffer Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no m.." hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." group.long 0x230++0x3 line.long 0x00 "DISPC_VID1_PRELOAD,The register configures the DMA buffer of the video 1 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame .." hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." group.long 0x234++0x3 line.long 0x00 "DISPC_VID2_PRELOAD,The register configures the DMA buffer of the video 2 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame .." hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." group.long 0x238++0x3 line.long 0x00 "DISPC_CONTROL2,The control register configures the Display Controller module for the secondary LCD output. Shadow registers are updated during the VFP start period of the secondary LCD, EVSYNC, or when.GOWB is set to 1 by software and the current WB fr.." bitfld.long 0x00 30.--31. " SPATIALTEMPORAL_DITHERINGFRAMES ,Spatial/Temporal dithering number of frames for the secondary LCD output wr: VFP start period of secondary LCD output - . - . - . - ." "Spatial_only,1,2,?..." bitfld.long 0x00 25.--26. " TDMUNUSED_BITS ,State of unused bits (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - . - . - . - ." "low_level_(0),high_level_(1),2,?..." bitfld.long 0x00 23.--24. " TDMCYCLE_FORMAT ,Cycle format (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 21.--22. " TDMPARALLEL_MODE ,Output Interface width (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " TDMENABLE ,Enable the multiple cycle format (TDM mode only used for Active Matrix mode with the RFBI enable bit off) for the secondary LCD output wr: VFP start period of secondary LCD output - . - ." "TDMDis,TDMEnb" bitfld.long 0x00 13. " TVOVERLAY_OPTIMIZATION ,Overlay Optimization for the TV output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization eve.." "0,1" textline " " bitfld.long 0x00 12. " OVERLAY_OPTIMIZATION ,Overlay Optimization for the secondary LCD output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization eve.." "0,1" bitfld.long 0x00 11. " STALLMODE ,STALL Mode for the secondary LCD output wr: VFP start period of secondary LCD output - . - ." "nMode,RFBIMode" bitfld.long 0x00 8.--9. " TFTDATALINES ,Number of lines of the secondary LCD interface wr: VFP start period of secondary LCD output - . - . - . - ." "OaLSB12b,OaLSB16b,OaLSB18b,OaLSB24b" textline " " bitfld.long 0x00 7. " STDITHER_ENABLE ,Spatial Temporal dithering enable for the secondary LCD output wr: VFP start period of secondary LCD output - . - ." "0,1" bitfld.long 0x00 6. " GOWB ,GO Command for the write-back output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the write-back output to the memory. wr:immediate - . - ." "HfUISR,UfPSR" bitfld.long 0x00 5. " GOLCD ,GO Command for the secondary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the secondary LCD output. wr:immediate - . - ." "HfUISR,UfPSR" textline " " bitfld.long 0x00 4. " M8B ,Mono 8-bit mode of the secondary LCD wr: VFP start period of secondary LCD output - . - ." "4PixtoPanel,8PixtoPanel" bitfld.long 0x00 3. " STNTFT ,LCD Display type of the secondary LCD wr: VFP start period of secondary LCD output - . - ." "STNdispEnb,ATFTDisEnb" bitfld.long 0x00 2. " MONOCOLOR ,Monochrome/Color selection for the secondary LCD wr: VFP start period of secondary LCD output - . - ." "ColOpEnb,MonOpEnb" textline " " bitfld.long 0x00 0. " LCDENABLE ,Enable the secondary LCD output wr:immediate - . - ." "LCDOpDis,LCDOpEnb" group.long 0x370++0x3 line.long 0x00 "DISPC_VID3_ATTRIBUTES,The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame.." bitfld.long 0x00 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate - . - . - ." "PrimaryLCDSel,SecondaryLCDSel,2,WriteBacksel1" bitfld.long 0x00 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. - . - ." "INC,BLCK" bitfld.long 0x00 28. " PREMULTIPLYALPHA ,The field configures the DISPC VID3 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data. - . - ." "0,1" textline " " bitfld.long 0x00 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is s.." "zorder0,zorder1,zorder2,zorder3" bitfld.long 0x00 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled. - . - ." "ZorderDis,ZorderEnb" bitfld.long 0x00 24. " SELFREFRESH ,Enables the self refresh of the video window from its own DMA buffer only. - . - ." "SelfRefreshDis,SelfRefreshEnb" textline " " bitfld.long 0x00 23. " ARBITRATION ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. Whe.." "NormalPrio,HighPrio" bitfld.long 0x00 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0. - . - ." "Initial,Double" bitfld.long 0x00 21. " VERTICALTAPS ,Video Vertical Resize Tap Number - . - ." "taps3,taps5" textline " " bitfld.long 0x00 20. " DMAOPTIMIZATION ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 19. " BUFPRELOAD ,Video Preload Value - . - ." "DefVal,HighThres" bitfld.long 0x00 17. " SELFREFRESHAUTO ,Automatic self-refresh mode - . - ." "SelfRefreshAutoDis,SelfrefreshAutoEn" textline " " bitfld.long 0x00 16. " CHANNELOUT ,Video Channel Out configuration: LCD, WB or TV. wr: immediate - . - ." "LCDOp,TVOp" bitfld.long 0x00 14.--15. " BURSTSIZE ,Video DMA Burst Size - . - . - . - ." "Burst2x128b,Burst4x128b,Burst8x128b,Res" bitfld.long 0x00 12.--13. " ROTATION ,Video Rotation Flag - . - . - . - ." "NoRot,Rot90,Rot180,Rot270" textline " " bitfld.long 0x00 11. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 10. " REPLICATIONENABLE ,Replication Enable - . - ." "VRepLDis,VRepLEnb" bitfld.long 0x00 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV. - . - ." "ColSpCDis,ColSpCEnb" textline " " bitfld.long 0x00 8. " VRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 7. " HRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x00 5.--6. " RESIZEENABLE ,Video Resize Enable - . - . - . - ." "ReSizeProc,HReSize,2,3" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Video Format. It defines the pixel format when fetching the video 3 picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "NV12,RGBx12,RGBA12,3,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24,YUV2,UYVY,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,Video Enable - . - ." "VideoDis,VideoEnb" group.long 0x374++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x378++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GY ,GY Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " RCB ,RCb Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x37C++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " GCB ,GCb Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " GCR ,GCr Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x380++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 16.--26. 1. " BCR ,BCr coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " BY ,BY coefficient Encoded signed value (from -1024 to 1023)." group.long 0x384++0x3 line.long 0x00 "DISPC_VID3_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to.." hexmask.long.word 0x00 0.--10. 1. " BCB ,BCb Coefficient Encoded signed value (from -1024 to 1023)." rgroup.long 0x388++0x3 line.long 0x00 "DISPC_VID3_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 3." hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,DMA buffer Size in number of 128-bits." group.long 0x38C++0x3 line.long 0x00 "DISPC_VID3_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software an.." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." group.long 0x390++0x3 line.long 0x00 "DISPC_VID3_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secon.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x394++0x3 line.long 0x00 "DISPC_VID3_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 3 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or wh.." hexmask.long.word 0x00 16.--26. 1. " ORGSIZEY ,Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of .." hexmask.long.word 0x00 0.--10. 1. " ORGSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line .." group.long 0x398++0x3 line.long 0x00 "DISPC_VID3_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 3. For more information, see, Predecimation. The register is used only when the TILER is not present in the.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The v.." group.long 0x39C++0x3 line.long 0x00 "DISPC_VID3_POSITION,The register configures the position of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is .." hexmask.long.word 0x00 16.--26. 1. " POSY ,Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0." hexmask.long.word 0x00 0.--10. 1. " POSX ,X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0." group.long 0x3A0++0x3 line.long 0x00 "DISPC_VID3_PRELOAD,The register configures the DMA buffer of the video 3 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame .." hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." group.long 0x3A4++0x3 line.long 0x00 "DISPC_VID3_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means ne.." group.long 0x3A8++0x3 line.long 0x00 "DISPC_VID3_SIZE,The register configures the size of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished.." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the video 3 Encoded value (from 1 to 2048) to specify the number of lines of the video window 3. Program to value minus 1." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the video window 3 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 3. Program to value minus 1." group.long 0x3AC++0x3 line.long 0x00 "DISPC_DEFAULT_COLOR2,The control register allows to configure the default solid background color for the secondary LCD Shadow register, updated on VFP start period of secondary LCD" hexmask.long.tbyte 0x00 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays." group.long 0x3B0++0x3 line.long 0x00 "DISPC_TRANS_COLOR2,The register sets the transparency color value for the video/graphics overlays for the secondary LCD output. Shadow register, updated on VFP start period of the secondary LCD" hexmask.long.tbyte 0x00 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [2.." group.long 0x3B4++0x3 line.long 0x00 "DISPC_CPR2_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 22.--31. 1. " BR ,BR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " BG ,BG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " BB ,BB Coefficient Encoded signed value (from -512 to 511)." group.long 0x3B8++0x3 line.long 0x00 "DISPC_CPR2_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 22.--31. 1. " GR ,GR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " GG ,GG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " GB ,GB Coefficient Encoded signed value (from -512 to 511)." group.long 0x3BC++0x3 line.long 0x00 "DISPC_CPR2_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 22.--31. 1. " RR ,RR Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 11.--20. 1. " RG ,RG Coefficient Encoded signed value (from -512 to 511)." hexmask.long.word 0x00 0.--9. 1. " RB ,RB Coefficient Encoded signed value (from -512 to 511)." group.long 0x3C0++0x3 line.long 0x00 "DISPC_DATA2_CYCLE1,The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x3C4++0x3 line.long 0x00 "DISPC_DATA2_CYCLE2,The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x3C8++0x3 line.long 0x00 "DISPC_DATA2_CYCLE3,The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0x3CC++0x3 line.long 0x00 "DISPC_SIZE_LCD2,The register configures the panel size (horizontal and vertical). It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD. A delta value is used to indicate if the odd field has same vertic.." hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel Encoded value (from 1 to 2048) to specify the number of lines per panel (program to value minus 1)." bitfld.long 0x00 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field - . - . - ." "Same,PlusOne,MinusOne,3" hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only va.." group.long 0x400++0x3 line.long 0x00 "DISPC_TIMING_H2,The register configures the timing logic for the HSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 20.--31. 1. " HBP ,Horizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to valu.." hexmask.long.word 0x00 8.--19. 1. " HFP ,Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1)." hexmask.long.byte 0x00 0.--7. 1. " HSW ,Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1)." group.long 0x404++0x3 line.long 0x00 "DISPC_TIMING_V2,The register configures the timing logic for the VSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x00 20.--31. 1. " VBP ,Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display." hexmask.long.word 0x00 8.--19. 1. " VFP ,Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame." hexmask.long.byte 0x00 0.--7. 1. " VSW ,Vertical synchronization pulse width In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of .." group.long 0x408++0x3 line.long 0x00 "DISPC_POL_FREQ2,The register configures the signal configuration. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x00 18. " ALIGN ,Defines the alignment between HSYNC and VSYNC assertion. - . - ." "notAligned,Aligned" bitfld.long 0x00 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/Off - . - ." "DOpEdPCk,DBit16" bitfld.long 0x00 16. " RF ,Program HSYNC/VSYNC Rise or Fall - . - ." "DFEdPCk,DRiEdPCk" textline " " bitfld.long 0x00 15. " IEO ,Invert output enable - . - ." "ACBaHigh,ACBaLow" bitfld.long 0x00 14. " IPC ,Invert pixel clock - . - ." "DrPCk,DfPCk" bitfld.long 0x00 13. " IHS ,Invert HSYNC - . - ." "LCkpinAh,LCkpinAl" textline " " bitfld.long 0x00 12. " IVS ,Invert VSYNC - . - ." "FCkpinAh,FCkpinAl" bitfld.long 0x00 8.--11. " ACBI ,AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " ACB ,AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supp.." group.long 0x40C++0x3 line.long 0x00 "DISPC_DIVISOR2,The register configures the divisors. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.byte 0x00 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD2_CLK. The value 0 is invalid." hexmask.long.byte 0x00 0.--7. 1. " PCD ,Pixel Clock Divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD2_CLK divided byDISPC_DIVISOR2.LCD value. The values 0 is invalid." group.long 0x570++0x3 line.long 0x00 "DISPC_WB_ATTRIBUTES,The register configures the attributes of the viwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is direc.." bitfld.long 0x00 28.--31. " IDLENUMBER ,Determines the number of idles between requests on the L3 interconnect. It is only used when the write-back pipeline does data transfer from memory to memory. When the output of an overlay is stored in memory through t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " IDLESIZE ,Determines if the IDLENUMBER corresponds to a number of bursts or singles. - . - ." "IdleSingle,IdleBurst" bitfld.long 0x00 24.--26. " CAPTUREMODE ,Defines the frame rate capture. - . - . - . - . - . - . - . - ." "All,Only1,Only1_2,Only1_3,Only1_4,Only1_5,Only1_6,Only1_7" textline " " bitfld.long 0x00 23. " ARBITRATION ,Determines the priority of the write-back pipeline. The write-back pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between.." "NormalPrio,HighPrio" bitfld.long 0x00 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0. - . - ." "Initial,Double" bitfld.long 0x00 21. " VERTICALTAPS ,Video Vertical Resize Tap Number - . - ." "taps3,taps5" textline " " bitfld.long 0x00 19. " WRITEBACKMODE ,When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel. 0x0: Capture mode (default mode) 0x1: Memory-to-memo.." "0,1" bitfld.long 0x00 16.--18. " CHANNELIN ,Video Channel In configuration wr: immediate - . - . - . - . - . - . - ." "LCD1,LCD2,TV,Gfx,Vid1,Vid2,Vid3,7" bitfld.long 0x00 14.--15. " BURSTSIZE ,Write-back DMA Burst Size - . - . - . - ." "Burst2x128b,Burst4x128b,Burst8x128b,Res" textline " " bitfld.long 0x00 11. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 10. " TRUNCATIONENABLE ,It applies only when the input format to the write-back pipeline from the overlay or directly from one of the pipelines is ARGB32. If the format is one of the YUV supported formats, the bit field is ignored. -.." "WBTruncDis,WBTruncEnb" bitfld.long 0x00 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV. - . - ." "ColSpCDis,ColSpCEnb" textline " " bitfld.long 0x00 8. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. - . - ." "1D_burst,2D_burst" bitfld.long 0x00 7. " ALPHAENABLE ,Premultiplied alpha enable Read 0x1: Enabled Read 0x0: Disabled. This bit also disable the logic present in the associated channel out that compute the alpha component sent to the WB pipe. When the WB is conf.." "0,1" bitfld.long 0x00 5.--6. " RESIZEENABLE ,Resize Enable - . - . - . - ." "ReSizeProc,HReSize,2,3" textline " " bitfld.long 0x00 1.--4. " FORMAT ,Write-back Format. It defines the pixel format when storing the write-back picture into memory. - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "NV12,RGBx12,RGBA12,3,xRGB12,ARGB16,RGB16,ARGB16_1,xRGB24,RGB24,YUV2,UYVY,ARGB32,RGBA32,RGBx24,xRGB15" bitfld.long 0x00 0. " ENABLE ,Write-back Enable. wr: immediate - . - ." "WBDis,WBEnb" group.long 0x574++0x3 line.long 0x00 "DISPC_WB_CONV_COEF0,The register configures the color space conversion matrix coefficients for the write back pipeline (YUV4:4:4 to RGB24) Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the .." hexmask.long.word 0x00 16.--26. 1. " YG ,YG Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " YR ,YR Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x578++0x3 line.long 0x00 "DISPC_WB_CONV_COEF1,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline.." hexmask.long.word 0x00 16.--26. 1. " CRR ,CrR Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " YB ,YB Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x57C++0x3 line.long 0x00 "DISPC_WB_CONV_COEF2,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline.." hexmask.long.word 0x00 16.--26. 1. " CRB ,CrB Coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " CRG ,CrG Coefficient Encoded signed value (from -1024 to 1023)." group.long 0x580++0x3 line.long 0x00 "DISPC_WB_CONV_COEF3,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline.." hexmask.long.word 0x00 16.--26. 1. " CBG ,CbG coefficient Encoded signed value (from -1024 to 1023)." hexmask.long.word 0x00 0.--10. 1. " CBR ,CbR coefficient Encoded signed value (from -1024 to 1023)." group.long 0x584++0x3 line.long 0x00 "DISPC_WB_CONV_COEF4,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline.." hexmask.long.word 0x00 0.--10. 1. " CBB ,CbB Coefficient Encoded signed value (from -1024 to 1023)." rgroup.long 0x588++0x3 line.long 0x00 "DISPC_WB_BUF_SIZE_STATUS,The register defines the DMA buffer size for the write back pipeline." hexmask.long.word 0x00 0.--15. 1. " BUFSIZE ,DMA buffer Size in number of 128-bits." group.long 0x58C++0x3 line.long 0x00 "DISPC_WB_BUF_THRESHOLD,The register configures the DMA buffer associated with the write-back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pip.." hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." hexmask.long.word 0x00 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer High Threshold Number of 128-bits defining the threshold value." group.long 0x590++0x3 line.long 0x00 "DISPC_WB_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the write back pipeline. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finish.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x594++0x3 line.long 0x00 "DISPC_WB_PICTURE_SIZE,The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in.." hexmask.long.word 0x00 16.--26. 1. " ORGSIZEY ,Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1)." hexmask.long.word 0x00 0.--10. 1. " ORGSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line .." group.long 0x598++0x3 line.long 0x00 "DISPC_WB_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the write back pipeline. The register is used only when the TILER is not present in the system in order to perform low perform.." hexmask.long.byte 0x00 0.--7. 1. " PIXELINC ,Values other than 1 are invalid" group.long 0x5A4++0x3 line.long 0x00 "DISPC_WB_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the vwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no mor.." hexmask.long 0x00 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means ne.." group.long 0x5A8++0x3 line.long 0x00 "DISPC_WB_SIZE,The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline. When the overlay is output on the primary LCD or secondary LCD or TV outputs, .." hexmask.long.word 0x00 16.--26. 1. " SIZEY ,Number of lines of the Write-back picture Encoded value (from 1 to 2048) to specify the number of lines of the write-back picture. Program to value minus 1." hexmask.long.word 0x00 0.--10. 1. " SIZEX ,Number of pixels of the Write-back picture Encoded value (from 1 to 2048) to specify the number of pixels of the write-back picture. Program to value minus 1." group.long 0x620++0x3 line.long 0x00 "DISPC_CONFIG2,The control register configures the Display Controller module for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD or EVSYNC" bitfld.long 0x00 25. " FULLRANGE ,Color Space Conversion full range setting. - . - ." "Limrange,FullRange" bitfld.long 0x00 24. " COLORCONV_ENABLE ,Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1. - . - ." "0,1" bitfld.long 0x00 23. " FIDFIRST ,Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. - . - ." "Even,Odd" textline " " bitfld.long 0x00 22. " OUTPUTMODE_ENABLE ,Selects between progressive and interlace mode for the secondary LCD output. - . - ." "0,Interlace_mode_selected." bitfld.long 0x00 16. " BUFFERHAND_CHECK ,Controls the handcheck between DMA buffer and STALL signal in order to prevent from underflow. The bit shall be set to 0 when the module is not in STALL mode. (secondary LCD output) - . - ." "0,1" bitfld.long 0x00 15. " CPR ,Color Phase Rotation Control secondary LCD output). It shall be reset when ColorConvEnable bit field is set to 1. wr: VFP start period of secondary LCD output - . - ." "CPRDis,CPREnb" textline " " bitfld.long 0x00 11. " TCKLCD_SELECTION ,Transparency Color Key Selection (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "0,1" bitfld.long 0x00 10. " TCKLCDENABLE ,Transparency Color Key Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "DisTCK,EnbTCK" bitfld.long 0x00 8. " ACBIASGATED ,ACBias Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "ACBGDis,ACBGEnb" textline " " bitfld.long 0x00 7. " VSYNCGATED ,VSYNC Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "VGDis,VGEnb" bitfld.long 0x00 6. " HSYNCGATED ,HSYNC Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "HGDis,HGEnb" bitfld.long 0x00 5. " PIXELCLOCK_GATED ,Pixel Clock Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "0,1" textline " " bitfld.long 0x00 4. " PIXELDATA_GATED ,Pixel Data Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "0,1" bitfld.long 0x00 0. " PIXELGATED ,Pixel Gated Enable (only for Active Matrix) (secondary LCD output) wr: VFP start period of secondary LCD output - . - ." "PclkTogA,PclkTogV" group.long 0x624++0x3 line.long 0x00 "DISPC_VID1_ATTRIBUTES2,The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB fram.." bitfld.long 0x00 8. " YUVCHROMARE_SAMPLING ,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphas.." "0,1" bitfld.long 0x00 4.--6. " VC1_RANGE__CBCR ,Defines the VC-1 range value for the CbCr component from 0 to 7." "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " VC1_RANGE_Y ,Defines the VC-1 range value for the Y component from 0 to 7." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " VC1ENABLE ,Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats. - . - ." "VC1Dis,VC1Enb" group.long 0x628++0x3 line.long 0x00 "DISPC_VID2_ATTRIBUTES2,The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB fram.." bitfld.long 0x00 8. " YUVCHROMARE_SAMPLING ,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphas.." "0,1" bitfld.long 0x00 4.--6. " VC1_RANGE__CBCR ,Defines the VC-1 range value for the CbCr component from 0 to 7." "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " VC1_RANGE_Y ,Defines the VC-1 range value for the Y component from 0 to 7." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " VC1ENABLE ,Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats. - . - ." "VC1Dis,VC1Enb" group.long 0x62C++0x3 line.long 0x00 "DISPC_VID3_ATTRIBUTES2,The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB fram.." bitfld.long 0x00 8. " YUVCHROMARE_SAMPLING ,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphas.." "0,1" bitfld.long 0x00 4.--6. " VC1_RANGE__CBCR ,Defines the VC-1 range value for the CbCr component from 0 to 7." "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " VC1_RANGE_Y ,Defines the VC-1 range value for the Y component from 0 to 7." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " VC1ENABLE ,Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats. - . - ." "VC1Dis,VC1Enb" wgroup.long 0x630++0x3 line.long 0x00 "DISPC_GAMMA_TABLE0,The register configures the look up table used as color look up table for BITMAP formats (1-, 2-, 4, and 8-bpp) on the graphics pipeline or as gamma table on the primary LCD output." hexmask.long.byte 0x00 24.--31. 1. " INDEX ,Defines the location in the table where the bit field VALUE is stored." hexmask.long.byte 0x00 16.--23. 1. " VALUE_R ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." hexmask.long.byte 0x00 8.--15. 1. " VALUE_G ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." textline " " hexmask.long.byte 0x00 0.--7. 1. " VALUE_B ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." wgroup.long 0x634++0x3 line.long 0x00 "DISPC_GAMMA_TABLE1,The register configures the gamma table on the secondary LCD output." hexmask.long.byte 0x00 24.--31. 1. " INDEX ,Defines the location in the table where the bit field VALUE is stored." hexmask.long.byte 0x00 16.--23. 1. " VALUE_R ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." hexmask.long.byte 0x00 8.--15. 1. " VALUE_G ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." textline " " hexmask.long.byte 0x00 0.--7. 1. " VALUE_B ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX." wgroup.long 0x638++0x3 line.long 0x00 "DISPC_GAMMA_TABLE2,The register configures the gamma table on the TV output." bitfld.long 0x00 31. " INDEX ,Setting this bit to 1 resets the internal index counter to zero. Each subsequent access to the register (with the INDEX bit kept at 0) increments the address for the next storage location into the table memory." "0,1" hexmask.long.word 0x00 20.--29. 1. " VALUE_R ,10-bit color component value to store in the table." hexmask.long.word 0x00 10.--19. 1. " VALUE_G ,10-bit color component value to store in the table." textline " " hexmask.long.word 0x00 0.--9. 1. " VALUE_B ,10-bit color component value to store in the table." group.long 0x63C++0x3 line.long 0x00 "DISPC_VID1_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats..." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x6A8++0x3 line.long 0x00 "DISPC_VID2_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats..." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x724++0x3 line.long 0x00 "DISPC_VID3_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats..." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x790++0x3 line.long 0x00 "DISPC_WB_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the write-back pipeline. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV forma.." hexmask.long.word 0x00 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." hexmask.long.word 0x00 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." group.long 0x800++0x3 line.long 0x00 "DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipeline (graphics, video1, video2, video3 and write-back). Both TOP and BOTTOM must be allocated to the same pipeline." bitfld.long 0x00 27.--29. " WB_BOTTOM__BUFFER ,Write-back DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to write-back pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " WB_TOP__BUFFER ,Write-back DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to write-back pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. " VID3_BOTTOM__BUFFER ,Video3 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video3 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18.--20. " VID3_TOP__BUFFER ,Video3 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video3 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " VID2_BOTTOM__BUFFER ,Video2 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video2 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " VID2_TOP__BUFFER ,Video2 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video2 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " VID1_BOTTOM__BUFFER ,Video1 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video1 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " VID1_TOP__BUFFER ,Video1 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video 1 pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " GFX_BOTTOM__BUFFER ,Graphics DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to graphics pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " GFX_TOP__BUFFER ,Graphics DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to graphics pipeline. - . - . - . - . - ." "0,1,2,3,4,5,6,7" group.long 0x804++0x3 line.long 0x00 "DISPC_DIVISOR,The register configures the divisor value for generating the core functional clock. There is a backward compatibility mode enabled by default in order to use.LCD value instead of .LCD bit field for generating the core functional clock." hexmask.long.byte 0x00 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the frequency of the Display Controller logic clock based on the function clock. The value 0 is invalid." bitfld.long 0x00 0. " ENABLE ,When the bit field is set to 1, the bit field LCD is used to generated the core functional clock from the input clock. When the bit field is set to 0, the valueDISPC_DIVISOR1.LCD is used instead. - . - .." "Disable,Enable" group.long 0x810++0x3 line.long 0x00 "DISPC_WB_ATTRIBUTES2,The register set the counter to control the delay to flush the WB pipe after the end of the frame in capture mode. Shadow register, updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending.." hexmask.long.byte 0x00 0.--7. 1. " WBDELAYCOUNT ,Delays the WB pipe flush after the end of the frame.delay = n x (1/F_clk) n = 0:255" tree.end tree.end tree.end tree.open "MIPI_Display_Serial_Interface" tree.open "DSI1_PLLCTRL_L4_PER" tree "DSI1_PLLCTRL_L4_PER" base ad:0x48044300 width 28. group.long 0x0++0x3 line.long 0x00 "DSI_PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. " HSDIV_SYSRESET ,Force HSDIVIDER SYSRESET - . - ." "0,1" bitfld.long 0x00 3. " PLL_SYSRESET ,Force DSI PLL SYSRESET - . - ." "0,1" bitfld.long 0x00 2. " PLL_HALTMODE ,Allow PLL to be halted if no activity. Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ." "0,1" textline " " bitfld.long 0x00 1. " PLL_GATEMODE ,Allow PLL clock gating for power saving Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ." "CLKIN4DDR_clock_on,1" bitfld.long 0x00 0. " PLL_AUTOMODE ,Automatic update mode. If this bit is set then the configuration updates will be synchronised to DISPCUpdateSync. If this bit is clear configuration updates will be done immediately. Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ..." "Manual_mode,Automatic_mode" rgroup.long 0x4++0x3 line.long 0x00 "DSI_PLL_STATUS,This register contains the status information" bitfld.long 0x00 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledge - . - ." "0,1" bitfld.long 0x00 11. " M7_CLOCK_ACK ,Acknowledge for enable of clock Verify the status before selecting this source in the clock mux - . - ." "M7_clock_inactive,M7_clock_active" bitfld.long 0x00 9. " BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER - . - ." "0,1" textline " " bitfld.long 0x00 8. " M5_CLOCK_ACK ,Acknowledge for enable of DSI Protcol Engine clock Verify the status before selecting this source in the DSI Protcol Engine clock mux - . - ." "0,1" bitfld.long 0x00 7. " M4_CLOCK_ACK ,Acknowledge for enable of clock Verify the status before selecting this source in the clock mux - . - ." "M4_clock_inactive,M4_clock_active" bitfld.long 0x00 6. " PLL_BYPASS ,DSI PLL Bypass status - . - ." "PLL_not_bypassing,PLL_bypass" textline " " bitfld.long 0x00 5. " PLL_HIGHJITTER ,PLL High Jitter status - . - ." "0,1" bitfld.long 0x00 4. " PLL_LIMP ,PLL Limp status - . - ." "LIMP_mode_inactive,LIMP_mode_active" bitfld.long 0x00 3. " PLL_LOSSREF ,PLL Reference Loss status - . - ." "Reference_input_active,Reference_input_inactive" textline " " bitfld.long 0x00 2. " PLL_RECAL ,PLL recalibration status If this bit is active, the PLL needs to be recalibrated - . - ." "0,Recalibration_is_required" bitfld.long 0x00 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit - . - ." "0,PLL_is_locked" bitfld.long 0x00 0. " DSI1_PLLCTRL_RESET_DONE ,DSI1_PLLCTRL reset done status - . - ." "0,Reset_has_completed" group.long 0x8++0x3 line.long 0x00 "DSI_PLL_GO,This register contains the GO bit" bitfld.long 0x00 0. " PLL_GO ,Request (re-)locking sequence of the PLL. If the AutoMode bit is set, then this will be deferred until DISPCUpdate Sync goes active - . - ." "No_pending_action,1" group.long 0xC++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x00 26.--30. " M5_CLOCK_DIV ,Divider value for Protocol Engine clock source M5REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--25. " M4_CLOCK_DIV ,Divider value for clock source M4REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 9.--20. 1. " PLL_REGM ,M Divider for PLL" textline " " hexmask.long.byte 0x00 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference)Note: As a result of device-specific integration, the 8th MSB of this field has no effect; thus, the divider factor can be 0 to 127.. - ." bitfld.long 0x00 0. " PLL_STOPMODE ,PLL STOPMODE - . - ." "0,STOPMODE_is_selected" group.long 0x10++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x00 26. " M7_CLOCK_PWDN ,Power down for M7 clock source - . - ." "0,1" bitfld.long 0x00 25. " M7_CLOCK_EN ,Enable for M7 clock source - . - ." "0,1" bitfld.long 0x00 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode - . - ." "0,1" textline " " bitfld.long 0x00 19. " M5_CLOCK_PWDN ,Power down for Protocol Engine clock source - . - ." "0,1" bitfld.long 0x00 18. " M5_CLOCK_EN ,Enable for Protocol Engine clock source - . - ." "0,1" bitfld.long 0x00 17. " M4_CLOCK_PWDN ,Power down for M4 clock source - . - ." "0,1" textline " " bitfld.long 0x00 16. " M4_CLOCK_EN ,Enable for M4 clock source - . - ." "0,1" bitfld.long 0x00 15. " BYPASSEN ,Selects functional clock asCLKIN4DDR clock source - . - ." "0,1" bitfld.long 0x00 14. " PHY_CLKINEN ,CLKIN4DDR clock control - . - ." "0,1" textline " " bitfld.long 0x00 13. " PLL_REFEN ,PLL reference clock control - . - ." "0,1" bitfld.long 0x00 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLL - . - . - ." "Phase_Lock,Frequency_Lock,Spare,3" bitfld.long 0x00 8. " PLL_DRIFTGUARDEN ,PLL DRIFTGUARDEN - . - ." "0,1" textline " " bitfld.long 0x00 6. " PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY - . - ." "0,LOWCURRSTBY_is_selected" bitfld.long 0x00 5. " PLL_PLLLPMODE ,Select the power / performance of the PLL - . - ." "0,1" bitfld.long 0x00 0. " PLL_IDLE ,PLL IDLE: - . - ." "0,IDLE_is_selected" group.long 0x14++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x00 5.--9. " M7_CLOCK_DIV ,Divider value for M7 divider." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x18++0x3 line.long 0x00 "DSI_PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x00 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum. - . - ." "0,1" bitfld.long 0x00 0. " EN_SSC ,Spread Spectrum Clockiing enable - . - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "DSI_PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" hexmask.long.word 0x00 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for SSC - The ModFreqDivider is split into Mantissa and 2Exponent(ModFreqDivider = ModFreqDividerMantissa * 2ModFreqDividerExponent). . - . Bits [29:23] define the Mantissa.. - . B.." hexmask.long.tbyte 0x00 0.--19. 1. " DELTAM ,DeltaM control for SSC. Split into integer and fractional parts.Bits [19:18] define the integer part.. - . Bits [17:0] define the fractional part.. - ." tree.end tree "DSI2_PLLCTRL_L4_PER" base ad:0x48045300 width 28. group.long 0x0++0x3 line.long 0x00 "DSI_PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. " HSDIV_SYSRESET ,Force HSDIVIDER SYSRESET - . - ." "0,1" bitfld.long 0x00 3. " PLL_SYSRESET ,Force DSI PLL SYSRESET - . - ." "0,1" bitfld.long 0x00 2. " PLL_HALTMODE ,Allow PLL to be halted if no activity. Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ." "0,1" textline " " bitfld.long 0x00 1. " PLL_GATEMODE ,Allow PLL clock gating for power saving Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ." "CLKIN4DDR_clock_on,1" bitfld.long 0x00 0. " PLL_AUTOMODE ,Automatic update mode. If this bit is set then the configuration updates will be synchronised to DISPCUpdateSync. If this bit is clear configuration updates will be done immediately. Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ..." "Manual_mode,Automatic_mode" rgroup.long 0x4++0x3 line.long 0x00 "DSI_PLL_STATUS,This register contains the status information" bitfld.long 0x00 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledge - . - ." "0,1" bitfld.long 0x00 11. " M7_CLOCK_ACK ,Acknowledge for enable of clock Verify the status before selecting this source in the clock mux - . - ." "M7_clock_inactive,M7_clock_active" bitfld.long 0x00 9. " BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER - . - ." "0,1" textline " " bitfld.long 0x00 8. " M5_CLOCK_ACK ,Acknowledge for enable of DSI Protcol Engine clock Verify the status before selecting this source in the DSI Protcol Engine clock mux - . - ." "0,1" bitfld.long 0x00 7. " M4_CLOCK_ACK ,Acknowledge for enable of clock Verify the status before selecting this source in the clock mux - . - ." "M4_clock_inactive,M4_clock_active" bitfld.long 0x00 6. " PLL_BYPASS ,DSI PLL Bypass status - . - ." "PLL_not_bypassing,PLL_bypass" textline " " bitfld.long 0x00 5. " PLL_HIGHJITTER ,PLL High Jitter status - . - ." "0,1" bitfld.long 0x00 4. " PLL_LIMP ,PLL Limp status - . - ." "LIMP_mode_inactive,LIMP_mode_active" bitfld.long 0x00 3. " PLL_LOSSREF ,PLL Reference Loss status - . - ." "Reference_input_active,Reference_input_inactive" textline " " bitfld.long 0x00 2. " PLL_RECAL ,PLL recalibration status If this bit is active, the PLL needs to be recalibrated - . - ." "0,Recalibration_is_required" bitfld.long 0x00 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit - . - ." "0,PLL_is_locked" bitfld.long 0x00 0. " DSI1_PLLCTRL_RESET_DONE ,DSI1_PLLCTRL reset done status - . - ." "0,Reset_has_completed" group.long 0x8++0x3 line.long 0x00 "DSI_PLL_GO,This register contains the GO bit" bitfld.long 0x00 0. " PLL_GO ,Request (re-)locking sequence of the PLL. If the AutoMode bit is set, then this will be deferred until DISPCUpdate Sync goes active - . - ." "No_pending_action,1" group.long 0xC++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x00 26.--30. " M5_CLOCK_DIV ,Divider value for Protocol Engine clock source M5REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--25. " M4_CLOCK_DIV ,Divider value for clock source M4REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 9.--20. 1. " PLL_REGM ,M Divider for PLL" textline " " hexmask.long.byte 0x00 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference)Note: As a result of device-specific integration, the 8th MSB of this field has no effect; thus, the divider factor can be 0 to 127.. - ." bitfld.long 0x00 0. " PLL_STOPMODE ,PLL STOPMODE - . - ." "0,STOPMODE_is_selected" group.long 0x10++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x00 26. " M7_CLOCK_PWDN ,Power down for M7 clock source - . - ." "0,1" bitfld.long 0x00 25. " M7_CLOCK_EN ,Enable for M7 clock source - . - ." "0,1" bitfld.long 0x00 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode - . - ." "0,1" textline " " bitfld.long 0x00 19. " M5_CLOCK_PWDN ,Power down for Protocol Engine clock source - . - ." "0,1" bitfld.long 0x00 18. " M5_CLOCK_EN ,Enable for Protocol Engine clock source - . - ." "0,1" bitfld.long 0x00 17. " M4_CLOCK_PWDN ,Power down for M4 clock source - . - ." "0,1" textline " " bitfld.long 0x00 16. " M4_CLOCK_EN ,Enable for M4 clock source - . - ." "0,1" bitfld.long 0x00 15. " BYPASSEN ,Selects functional clock asCLKIN4DDR clock source - . - ." "0,1" bitfld.long 0x00 14. " PHY_CLKINEN ,CLKIN4DDR clock control - . - ." "0,1" textline " " bitfld.long 0x00 13. " PLL_REFEN ,PLL reference clock control - . - ." "0,1" bitfld.long 0x00 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLL - . - . - ." "Phase_Lock,Frequency_Lock,Spare,3" bitfld.long 0x00 8. " PLL_DRIFTGUARDEN ,PLL DRIFTGUARDEN - . - ." "0,1" textline " " bitfld.long 0x00 6. " PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY - . - ." "0,LOWCURRSTBY_is_selected" bitfld.long 0x00 5. " PLL_PLLLPMODE ,Select the power / performance of the PLL - . - ." "0,1" bitfld.long 0x00 0. " PLL_IDLE ,PLL IDLE: - . - ." "0,IDLE_is_selected" group.long 0x14++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x00 5.--9. " M7_CLOCK_DIV ,Divider value for M7 divider." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x18++0x3 line.long 0x00 "DSI_PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x00 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum. - . - ." "0,1" bitfld.long 0x00 0. " EN_SSC ,Spread Spectrum Clockiing enable - . - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "DSI_PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" hexmask.long.word 0x00 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for SSC - The ModFreqDivider is split into Mantissa and 2Exponent(ModFreqDivider = ModFreqDividerMantissa * 2ModFreqDividerExponent). . - . Bits [29:23] define the Mantissa.. - . B.." hexmask.long.tbyte 0x00 0.--19. 1. " DELTAM ,DeltaM control for SSC. Split into integer and fractional parts.Bits [19:18] define the integer part.. - . Bits [17:0] define the fractional part.. - ." tree.end tree "DSI1_PLLCTRL_L3" base ad:0x58004300 width 28. group.long 0x0++0x3 line.long 0x00 "DSI_PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. " HSDIV_SYSRESET ,Force HSDIVIDER SYSRESET - . - ." "0,1" bitfld.long 0x00 3. " PLL_SYSRESET ,Force DSI PLL SYSRESET - . - ." "0,1" bitfld.long 0x00 2. " PLL_HALTMODE ,Allow PLL to be halted if no activity. Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ." "0,1" textline " " bitfld.long 0x00 1. " PLL_GATEMODE ,Allow PLL clock gating for power saving Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ." "CLKIN4DDR_clock_on,1" bitfld.long 0x00 0. " PLL_AUTOMODE ,Automatic update mode. If this bit is set then the configuration updates will be synchronised to DISPCUpdateSync. If this bit is clear configuration updates will be done immediately. Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ..." "Manual_mode,Automatic_mode" rgroup.long 0x4++0x3 line.long 0x00 "DSI_PLL_STATUS,This register contains the status information" bitfld.long 0x00 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledge - . - ." "0,1" bitfld.long 0x00 11. " M7_CLOCK_ACK ,Acknowledge for enable of clock Verify the status before selecting this source in the clock mux - . - ." "M7_clock_inactive,M7_clock_active" bitfld.long 0x00 9. " BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER - . - ." "0,1" textline " " bitfld.long 0x00 8. " M5_CLOCK_ACK ,Acknowledge for enable of DSI Protcol Engine clock Verify the status before selecting this source in the DSI Protcol Engine clock mux - . - ." "0,1" bitfld.long 0x00 7. " M4_CLOCK_ACK ,Acknowledge for enable of clock Verify the status before selecting this source in the clock mux - . - ." "M4_clock_inactive,M4_clock_active" bitfld.long 0x00 6. " PLL_BYPASS ,DSI PLL Bypass status - . - ." "PLL_not_bypassing,PLL_bypass" textline " " bitfld.long 0x00 5. " PLL_HIGHJITTER ,PLL High Jitter status - . - ." "0,1" bitfld.long 0x00 4. " PLL_LIMP ,PLL Limp status - . - ." "LIMP_mode_inactive,LIMP_mode_active" bitfld.long 0x00 3. " PLL_LOSSREF ,PLL Reference Loss status - . - ." "Reference_input_active,Reference_input_inactive" textline " " bitfld.long 0x00 2. " PLL_RECAL ,PLL recalibration status If this bit is active, the PLL needs to be recalibrated - . - ." "0,Recalibration_is_required" bitfld.long 0x00 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit - . - ." "0,PLL_is_locked" bitfld.long 0x00 0. " DSI1_PLLCTRL_RESET_DONE ,DSI1_PLLCTRL reset done status - . - ." "0,Reset_has_completed" group.long 0x8++0x3 line.long 0x00 "DSI_PLL_GO,This register contains the GO bit" bitfld.long 0x00 0. " PLL_GO ,Request (re-)locking sequence of the PLL. If the AutoMode bit is set, then this will be deferred until DISPCUpdate Sync goes active - . - ." "No_pending_action,1" group.long 0xC++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x00 26.--30. " M5_CLOCK_DIV ,Divider value for Protocol Engine clock source M5REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--25. " M4_CLOCK_DIV ,Divider value for clock source M4REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 9.--20. 1. " PLL_REGM ,M Divider for PLL" textline " " hexmask.long.byte 0x00 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference)Note: As a result of device-specific integration, the 8th MSB of this field has no effect; thus, the divider factor can be 0 to 127.. - ." bitfld.long 0x00 0. " PLL_STOPMODE ,PLL STOPMODE - . - ." "0,STOPMODE_is_selected" group.long 0x10++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x00 26. " M7_CLOCK_PWDN ,Power down for M7 clock source - . - ." "0,1" bitfld.long 0x00 25. " M7_CLOCK_EN ,Enable for M7 clock source - . - ." "0,1" bitfld.long 0x00 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode - . - ." "0,1" textline " " bitfld.long 0x00 19. " M5_CLOCK_PWDN ,Power down for Protocol Engine clock source - . - ." "0,1" bitfld.long 0x00 18. " M5_CLOCK_EN ,Enable for Protocol Engine clock source - . - ." "0,1" bitfld.long 0x00 17. " M4_CLOCK_PWDN ,Power down for M4 clock source - . - ." "0,1" textline " " bitfld.long 0x00 16. " M4_CLOCK_EN ,Enable for M4 clock source - . - ." "0,1" bitfld.long 0x00 15. " BYPASSEN ,Selects functional clock asCLKIN4DDR clock source - . - ." "0,1" bitfld.long 0x00 14. " PHY_CLKINEN ,CLKIN4DDR clock control - . - ." "0,1" textline " " bitfld.long 0x00 13. " PLL_REFEN ,PLL reference clock control - . - ." "0,1" bitfld.long 0x00 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLL - . - . - ." "Phase_Lock,Frequency_Lock,Spare,3" bitfld.long 0x00 8. " PLL_DRIFTGUARDEN ,PLL DRIFTGUARDEN - . - ." "0,1" textline " " bitfld.long 0x00 6. " PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY - . - ." "0,LOWCURRSTBY_is_selected" bitfld.long 0x00 5. " PLL_PLLLPMODE ,Select the power / performance of the PLL - . - ." "0,1" bitfld.long 0x00 0. " PLL_IDLE ,PLL IDLE: - . - ." "0,IDLE_is_selected" group.long 0x14++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x00 5.--9. " M7_CLOCK_DIV ,Divider value for M7 divider." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x18++0x3 line.long 0x00 "DSI_PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x00 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum. - . - ." "0,1" bitfld.long 0x00 0. " EN_SSC ,Spread Spectrum Clockiing enable - . - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "DSI_PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" hexmask.long.word 0x00 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for SSC - The ModFreqDivider is split into Mantissa and 2Exponent(ModFreqDivider = ModFreqDividerMantissa * 2ModFreqDividerExponent). . - . Bits [29:23] define the Mantissa.. - . B.." hexmask.long.tbyte 0x00 0.--19. 1. " DELTAM ,DeltaM control for SSC. Split into integer and fractional parts.Bits [19:18] define the integer part.. - . Bits [17:0] define the fractional part.. - ." tree.end tree "DSI2_PLLCTRL_L3" base ad:0x58005300 width 28. group.long 0x0++0x3 line.long 0x00 "DSI_PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. " HSDIV_SYSRESET ,Force HSDIVIDER SYSRESET - . - ." "0,1" bitfld.long 0x00 3. " PLL_SYSRESET ,Force DSI PLL SYSRESET - . - ." "0,1" bitfld.long 0x00 2. " PLL_HALTMODE ,Allow PLL to be halted if no activity. Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ." "0,1" textline " " bitfld.long 0x00 1. " PLL_GATEMODE ,Allow PLL clock gating for power saving Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ." "CLKIN4DDR_clock_on,1" bitfld.long 0x00 0. " PLL_AUTOMODE ,Automatic update mode. If this bit is set then the configuration updates will be synchronised to DISPCUpdateSync. If this bit is clear configuration updates will be done immediately. Reserved when DSI1_PLLCTRL_AUTO is 0. - . - ..." "Manual_mode,Automatic_mode" rgroup.long 0x4++0x3 line.long 0x00 "DSI_PLL_STATUS,This register contains the status information" bitfld.long 0x00 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledge - . - ." "0,1" bitfld.long 0x00 11. " M7_CLOCK_ACK ,Acknowledge for enable of clock Verify the status before selecting this source in the clock mux - . - ." "M7_clock_inactive,M7_clock_active" bitfld.long 0x00 9. " BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER - . - ." "0,1" textline " " bitfld.long 0x00 8. " M5_CLOCK_ACK ,Acknowledge for enable of DSI Protcol Engine clock Verify the status before selecting this source in the DSI Protcol Engine clock mux - . - ." "0,1" bitfld.long 0x00 7. " M4_CLOCK_ACK ,Acknowledge for enable of clock Verify the status before selecting this source in the clock mux - . - ." "M4_clock_inactive,M4_clock_active" bitfld.long 0x00 6. " PLL_BYPASS ,DSI PLL Bypass status - . - ." "PLL_not_bypassing,PLL_bypass" textline " " bitfld.long 0x00 5. " PLL_HIGHJITTER ,PLL High Jitter status - . - ." "0,1" bitfld.long 0x00 4. " PLL_LIMP ,PLL Limp status - . - ." "LIMP_mode_inactive,LIMP_mode_active" bitfld.long 0x00 3. " PLL_LOSSREF ,PLL Reference Loss status - . - ." "Reference_input_active,Reference_input_inactive" textline " " bitfld.long 0x00 2. " PLL_RECAL ,PLL recalibration status If this bit is active, the PLL needs to be recalibrated - . - ." "0,Recalibration_is_required" bitfld.long 0x00 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit - . - ." "0,PLL_is_locked" bitfld.long 0x00 0. " DSI1_PLLCTRL_RESET_DONE ,DSI1_PLLCTRL reset done status - . - ." "0,Reset_has_completed" group.long 0x8++0x3 line.long 0x00 "DSI_PLL_GO,This register contains the GO bit" bitfld.long 0x00 0. " PLL_GO ,Request (re-)locking sequence of the PLL. If the AutoMode bit is set, then this will be deferred until DISPCUpdate Sync goes active - . - ." "No_pending_action,1" group.long 0xC++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x00 26.--30. " M5_CLOCK_DIV ,Divider value for Protocol Engine clock source M5REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--25. " M4_CLOCK_DIV ,Divider value for clock source M4REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 9.--20. 1. " PLL_REGM ,M Divider for PLL" textline " " hexmask.long.byte 0x00 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference)Note: As a result of device-specific integration, the 8th MSB of this field has no effect; thus, the divider factor can be 0 to 127.. - ." bitfld.long 0x00 0. " PLL_STOPMODE ,PLL STOPMODE - . - ." "0,STOPMODE_is_selected" group.long 0x10++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x00 26. " M7_CLOCK_PWDN ,Power down for M7 clock source - . - ." "0,1" bitfld.long 0x00 25. " M7_CLOCK_EN ,Enable for M7 clock source - . - ." "0,1" bitfld.long 0x00 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode - . - ." "0,1" textline " " bitfld.long 0x00 19. " M5_CLOCK_PWDN ,Power down for Protocol Engine clock source - . - ." "0,1" bitfld.long 0x00 18. " M5_CLOCK_EN ,Enable for Protocol Engine clock source - . - ." "0,1" bitfld.long 0x00 17. " M4_CLOCK_PWDN ,Power down for M4 clock source - . - ." "0,1" textline " " bitfld.long 0x00 16. " M4_CLOCK_EN ,Enable for M4 clock source - . - ." "0,1" bitfld.long 0x00 15. " BYPASSEN ,Selects functional clock asCLKIN4DDR clock source - . - ." "0,1" bitfld.long 0x00 14. " PHY_CLKINEN ,CLKIN4DDR clock control - . - ." "0,1" textline " " bitfld.long 0x00 13. " PLL_REFEN ,PLL reference clock control - . - ." "0,1" bitfld.long 0x00 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLL - . - . - ." "Phase_Lock,Frequency_Lock,Spare,3" bitfld.long 0x00 8. " PLL_DRIFTGUARDEN ,PLL DRIFTGUARDEN - . - ." "0,1" textline " " bitfld.long 0x00 6. " PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY - . - ." "0,LOWCURRSTBY_is_selected" bitfld.long 0x00 5. " PLL_PLLLPMODE ,Select the power / performance of the PLL - . - ." "0,1" bitfld.long 0x00 0. " PLL_IDLE ,PLL IDLE: - . - ." "0,IDLE_is_selected" group.long 0x14++0x3 line.long 0x00 "DSI_PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x00 5.--9. " M7_CLOCK_DIV ,Divider value for M7 divider." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x18++0x3 line.long 0x00 "DSI_PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x00 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum. - . - ." "0,1" bitfld.long 0x00 0. " EN_SSC ,Spread Spectrum Clockiing enable - . - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "DSI_PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" hexmask.long.word 0x00 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for SSC - The ModFreqDivider is split into Mantissa and 2Exponent(ModFreqDivider = ModFreqDividerMantissa * 2ModFreqDividerExponent). . - . Bits [29:23] define the Mantissa.. - . B.." hexmask.long.tbyte 0x00 0.--19. 1. " DELTAM ,DeltaM control for SSC. Split into integer and fractional parts.Bits [19:18] define the integer part.. - . Bits [17:0] define the fractional part.. - ." tree.end tree.end tree.open "DSI1_PHY_L4_PER" tree "DSI1_PHY_L4_PER" base ad:0x48044200 width 19. group.long 0x0++0x3 line.long 0x00 "DSI_PHY_REGISTER0,Configuration register for HS mode timings" hexmask.long.byte 0x00 24.--31. 1. " REG_THSPREPARE ,REG_THSPREPARE timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: 40 ns + 4 * UI ? 85 ns + 6 * UI. UI = Unit Interval, equal to the duration of any HS state on the clock lane.. - . - Def.." hexmask.long.byte 0x00 16.--23. 1. " REG_THSPRPR_THSZERO ,REG_THSPREPARE_THSZERO timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 145 ns + 10 * UI.. - . - Default value is programmed for 400 MHz. . - ." hexmask.long.byte 0x00 8.--15. 1. " REG_THSTRAIL ,REG_THSTRAIL timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 60 ns + 4 * UI.. - . - Default value is programmed for 400 MHz. . - ." textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_THSEXIT ,REG_THSEXIT timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 100 ns.. - . - Default value is programmed for 400 MHz. . - ." group.long 0x4++0x3 line.long 0x00 "DSI_PHY_REGISTER1,Configuration register for LP mode and HS mode timings" bitfld.long 0x00 29.--31. " REG_TTAGO ,TTA-GO timing in terms of number of TXCLKESC clocks. 0x0: 2 cycles - . - . - . - . - . - . - . Default value: 4 cycles. - ." "0,3_cycles,4_cycles,5_cycles,6_cycles,7_cycles,8_cycles,9_cycles" bitfld.long 0x00 27.--28. " REG_TTASURE ,TTA-SURE timing in terms of number of TXCLKESC clocks. - . - . - . - . Default value: 2 cycles. - ." "2_cycles,1_cycles,3_cycles,4_cycles" bitfld.long 0x00 24.--26. " REG_TTAGET ,TTA-GET timing in terms of number of TXCLKESC clocks. - . - . - . - . - . - . - . - . Default value: 5 cycles. - ." "3_cycles,4_cycles,5_cycles,6_cycles,7_cycles,8_cycles,9_cycles,10_cycles" textline " " bitfld.long 0x00 16.--20. " REG_TLPXBY2 ,(TLPX)/2 timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4. - Default value is programmed for 400 MHz. This is the internal timer value. The value seen on line will have variance due to rise/fall mismatc.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " REG_TCLKTRAIL ,REG_TCLKTRAIL timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 60 ns.. - . - Default value is programmed for 400 MHz . - ." hexmask.long.byte 0x00 0.--7. 1. " REG_TCLKZERO ,REG_TCLKZERO timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: (REG_TCLKPREPARE + REG_TCLKZERO) &gt; 300 ns.. - . Derived specification for REG_TCLKZERO (Min REG_TCLKPREPARE .." group.long 0x8++0x3 line.long 0x00 "DSI_PHY_REGISTER2,Sync pattern" hexmask.long.byte 0x00 24.--31. 1. " HSSYNCPATTERN ,Default : 184 (10111000). MSB (last received bit of sync pattern), LSB (first received bit of sync pattern)." bitfld.long 0x00 16. " OVRRDULPMTX ,Global enable of the weak pulldown on the DSI lanes, configured through the [15:11] REGULPMTX bit field: - . - ." "0,1" bitfld.long 0x00 11.--15. " REGULPMTX ,Configuration of the weak pulldowns on the DSI lanes.For each bit, the following settings apply:. - . - . - . Bit [15]: DSI lane 4 (applies only to DSI1; reserved for DSI2). - . Bit [14]: DSI lane 3 (applies only to DSI1; r.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_TCLKPREPARE ,TCLK-PREPARE timing parameter in multiples of DDR clock period.D-PHY specification: 38 ns ? 95 ns.. - . - Default value is programmed for 400 MHz. . - ." group.long 0xC++0x3 line.long 0x00 "DSI_PHY_REGISTER3,Transmitted pattern" hexmask.long.byte 0x00 24.--31. 1. " REG_TXTRIGGERESC3 ,Transmitted pattern when REG_TXTRIGGERESC3 is asserted (first bit transmitted to last bit transmitted). Default: 01100010" hexmask.long.byte 0x00 16.--23. 1. " REG_TXTRIGGERESC2 ,Default: 01011101" hexmask.long.byte 0x00 8.--15. 1. " REG_TXTRIGGERESC1 ,Default: 00100001" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_TXTRIGGERESC0 ,Default: 10100000" group.long 0x10++0x3 line.long 0x00 "DSI_PHY_REGISTER4,Received pattern" hexmask.long.byte 0x00 24.--31. 1. " REG_RXTRIGGERESC3 ,Received pattern for which REG_RXTRIGGERESC3 is asserted (first bit transmitted to last bit transmitted). Default: 01100010" hexmask.long.byte 0x00 16.--23. 1. " REG_RXTRIGGERESC2 ,Default: 01011101" hexmask.long.byte 0x00 8.--15. 1. " REG_RXTRIGGERESC1 ,Default: 00100001" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_RXTRIGGERESC0 ,Default: 10100000" rgroup.long 0x14++0x3 line.long 0x00 "DSI_PHY_REGISTER5,Reset done bits" bitfld.long 0x00 31. " RESETDONETXBYTECLK ,RESETDONETXBYTECLK 0x0: No reset 0x1: Reset done for the TXBYTECLK domain" "0,1" bitfld.long 0x00 30. " RESETDONESCPCLK ,RESETDONESCPCLK 0x0: No reset 0x1: Reset done for the SCP clock domain" "0,1" bitfld.long 0x00 29. " RESETDONEPWRCLK ,RESETDONEPWRCLK 0x0: No reset 0x1: Reset done for the PWR clock domain" "0,1" textline " " bitfld.long 0x00 28. " RESETDONETXCLKESC4 ,RESETDONETXCLKESC4 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 4" "0,1" bitfld.long 0x00 27. " RESETDONETXCLKESC3 ,RESETDONETXCLKESC3 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 3" "0,1" bitfld.long 0x00 26. " RESETDONETXCLKESC2 ,RESETDONETXCLKESC2 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 2" "0,1" textline " " bitfld.long 0x00 25. " RESETDONETXCLKESC1 ,RESETDONETXCLKESC1 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 1" "0,1" bitfld.long 0x00 24. " RESETDONETXCLKESC0 ,RESETDONETXCLKESC0 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 0" "0,1" tree.end tree "DSI2_PHY_L4_PER" base ad:0x48045200 width 19. group.long 0x0++0x3 line.long 0x00 "DSI_PHY_REGISTER0,Configuration register for HS mode timings" hexmask.long.byte 0x00 24.--31. 1. " REG_THSPREPARE ,REG_THSPREPARE timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: 40 ns + 4 * UI ? 85 ns + 6 * UI. UI = Unit Interval, equal to the duration of any HS state on the clock lane.. - . - Def.." hexmask.long.byte 0x00 16.--23. 1. " REG_THSPRPR_THSZERO ,REG_THSPREPARE_THSZERO timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 145 ns + 10 * UI.. - . - Default value is programmed for 400 MHz. . - ." hexmask.long.byte 0x00 8.--15. 1. " REG_THSTRAIL ,REG_THSTRAIL timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 60 ns + 4 * UI.. - . - Default value is programmed for 400 MHz. . - ." textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_THSEXIT ,REG_THSEXIT timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 100 ns.. - . - Default value is programmed for 400 MHz. . - ." group.long 0x4++0x3 line.long 0x00 "DSI_PHY_REGISTER1,Configuration register for LP mode and HS mode timings" bitfld.long 0x00 29.--31. " REG_TTAGO ,TTA-GO timing in terms of number of TXCLKESC clocks. 0x0: 2 cycles - . - . - . - . - . - . - . Default value: 4 cycles. - ." "0,3_cycles,4_cycles,5_cycles,6_cycles,7_cycles,8_cycles,9_cycles" bitfld.long 0x00 27.--28. " REG_TTASURE ,TTA-SURE timing in terms of number of TXCLKESC clocks. - . - . - . - . Default value: 2 cycles. - ." "2_cycles,1_cycles,3_cycles,4_cycles" bitfld.long 0x00 24.--26. " REG_TTAGET ,TTA-GET timing in terms of number of TXCLKESC clocks. - . - . - . - . - . - . - . - . Default value: 5 cycles. - ." "3_cycles,4_cycles,5_cycles,6_cycles,7_cycles,8_cycles,9_cycles,10_cycles" textline " " bitfld.long 0x00 16.--20. " REG_TLPXBY2 ,(TLPX)/2 timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4. - Default value is programmed for 400 MHz. This is the internal timer value. The value seen on line will have variance due to rise/fall mismatc.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " REG_TCLKTRAIL ,REG_TCLKTRAIL timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 60 ns.. - . - Default value is programmed for 400 MHz . - ." hexmask.long.byte 0x00 0.--7. 1. " REG_TCLKZERO ,REG_TCLKZERO timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: (REG_TCLKPREPARE + REG_TCLKZERO) &gt; 300 ns.. - . Derived specification for REG_TCLKZERO (Min REG_TCLKPREPARE .." group.long 0x8++0x3 line.long 0x00 "DSI_PHY_REGISTER2,Sync pattern" hexmask.long.byte 0x00 24.--31. 1. " HSSYNCPATTERN ,Default : 184 (10111000). MSB (last received bit of sync pattern), LSB (first received bit of sync pattern)." bitfld.long 0x00 16. " OVRRDULPMTX ,Global enable of the weak pulldown on the DSI lanes, configured through the [15:11] REGULPMTX bit field: - . - ." "0,1" bitfld.long 0x00 11.--15. " REGULPMTX ,Configuration of the weak pulldowns on the DSI lanes.For each bit, the following settings apply:. - . - . - . Bit [15]: DSI lane 4 (applies only to DSI1; reserved for DSI2). - . Bit [14]: DSI lane 3 (applies only to DSI1; r.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_TCLKPREPARE ,TCLK-PREPARE timing parameter in multiples of DDR clock period.D-PHY specification: 38 ns ? 95 ns.. - . - Default value is programmed for 400 MHz. . - ." group.long 0xC++0x3 line.long 0x00 "DSI_PHY_REGISTER3,Transmitted pattern" hexmask.long.byte 0x00 24.--31. 1. " REG_TXTRIGGERESC3 ,Transmitted pattern when REG_TXTRIGGERESC3 is asserted (first bit transmitted to last bit transmitted). Default: 01100010" hexmask.long.byte 0x00 16.--23. 1. " REG_TXTRIGGERESC2 ,Default: 01011101" hexmask.long.byte 0x00 8.--15. 1. " REG_TXTRIGGERESC1 ,Default: 00100001" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_TXTRIGGERESC0 ,Default: 10100000" group.long 0x10++0x3 line.long 0x00 "DSI_PHY_REGISTER4,Received pattern" hexmask.long.byte 0x00 24.--31. 1. " REG_RXTRIGGERESC3 ,Received pattern for which REG_RXTRIGGERESC3 is asserted (first bit transmitted to last bit transmitted). Default: 01100010" hexmask.long.byte 0x00 16.--23. 1. " REG_RXTRIGGERESC2 ,Default: 01011101" hexmask.long.byte 0x00 8.--15. 1. " REG_RXTRIGGERESC1 ,Default: 00100001" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_RXTRIGGERESC0 ,Default: 10100000" rgroup.long 0x14++0x3 line.long 0x00 "DSI_PHY_REGISTER5,Reset done bits" bitfld.long 0x00 31. " RESETDONETXBYTECLK ,RESETDONETXBYTECLK 0x0: No reset 0x1: Reset done for the TXBYTECLK domain" "0,1" bitfld.long 0x00 30. " RESETDONESCPCLK ,RESETDONESCPCLK 0x0: No reset 0x1: Reset done for the SCP clock domain" "0,1" bitfld.long 0x00 29. " RESETDONEPWRCLK ,RESETDONEPWRCLK 0x0: No reset 0x1: Reset done for the PWR clock domain" "0,1" textline " " bitfld.long 0x00 28. " RESETDONETXCLKESC4 ,RESETDONETXCLKESC4 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 4" "0,1" bitfld.long 0x00 27. " RESETDONETXCLKESC3 ,RESETDONETXCLKESC3 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 3" "0,1" bitfld.long 0x00 26. " RESETDONETXCLKESC2 ,RESETDONETXCLKESC2 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 2" "0,1" textline " " bitfld.long 0x00 25. " RESETDONETXCLKESC1 ,RESETDONETXCLKESC1 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 1" "0,1" bitfld.long 0x00 24. " RESETDONETXCLKESC0 ,RESETDONETXCLKESC0 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 0" "0,1" tree.end tree "DSI1_PHY_L3" base ad:0x58004200 width 19. group.long 0x0++0x3 line.long 0x00 "DSI_PHY_REGISTER0,Configuration register for HS mode timings" hexmask.long.byte 0x00 24.--31. 1. " REG_THSPREPARE ,REG_THSPREPARE timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: 40 ns + 4 * UI ? 85 ns + 6 * UI. UI = Unit Interval, equal to the duration of any HS state on the clock lane.. - . - Def.." hexmask.long.byte 0x00 16.--23. 1. " REG_THSPRPR_THSZERO ,REG_THSPREPARE_THSZERO timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 145 ns + 10 * UI.. - . - Default value is programmed for 400 MHz. . - ." hexmask.long.byte 0x00 8.--15. 1. " REG_THSTRAIL ,REG_THSTRAIL timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 60 ns + 4 * UI.. - . - Default value is programmed for 400 MHz. . - ." textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_THSEXIT ,REG_THSEXIT timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 100 ns.. - . - Default value is programmed for 400 MHz. . - ." group.long 0x4++0x3 line.long 0x00 "DSI_PHY_REGISTER1,Configuration register for LP mode and HS mode timings" bitfld.long 0x00 29.--31. " REG_TTAGO ,TTA-GO timing in terms of number of TXCLKESC clocks. 0x0: 2 cycles - . - . - . - . - . - . - . Default value: 4 cycles. - ." "0,3_cycles,4_cycles,5_cycles,6_cycles,7_cycles,8_cycles,9_cycles" bitfld.long 0x00 27.--28. " REG_TTASURE ,TTA-SURE timing in terms of number of TXCLKESC clocks. - . - . - . - . Default value: 2 cycles. - ." "2_cycles,1_cycles,3_cycles,4_cycles" bitfld.long 0x00 24.--26. " REG_TTAGET ,TTA-GET timing in terms of number of TXCLKESC clocks. - . - . - . - . - . - . - . - . Default value: 5 cycles. - ." "3_cycles,4_cycles,5_cycles,6_cycles,7_cycles,8_cycles,9_cycles,10_cycles" textline " " bitfld.long 0x00 16.--20. " REG_TLPXBY2 ,(TLPX)/2 timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4. - Default value is programmed for 400 MHz. This is the internal timer value. The value seen on line will have variance due to rise/fall mismatc.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " REG_TCLKTRAIL ,REG_TCLKTRAIL timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 60 ns.. - . - Default value is programmed for 400 MHz . - ." hexmask.long.byte 0x00 0.--7. 1. " REG_TCLKZERO ,REG_TCLKZERO timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: (REG_TCLKPREPARE + REG_TCLKZERO) &gt; 300 ns.. - . Derived specification for REG_TCLKZERO (Min REG_TCLKPREPARE .." group.long 0x8++0x3 line.long 0x00 "DSI_PHY_REGISTER2,Sync pattern" hexmask.long.byte 0x00 24.--31. 1. " HSSYNCPATTERN ,Default : 184 (10111000). MSB (last received bit of sync pattern), LSB (first received bit of sync pattern)." bitfld.long 0x00 16. " OVRRDULPMTX ,Global enable of the weak pulldown on the DSI lanes, configured through the [15:11] REGULPMTX bit field: - . - ." "0,1" bitfld.long 0x00 11.--15. " REGULPMTX ,Configuration of the weak pulldowns on the DSI lanes.For each bit, the following settings apply:. - . - . - . Bit [15]: DSI lane 4 (applies only to DSI1; reserved for DSI2). - . Bit [14]: DSI lane 3 (applies only to DSI1; r.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_TCLKPREPARE ,TCLK-PREPARE timing parameter in multiples of DDR clock period.D-PHY specification: 38 ns ? 95 ns.. - . - Default value is programmed for 400 MHz. . - ." group.long 0xC++0x3 line.long 0x00 "DSI_PHY_REGISTER3,Transmitted pattern" hexmask.long.byte 0x00 24.--31. 1. " REG_TXTRIGGERESC3 ,Transmitted pattern when REG_TXTRIGGERESC3 is asserted (first bit transmitted to last bit transmitted). Default: 01100010" hexmask.long.byte 0x00 16.--23. 1. " REG_TXTRIGGERESC2 ,Default: 01011101" hexmask.long.byte 0x00 8.--15. 1. " REG_TXTRIGGERESC1 ,Default: 00100001" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_TXTRIGGERESC0 ,Default: 10100000" group.long 0x10++0x3 line.long 0x00 "DSI_PHY_REGISTER4,Received pattern" hexmask.long.byte 0x00 24.--31. 1. " REG_RXTRIGGERESC3 ,Received pattern for which REG_RXTRIGGERESC3 is asserted (first bit transmitted to last bit transmitted). Default: 01100010" hexmask.long.byte 0x00 16.--23. 1. " REG_RXTRIGGERESC2 ,Default: 01011101" hexmask.long.byte 0x00 8.--15. 1. " REG_RXTRIGGERESC1 ,Default: 00100001" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_RXTRIGGERESC0 ,Default: 10100000" rgroup.long 0x14++0x3 line.long 0x00 "DSI_PHY_REGISTER5,Reset done bits" bitfld.long 0x00 31. " RESETDONETXBYTECLK ,RESETDONETXBYTECLK 0x0: No reset 0x1: Reset done for the TXBYTECLK domain" "0,1" bitfld.long 0x00 30. " RESETDONESCPCLK ,RESETDONESCPCLK 0x0: No reset 0x1: Reset done for the SCP clock domain" "0,1" bitfld.long 0x00 29. " RESETDONEPWRCLK ,RESETDONEPWRCLK 0x0: No reset 0x1: Reset done for the PWR clock domain" "0,1" textline " " bitfld.long 0x00 28. " RESETDONETXCLKESC4 ,RESETDONETXCLKESC4 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 4" "0,1" bitfld.long 0x00 27. " RESETDONETXCLKESC3 ,RESETDONETXCLKESC3 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 3" "0,1" bitfld.long 0x00 26. " RESETDONETXCLKESC2 ,RESETDONETXCLKESC2 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 2" "0,1" textline " " bitfld.long 0x00 25. " RESETDONETXCLKESC1 ,RESETDONETXCLKESC1 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 1" "0,1" bitfld.long 0x00 24. " RESETDONETXCLKESC0 ,RESETDONETXCLKESC0 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 0" "0,1" tree.end tree "DSI2_PHY_L3" base ad:0x58005200 width 19. group.long 0x0++0x3 line.long 0x00 "DSI_PHY_REGISTER0,Configuration register for HS mode timings" hexmask.long.byte 0x00 24.--31. 1. " REG_THSPREPARE ,REG_THSPREPARE timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: 40 ns + 4 * UI ? 85 ns + 6 * UI. UI = Unit Interval, equal to the duration of any HS state on the clock lane.. - . - Def.." hexmask.long.byte 0x00 16.--23. 1. " REG_THSPRPR_THSZERO ,REG_THSPREPARE_THSZERO timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 145 ns + 10 * UI.. - . - Default value is programmed for 400 MHz. . - ." hexmask.long.byte 0x00 8.--15. 1. " REG_THSTRAIL ,REG_THSTRAIL timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 60 ns + 4 * UI.. - . - Default value is programmed for 400 MHz. . - ." textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_THSEXIT ,REG_THSEXIT timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 100 ns.. - . - Default value is programmed for 400 MHz. . - ." group.long 0x4++0x3 line.long 0x00 "DSI_PHY_REGISTER1,Configuration register for LP mode and HS mode timings" bitfld.long 0x00 29.--31. " REG_TTAGO ,TTA-GO timing in terms of number of TXCLKESC clocks. 0x0: 2 cycles - . - . - . - . - . - . - . Default value: 4 cycles. - ." "0,3_cycles,4_cycles,5_cycles,6_cycles,7_cycles,8_cycles,9_cycles" bitfld.long 0x00 27.--28. " REG_TTASURE ,TTA-SURE timing in terms of number of TXCLKESC clocks. - . - . - . - . Default value: 2 cycles. - ." "2_cycles,1_cycles,3_cycles,4_cycles" bitfld.long 0x00 24.--26. " REG_TTAGET ,TTA-GET timing in terms of number of TXCLKESC clocks. - . - . - . - . - . - . - . - . Default value: 5 cycles. - ." "3_cycles,4_cycles,5_cycles,6_cycles,7_cycles,8_cycles,9_cycles,10_cycles" textline " " bitfld.long 0x00 16.--20. " REG_TLPXBY2 ,(TLPX)/2 timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4. - Default value is programmed for 400 MHz. This is the internal timer value. The value seen on line will have variance due to rise/fall mismatc.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " REG_TCLKTRAIL ,REG_TCLKTRAIL timing parameter in multiples of DDR clock frequency. DDR clock = CLKIN4DDR/4.D-PHY specification: &gt; 60 ns.. - . - Default value is programmed for 400 MHz . - ." hexmask.long.byte 0x00 0.--7. 1. " REG_TCLKZERO ,REG_TCLKZERO timing parameter in multiples of DDR clock period. DDR clock = CLKIN4DDR/4.D-PHY specification: (REG_TCLKPREPARE + REG_TCLKZERO) &gt; 300 ns.. - . Derived specification for REG_TCLKZERO (Min REG_TCLKPREPARE .." group.long 0x8++0x3 line.long 0x00 "DSI_PHY_REGISTER2,Sync pattern" hexmask.long.byte 0x00 24.--31. 1. " HSSYNCPATTERN ,Default : 184 (10111000). MSB (last received bit of sync pattern), LSB (first received bit of sync pattern)." bitfld.long 0x00 16. " OVRRDULPMTX ,Global enable of the weak pulldown on the DSI lanes, configured through the [15:11] REGULPMTX bit field: - . - ." "0,1" bitfld.long 0x00 11.--15. " REGULPMTX ,Configuration of the weak pulldowns on the DSI lanes.For each bit, the following settings apply:. - . - . - . Bit [15]: DSI lane 4 (applies only to DSI1; reserved for DSI2). - . Bit [14]: DSI lane 3 (applies only to DSI1; r.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_TCLKPREPARE ,TCLK-PREPARE timing parameter in multiples of DDR clock period.D-PHY specification: 38 ns ? 95 ns.. - . - Default value is programmed for 400 MHz. . - ." group.long 0xC++0x3 line.long 0x00 "DSI_PHY_REGISTER3,Transmitted pattern" hexmask.long.byte 0x00 24.--31. 1. " REG_TXTRIGGERESC3 ,Transmitted pattern when REG_TXTRIGGERESC3 is asserted (first bit transmitted to last bit transmitted). Default: 01100010" hexmask.long.byte 0x00 16.--23. 1. " REG_TXTRIGGERESC2 ,Default: 01011101" hexmask.long.byte 0x00 8.--15. 1. " REG_TXTRIGGERESC1 ,Default: 00100001" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_TXTRIGGERESC0 ,Default: 10100000" group.long 0x10++0x3 line.long 0x00 "DSI_PHY_REGISTER4,Received pattern" hexmask.long.byte 0x00 24.--31. 1. " REG_RXTRIGGERESC3 ,Received pattern for which REG_RXTRIGGERESC3 is asserted (first bit transmitted to last bit transmitted). Default: 01100010" hexmask.long.byte 0x00 16.--23. 1. " REG_RXTRIGGERESC2 ,Default: 01011101" hexmask.long.byte 0x00 8.--15. 1. " REG_RXTRIGGERESC1 ,Default: 00100001" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_RXTRIGGERESC0 ,Default: 10100000" rgroup.long 0x14++0x3 line.long 0x00 "DSI_PHY_REGISTER5,Reset done bits" bitfld.long 0x00 31. " RESETDONETXBYTECLK ,RESETDONETXBYTECLK 0x0: No reset 0x1: Reset done for the TXBYTECLK domain" "0,1" bitfld.long 0x00 30. " RESETDONESCPCLK ,RESETDONESCPCLK 0x0: No reset 0x1: Reset done for the SCP clock domain" "0,1" bitfld.long 0x00 29. " RESETDONEPWRCLK ,RESETDONEPWRCLK 0x0: No reset 0x1: Reset done for the PWR clock domain" "0,1" textline " " bitfld.long 0x00 28. " RESETDONETXCLKESC4 ,RESETDONETXCLKESC4 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 4" "0,1" bitfld.long 0x00 27. " RESETDONETXCLKESC3 ,RESETDONETXCLKESC3 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 3" "0,1" bitfld.long 0x00 26. " RESETDONETXCLKESC2 ,RESETDONETXCLKESC2 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 2" "0,1" textline " " bitfld.long 0x00 25. " RESETDONETXCLKESC1 ,RESETDONETXCLKESC1 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 1" "0,1" bitfld.long 0x00 24. " RESETDONETXCLKESC0 ,RESETDONETXCLKESC0 0x0: No reset 0x1: Reset done for the TXCLKESC domain for lane 0" "0,1" tree.end tree.end tree.open "DSI1_PROTOCOL_ENGINE_L4_PER" tree "DSI1_PROTOCOL_ENGINE_L4_PER" base ad:0x48044000 tree "Channel_0" width 32. group.long 0xA8++0x3 line.long 0x00 "DSI_TE_HSYNC_NUMBER_j_0,The register configures the number of HSYNC to synchronize the beginning of the transfer on DSI link based on the number of HSYNC pulse received on the TE line. The input TE signal is asynchronous and needs to be resynchronizred.." hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number Line number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer. Any HSYNC before VSYNC is ignored." group.long 0xA0++0x3 line.long 0x00 "DSI_TE_HSYNC_WIDTH_j_0,The register configures the TE HSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width Minimum HSYNC pulse width. Number of DSI_CLK clock cycles times 256 to determine when HSYNC pulse occurs. The value 0 is invalid." group.long 0xA4++0x3 line.long 0x00 "DSI_TE_VSYNC_WIDTH_j_0,The register configures the TE VSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width Minimum VSYNC pulse width. Number of DSI_CLK cycles times 256 to determine when VSYNC pulse occurs. The value 0 is invalid. The value shall be greater than MIN_HSYNC_PULSE_WIDTH when DSI_TE_HSY.." group.long 0x100++0x3 line.long 0x00 "DSI_VC_CTRL_i_0,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x11C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_0,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x118++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_0,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x108++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_0,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x10C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_0,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x110++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_0,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x104++0x3 line.long 0x00 "DSI_VC_TE_i_0,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_1" width 32. group.long 0xB4++0x3 line.long 0x00 "DSI_TE_HSYNC_NUMBER_j_1,The register configures the number of HSYNC to synchronize the beginning of the transfer on DSI link based on the number of HSYNC pulse received on the TE line. The input TE signal is asynchronous and needs to be resynchronizred.." hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number Line number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer. Any HSYNC before VSYNC is ignored." group.long 0xAC++0x3 line.long 0x00 "DSI_TE_HSYNC_WIDTH_j_1,The register configures the TE HSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width Minimum HSYNC pulse width. Number of DSI_CLK clock cycles times 256 to determine when HSYNC pulse occurs. The value 0 is invalid." group.long 0xB0++0x3 line.long 0x00 "DSI_TE_VSYNC_WIDTH_j_1,The register configures the TE VSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width Minimum VSYNC pulse width. Number of DSI_CLK cycles times 256 to determine when VSYNC pulse occurs. The value 0 is invalid. The value shall be greater than MIN_HSYNC_PULSE_WIDTH when DSI_TE_HSY.." group.long 0x120++0x3 line.long 0x00 "DSI_VC_CTRL_i_1,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x13C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_1,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x138++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_1,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x128++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_1,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x12C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_1,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x130++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_1,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x124++0x3 line.long 0x00 "DSI_VC_TE_i_1,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_2" width 32. group.long 0x140++0x3 line.long 0x00 "DSI_VC_CTRL_i_2,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x15C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_2,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x158++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_2,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x148++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_2,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x14C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_2,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x150++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_2,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x144++0x3 line.long 0x00 "DSI_VC_TE_i_2,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_3" width 32. group.long 0x160++0x3 line.long 0x00 "DSI_VC_CTRL_i_3,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x17C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_3,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x178++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_3,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x168++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_3,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x16C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_3,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x170++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_3,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x164++0x3 line.long 0x00 "DSI_VC_TE_i_3,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end textline "" width 26. rgroup.long 0x0++0x3 line.long 0x00 "DSI_REVISION,IP Revision" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "DSI_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period - . - . - . - ." "OCPFuncOff,FuncOff,OCPOff,OCPFuncOn" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, Idle req/ack control - . - . - . - ." "fIdle,nIdle,sIdle,Res" bitfld.long 0x00 2. " ENWAKEUP ,Wake-up mode enable bit - . - ." "WakeUpDis,WakeUpEnb" textline " " bitfld.long 0x00 1. " SOFT_RESET ,Software reset. Set the bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads return 0. - . - ." "Normal,Reset" bitfld.long 0x00 0. " AUTO_IDLE ,Internal interface gating strategy - . - ." "Free,Gated" rgroup.long 0x14++0x3 line.long 0x00 "DSI_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module, excluding the interrupt status register." bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring - . - ." "ResetOngoing,ResetCompleted" group.long 0x18++0x3 line.long 0x00 "DSI_IRQSTATUS,INTERRUPT STATUS REGISTER - All virtual channels + Complex I/O + PLL This register associates one bit for each virtual channel in order to determine which virtual channel has generated the interrupt. The virtual channel shall be enabled f.." bitfld.long 0x00 22. " TE1_LINE_IRQ ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE1 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . - ." "False,True" bitfld.long 0x00 21. " TE0_LINE_IRQ ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE0 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - ..." "False,True" bitfld.long 0x00 20. " TA_TO_IRQ ,Turn-around Time out. - . - ." "False,True" textline " " bitfld.long 0x00 18. " SYNC_LOST_IRQ ,Synchronization with Video port is lost (Video mode only) - . - ." "False,True" bitfld.long 0x00 17. " ACK_TRIGGER_IRQ ,Acknowledge Trigger - . - ." "False,True" bitfld.long 0x00 16. " TE_TRIGGER_IRQ ,Tearing Effect Trigger - . - ." "False,True" textline " " bitfld.long 0x00 15. " LP_RX_TO_IRQ ,Interrupt for Low Power Rx Time out - . - ." "False,True" bitfld.long 0x00 14. " HS_TX_TO_IRQ ,Interrupt for High Speed Tx Time out. - . - ." "False,True" bitfld.long 0x00 10. " COMPLEXIO_ERR_IRQ ,Error signaling from Complex I/O: status of the complex I/O errors received from the complex I/O (events are defined inDSI_COMPLEXIO_IRQSTATUS). - . - ." "False,True" textline " " bitfld.long 0x00 9. " PLL_RECAL_IRQ ,PLL recal event (assertion of DSIRecal signal from the DSI PLL Control module) - . - ." "False,True" bitfld.long 0x00 8. " PLL_UNLOCK_IRQ ,PLL un-clock event (de-assertion of DSILock signal from the DSI PLL Control module) - . - ." "False,True" bitfld.long 0x00 7. " PLL_LOCK_IRQ ,PLL clock event (assertion of DSILock signal from the DSI PLL Control module) - . - ." "False,True" textline " " bitfld.long 0x00 5. " RESYNCHRONIZATION_IRQ ,Video mode resynchronization indicates to the software users that the video port works but the configuration of the timings for the display controller (DISPC) and for DSI Protocol engine may need to be modified to avoid the .." "False,True" bitfld.long 0x00 4. " WAKEUP_IRQ ,Wakeup - . - ." "False,True" bitfld.long 0x00 3. " VIRTUAL_CHANNEL3_IRQ ,Virtual channel 3 - . - ." "False,True" textline " " bitfld.long 0x00 2. " VIRTUAL_CHANNEL2_IRQ ,Virtual channel 2 - . - ." "False,True" bitfld.long 0x00 1. " VIRTUAL_CHANNEL1_IRQ ,Virtual channel 1 - . - ." "False,True" bitfld.long 0x00 0. " VIRTUAL_CHANNEL0_IRQ ,Virtual channel 0 - . - ." "False,True" group.long 0x1C++0x3 line.long 0x00 "DSI_IRQENABLE,INTERRUPT ENABLE REGISTER - This register associates one bit for each virtual channel in order to enable/disable each virtual channel individually." bitfld.long 0x00 22. " TE1_LINE_IRQ_EN ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE1 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . - ." "Disable,Enable" bitfld.long 0x00 21. " TE0_LINE_IRQ_EN ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE0 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . -.." "Disable,Enable" bitfld.long 0x00 20. " TA_TO_IRQ_EN ,Turn-around Time out. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 18. " SYNC_LOST_IRQ_EN ,Synchronization with Video port is lost (Video mode only) - . - ." "Disable,Enable" bitfld.long 0x00 17. " ACK_TRIGGER_IRQ_EN ,Acknowledge trigger - . - ." "Disable,Enable" bitfld.long 0x00 16. " TE_TRIGGER_IRQ_EN ,Tearing Effect trigger - . - ." "Disable,Enable" textline " " bitfld.long 0x00 15. " LP_RX_TO_IRQ_EN ,Interrupt for Low Power Rx Time out. - . - ." "Disable,Enable" bitfld.long 0x00 14. " HS_TX_TO_IRQ_EN ,Interrupt for High Speed Tx Time out. - . - ." "Disable,Enable" bitfld.long 0x00 9. " PLL_RECAL_IRQ_EN ,PLL recal event (assertion of DSIRecal signal from the DSI PLL Control module) - . - ." "Disable,Enable" textline " " bitfld.long 0x00 8. " PLL_UNLOCK_IRQ_EN ,PLL un-clock event (de-assertion of DSILock signal from the DSI PLL Control module) - . - ." "Disable,Enable" bitfld.long 0x00 7. " PLL_LOCK_IRQ_EN ,PLL clock event (assertion of DSILock signal from the DSI PLL Control module) - . - ." "Disable,Enable" bitfld.long 0x00 5. " RESYNCHRONIZATION_IRQ_EN ,Video mode resynchronization - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " WAKEUP_IRQ_EN ,Wakeup - . - ." "Disable,Enable" group.long 0x40++0x3 line.long 0x00 "DSI_CTRL,GLOBAL CONTROL REGISTER This register controls the DSI Protocol Engine module. This register shall not be modified dynamically (except IF_EN bit fields)." bitfld.long 0x00 24. " DISPC_UPDATE_SYNC ,Determines if the Dispc_Update_Sync signal from the display controller is used. - . - ." "Disable,Enable" bitfld.long 0x00 23. " HSA_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" bitfld.long 0x00 22. " HBP_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" textline " " bitfld.long 0x00 21. " HFP_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" bitfld.long 0x00 20. " BLANKING_MODE ,Blanking mode - . - ." "LPS,HS" bitfld.long 0x00 19. " EOT_ENABLE ,Enable EOT packets at the end of HS transmission. - . - ." "EOT_OFF,EOT_ON" textline " " bitfld.long 0x00 18. " VP_HSYNC_END ,HSYNC end pulse. - . - ." "Disable,Enable" bitfld.long 0x00 17. " VP_HSYNC_START ,HSYNC start pulse. - . - ." "Disable,Enable" bitfld.long 0x00 16. " VP_VSYNC_END ,VSYNC end pulse. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 15. " VP_VSYNC_START ,VSYNC start pulse. - . - ." "Disable,Enable" bitfld.long 0x00 14. " TRIGGER_RESET_MODE ,Selection of the trigger reset mode - . - ." "Synchronized,Immediate" bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port. The valid values are from 0 toDSI_GNQ[17:16] VP1_NB_LINE_BUFFER. - . - . - ." "f0,f1,f2,3" textline " " bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity - . - ." "Low,High" textline " " bitfld.long 0x00 8. " VP_CLK_POL ,VP pixel clock polarity - . - ." "Falling,Rising" bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus - . - . - ." "f16,f18,f24,3" bitfld.long 0x00 5. " TRIGGER_RESET ,Send the reset trigger to the peripheral. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP_CLK and VP_PCLK. The clock VP_PCLK is generated from VP_CLK. It is divided down. The information is only used when the video port is used to provide data in command mode. In the.." "RATIO2,RATIO3ANDHIGHER" bitfld.long 0x00 3. " TX_FIFO_ARBITRATION ,Defines the arbitration scheme for granting the virtual channel pending ready requests in the TX FIFO - . - ." "RoundRobin,Sequential" bitfld.long 0x00 2. " ECC_RX_EN ,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " CS_RX_EN ,Enables the checksum check for the received payload (long packet only for all virtual channel ids). - . - ." "Disable,Enable" bitfld.long 0x00 0. " IF_EN ,Enables the module. When the module is disabled the signals from the complex I/O are gated (no updates of the interrupt status register). It is not possible to change the bit fields in the register DSI_CTRL .." "Disable,Enable" rgroup.long 0x44++0x3 line.long 0x00 "DSI_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design." bitfld.long 0x00 24. " NB_VIDEO_PORTS ,Number of video ports - . - ." "Single_VP,Dual_VP" bitfld.long 0x00 22.--23. " VP2_NB_LINE_BUFFER ,Determines the number of video buffer lines associated to video port 2. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 18.--20. " VP2_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 2 . - . - . - . - . - . - ." "0,f1,f2,f3,f4,f5,f6,7" textline " " bitfld.long 0x00 16.--17. " VP1_NB_LINE_BUFFER ,Determines the number of video buffer lines associated to video port 1. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 12.--14. " VP1_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 1 . - . - . - . - . - . - ." "0,f1,f2,f3,f4,f5,f6,7" bitfld.long 0x00 9.--11. " NB_DATA_LANES ,Determines the number of data lanes supported by the DSI protocol engine . - . - . - . - ." "0,f1,f2,f3,f4,5,6,7" textline " " bitfld.long 0x00 6.--8. " NB_DMA_REQUEST ,Determines the number of DMA_REQ signals. - . - . - . - . - ." "f0,f1,f2,f3,f4,5,6,7" bitfld.long 0x00 3.--5. " RX_FIFODEPTH ,Determines the data RX FIFO depth (32-bit words) on the slave port. - . - . - . - ." "0,1,2,3,f32,f64,f128,f256" bitfld.long 0x00 0.--2. " TX_FIFODEPTH ,Determines the data TX FIFO depth (33-bit words) on the slave port. - . - . - . - ." "0,1,2,3,f32,f64,f128,f256" group.long 0x48++0x3 line.long 0x00 "DSI_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in add.." bitfld.long 0x00 31. " SHADOWING ,Shadowing configuration. - . - ." "Disable,Enable" bitfld.long 0x00 30. " GOBIT ,Allows the synchronized update of the shadow registers when the signal DISPCUpdateSync is active. - . - ." "Reset,Set" bitfld.long 0x00 29. " RESET_DONE ,Internal reset monitoring of the power domain using the TXBYTECLKHS clock from the complex I/O - . - ." "ResetOngoing,ResetCompleted" textline " " bitfld.long 0x00 27.--28. " PWR_CMD ,Command for power control of the complex I/O - . - . - ." "STATE_OFF,STATE_ON,STATE_ULP,3" bitfld.long 0x00 25.--26. " PWR_STATUS ,Status of the power control of the complex I/O - . - . - ." "STATE_OFF,STATE_ON,STATE_ULP,3" bitfld.long 0x00 19. " DATA4_POL ,+/- differential pin order of DATA lane 4. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "PlusMinus,MinusPlus" textline " " bitfld.long 0x00 16.--18. " DATA4_POSITION ,Position and order of the DATA lane 4. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" bitfld.long 0x00 15. " DATA3_POL ,+/- differential pin order of DATA lane 3. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 12.--14. " DATA3_POSITION ,Position and order of the DATA lane 3. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" textline " " bitfld.long 0x00 11. " DATA2_POL ,+/- differential pin order of DATA lane 2. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 8.--10. " DATA2_POSITION ,Position and order of the DATA lane 2. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" bitfld.long 0x00 7. " DATA1_POL ,+/- pin differential pin order of DATA lane 1 - . - ." "PlusMinus,MinusPlus" textline " " bitfld.long 0x00 4.--6. " DATA1_POSITION ,Position and order of the DATA lane 1. The data lane 1 is always present. - . - . - . - . - . - ." "0,Position_1,Position_2,Position_3,Position_4,Position_5,6,7" bitfld.long 0x00 3. " CLOCK_POL ,+/- differential pin order of CLOCK lane. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 0.--2. " CLOCK_POSITION ,Position and order of the CLOCK lane. 0, 5, 6 and 7 are reserved. The clock lane is always present but cannot be at the position 5 even if the COMPLEX I/O consists of 5 lanes. - . - . - . - . - . - . - . - ." "0,Position_1,Position_2,Position_3,Position_4,5,6,7" group.long 0x4C++0x3 line.long 0x00 "DSI_COMPLEXIO_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex I/O" bitfld.long 0x00 31. " ULPSACTIVENOT_ALL1_IRQ ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high. - . - ." "False,True" bitfld.long 0x00 30. " ULPSACTIVENOT_ALL0_IRQ ,All signals ULPSActiveNOT are 0 - . - ." "False,True" bitfld.long 0x00 29. " ERRCONTENTIONLP1_5_IRQ ,Contention LP1 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 28. " ERRCONTENTIONLP0_5_IRQ ,Contention LP0 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 27. " ERRCONTENTIONLP1_4_IRQ ,Contention LP1 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 26. " ERRCONTENTIONLP0_4_IRQ ,Contention LP0 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 25. " ERRCONTENTIONLP1_3_IRQ ,Contention LP1 error for lane 3 - . - ." "False,True" bitfld.long 0x00 24. " ERRCONTENTIONLP0_3_IRQ ,Contention LP0 error for lane 3 - . - ." "False,True" bitfld.long 0x00 23. " ERRCONTENTIONLP1_2_IRQ ,Contention LP1 error for lane 2 - . - ." "False,True" textline " " bitfld.long 0x00 22. " ERRCONTENTIONLP0_2_IRQ ,Contention LP0 error for lane 2 - . - ." "False,True" bitfld.long 0x00 21. " ERRCONTENTIONLP1_1_IRQ ,Contention LP1 error for lane 1 - . - ." "False,True" bitfld.long 0x00 20. " ERRCONTENTIONLP0_1_IRQ ,Contention LP0 error for lane 1 - . - ." "False,True" textline " " bitfld.long 0x00 19. " STATEULPS5_IRQ ,lane 5 in ULTRALOW-POWER State Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 18. " STATEULPS4_IRQ ,lane 4 in ultralow-power mode Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 17. " STATEULPS3_IRQ ,lane 3 in ULTRALOW-POWER state - . - ." "False,True" textline " " bitfld.long 0x00 16. " STATEULPS2_IRQ ,lane 2 in ULTRALOW-POWER state - . - ." "False,True" bitfld.long 0x00 15. " STATEULPS1_IRQ ,lane 1 in ULTRALOW-POWER state - . - ." "False,True" bitfld.long 0x00 14. " ERRCONTROL5_IRQ ,Control error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 13. " ERRCONTROL4_IRQ ,Control error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 12. " ERRCONTROL3_IRQ ,Control error for lane 3 - . - ." "False,True" bitfld.long 0x00 11. " ERRCONTROL2_IRQ ,Control error for lane 2 - . - ." "False,True" textline " " bitfld.long 0x00 10. " ERRCONTROL1_IRQ ,Control error for lane 1 - . - ." "False,True" bitfld.long 0x00 9. " ERRESC5_IRQ ,Escape entry error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 8. " ERRESC4_IRQ ,Escape entry error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 7. " ERRESC3_IRQ ,Escape entry error for lane 3 - . - ." "False,True" bitfld.long 0x00 6. " ERRESC2_IRQ ,Escape entry error for lane 2 - . - ." "False,True" bitfld.long 0x00 5. " ERRESC1_IRQ ,Escape entry error for lane 1 - . - ." "False,True" textline " " bitfld.long 0x00 4. " ERRSYNCESC5_IRQ ,Low power Data transmission synchronization error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 3. " ERRSYNCESC4_IRQ ,Low power Data transmission synchronization error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 2. " ERRSYNCESC3_IRQ ,Low power Data transmission synchronization error for lane 3 - . - ." "False,True" textline " " bitfld.long 0x00 1. " ERRSYNCESC2_IRQ ,Low power Data transmission synchronization error for lane 2 - . - ." "False,True" bitfld.long 0x00 0. " ERRSYNCESC1_IRQ ,Low power Data transmission synchronization error for lane 1 - . - ." "False,True" group.long 0x50++0x3 line.long 0x00 "DSI_COMPLEXIO_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex I/O" bitfld.long 0x00 31. " ULPSACTIVENOT_ALL1_IRQ_EN ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high. - . - ." "Disable,Enable" bitfld.long 0x00 30. " ULPSACTIVENOT_ALL0_IRQ_EN ,All signals ULPSActiveNOT are 0 - . - ." "Disable,Enable" bitfld.long 0x00 29. " ERRCONTENTIONLP1_5_IRQ_EN ,Contention LP1 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " ERRCONTENTIONLP0_5_IRQ_EN ,Contention LP0 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 27. " ERRCONTENTIONLP1_4_IRQ_EN ,Contention LP1 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 26. " ERRCONTENTIONLP0_4_IRQ_EN ,Contention LP0 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 25. " ERRCONTENTIONLP1_3_IRQ_EN ,Contention LP1 error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 24. " ERRCONTENTIONLP0_3_IRQ_EN ,Contention LP0 error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 23. " ERRCONTENTIONLP1_2_IRQ_EN ,Contention LP1 error for lane 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 22. " ERRCONTENTIONLP0_2_IRQ_EN ,Contention LP0 error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 21. " ERRCONTENTIONLP1_1_IRQ_EN ,Contention LP1 error for lane 1 - . - ." "Disable,Enable" bitfld.long 0x00 20. " ERRCONTENTIONLP0_1_IRQ_EN ,Contention LP0 error for lane 1 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 19. " STATEULPS5_IRQ_EN ,lane 5 in ULTRALOW-POWER state Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 18. " STATEULPS4_IRQ_EN ,lane 4 in ULTRALOW-POWER state Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 17. " STATEULPS3_IRQ_EN ,lane 3 in ULTRALOW-POWER state - . - ." "Disable,Enable" textline " " bitfld.long 0x00 16. " STATEULPS2_IRQ_EN ,lane 2 in ULTRALOW-POWER state - . - ." "Disable,Enable" bitfld.long 0x00 15. " STATEULPS1_IRQ_EN ,lane 1 in ULTRALOW-POWER state - . - ." "Disable,Enable" bitfld.long 0x00 14. " ERRCONTROL5_IRQ_EN ,Control error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " ERRCONTROL4_IRQ_EN ,Control error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 12. " ERRCONTROL3_IRQ_EN ,Control error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 11. " ERRCONTROL2_IRQ_EN ,Control error for lane 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 10. " ERRCONTROL1_IRQ_EN ,Control error for lane 1 - . - ." "Disable,Enable" bitfld.long 0x00 9. " ERRESC5_IRQ_EN ,Escape entry error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 8. " ERRESC4_IRQ_EN ,Escape entry error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " ERRESC3_IRQ_EN ,Escape entry error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 6. " ERRESC2_IRQ_EN ,Escape entry error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 5. " ERRESC1_IRQ_EN ,Escape entry error for lane 1 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " ERRSYNCSESC5_IRQ_EN ,Low power Data transmission synchronization error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 3. " ERRSYNCSESC4_IRQ_EN ,Low power Data transmission synchronization error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 2. " ERRSYNCSESC3_IRQ_EN ,Low power Data transmission synchronization error for lane 3 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " ERRSYNCSESC2_IRQ_EN ,Low power Data transmission synchronization error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 0. " ERRSYNCSESC1_IRQ_EN ,Low power Data transmission synchronization error for lane 1 - . - ." "Disable,Enable" group.long 0x54++0x3 line.long 0x00 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION. The register can be modified only when IF_EN is reset." bitfld.long 0x00 30.--31. " PLL_PWR_CMD ,Command for power control of the DSI PLL Control module - . - . - . - ." "STATE_OFF,STATE_ON_HSCLK,STATE_ON_ALL,STATE_ON_DIV" bitfld.long 0x00 28.--29. " PLL_PWR_STATUS ,Status of the power control of the DSI PLL Control module - . - . - . - ." "STATE_OFF,STATE_ON_HSCLK,STATE_ON_ALL,STATE_ON_DIV" bitfld.long 0x00 21. " LP_RX_SYNCHRO_ENABLE ,Defines if the functional is higher or lower than 30 MHz. The information is used to define synchronization to be used for RxValidEsc. - . - ." "LowSpeed,HighSpeed" textline " " bitfld.long 0x00 20. " LP_CLK_ENABLE ,Controls the gating of the TXCLKESC clock. - . - ." "Disable,Enable" bitfld.long 0x00 19. " HS_MANUAL_STOP_CTRL ,In case HS_AUTO_STOP_ENABLE=0, the bit field allows manual control of the assertion/de-assertion of the signal DSIStopClk by the user. - . - ." "Deassertion,Assertion" bitfld.long 0x00 18. " HS_AUTO_STOP_ENABLE ,Enables the automatic assertion/de-assertion of DSIStopClk signal. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 16.--17. " LP_CLK_NULL_PACKET_SIZE ,Indicates the size of LP NULL Packets to be sent automatically when after the last LP packet transfer. It is used by the receiver to drain its internal pipeline. The valid values are from 0 to 3 bytes for the payload size." "0,1,2,3" bitfld.long 0x00 15. " LP_CLK_NULL_PACKET_ENABLE ,Enables the generation of NULL packet in low speed. - . - ." "Disable,Enable" bitfld.long 0x00 14. " CIO_CLK_ICG ,Gates SCPClk clock provided to DSI_PHY and PLL-CTRL module. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " DDR_CLK_ALWAYS_ON ,Defines if the DDR clock is also sent when there is no HS packets sent to the peripheral (low-power mode). So TXRequest for the clock lane is not de-asserted. - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " LP_CLK_DIVISOR ,Defines the ratio to be used for the generation of the low-power mode clock from DSI functional clock. The supported values are from 1 to 8191(the value 0 is invalid). The output frequency shall be in the ra.." group.long 0x58++0x3 line.long 0x00 "DSI_TIMING1,TIMING1 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be modified while [0] IF_EN is set to '1'. It is used to indicate the number of DSI1_CLK and DSI2_CLK functional clocks cycles for the timers F.." bitfld.long 0x00 31. " TA_TO ,Enables the turn-around timer - . - ." "Deassertion,Assertion" bitfld.long 0x00 30. " TA_TO_X16 ,Multiplication factor for the number of DSI_CLK functional clocks cycles defined in TA_TO_COUNTER bit field - . - ." "Disable,Enable" bitfld.long 0x00 29. " TA_TO_X8 ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in TA_TO_COUNTER bit field - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 16.--28. 1. " TA_TO_COUNTER ,Turn around counter. It indicates the number of DSI_CLK function clock to wait for the change of the Direction PPI signal according to the TurnRequest signal The value is from 0 to 8191." bitfld.long 0x00 15. " FORCE_TX_STOP_MODE_IO ,Control of ForceTxStopMode signal - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " STOP_STATE_X16_IO ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit field - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " STOP_STATE_X4_IO ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit field - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " STOP_STATE_COUNTER_IO ,Stop state counter. It indicates the number of DSI_CLK function clock to assert ForceTXStopMode signal. The value is from 0 to 8191." group.long 0x5C++0x3 line.long 0x00 "DSI_TIMING2,TIMING2 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be modified while [0] IF_EN is set to '1'. It is used to indicate the number of DSI_FCLK clock cycles for the timer LP_RX_TIMER and the number .." bitfld.long 0x00 31. " HS_TX_TO ,Enables the HS TX timer. - . - ." "Deassertion,Assertion" bitfld.long 0x00 30. " HS_TX_TO_X64 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit field. BYTE_CLK is a high speed transmit byte clock signal generated by the DSI_PHY. - . - ." "Disable,Enable" bitfld.long 0x00 29. " HS_TX_TO_X16 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 16.--28. 1. " HS_TX_TO_COUNTER ,HS_TX_TIMER counter. It indicates the number of BYTE_CLK function clock for the HS TX timer. The value is from 0 to 8191." bitfld.long 0x00 15. " LP_RX_TO ,Enables the LP RX timer. - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " LP_RX_TO_X16 ,Multiplication factor for the number of DSI_FCLK clock cycles defined in LP_RX_COUNTER bit field - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " LP_RX_TO_X4 ,Multiplication factor for the number of DSI_FCLK clock cycles defined in LP_RX_COUNTER bit - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " LP_RX_TO_COUNTER ,LP_RX_TIMER counter. It indicates the number of DSI_FCLK clock for the LP RX timer. The value is from 0 to 8191." group.long 0x60++0x3 line.long 0x00 "DSI_VM_TIMING1,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 24.--31. 1. " HSA ,Defines the horizontal Sync active period used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 255." hexmask.long.word 0x00 12.--23. 1. " HFP ,Defines the horizontal front porch used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 4095" hexmask.long.word 0x00 0.--11. 1. " HBP ,Defines the horizontal back porch used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 4095" group.long 0x64++0x3 line.long 0x00 "DSI_VM_TIMING2,VIDEO MODE TIMING REGISTER This register defines the video mode timing." bitfld.long 0x00 24.--27. " WINDOW_SYNC ,Number of BYTE clock cycles for the synchronization window. An interrupt for synchronization lost is generated when the received synchornization on video port is not inside the window. DSI does not change its own timings if .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " VSA ,Defines the vertical Sync active period used in video mode in number of lines. The supported values are from 0 to 255 It is used to generate the short packet for End of Vertical synchronization." hexmask.long.byte 0x00 8.--15. 1. " VFP ,Defines the vertical front porch used in video mode in number of lines. The supported values are from 0 to 255" textline " " hexmask.long.byte 0x00 0.--7. 1. " VBP ,Defines the vertical back porch used in video mode in number of lines. The supported values are from 0 to 255" group.long 0x68++0x3 line.long 0x00 "DSI_VM_TIMING3,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.word 0x00 16.--31. 1. " TL ,Defines the number of length of the line in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 8192. The values from 8193 to 65535 are not supported." hexmask.long.word 0x00 0.--15. 1. " VACT ,Defines the number of active lines used in video mode. The supported values are from 0 to 65535" group.long 0x6C++0x3 line.long 0x00 "DSI_CLK_TIMING,CLOCK TIMING REGISTER This register controls the DSI Protocol Engine module timers. This register shall not be modified while .IF_EN is set to '1'." hexmask.long.byte 0x00 8.--15. 1. " DDR_CLK_PRE ,Indicates the number of TXBYTECLKHS clock cycles between the start of the DDR clock and the assertion of the data request signal. The values from 1 to 255 are valid. The value 0 is reserved. The value is not used ifDSI_CLK_C.." hexmask.long.byte 0x00 0.--7. 1. " DDR_CLK_POST ,Indicates the number of TXBYTECLKHS clock cycles after the de-assertion of the data request signal and the stop of the DDR clock. The values from 1 to 255 are valid. The value 0 is reserved. The value i.." group.long 0x70++0x3 line.long 0x00 "DSI_TX_FIFO_VC_SIZE,Defines the corresponding memory entries allocated for each virtual channel. The virtual channel shall be disabled in order to allocate/un-allocate some entries in the TX FIFO." bitfld.long 0x00 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7" group.long 0x74++0x3 line.long 0x00 "DSI_RX_FIFO_VC_SIZE,Defines the corresponding memory entries allocated for each virtual channel and the addresses. The virtual channel shall be disabled in order to allocate/un-allocate some entries in the RX FIFO." bitfld.long 0x00 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7" group.long 0x78++0x3 line.long 0x00 "DSI_COMPLEXIO_CFG2,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the ULPS for each lane." bitfld.long 0x00 17. " LP_BUSY ,Indicates when there are still pending operations for VCs configured for LP mode. Forced to 1 when at least one VC is enabled and configured for LP mode. - . - ." "False,True" bitfld.long 0x00 16. " HS_BUSY ,Indicates when there are still pending operations for VCs configured for HS mode. Forced to 1 when at least one VC is enabled and configured for HS mode. - . - ." "False,True" bitfld.long 0x00 9. " LANE5_ULPS_SIG2 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 5. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pend.." "Inactive,Active" textline " " bitfld.long 0x00 8. " LANE4_ULPS_SIG2 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 4. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI .." "Inactive,Active" bitfld.long 0x00 7. " LANE3_ULPS_SIG2 ,Enables the ULPS for the lane 3. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" bitfld.long 0x00 6. " LANE2_ULPS_SIG2 ,Enables the ULPS for the lane 2. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" textline " " bitfld.long 0x00 5. " LANE1_ULPS_SIG2 ,Enables the ULPS for the lane 1. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine has control of th.." "Inactive,Active" bitfld.long 0x00 4. " LANE5_ULPS_SIG1 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 5. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending.." "Inactive,Active" bitfld.long 0x00 3. " LANE4_ULPS_SIG1 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 4. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending.." "Inactive,Active" textline " " bitfld.long 0x00 2. " LANE3_ULPS_SIG1 ,Enables the ULPS for the lane 3. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine has control of th.." "Inactive,Active" bitfld.long 0x00 1. " LANE2_ULPS_SIG1 ,Enables the ULPS for the lane 2. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" bitfld.long 0x00 0. " LANE1_ULPS_SIG1 ,Enables the ULPS for the lane 1. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" rgroup.long 0x7C++0x3 line.long 0x00 "DSI_RX_FIFO_VC_FULLNESS,Defines the fullness of each space allocated for each virtual channel." hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 3.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 2.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 1.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." textline " " hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 0.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." group.long 0x80++0x3 line.long 0x00 "DSI_VM_TIMING4,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 16.--23. 1. " HSA_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HSA blanking period. The supported values are from 0 to 255." hexmask.long.byte 0x00 8.--15. 1. " HFP_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HFP blanking period. The supported values are from 0 to 255" hexmask.long.byte 0x00 0.--7. 1. " HBP_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HBP blanking period. The supported values are from 0 to 255" rgroup.long 0x84++0x3 line.long 0x00 "DSI_TX_FIFO_VC_EMPTINESS,Defines the emptiness of each space allocated for each virtual channel." hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 3.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 2.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 1.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." textline " " hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 0.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." group.long 0x88++0x3 line.long 0x00 "DSI_VM_TIMING5,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 16.--23. 1. " HSA_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HSA blanking period. The supported values are from 0 to 255." hexmask.long.byte 0x00 8.--15. 1. " HFP_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HFP blanking period. The supported values are from 0 to 255" hexmask.long.byte 0x00 0.--7. 1. " HBP_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HBP blanking period. The supported values are from 0 to 255" group.long 0x8C++0x3 line.long 0x00 "DSI_VM_TIMING6,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.word 0x00 16.--31. 1. " BL_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during blanking periods during VSA, VBP, VFP periods inside one video frame on PPI link. .." hexmask.long.word 0x00 0.--15. 1. " BL_LP_INTERLEAVING ,Defines the maximum number of bytes of Low Power command mode packets that can be sent on PPI link during blanking periods during VSA, VBP or VFP periods inside one video frame on PPI link. The supported .." group.long 0x90++0x3 line.long 0x00 "DSI_VM_TIMING7,Defines the minimum number of HS bytes clock cycles that are required to allow for the delays in entering and exiting HS mode. The supported values are from 0 to 65535" hexmask.long.word 0x00 16.--31. 1. " ENTER_HS_MODE_LATENCY ,Defines the number of TXBYTECLKHS clock cycles necessary for entering to HS mode. It corresponds to the delay in number of HS clock cycles from assertion of TxRequestHS signal to 1 until assertion of TxReadyHS signal to 1. T.." hexmask.long.word 0x00 0.--15. 1. " EXIT_HS_MODE_LATENCY ,Defines the number of TXBYTECLKHS clock cycles necessary for exiting from HS mode. It corresponds to the maximum delay in number of TXBYTECLKHS clock from de-assertion of TxRequestHS signal until PPI link.." group.long 0x94++0x3 line.long 0x00 "DSI_STOPCLK_TIMING,Number of functional clock cycles to wait for TXBYTECLKHS to stop/start after change in DSIStopClk signal" hexmask.long.byte 0x00 0.--7. 1. " DSI_STOPCLK_LATENCY ,Clock gating latency from DSI Protocol to TXBYTECLKHS" group.long 0x98++0x3 line.long 0x00 "DSI_CTRL2,Additional control bits for use with Video Port 2" bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port. The valid values are from 0 toDSI_GNQ[23:22] VP2_NB_LINE_BUFFER. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity - . - ." "Low,High" textline " " bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity - . - ." "Low,High" bitfld.long 0x00 8. " VP_CLK_POL ,VP pixel clock polarity - . - ." "Falling,Rising" bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus - . - . - ." "f16,f18,f24,3" textline " " bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP_CLK and VP_PCLK. The clock VP_PCLK is generated from VP_CLK. It is divided down. The information is only used when the video port is used to provide data in command mode. In the.." "RATIO2,RATIO3ANDHIGHER" group.long 0x9C++0x3 line.long 0x00 "DSI_VM_TIMING8,VIDEO MODE TIMING REGISTER This register defines the video mode timing." bitfld.long 0x00 0.--1. " HFPX ,Extension to the HFP register. Additional bits added to MSB." "0,1,2,3" tree.end tree "DSI2_PROTOCOL_ENGINE_L4_PER" base ad:0x48045000 tree "Channel_0" width 32. group.long 0xA8++0x3 line.long 0x00 "DSI_TE_HSYNC_NUMBER_j_0,The register configures the number of HSYNC to synchronize the beginning of the transfer on DSI link based on the number of HSYNC pulse received on the TE line. The input TE signal is asynchronous and needs to be resynchronizred.." hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number Line number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer. Any HSYNC before VSYNC is ignored." group.long 0xA0++0x3 line.long 0x00 "DSI_TE_HSYNC_WIDTH_j_0,The register configures the TE HSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width Minimum HSYNC pulse width. Number of DSI_CLK clock cycles times 256 to determine when HSYNC pulse occurs. The value 0 is invalid." group.long 0xA4++0x3 line.long 0x00 "DSI_TE_VSYNC_WIDTH_j_0,The register configures the TE VSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width Minimum VSYNC pulse width. Number of DSI_CLK cycles times 256 to determine when VSYNC pulse occurs. The value 0 is invalid. The value shall be greater than MIN_HSYNC_PULSE_WIDTH when DSI_TE_HSY.." group.long 0x100++0x3 line.long 0x00 "DSI_VC_CTRL_i_0,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x11C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_0,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x118++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_0,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x108++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_0,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x10C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_0,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x110++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_0,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x104++0x3 line.long 0x00 "DSI_VC_TE_i_0,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_1" width 32. group.long 0xB4++0x3 line.long 0x00 "DSI_TE_HSYNC_NUMBER_j_1,The register configures the number of HSYNC to synchronize the beginning of the transfer on DSI link based on the number of HSYNC pulse received on the TE line. The input TE signal is asynchronous and needs to be resynchronizred.." hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number Line number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer. Any HSYNC before VSYNC is ignored." group.long 0xAC++0x3 line.long 0x00 "DSI_TE_HSYNC_WIDTH_j_1,The register configures the TE HSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width Minimum HSYNC pulse width. Number of DSI_CLK clock cycles times 256 to determine when HSYNC pulse occurs. The value 0 is invalid." group.long 0xB0++0x3 line.long 0x00 "DSI_TE_VSYNC_WIDTH_j_1,The register configures the TE VSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width Minimum VSYNC pulse width. Number of DSI_CLK cycles times 256 to determine when VSYNC pulse occurs. The value 0 is invalid. The value shall be greater than MIN_HSYNC_PULSE_WIDTH when DSI_TE_HSY.." group.long 0x120++0x3 line.long 0x00 "DSI_VC_CTRL_i_1,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x13C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_1,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x138++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_1,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x128++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_1,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x12C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_1,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x130++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_1,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x124++0x3 line.long 0x00 "DSI_VC_TE_i_1,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_2" width 32. group.long 0x140++0x3 line.long 0x00 "DSI_VC_CTRL_i_2,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x15C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_2,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x158++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_2,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x148++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_2,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x14C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_2,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x150++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_2,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x144++0x3 line.long 0x00 "DSI_VC_TE_i_2,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_3" width 32. group.long 0x160++0x3 line.long 0x00 "DSI_VC_CTRL_i_3,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x17C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_3,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x178++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_3,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x168++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_3,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x16C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_3,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x170++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_3,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x164++0x3 line.long 0x00 "DSI_VC_TE_i_3,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end textline "" width 26. rgroup.long 0x0++0x3 line.long 0x00 "DSI_REVISION,IP Revision" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "DSI_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period - . - . - . - ." "OCPFuncOff,FuncOff,OCPOff,OCPFuncOn" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, Idle req/ack control - . - . - . - ." "fIdle,nIdle,sIdle,Res" bitfld.long 0x00 2. " ENWAKEUP ,Wake-up mode enable bit - . - ." "WakeUpDis,WakeUpEnb" textline " " bitfld.long 0x00 1. " SOFT_RESET ,Software reset. Set the bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads return 0. - . - ." "Normal,Reset" bitfld.long 0x00 0. " AUTO_IDLE ,Internal interface gating strategy - . - ." "Free,Gated" rgroup.long 0x14++0x3 line.long 0x00 "DSI_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module, excluding the interrupt status register." bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring - . - ." "ResetOngoing,ResetCompleted" group.long 0x18++0x3 line.long 0x00 "DSI_IRQSTATUS,INTERRUPT STATUS REGISTER - All virtual channels + Complex I/O + PLL This register associates one bit for each virtual channel in order to determine which virtual channel has generated the interrupt. The virtual channel shall be enabled f.." bitfld.long 0x00 22. " TE1_LINE_IRQ ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE1 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . - ." "False,True" bitfld.long 0x00 21. " TE0_LINE_IRQ ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE0 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - ..." "False,True" bitfld.long 0x00 20. " TA_TO_IRQ ,Turn-around Time out. - . - ." "False,True" textline " " bitfld.long 0x00 18. " SYNC_LOST_IRQ ,Synchronization with Video port is lost (Video mode only) - . - ." "False,True" bitfld.long 0x00 17. " ACK_TRIGGER_IRQ ,Acknowledge Trigger - . - ." "False,True" bitfld.long 0x00 16. " TE_TRIGGER_IRQ ,Tearing Effect Trigger - . - ." "False,True" textline " " bitfld.long 0x00 15. " LP_RX_TO_IRQ ,Interrupt for Low Power Rx Time out - . - ." "False,True" bitfld.long 0x00 14. " HS_TX_TO_IRQ ,Interrupt for High Speed Tx Time out. - . - ." "False,True" bitfld.long 0x00 10. " COMPLEXIO_ERR_IRQ ,Error signaling from Complex I/O: status of the complex I/O errors received from the complex I/O (events are defined inDSI_COMPLEXIO_IRQSTATUS). - . - ." "False,True" textline " " bitfld.long 0x00 9. " PLL_RECAL_IRQ ,PLL recal event (assertion of DSIRecal signal from the DSI PLL Control module) - . - ." "False,True" bitfld.long 0x00 8. " PLL_UNLOCK_IRQ ,PLL un-clock event (de-assertion of DSILock signal from the DSI PLL Control module) - . - ." "False,True" bitfld.long 0x00 7. " PLL_LOCK_IRQ ,PLL clock event (assertion of DSILock signal from the DSI PLL Control module) - . - ." "False,True" textline " " bitfld.long 0x00 5. " RESYNCHRONIZATION_IRQ ,Video mode resynchronization indicates to the software users that the video port works but the configuration of the timings for the display controller (DISPC) and for DSI Protocol engine may need to be modified to avoid the .." "False,True" bitfld.long 0x00 4. " WAKEUP_IRQ ,Wakeup - . - ." "False,True" bitfld.long 0x00 3. " VIRTUAL_CHANNEL3_IRQ ,Virtual channel 3 - . - ." "False,True" textline " " bitfld.long 0x00 2. " VIRTUAL_CHANNEL2_IRQ ,Virtual channel 2 - . - ." "False,True" bitfld.long 0x00 1. " VIRTUAL_CHANNEL1_IRQ ,Virtual channel 1 - . - ." "False,True" bitfld.long 0x00 0. " VIRTUAL_CHANNEL0_IRQ ,Virtual channel 0 - . - ." "False,True" group.long 0x1C++0x3 line.long 0x00 "DSI_IRQENABLE,INTERRUPT ENABLE REGISTER - This register associates one bit for each virtual channel in order to enable/disable each virtual channel individually." bitfld.long 0x00 22. " TE1_LINE_IRQ_EN ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE1 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . - ." "Disable,Enable" bitfld.long 0x00 21. " TE0_LINE_IRQ_EN ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE0 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . -.." "Disable,Enable" bitfld.long 0x00 20. " TA_TO_IRQ_EN ,Turn-around Time out. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 18. " SYNC_LOST_IRQ_EN ,Synchronization with Video port is lost (Video mode only) - . - ." "Disable,Enable" bitfld.long 0x00 17. " ACK_TRIGGER_IRQ_EN ,Acknowledge trigger - . - ." "Disable,Enable" bitfld.long 0x00 16. " TE_TRIGGER_IRQ_EN ,Tearing Effect trigger - . - ." "Disable,Enable" textline " " bitfld.long 0x00 15. " LP_RX_TO_IRQ_EN ,Interrupt for Low Power Rx Time out. - . - ." "Disable,Enable" bitfld.long 0x00 14. " HS_TX_TO_IRQ_EN ,Interrupt for High Speed Tx Time out. - . - ." "Disable,Enable" bitfld.long 0x00 9. " PLL_RECAL_IRQ_EN ,PLL recal event (assertion of DSIRecal signal from the DSI PLL Control module) - . - ." "Disable,Enable" textline " " bitfld.long 0x00 8. " PLL_UNLOCK_IRQ_EN ,PLL un-clock event (de-assertion of DSILock signal from the DSI PLL Control module) - . - ." "Disable,Enable" bitfld.long 0x00 7. " PLL_LOCK_IRQ_EN ,PLL clock event (assertion of DSILock signal from the DSI PLL Control module) - . - ." "Disable,Enable" bitfld.long 0x00 5. " RESYNCHRONIZATION_IRQ_EN ,Video mode resynchronization - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " WAKEUP_IRQ_EN ,Wakeup - . - ." "Disable,Enable" group.long 0x40++0x3 line.long 0x00 "DSI_CTRL,GLOBAL CONTROL REGISTER This register controls the DSI Protocol Engine module. This register shall not be modified dynamically (except IF_EN bit fields)." bitfld.long 0x00 24. " DISPC_UPDATE_SYNC ,Determines if the Dispc_Update_Sync signal from the display controller is used. - . - ." "Disable,Enable" bitfld.long 0x00 23. " HSA_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" bitfld.long 0x00 22. " HBP_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" textline " " bitfld.long 0x00 21. " HFP_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" bitfld.long 0x00 20. " BLANKING_MODE ,Blanking mode - . - ." "LPS,HS" bitfld.long 0x00 19. " EOT_ENABLE ,Enable EOT packets at the end of HS transmission. - . - ." "EOT_OFF,EOT_ON" textline " " bitfld.long 0x00 18. " VP_HSYNC_END ,HSYNC end pulse. - . - ." "Disable,Enable" bitfld.long 0x00 17. " VP_HSYNC_START ,HSYNC start pulse. - . - ." "Disable,Enable" bitfld.long 0x00 16. " VP_VSYNC_END ,VSYNC end pulse. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 15. " VP_VSYNC_START ,VSYNC start pulse. - . - ." "Disable,Enable" bitfld.long 0x00 14. " TRIGGER_RESET_MODE ,Selection of the trigger reset mode - . - ." "Synchronized,Immediate" bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port. The valid values are from 0 toDSI_GNQ[17:16] VP1_NB_LINE_BUFFER. - . - . - ." "f0,f1,f2,3" textline " " bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity - . - ." "Low,High" textline " " bitfld.long 0x00 8. " VP_CLK_POL ,VP pixel clock polarity - . - ." "Falling,Rising" bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus - . - . - ." "f16,f18,f24,3" bitfld.long 0x00 5. " TRIGGER_RESET ,Send the reset trigger to the peripheral. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP_CLK and VP_PCLK. The clock VP_PCLK is generated from VP_CLK. It is divided down. The information is only used when the video port is used to provide data in command mode. In the.." "RATIO2,RATIO3ANDHIGHER" bitfld.long 0x00 3. " TX_FIFO_ARBITRATION ,Defines the arbitration scheme for granting the virtual channel pending ready requests in the TX FIFO - . - ." "RoundRobin,Sequential" bitfld.long 0x00 2. " ECC_RX_EN ,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " CS_RX_EN ,Enables the checksum check for the received payload (long packet only for all virtual channel ids). - . - ." "Disable,Enable" bitfld.long 0x00 0. " IF_EN ,Enables the module. When the module is disabled the signals from the complex I/O are gated (no updates of the interrupt status register). It is not possible to change the bit fields in the register DSI_CTRL .." "Disable,Enable" rgroup.long 0x44++0x3 line.long 0x00 "DSI_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design." bitfld.long 0x00 24. " NB_VIDEO_PORTS ,Number of video ports - . - ." "Single_VP,Dual_VP" bitfld.long 0x00 22.--23. " VP2_NB_LINE_BUFFER ,Determines the number of video buffer lines associated to video port 2. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 18.--20. " VP2_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 2 . - . - . - . - . - . - ." "0,f1,f2,f3,f4,f5,f6,7" textline " " bitfld.long 0x00 16.--17. " VP1_NB_LINE_BUFFER ,Determines the number of video buffer lines associated to video port 1. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 12.--14. " VP1_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 1 . - . - . - . - . - . - ." "0,f1,f2,f3,f4,f5,f6,7" bitfld.long 0x00 9.--11. " NB_DATA_LANES ,Determines the number of data lanes supported by the DSI protocol engine . - . - . - . - ." "0,f1,f2,f3,f4,5,6,7" textline " " bitfld.long 0x00 6.--8. " NB_DMA_REQUEST ,Determines the number of DMA_REQ signals. - . - . - . - . - ." "f0,f1,f2,f3,f4,5,6,7" bitfld.long 0x00 3.--5. " RX_FIFODEPTH ,Determines the data RX FIFO depth (32-bit words) on the slave port. - . - . - . - ." "0,1,2,3,f32,f64,f128,f256" bitfld.long 0x00 0.--2. " TX_FIFODEPTH ,Determines the data TX FIFO depth (33-bit words) on the slave port. - . - . - . - ." "0,1,2,3,f32,f64,f128,f256" group.long 0x48++0x3 line.long 0x00 "DSI_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in add.." bitfld.long 0x00 31. " SHADOWING ,Shadowing configuration. - . - ." "Disable,Enable" bitfld.long 0x00 30. " GOBIT ,Allows the synchronized update of the shadow registers when the signal DISPCUpdateSync is active. - . - ." "Reset,Set" bitfld.long 0x00 29. " RESET_DONE ,Internal reset monitoring of the power domain using the TXBYTECLKHS clock from the complex I/O - . - ." "ResetOngoing,ResetCompleted" textline " " bitfld.long 0x00 27.--28. " PWR_CMD ,Command for power control of the complex I/O - . - . - ." "STATE_OFF,STATE_ON,STATE_ULP,3" bitfld.long 0x00 25.--26. " PWR_STATUS ,Status of the power control of the complex I/O - . - . - ." "STATE_OFF,STATE_ON,STATE_ULP,3" bitfld.long 0x00 19. " DATA4_POL ,+/- differential pin order of DATA lane 4. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "PlusMinus,MinusPlus" textline " " bitfld.long 0x00 16.--18. " DATA4_POSITION ,Position and order of the DATA lane 4. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" bitfld.long 0x00 15. " DATA3_POL ,+/- differential pin order of DATA lane 3. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 12.--14. " DATA3_POSITION ,Position and order of the DATA lane 3. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" textline " " bitfld.long 0x00 11. " DATA2_POL ,+/- differential pin order of DATA lane 2. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 8.--10. " DATA2_POSITION ,Position and order of the DATA lane 2. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" bitfld.long 0x00 7. " DATA1_POL ,+/- pin differential pin order of DATA lane 1 - . - ." "PlusMinus,MinusPlus" textline " " bitfld.long 0x00 4.--6. " DATA1_POSITION ,Position and order of the DATA lane 1. The data lane 1 is always present. - . - . - . - . - . - ." "0,Position_1,Position_2,Position_3,Position_4,Position_5,6,7" bitfld.long 0x00 3. " CLOCK_POL ,+/- differential pin order of CLOCK lane. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 0.--2. " CLOCK_POSITION ,Position and order of the CLOCK lane. 0, 5, 6 and 7 are reserved. The clock lane is always present but cannot be at the position 5 even if the COMPLEX I/O consists of 5 lanes. - . - . - . - . - . - . - . - ." "0,Position_1,Position_2,Position_3,Position_4,5,6,7" group.long 0x4C++0x3 line.long 0x00 "DSI_COMPLEXIO_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex I/O" bitfld.long 0x00 31. " ULPSACTIVENOT_ALL1_IRQ ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high. - . - ." "False,True" bitfld.long 0x00 30. " ULPSACTIVENOT_ALL0_IRQ ,All signals ULPSActiveNOT are 0 - . - ." "False,True" bitfld.long 0x00 29. " ERRCONTENTIONLP1_5_IRQ ,Contention LP1 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 28. " ERRCONTENTIONLP0_5_IRQ ,Contention LP0 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 27. " ERRCONTENTIONLP1_4_IRQ ,Contention LP1 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 26. " ERRCONTENTIONLP0_4_IRQ ,Contention LP0 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 25. " ERRCONTENTIONLP1_3_IRQ ,Contention LP1 error for lane 3 - . - ." "False,True" bitfld.long 0x00 24. " ERRCONTENTIONLP0_3_IRQ ,Contention LP0 error for lane 3 - . - ." "False,True" bitfld.long 0x00 23. " ERRCONTENTIONLP1_2_IRQ ,Contention LP1 error for lane 2 - . - ." "False,True" textline " " bitfld.long 0x00 22. " ERRCONTENTIONLP0_2_IRQ ,Contention LP0 error for lane 2 - . - ." "False,True" bitfld.long 0x00 21. " ERRCONTENTIONLP1_1_IRQ ,Contention LP1 error for lane 1 - . - ." "False,True" bitfld.long 0x00 20. " ERRCONTENTIONLP0_1_IRQ ,Contention LP0 error for lane 1 - . - ." "False,True" textline " " bitfld.long 0x00 19. " STATEULPS5_IRQ ,lane 5 in ULTRALOW-POWER State Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 18. " STATEULPS4_IRQ ,lane 4 in ultralow-power mode Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 17. " STATEULPS3_IRQ ,lane 3 in ULTRALOW-POWER state - . - ." "False,True" textline " " bitfld.long 0x00 16. " STATEULPS2_IRQ ,lane 2 in ULTRALOW-POWER state - . - ." "False,True" bitfld.long 0x00 15. " STATEULPS1_IRQ ,lane 1 in ULTRALOW-POWER state - . - ." "False,True" bitfld.long 0x00 14. " ERRCONTROL5_IRQ ,Control error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 13. " ERRCONTROL4_IRQ ,Control error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 12. " ERRCONTROL3_IRQ ,Control error for lane 3 - . - ." "False,True" bitfld.long 0x00 11. " ERRCONTROL2_IRQ ,Control error for lane 2 - . - ." "False,True" textline " " bitfld.long 0x00 10. " ERRCONTROL1_IRQ ,Control error for lane 1 - . - ." "False,True" bitfld.long 0x00 9. " ERRESC5_IRQ ,Escape entry error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 8. " ERRESC4_IRQ ,Escape entry error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 7. " ERRESC3_IRQ ,Escape entry error for lane 3 - . - ." "False,True" bitfld.long 0x00 6. " ERRESC2_IRQ ,Escape entry error for lane 2 - . - ." "False,True" bitfld.long 0x00 5. " ERRESC1_IRQ ,Escape entry error for lane 1 - . - ." "False,True" textline " " bitfld.long 0x00 4. " ERRSYNCESC5_IRQ ,Low power Data transmission synchronization error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 3. " ERRSYNCESC4_IRQ ,Low power Data transmission synchronization error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 2. " ERRSYNCESC3_IRQ ,Low power Data transmission synchronization error for lane 3 - . - ." "False,True" textline " " bitfld.long 0x00 1. " ERRSYNCESC2_IRQ ,Low power Data transmission synchronization error for lane 2 - . - ." "False,True" bitfld.long 0x00 0. " ERRSYNCESC1_IRQ ,Low power Data transmission synchronization error for lane 1 - . - ." "False,True" group.long 0x50++0x3 line.long 0x00 "DSI_COMPLEXIO_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex I/O" bitfld.long 0x00 31. " ULPSACTIVENOT_ALL1_IRQ_EN ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high. - . - ." "Disable,Enable" bitfld.long 0x00 30. " ULPSACTIVENOT_ALL0_IRQ_EN ,All signals ULPSActiveNOT are 0 - . - ." "Disable,Enable" bitfld.long 0x00 29. " ERRCONTENTIONLP1_5_IRQ_EN ,Contention LP1 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " ERRCONTENTIONLP0_5_IRQ_EN ,Contention LP0 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 27. " ERRCONTENTIONLP1_4_IRQ_EN ,Contention LP1 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 26. " ERRCONTENTIONLP0_4_IRQ_EN ,Contention LP0 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 25. " ERRCONTENTIONLP1_3_IRQ_EN ,Contention LP1 error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 24. " ERRCONTENTIONLP0_3_IRQ_EN ,Contention LP0 error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 23. " ERRCONTENTIONLP1_2_IRQ_EN ,Contention LP1 error for lane 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 22. " ERRCONTENTIONLP0_2_IRQ_EN ,Contention LP0 error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 21. " ERRCONTENTIONLP1_1_IRQ_EN ,Contention LP1 error for lane 1 - . - ." "Disable,Enable" bitfld.long 0x00 20. " ERRCONTENTIONLP0_1_IRQ_EN ,Contention LP0 error for lane 1 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 19. " STATEULPS5_IRQ_EN ,lane 5 in ULTRALOW-POWER state Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 18. " STATEULPS4_IRQ_EN ,lane 4 in ULTRALOW-POWER state Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 17. " STATEULPS3_IRQ_EN ,lane 3 in ULTRALOW-POWER state - . - ." "Disable,Enable" textline " " bitfld.long 0x00 16. " STATEULPS2_IRQ_EN ,lane 2 in ULTRALOW-POWER state - . - ." "Disable,Enable" bitfld.long 0x00 15. " STATEULPS1_IRQ_EN ,lane 1 in ULTRALOW-POWER state - . - ." "Disable,Enable" bitfld.long 0x00 14. " ERRCONTROL5_IRQ_EN ,Control error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " ERRCONTROL4_IRQ_EN ,Control error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 12. " ERRCONTROL3_IRQ_EN ,Control error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 11. " ERRCONTROL2_IRQ_EN ,Control error for lane 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 10. " ERRCONTROL1_IRQ_EN ,Control error for lane 1 - . - ." "Disable,Enable" bitfld.long 0x00 9. " ERRESC5_IRQ_EN ,Escape entry error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 8. " ERRESC4_IRQ_EN ,Escape entry error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " ERRESC3_IRQ_EN ,Escape entry error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 6. " ERRESC2_IRQ_EN ,Escape entry error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 5. " ERRESC1_IRQ_EN ,Escape entry error for lane 1 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " ERRSYNCSESC5_IRQ_EN ,Low power Data transmission synchronization error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 3. " ERRSYNCSESC4_IRQ_EN ,Low power Data transmission synchronization error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 2. " ERRSYNCSESC3_IRQ_EN ,Low power Data transmission synchronization error for lane 3 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " ERRSYNCSESC2_IRQ_EN ,Low power Data transmission synchronization error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 0. " ERRSYNCSESC1_IRQ_EN ,Low power Data transmission synchronization error for lane 1 - . - ." "Disable,Enable" group.long 0x54++0x3 line.long 0x00 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION. The register can be modified only when IF_EN is reset." bitfld.long 0x00 30.--31. " PLL_PWR_CMD ,Command for power control of the DSI PLL Control module - . - . - . - ." "STATE_OFF,STATE_ON_HSCLK,STATE_ON_ALL,STATE_ON_DIV" bitfld.long 0x00 28.--29. " PLL_PWR_STATUS ,Status of the power control of the DSI PLL Control module - . - . - . - ." "STATE_OFF,STATE_ON_HSCLK,STATE_ON_ALL,STATE_ON_DIV" bitfld.long 0x00 21. " LP_RX_SYNCHRO_ENABLE ,Defines if the functional is higher or lower than 30 MHz. The information is used to define synchronization to be used for RxValidEsc. - . - ." "LowSpeed,HighSpeed" textline " " bitfld.long 0x00 20. " LP_CLK_ENABLE ,Controls the gating of the TXCLKESC clock. - . - ." "Disable,Enable" bitfld.long 0x00 19. " HS_MANUAL_STOP_CTRL ,In case HS_AUTO_STOP_ENABLE=0, the bit field allows manual control of the assertion/de-assertion of the signal DSIStopClk by the user. - . - ." "Deassertion,Assertion" bitfld.long 0x00 18. " HS_AUTO_STOP_ENABLE ,Enables the automatic assertion/de-assertion of DSIStopClk signal. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 16.--17. " LP_CLK_NULL_PACKET_SIZE ,Indicates the size of LP NULL Packets to be sent automatically when after the last LP packet transfer. It is used by the receiver to drain its internal pipeline. The valid values are from 0 to 3 bytes for the payload size." "0,1,2,3" bitfld.long 0x00 15. " LP_CLK_NULL_PACKET_ENABLE ,Enables the generation of NULL packet in low speed. - . - ." "Disable,Enable" bitfld.long 0x00 14. " CIO_CLK_ICG ,Gates SCPClk clock provided to DSI_PHY and PLL-CTRL module. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " DDR_CLK_ALWAYS_ON ,Defines if the DDR clock is also sent when there is no HS packets sent to the peripheral (low-power mode). So TXRequest for the clock lane is not de-asserted. - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " LP_CLK_DIVISOR ,Defines the ratio to be used for the generation of the low-power mode clock from DSI functional clock. The supported values are from 1 to 8191(the value 0 is invalid). The output frequency shall be in the ra.." group.long 0x58++0x3 line.long 0x00 "DSI_TIMING1,TIMING1 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be modified while [0] IF_EN is set to '1'. It is used to indicate the number of DSI1_CLK and DSI2_CLK functional clocks cycles for the timers F.." bitfld.long 0x00 31. " TA_TO ,Enables the turn-around timer - . - ." "Deassertion,Assertion" bitfld.long 0x00 30. " TA_TO_X16 ,Multiplication factor for the number of DSI_CLK functional clocks cycles defined in TA_TO_COUNTER bit field - . - ." "Disable,Enable" bitfld.long 0x00 29. " TA_TO_X8 ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in TA_TO_COUNTER bit field - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 16.--28. 1. " TA_TO_COUNTER ,Turn around counter. It indicates the number of DSI_CLK function clock to wait for the change of the Direction PPI signal according to the TurnRequest signal The value is from 0 to 8191." bitfld.long 0x00 15. " FORCE_TX_STOP_MODE_IO ,Control of ForceTxStopMode signal - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " STOP_STATE_X16_IO ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit field - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " STOP_STATE_X4_IO ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit field - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " STOP_STATE_COUNTER_IO ,Stop state counter. It indicates the number of DSI_CLK function clock to assert ForceTXStopMode signal. The value is from 0 to 8191." group.long 0x5C++0x3 line.long 0x00 "DSI_TIMING2,TIMING2 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be modified while [0] IF_EN is set to '1'. It is used to indicate the number of DSI_FCLK clock cycles for the timer LP_RX_TIMER and the number .." bitfld.long 0x00 31. " HS_TX_TO ,Enables the HS TX timer. - . - ." "Deassertion,Assertion" bitfld.long 0x00 30. " HS_TX_TO_X64 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit field. BYTE_CLK is a high speed transmit byte clock signal generated by the DSI_PHY. - . - ." "Disable,Enable" bitfld.long 0x00 29. " HS_TX_TO_X16 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 16.--28. 1. " HS_TX_TO_COUNTER ,HS_TX_TIMER counter. It indicates the number of BYTE_CLK function clock for the HS TX timer. The value is from 0 to 8191." bitfld.long 0x00 15. " LP_RX_TO ,Enables the LP RX timer. - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " LP_RX_TO_X16 ,Multiplication factor for the number of DSI_FCLK clock cycles defined in LP_RX_COUNTER bit field - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " LP_RX_TO_X4 ,Multiplication factor for the number of DSI_FCLK clock cycles defined in LP_RX_COUNTER bit - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " LP_RX_TO_COUNTER ,LP_RX_TIMER counter. It indicates the number of DSI_FCLK clock for the LP RX timer. The value is from 0 to 8191." group.long 0x60++0x3 line.long 0x00 "DSI_VM_TIMING1,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 24.--31. 1. " HSA ,Defines the horizontal Sync active period used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 255." hexmask.long.word 0x00 12.--23. 1. " HFP ,Defines the horizontal front porch used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 4095" hexmask.long.word 0x00 0.--11. 1. " HBP ,Defines the horizontal back porch used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 4095" group.long 0x64++0x3 line.long 0x00 "DSI_VM_TIMING2,VIDEO MODE TIMING REGISTER This register defines the video mode timing." bitfld.long 0x00 24.--27. " WINDOW_SYNC ,Number of BYTE clock cycles for the synchronization window. An interrupt for synchronization lost is generated when the received synchornization on video port is not inside the window. DSI does not change its own timings if .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " VSA ,Defines the vertical Sync active period used in video mode in number of lines. The supported values are from 0 to 255 It is used to generate the short packet for End of Vertical synchronization." hexmask.long.byte 0x00 8.--15. 1. " VFP ,Defines the vertical front porch used in video mode in number of lines. The supported values are from 0 to 255" textline " " hexmask.long.byte 0x00 0.--7. 1. " VBP ,Defines the vertical back porch used in video mode in number of lines. The supported values are from 0 to 255" group.long 0x68++0x3 line.long 0x00 "DSI_VM_TIMING3,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.word 0x00 16.--31. 1. " TL ,Defines the number of length of the line in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 8192. The values from 8193 to 65535 are not supported." hexmask.long.word 0x00 0.--15. 1. " VACT ,Defines the number of active lines used in video mode. The supported values are from 0 to 65535" group.long 0x6C++0x3 line.long 0x00 "DSI_CLK_TIMING,CLOCK TIMING REGISTER This register controls the DSI Protocol Engine module timers. This register shall not be modified while .IF_EN is set to '1'." hexmask.long.byte 0x00 8.--15. 1. " DDR_CLK_PRE ,Indicates the number of TXBYTECLKHS clock cycles between the start of the DDR clock and the assertion of the data request signal. The values from 1 to 255 are valid. The value 0 is reserved. The value is not used ifDSI_CLK_C.." hexmask.long.byte 0x00 0.--7. 1. " DDR_CLK_POST ,Indicates the number of TXBYTECLKHS clock cycles after the de-assertion of the data request signal and the stop of the DDR clock. The values from 1 to 255 are valid. The value 0 is reserved. The value i.." group.long 0x70++0x3 line.long 0x00 "DSI_TX_FIFO_VC_SIZE,Defines the corresponding memory entries allocated for each virtual channel. The virtual channel shall be disabled in order to allocate/un-allocate some entries in the TX FIFO." bitfld.long 0x00 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7" group.long 0x74++0x3 line.long 0x00 "DSI_RX_FIFO_VC_SIZE,Defines the corresponding memory entries allocated for each virtual channel and the addresses. The virtual channel shall be disabled in order to allocate/un-allocate some entries in the RX FIFO." bitfld.long 0x00 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7" group.long 0x78++0x3 line.long 0x00 "DSI_COMPLEXIO_CFG2,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the ULPS for each lane." bitfld.long 0x00 17. " LP_BUSY ,Indicates when there are still pending operations for VCs configured for LP mode. Forced to 1 when at least one VC is enabled and configured for LP mode. - . - ." "False,True" bitfld.long 0x00 16. " HS_BUSY ,Indicates when there are still pending operations for VCs configured for HS mode. Forced to 1 when at least one VC is enabled and configured for HS mode. - . - ." "False,True" bitfld.long 0x00 9. " LANE5_ULPS_SIG2 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 5. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pend.." "Inactive,Active" textline " " bitfld.long 0x00 8. " LANE4_ULPS_SIG2 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 4. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI .." "Inactive,Active" bitfld.long 0x00 7. " LANE3_ULPS_SIG2 ,Enables the ULPS for the lane 3. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" bitfld.long 0x00 6. " LANE2_ULPS_SIG2 ,Enables the ULPS for the lane 2. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" textline " " bitfld.long 0x00 5. " LANE1_ULPS_SIG2 ,Enables the ULPS for the lane 1. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine has control of th.." "Inactive,Active" bitfld.long 0x00 4. " LANE5_ULPS_SIG1 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 5. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending.." "Inactive,Active" bitfld.long 0x00 3. " LANE4_ULPS_SIG1 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 4. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending.." "Inactive,Active" textline " " bitfld.long 0x00 2. " LANE3_ULPS_SIG1 ,Enables the ULPS for the lane 3. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine has control of th.." "Inactive,Active" bitfld.long 0x00 1. " LANE2_ULPS_SIG1 ,Enables the ULPS for the lane 2. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" bitfld.long 0x00 0. " LANE1_ULPS_SIG1 ,Enables the ULPS for the lane 1. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" rgroup.long 0x7C++0x3 line.long 0x00 "DSI_RX_FIFO_VC_FULLNESS,Defines the fullness of each space allocated for each virtual channel." hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 3.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 2.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 1.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." textline " " hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 0.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." group.long 0x80++0x3 line.long 0x00 "DSI_VM_TIMING4,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 16.--23. 1. " HSA_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HSA blanking period. The supported values are from 0 to 255." hexmask.long.byte 0x00 8.--15. 1. " HFP_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HFP blanking period. The supported values are from 0 to 255" hexmask.long.byte 0x00 0.--7. 1. " HBP_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HBP blanking period. The supported values are from 0 to 255" rgroup.long 0x84++0x3 line.long 0x00 "DSI_TX_FIFO_VC_EMPTINESS,Defines the emptiness of each space allocated for each virtual channel." hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 3.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 2.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 1.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." textline " " hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 0.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." group.long 0x88++0x3 line.long 0x00 "DSI_VM_TIMING5,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 16.--23. 1. " HSA_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HSA blanking period. The supported values are from 0 to 255." hexmask.long.byte 0x00 8.--15. 1. " HFP_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HFP blanking period. The supported values are from 0 to 255" hexmask.long.byte 0x00 0.--7. 1. " HBP_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HBP blanking period. The supported values are from 0 to 255" group.long 0x8C++0x3 line.long 0x00 "DSI_VM_TIMING6,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.word 0x00 16.--31. 1. " BL_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during blanking periods during VSA, VBP, VFP periods inside one video frame on PPI link. .." hexmask.long.word 0x00 0.--15. 1. " BL_LP_INTERLEAVING ,Defines the maximum number of bytes of Low Power command mode packets that can be sent on PPI link during blanking periods during VSA, VBP or VFP periods inside one video frame on PPI link. The supported .." group.long 0x90++0x3 line.long 0x00 "DSI_VM_TIMING7,Defines the minimum number of HS bytes clock cycles that are required to allow for the delays in entering and exiting HS mode. The supported values are from 0 to 65535" hexmask.long.word 0x00 16.--31. 1. " ENTER_HS_MODE_LATENCY ,Defines the number of TXBYTECLKHS clock cycles necessary for entering to HS mode. It corresponds to the delay in number of HS clock cycles from assertion of TxRequestHS signal to 1 until assertion of TxReadyHS signal to 1. T.." hexmask.long.word 0x00 0.--15. 1. " EXIT_HS_MODE_LATENCY ,Defines the number of TXBYTECLKHS clock cycles necessary for exiting from HS mode. It corresponds to the maximum delay in number of TXBYTECLKHS clock from de-assertion of TxRequestHS signal until PPI link.." group.long 0x94++0x3 line.long 0x00 "DSI_STOPCLK_TIMING,Number of functional clock cycles to wait for TXBYTECLKHS to stop/start after change in DSIStopClk signal" hexmask.long.byte 0x00 0.--7. 1. " DSI_STOPCLK_LATENCY ,Clock gating latency from DSI Protocol to TXBYTECLKHS" group.long 0x98++0x3 line.long 0x00 "DSI_CTRL2,Additional control bits for use with Video Port 2" bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port. The valid values are from 0 toDSI_GNQ[23:22] VP2_NB_LINE_BUFFER. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity - . - ." "Low,High" textline " " bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity - . - ." "Low,High" bitfld.long 0x00 8. " VP_CLK_POL ,VP pixel clock polarity - . - ." "Falling,Rising" bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus - . - . - ." "f16,f18,f24,3" textline " " bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP_CLK and VP_PCLK. The clock VP_PCLK is generated from VP_CLK. It is divided down. The information is only used when the video port is used to provide data in command mode. In the.." "RATIO2,RATIO3ANDHIGHER" group.long 0x9C++0x3 line.long 0x00 "DSI_VM_TIMING8,VIDEO MODE TIMING REGISTER This register defines the video mode timing." bitfld.long 0x00 0.--1. " HFPX ,Extension to the HFP register. Additional bits added to MSB." "0,1,2,3" tree.end tree "DSI1_PROTOCOL_ENGINE_L3" base ad:0x58004000 tree "Channel_0" width 32. group.long 0xA8++0x3 line.long 0x00 "DSI_TE_HSYNC_NUMBER_j_0,The register configures the number of HSYNC to synchronize the beginning of the transfer on DSI link based on the number of HSYNC pulse received on the TE line. The input TE signal is asynchronous and needs to be resynchronizred.." hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number Line number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer. Any HSYNC before VSYNC is ignored." group.long 0xA0++0x3 line.long 0x00 "DSI_TE_HSYNC_WIDTH_j_0,The register configures the TE HSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width Minimum HSYNC pulse width. Number of DSI_CLK clock cycles times 256 to determine when HSYNC pulse occurs. The value 0 is invalid." group.long 0xA4++0x3 line.long 0x00 "DSI_TE_VSYNC_WIDTH_j_0,The register configures the TE VSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width Minimum VSYNC pulse width. Number of DSI_CLK cycles times 256 to determine when VSYNC pulse occurs. The value 0 is invalid. The value shall be greater than MIN_HSYNC_PULSE_WIDTH when DSI_TE_HSY.." group.long 0x100++0x3 line.long 0x00 "DSI_VC_CTRL_i_0,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x11C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_0,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x118++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_0,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x108++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_0,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x10C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_0,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x110++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_0,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x104++0x3 line.long 0x00 "DSI_VC_TE_i_0,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_1" width 32. group.long 0xB4++0x3 line.long 0x00 "DSI_TE_HSYNC_NUMBER_j_1,The register configures the number of HSYNC to synchronize the beginning of the transfer on DSI link based on the number of HSYNC pulse received on the TE line. The input TE signal is asynchronous and needs to be resynchronizred.." hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number Line number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer. Any HSYNC before VSYNC is ignored." group.long 0xAC++0x3 line.long 0x00 "DSI_TE_HSYNC_WIDTH_j_1,The register configures the TE HSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width Minimum HSYNC pulse width. Number of DSI_CLK clock cycles times 256 to determine when HSYNC pulse occurs. The value 0 is invalid." group.long 0xB0++0x3 line.long 0x00 "DSI_TE_VSYNC_WIDTH_j_1,The register configures the TE VSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width Minimum VSYNC pulse width. Number of DSI_CLK cycles times 256 to determine when VSYNC pulse occurs. The value 0 is invalid. The value shall be greater than MIN_HSYNC_PULSE_WIDTH when DSI_TE_HSY.." group.long 0x120++0x3 line.long 0x00 "DSI_VC_CTRL_i_1,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x13C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_1,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x138++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_1,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x128++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_1,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x12C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_1,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x130++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_1,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x124++0x3 line.long 0x00 "DSI_VC_TE_i_1,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_2" width 32. group.long 0x140++0x3 line.long 0x00 "DSI_VC_CTRL_i_2,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x15C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_2,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x158++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_2,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x148++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_2,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x14C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_2,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x150++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_2,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x144++0x3 line.long 0x00 "DSI_VC_TE_i_2,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_3" width 32. group.long 0x160++0x3 line.long 0x00 "DSI_VC_CTRL_i_3,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x17C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_3,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x178++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_3,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x168++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_3,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x16C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_3,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x170++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_3,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x164++0x3 line.long 0x00 "DSI_VC_TE_i_3,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end textline "" width 26. rgroup.long 0x0++0x3 line.long 0x00 "DSI_REVISION,IP Revision" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "DSI_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period - . - . - . - ." "OCPFuncOff,FuncOff,OCPOff,OCPFuncOn" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, Idle req/ack control - . - . - . - ." "fIdle,nIdle,sIdle,Res" bitfld.long 0x00 2. " ENWAKEUP ,Wake-up mode enable bit - . - ." "WakeUpDis,WakeUpEnb" textline " " bitfld.long 0x00 1. " SOFT_RESET ,Software reset. Set the bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads return 0. - . - ." "Normal,Reset" bitfld.long 0x00 0. " AUTO_IDLE ,Internal interface gating strategy - . - ." "Free,Gated" rgroup.long 0x14++0x3 line.long 0x00 "DSI_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module, excluding the interrupt status register." bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring - . - ." "ResetOngoing,ResetCompleted" group.long 0x18++0x3 line.long 0x00 "DSI_IRQSTATUS,INTERRUPT STATUS REGISTER - All virtual channels + Complex I/O + PLL This register associates one bit for each virtual channel in order to determine which virtual channel has generated the interrupt. The virtual channel shall be enabled f.." bitfld.long 0x00 22. " TE1_LINE_IRQ ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE1 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . - ." "False,True" bitfld.long 0x00 21. " TE0_LINE_IRQ ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE0 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - ..." "False,True" bitfld.long 0x00 20. " TA_TO_IRQ ,Turn-around Time out. - . - ." "False,True" textline " " bitfld.long 0x00 18. " SYNC_LOST_IRQ ,Synchronization with Video port is lost (Video mode only) - . - ." "False,True" bitfld.long 0x00 17. " ACK_TRIGGER_IRQ ,Acknowledge Trigger - . - ." "False,True" bitfld.long 0x00 16. " TE_TRIGGER_IRQ ,Tearing Effect Trigger - . - ." "False,True" textline " " bitfld.long 0x00 15. " LP_RX_TO_IRQ ,Interrupt for Low Power Rx Time out - . - ." "False,True" bitfld.long 0x00 14. " HS_TX_TO_IRQ ,Interrupt for High Speed Tx Time out. - . - ." "False,True" bitfld.long 0x00 10. " COMPLEXIO_ERR_IRQ ,Error signaling from Complex I/O: status of the complex I/O errors received from the complex I/O (events are defined inDSI_COMPLEXIO_IRQSTATUS). - . - ." "False,True" textline " " bitfld.long 0x00 9. " PLL_RECAL_IRQ ,PLL recal event (assertion of DSIRecal signal from the DSI PLL Control module) - . - ." "False,True" bitfld.long 0x00 8. " PLL_UNLOCK_IRQ ,PLL un-clock event (de-assertion of DSILock signal from the DSI PLL Control module) - . - ." "False,True" bitfld.long 0x00 7. " PLL_LOCK_IRQ ,PLL clock event (assertion of DSILock signal from the DSI PLL Control module) - . - ." "False,True" textline " " bitfld.long 0x00 5. " RESYNCHRONIZATION_IRQ ,Video mode resynchronization indicates to the software users that the video port works but the configuration of the timings for the display controller (DISPC) and for DSI Protocol engine may need to be modified to avoid the .." "False,True" bitfld.long 0x00 4. " WAKEUP_IRQ ,Wakeup - . - ." "False,True" bitfld.long 0x00 3. " VIRTUAL_CHANNEL3_IRQ ,Virtual channel 3 - . - ." "False,True" textline " " bitfld.long 0x00 2. " VIRTUAL_CHANNEL2_IRQ ,Virtual channel 2 - . - ." "False,True" bitfld.long 0x00 1. " VIRTUAL_CHANNEL1_IRQ ,Virtual channel 1 - . - ." "False,True" bitfld.long 0x00 0. " VIRTUAL_CHANNEL0_IRQ ,Virtual channel 0 - . - ." "False,True" group.long 0x1C++0x3 line.long 0x00 "DSI_IRQENABLE,INTERRUPT ENABLE REGISTER - This register associates one bit for each virtual channel in order to enable/disable each virtual channel individually." bitfld.long 0x00 22. " TE1_LINE_IRQ_EN ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE1 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . - ." "Disable,Enable" bitfld.long 0x00 21. " TE0_LINE_IRQ_EN ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE0 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . -.." "Disable,Enable" bitfld.long 0x00 20. " TA_TO_IRQ_EN ,Turn-around Time out. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 18. " SYNC_LOST_IRQ_EN ,Synchronization with Video port is lost (Video mode only) - . - ." "Disable,Enable" bitfld.long 0x00 17. " ACK_TRIGGER_IRQ_EN ,Acknowledge trigger - . - ." "Disable,Enable" bitfld.long 0x00 16. " TE_TRIGGER_IRQ_EN ,Tearing Effect trigger - . - ." "Disable,Enable" textline " " bitfld.long 0x00 15. " LP_RX_TO_IRQ_EN ,Interrupt for Low Power Rx Time out. - . - ." "Disable,Enable" bitfld.long 0x00 14. " HS_TX_TO_IRQ_EN ,Interrupt for High Speed Tx Time out. - . - ." "Disable,Enable" bitfld.long 0x00 9. " PLL_RECAL_IRQ_EN ,PLL recal event (assertion of DSIRecal signal from the DSI PLL Control module) - . - ." "Disable,Enable" textline " " bitfld.long 0x00 8. " PLL_UNLOCK_IRQ_EN ,PLL un-clock event (de-assertion of DSILock signal from the DSI PLL Control module) - . - ." "Disable,Enable" bitfld.long 0x00 7. " PLL_LOCK_IRQ_EN ,PLL clock event (assertion of DSILock signal from the DSI PLL Control module) - . - ." "Disable,Enable" bitfld.long 0x00 5. " RESYNCHRONIZATION_IRQ_EN ,Video mode resynchronization - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " WAKEUP_IRQ_EN ,Wakeup - . - ." "Disable,Enable" group.long 0x40++0x3 line.long 0x00 "DSI_CTRL,GLOBAL CONTROL REGISTER This register controls the DSI Protocol Engine module. This register shall not be modified dynamically (except IF_EN bit fields)." bitfld.long 0x00 24. " DISPC_UPDATE_SYNC ,Determines if the Dispc_Update_Sync signal from the display controller is used. - . - ." "Disable,Enable" bitfld.long 0x00 23. " HSA_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" bitfld.long 0x00 22. " HBP_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" textline " " bitfld.long 0x00 21. " HFP_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" bitfld.long 0x00 20. " BLANKING_MODE ,Blanking mode - . - ." "LPS,HS" bitfld.long 0x00 19. " EOT_ENABLE ,Enable EOT packets at the end of HS transmission. - . - ." "EOT_OFF,EOT_ON" textline " " bitfld.long 0x00 18. " VP_HSYNC_END ,HSYNC end pulse. - . - ." "Disable,Enable" bitfld.long 0x00 17. " VP_HSYNC_START ,HSYNC start pulse. - . - ." "Disable,Enable" bitfld.long 0x00 16. " VP_VSYNC_END ,VSYNC end pulse. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 15. " VP_VSYNC_START ,VSYNC start pulse. - . - ." "Disable,Enable" bitfld.long 0x00 14. " TRIGGER_RESET_MODE ,Selection of the trigger reset mode - . - ." "Synchronized,Immediate" bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port. The valid values are from 0 toDSI_GNQ[17:16] VP1_NB_LINE_BUFFER. - . - . - ." "f0,f1,f2,3" textline " " bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity - . - ." "Low,High" textline " " bitfld.long 0x00 8. " VP_CLK_POL ,VP pixel clock polarity - . - ." "Falling,Rising" bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus - . - . - ." "f16,f18,f24,3" bitfld.long 0x00 5. " TRIGGER_RESET ,Send the reset trigger to the peripheral. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP_CLK and VP_PCLK. The clock VP_PCLK is generated from VP_CLK. It is divided down. The information is only used when the video port is used to provide data in command mode. In the.." "RATIO2,RATIO3ANDHIGHER" bitfld.long 0x00 3. " TX_FIFO_ARBITRATION ,Defines the arbitration scheme for granting the virtual channel pending ready requests in the TX FIFO - . - ." "RoundRobin,Sequential" bitfld.long 0x00 2. " ECC_RX_EN ,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " CS_RX_EN ,Enables the checksum check for the received payload (long packet only for all virtual channel ids). - . - ." "Disable,Enable" bitfld.long 0x00 0. " IF_EN ,Enables the module. When the module is disabled the signals from the complex I/O are gated (no updates of the interrupt status register). It is not possible to change the bit fields in the register DSI_CTRL .." "Disable,Enable" rgroup.long 0x44++0x3 line.long 0x00 "DSI_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design." bitfld.long 0x00 24. " NB_VIDEO_PORTS ,Number of video ports - . - ." "Single_VP,Dual_VP" bitfld.long 0x00 22.--23. " VP2_NB_LINE_BUFFER ,Determines the number of video buffer lines associated to video port 2. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 18.--20. " VP2_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 2 . - . - . - . - . - . - ." "0,f1,f2,f3,f4,f5,f6,7" textline " " bitfld.long 0x00 16.--17. " VP1_NB_LINE_BUFFER ,Determines the number of video buffer lines associated to video port 1. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 12.--14. " VP1_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 1 . - . - . - . - . - . - ." "0,f1,f2,f3,f4,f5,f6,7" bitfld.long 0x00 9.--11. " NB_DATA_LANES ,Determines the number of data lanes supported by the DSI protocol engine . - . - . - . - ." "0,f1,f2,f3,f4,5,6,7" textline " " bitfld.long 0x00 6.--8. " NB_DMA_REQUEST ,Determines the number of DMA_REQ signals. - . - . - . - . - ." "f0,f1,f2,f3,f4,5,6,7" bitfld.long 0x00 3.--5. " RX_FIFODEPTH ,Determines the data RX FIFO depth (32-bit words) on the slave port. - . - . - . - ." "0,1,2,3,f32,f64,f128,f256" bitfld.long 0x00 0.--2. " TX_FIFODEPTH ,Determines the data TX FIFO depth (33-bit words) on the slave port. - . - . - . - ." "0,1,2,3,f32,f64,f128,f256" group.long 0x48++0x3 line.long 0x00 "DSI_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in add.." bitfld.long 0x00 31. " SHADOWING ,Shadowing configuration. - . - ." "Disable,Enable" bitfld.long 0x00 30. " GOBIT ,Allows the synchronized update of the shadow registers when the signal DISPCUpdateSync is active. - . - ." "Reset,Set" bitfld.long 0x00 29. " RESET_DONE ,Internal reset monitoring of the power domain using the TXBYTECLKHS clock from the complex I/O - . - ." "ResetOngoing,ResetCompleted" textline " " bitfld.long 0x00 27.--28. " PWR_CMD ,Command for power control of the complex I/O - . - . - ." "STATE_OFF,STATE_ON,STATE_ULP,3" bitfld.long 0x00 25.--26. " PWR_STATUS ,Status of the power control of the complex I/O - . - . - ." "STATE_OFF,STATE_ON,STATE_ULP,3" bitfld.long 0x00 19. " DATA4_POL ,+/- differential pin order of DATA lane 4. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "PlusMinus,MinusPlus" textline " " bitfld.long 0x00 16.--18. " DATA4_POSITION ,Position and order of the DATA lane 4. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" bitfld.long 0x00 15. " DATA3_POL ,+/- differential pin order of DATA lane 3. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 12.--14. " DATA3_POSITION ,Position and order of the DATA lane 3. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" textline " " bitfld.long 0x00 11. " DATA2_POL ,+/- differential pin order of DATA lane 2. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 8.--10. " DATA2_POSITION ,Position and order of the DATA lane 2. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" bitfld.long 0x00 7. " DATA1_POL ,+/- pin differential pin order of DATA lane 1 - . - ." "PlusMinus,MinusPlus" textline " " bitfld.long 0x00 4.--6. " DATA1_POSITION ,Position and order of the DATA lane 1. The data lane 1 is always present. - . - . - . - . - . - ." "0,Position_1,Position_2,Position_3,Position_4,Position_5,6,7" bitfld.long 0x00 3. " CLOCK_POL ,+/- differential pin order of CLOCK lane. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 0.--2. " CLOCK_POSITION ,Position and order of the CLOCK lane. 0, 5, 6 and 7 are reserved. The clock lane is always present but cannot be at the position 5 even if the COMPLEX I/O consists of 5 lanes. - . - . - . - . - . - . - . - ." "0,Position_1,Position_2,Position_3,Position_4,5,6,7" group.long 0x4C++0x3 line.long 0x00 "DSI_COMPLEXIO_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex I/O" bitfld.long 0x00 31. " ULPSACTIVENOT_ALL1_IRQ ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high. - . - ." "False,True" bitfld.long 0x00 30. " ULPSACTIVENOT_ALL0_IRQ ,All signals ULPSActiveNOT are 0 - . - ." "False,True" bitfld.long 0x00 29. " ERRCONTENTIONLP1_5_IRQ ,Contention LP1 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 28. " ERRCONTENTIONLP0_5_IRQ ,Contention LP0 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 27. " ERRCONTENTIONLP1_4_IRQ ,Contention LP1 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 26. " ERRCONTENTIONLP0_4_IRQ ,Contention LP0 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 25. " ERRCONTENTIONLP1_3_IRQ ,Contention LP1 error for lane 3 - . - ." "False,True" bitfld.long 0x00 24. " ERRCONTENTIONLP0_3_IRQ ,Contention LP0 error for lane 3 - . - ." "False,True" bitfld.long 0x00 23. " ERRCONTENTIONLP1_2_IRQ ,Contention LP1 error for lane 2 - . - ." "False,True" textline " " bitfld.long 0x00 22. " ERRCONTENTIONLP0_2_IRQ ,Contention LP0 error for lane 2 - . - ." "False,True" bitfld.long 0x00 21. " ERRCONTENTIONLP1_1_IRQ ,Contention LP1 error for lane 1 - . - ." "False,True" bitfld.long 0x00 20. " ERRCONTENTIONLP0_1_IRQ ,Contention LP0 error for lane 1 - . - ." "False,True" textline " " bitfld.long 0x00 19. " STATEULPS5_IRQ ,lane 5 in ULTRALOW-POWER State Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 18. " STATEULPS4_IRQ ,lane 4 in ultralow-power mode Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 17. " STATEULPS3_IRQ ,lane 3 in ULTRALOW-POWER state - . - ." "False,True" textline " " bitfld.long 0x00 16. " STATEULPS2_IRQ ,lane 2 in ULTRALOW-POWER state - . - ." "False,True" bitfld.long 0x00 15. " STATEULPS1_IRQ ,lane 1 in ULTRALOW-POWER state - . - ." "False,True" bitfld.long 0x00 14. " ERRCONTROL5_IRQ ,Control error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 13. " ERRCONTROL4_IRQ ,Control error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 12. " ERRCONTROL3_IRQ ,Control error for lane 3 - . - ." "False,True" bitfld.long 0x00 11. " ERRCONTROL2_IRQ ,Control error for lane 2 - . - ." "False,True" textline " " bitfld.long 0x00 10. " ERRCONTROL1_IRQ ,Control error for lane 1 - . - ." "False,True" bitfld.long 0x00 9. " ERRESC5_IRQ ,Escape entry error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 8. " ERRESC4_IRQ ,Escape entry error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 7. " ERRESC3_IRQ ,Escape entry error for lane 3 - . - ." "False,True" bitfld.long 0x00 6. " ERRESC2_IRQ ,Escape entry error for lane 2 - . - ." "False,True" bitfld.long 0x00 5. " ERRESC1_IRQ ,Escape entry error for lane 1 - . - ." "False,True" textline " " bitfld.long 0x00 4. " ERRSYNCESC5_IRQ ,Low power Data transmission synchronization error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 3. " ERRSYNCESC4_IRQ ,Low power Data transmission synchronization error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 2. " ERRSYNCESC3_IRQ ,Low power Data transmission synchronization error for lane 3 - . - ." "False,True" textline " " bitfld.long 0x00 1. " ERRSYNCESC2_IRQ ,Low power Data transmission synchronization error for lane 2 - . - ." "False,True" bitfld.long 0x00 0. " ERRSYNCESC1_IRQ ,Low power Data transmission synchronization error for lane 1 - . - ." "False,True" group.long 0x50++0x3 line.long 0x00 "DSI_COMPLEXIO_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex I/O" bitfld.long 0x00 31. " ULPSACTIVENOT_ALL1_IRQ_EN ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high. - . - ." "Disable,Enable" bitfld.long 0x00 30. " ULPSACTIVENOT_ALL0_IRQ_EN ,All signals ULPSActiveNOT are 0 - . - ." "Disable,Enable" bitfld.long 0x00 29. " ERRCONTENTIONLP1_5_IRQ_EN ,Contention LP1 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " ERRCONTENTIONLP0_5_IRQ_EN ,Contention LP0 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 27. " ERRCONTENTIONLP1_4_IRQ_EN ,Contention LP1 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 26. " ERRCONTENTIONLP0_4_IRQ_EN ,Contention LP0 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 25. " ERRCONTENTIONLP1_3_IRQ_EN ,Contention LP1 error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 24. " ERRCONTENTIONLP0_3_IRQ_EN ,Contention LP0 error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 23. " ERRCONTENTIONLP1_2_IRQ_EN ,Contention LP1 error for lane 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 22. " ERRCONTENTIONLP0_2_IRQ_EN ,Contention LP0 error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 21. " ERRCONTENTIONLP1_1_IRQ_EN ,Contention LP1 error for lane 1 - . - ." "Disable,Enable" bitfld.long 0x00 20. " ERRCONTENTIONLP0_1_IRQ_EN ,Contention LP0 error for lane 1 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 19. " STATEULPS5_IRQ_EN ,lane 5 in ULTRALOW-POWER state Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 18. " STATEULPS4_IRQ_EN ,lane 4 in ULTRALOW-POWER state Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 17. " STATEULPS3_IRQ_EN ,lane 3 in ULTRALOW-POWER state - . - ." "Disable,Enable" textline " " bitfld.long 0x00 16. " STATEULPS2_IRQ_EN ,lane 2 in ULTRALOW-POWER state - . - ." "Disable,Enable" bitfld.long 0x00 15. " STATEULPS1_IRQ_EN ,lane 1 in ULTRALOW-POWER state - . - ." "Disable,Enable" bitfld.long 0x00 14. " ERRCONTROL5_IRQ_EN ,Control error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " ERRCONTROL4_IRQ_EN ,Control error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 12. " ERRCONTROL3_IRQ_EN ,Control error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 11. " ERRCONTROL2_IRQ_EN ,Control error for lane 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 10. " ERRCONTROL1_IRQ_EN ,Control error for lane 1 - . - ." "Disable,Enable" bitfld.long 0x00 9. " ERRESC5_IRQ_EN ,Escape entry error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 8. " ERRESC4_IRQ_EN ,Escape entry error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " ERRESC3_IRQ_EN ,Escape entry error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 6. " ERRESC2_IRQ_EN ,Escape entry error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 5. " ERRESC1_IRQ_EN ,Escape entry error for lane 1 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " ERRSYNCSESC5_IRQ_EN ,Low power Data transmission synchronization error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 3. " ERRSYNCSESC4_IRQ_EN ,Low power Data transmission synchronization error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 2. " ERRSYNCSESC3_IRQ_EN ,Low power Data transmission synchronization error for lane 3 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " ERRSYNCSESC2_IRQ_EN ,Low power Data transmission synchronization error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 0. " ERRSYNCSESC1_IRQ_EN ,Low power Data transmission synchronization error for lane 1 - . - ." "Disable,Enable" group.long 0x54++0x3 line.long 0x00 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION. The register can be modified only when IF_EN is reset." bitfld.long 0x00 30.--31. " PLL_PWR_CMD ,Command for power control of the DSI PLL Control module - . - . - . - ." "STATE_OFF,STATE_ON_HSCLK,STATE_ON_ALL,STATE_ON_DIV" bitfld.long 0x00 28.--29. " PLL_PWR_STATUS ,Status of the power control of the DSI PLL Control module - . - . - . - ." "STATE_OFF,STATE_ON_HSCLK,STATE_ON_ALL,STATE_ON_DIV" bitfld.long 0x00 21. " LP_RX_SYNCHRO_ENABLE ,Defines if the functional is higher or lower than 30 MHz. The information is used to define synchronization to be used for RxValidEsc. - . - ." "LowSpeed,HighSpeed" textline " " bitfld.long 0x00 20. " LP_CLK_ENABLE ,Controls the gating of the TXCLKESC clock. - . - ." "Disable,Enable" bitfld.long 0x00 19. " HS_MANUAL_STOP_CTRL ,In case HS_AUTO_STOP_ENABLE=0, the bit field allows manual control of the assertion/de-assertion of the signal DSIStopClk by the user. - . - ." "Deassertion,Assertion" bitfld.long 0x00 18. " HS_AUTO_STOP_ENABLE ,Enables the automatic assertion/de-assertion of DSIStopClk signal. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 16.--17. " LP_CLK_NULL_PACKET_SIZE ,Indicates the size of LP NULL Packets to be sent automatically when after the last LP packet transfer. It is used by the receiver to drain its internal pipeline. The valid values are from 0 to 3 bytes for the payload size." "0,1,2,3" bitfld.long 0x00 15. " LP_CLK_NULL_PACKET_ENABLE ,Enables the generation of NULL packet in low speed. - . - ." "Disable,Enable" bitfld.long 0x00 14. " CIO_CLK_ICG ,Gates SCPClk clock provided to DSI_PHY and PLL-CTRL module. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " DDR_CLK_ALWAYS_ON ,Defines if the DDR clock is also sent when there is no HS packets sent to the peripheral (low-power mode). So TXRequest for the clock lane is not de-asserted. - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " LP_CLK_DIVISOR ,Defines the ratio to be used for the generation of the low-power mode clock from DSI functional clock. The supported values are from 1 to 8191(the value 0 is invalid). The output frequency shall be in the ra.." group.long 0x58++0x3 line.long 0x00 "DSI_TIMING1,TIMING1 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be modified while [0] IF_EN is set to '1'. It is used to indicate the number of DSI1_CLK and DSI2_CLK functional clocks cycles for the timers F.." bitfld.long 0x00 31. " TA_TO ,Enables the turn-around timer - . - ." "Deassertion,Assertion" bitfld.long 0x00 30. " TA_TO_X16 ,Multiplication factor for the number of DSI_CLK functional clocks cycles defined in TA_TO_COUNTER bit field - . - ." "Disable,Enable" bitfld.long 0x00 29. " TA_TO_X8 ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in TA_TO_COUNTER bit field - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 16.--28. 1. " TA_TO_COUNTER ,Turn around counter. It indicates the number of DSI_CLK function clock to wait for the change of the Direction PPI signal according to the TurnRequest signal The value is from 0 to 8191." bitfld.long 0x00 15. " FORCE_TX_STOP_MODE_IO ,Control of ForceTxStopMode signal - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " STOP_STATE_X16_IO ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit field - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " STOP_STATE_X4_IO ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit field - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " STOP_STATE_COUNTER_IO ,Stop state counter. It indicates the number of DSI_CLK function clock to assert ForceTXStopMode signal. The value is from 0 to 8191." group.long 0x5C++0x3 line.long 0x00 "DSI_TIMING2,TIMING2 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be modified while [0] IF_EN is set to '1'. It is used to indicate the number of DSI_FCLK clock cycles for the timer LP_RX_TIMER and the number .." bitfld.long 0x00 31. " HS_TX_TO ,Enables the HS TX timer. - . - ." "Deassertion,Assertion" bitfld.long 0x00 30. " HS_TX_TO_X64 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit field. BYTE_CLK is a high speed transmit byte clock signal generated by the DSI_PHY. - . - ." "Disable,Enable" bitfld.long 0x00 29. " HS_TX_TO_X16 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 16.--28. 1. " HS_TX_TO_COUNTER ,HS_TX_TIMER counter. It indicates the number of BYTE_CLK function clock for the HS TX timer. The value is from 0 to 8191." bitfld.long 0x00 15. " LP_RX_TO ,Enables the LP RX timer. - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " LP_RX_TO_X16 ,Multiplication factor for the number of DSI_FCLK clock cycles defined in LP_RX_COUNTER bit field - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " LP_RX_TO_X4 ,Multiplication factor for the number of DSI_FCLK clock cycles defined in LP_RX_COUNTER bit - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " LP_RX_TO_COUNTER ,LP_RX_TIMER counter. It indicates the number of DSI_FCLK clock for the LP RX timer. The value is from 0 to 8191." group.long 0x60++0x3 line.long 0x00 "DSI_VM_TIMING1,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 24.--31. 1. " HSA ,Defines the horizontal Sync active period used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 255." hexmask.long.word 0x00 12.--23. 1. " HFP ,Defines the horizontal front porch used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 4095" hexmask.long.word 0x00 0.--11. 1. " HBP ,Defines the horizontal back porch used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 4095" group.long 0x64++0x3 line.long 0x00 "DSI_VM_TIMING2,VIDEO MODE TIMING REGISTER This register defines the video mode timing." bitfld.long 0x00 24.--27. " WINDOW_SYNC ,Number of BYTE clock cycles for the synchronization window. An interrupt for synchronization lost is generated when the received synchornization on video port is not inside the window. DSI does not change its own timings if .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " VSA ,Defines the vertical Sync active period used in video mode in number of lines. The supported values are from 0 to 255 It is used to generate the short packet for End of Vertical synchronization." hexmask.long.byte 0x00 8.--15. 1. " VFP ,Defines the vertical front porch used in video mode in number of lines. The supported values are from 0 to 255" textline " " hexmask.long.byte 0x00 0.--7. 1. " VBP ,Defines the vertical back porch used in video mode in number of lines. The supported values are from 0 to 255" group.long 0x68++0x3 line.long 0x00 "DSI_VM_TIMING3,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.word 0x00 16.--31. 1. " TL ,Defines the number of length of the line in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 8192. The values from 8193 to 65535 are not supported." hexmask.long.word 0x00 0.--15. 1. " VACT ,Defines the number of active lines used in video mode. The supported values are from 0 to 65535" group.long 0x6C++0x3 line.long 0x00 "DSI_CLK_TIMING,CLOCK TIMING REGISTER This register controls the DSI Protocol Engine module timers. This register shall not be modified while .IF_EN is set to '1'." hexmask.long.byte 0x00 8.--15. 1. " DDR_CLK_PRE ,Indicates the number of TXBYTECLKHS clock cycles between the start of the DDR clock and the assertion of the data request signal. The values from 1 to 255 are valid. The value 0 is reserved. The value is not used ifDSI_CLK_C.." hexmask.long.byte 0x00 0.--7. 1. " DDR_CLK_POST ,Indicates the number of TXBYTECLKHS clock cycles after the de-assertion of the data request signal and the stop of the DDR clock. The values from 1 to 255 are valid. The value 0 is reserved. The value i.." group.long 0x70++0x3 line.long 0x00 "DSI_TX_FIFO_VC_SIZE,Defines the corresponding memory entries allocated for each virtual channel. The virtual channel shall be disabled in order to allocate/un-allocate some entries in the TX FIFO." bitfld.long 0x00 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7" group.long 0x74++0x3 line.long 0x00 "DSI_RX_FIFO_VC_SIZE,Defines the corresponding memory entries allocated for each virtual channel and the addresses. The virtual channel shall be disabled in order to allocate/un-allocate some entries in the RX FIFO." bitfld.long 0x00 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7" group.long 0x78++0x3 line.long 0x00 "DSI_COMPLEXIO_CFG2,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the ULPS for each lane." bitfld.long 0x00 17. " LP_BUSY ,Indicates when there are still pending operations for VCs configured for LP mode. Forced to 1 when at least one VC is enabled and configured for LP mode. - . - ." "False,True" bitfld.long 0x00 16. " HS_BUSY ,Indicates when there are still pending operations for VCs configured for HS mode. Forced to 1 when at least one VC is enabled and configured for HS mode. - . - ." "False,True" bitfld.long 0x00 9. " LANE5_ULPS_SIG2 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 5. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pend.." "Inactive,Active" textline " " bitfld.long 0x00 8. " LANE4_ULPS_SIG2 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 4. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI .." "Inactive,Active" bitfld.long 0x00 7. " LANE3_ULPS_SIG2 ,Enables the ULPS for the lane 3. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" bitfld.long 0x00 6. " LANE2_ULPS_SIG2 ,Enables the ULPS for the lane 2. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" textline " " bitfld.long 0x00 5. " LANE1_ULPS_SIG2 ,Enables the ULPS for the lane 1. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine has control of th.." "Inactive,Active" bitfld.long 0x00 4. " LANE5_ULPS_SIG1 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 5. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending.." "Inactive,Active" bitfld.long 0x00 3. " LANE4_ULPS_SIG1 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 4. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending.." "Inactive,Active" textline " " bitfld.long 0x00 2. " LANE3_ULPS_SIG1 ,Enables the ULPS for the lane 3. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine has control of th.." "Inactive,Active" bitfld.long 0x00 1. " LANE2_ULPS_SIG1 ,Enables the ULPS for the lane 2. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" bitfld.long 0x00 0. " LANE1_ULPS_SIG1 ,Enables the ULPS for the lane 1. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" rgroup.long 0x7C++0x3 line.long 0x00 "DSI_RX_FIFO_VC_FULLNESS,Defines the fullness of each space allocated for each virtual channel." hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 3.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 2.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 1.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." textline " " hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 0.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." group.long 0x80++0x3 line.long 0x00 "DSI_VM_TIMING4,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 16.--23. 1. " HSA_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HSA blanking period. The supported values are from 0 to 255." hexmask.long.byte 0x00 8.--15. 1. " HFP_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HFP blanking period. The supported values are from 0 to 255" hexmask.long.byte 0x00 0.--7. 1. " HBP_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HBP blanking period. The supported values are from 0 to 255" rgroup.long 0x84++0x3 line.long 0x00 "DSI_TX_FIFO_VC_EMPTINESS,Defines the emptiness of each space allocated for each virtual channel." hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 3.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 2.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 1.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." textline " " hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 0.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." group.long 0x88++0x3 line.long 0x00 "DSI_VM_TIMING5,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 16.--23. 1. " HSA_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HSA blanking period. The supported values are from 0 to 255." hexmask.long.byte 0x00 8.--15. 1. " HFP_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HFP blanking period. The supported values are from 0 to 255" hexmask.long.byte 0x00 0.--7. 1. " HBP_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HBP blanking period. The supported values are from 0 to 255" group.long 0x8C++0x3 line.long 0x00 "DSI_VM_TIMING6,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.word 0x00 16.--31. 1. " BL_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during blanking periods during VSA, VBP, VFP periods inside one video frame on PPI link. .." hexmask.long.word 0x00 0.--15. 1. " BL_LP_INTERLEAVING ,Defines the maximum number of bytes of Low Power command mode packets that can be sent on PPI link during blanking periods during VSA, VBP or VFP periods inside one video frame on PPI link. The supported .." group.long 0x90++0x3 line.long 0x00 "DSI_VM_TIMING7,Defines the minimum number of HS bytes clock cycles that are required to allow for the delays in entering and exiting HS mode. The supported values are from 0 to 65535" hexmask.long.word 0x00 16.--31. 1. " ENTER_HS_MODE_LATENCY ,Defines the number of TXBYTECLKHS clock cycles necessary for entering to HS mode. It corresponds to the delay in number of HS clock cycles from assertion of TxRequestHS signal to 1 until assertion of TxReadyHS signal to 1. T.." hexmask.long.word 0x00 0.--15. 1. " EXIT_HS_MODE_LATENCY ,Defines the number of TXBYTECLKHS clock cycles necessary for exiting from HS mode. It corresponds to the maximum delay in number of TXBYTECLKHS clock from de-assertion of TxRequestHS signal until PPI link.." group.long 0x94++0x3 line.long 0x00 "DSI_STOPCLK_TIMING,Number of functional clock cycles to wait for TXBYTECLKHS to stop/start after change in DSIStopClk signal" hexmask.long.byte 0x00 0.--7. 1. " DSI_STOPCLK_LATENCY ,Clock gating latency from DSI Protocol to TXBYTECLKHS" group.long 0x98++0x3 line.long 0x00 "DSI_CTRL2,Additional control bits for use with Video Port 2" bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port. The valid values are from 0 toDSI_GNQ[23:22] VP2_NB_LINE_BUFFER. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity - . - ." "Low,High" textline " " bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity - . - ." "Low,High" bitfld.long 0x00 8. " VP_CLK_POL ,VP pixel clock polarity - . - ." "Falling,Rising" bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus - . - . - ." "f16,f18,f24,3" textline " " bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP_CLK and VP_PCLK. The clock VP_PCLK is generated from VP_CLK. It is divided down. The information is only used when the video port is used to provide data in command mode. In the.." "RATIO2,RATIO3ANDHIGHER" group.long 0x9C++0x3 line.long 0x00 "DSI_VM_TIMING8,VIDEO MODE TIMING REGISTER This register defines the video mode timing." bitfld.long 0x00 0.--1. " HFPX ,Extension to the HFP register. Additional bits added to MSB." "0,1,2,3" tree.end tree "DSI2_PROTOCOL_ENGINE_L3" base ad:0x58005000 tree "Channel_0" width 32. group.long 0xA8++0x3 line.long 0x00 "DSI_TE_HSYNC_NUMBER_j_0,The register configures the number of HSYNC to synchronize the beginning of the transfer on DSI link based on the number of HSYNC pulse received on the TE line. The input TE signal is asynchronous and needs to be resynchronizred.." hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number Line number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer. Any HSYNC before VSYNC is ignored." group.long 0xA0++0x3 line.long 0x00 "DSI_TE_HSYNC_WIDTH_j_0,The register configures the TE HSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width Minimum HSYNC pulse width. Number of DSI_CLK clock cycles times 256 to determine when HSYNC pulse occurs. The value 0 is invalid." group.long 0xA4++0x3 line.long 0x00 "DSI_TE_VSYNC_WIDTH_j_0,The register configures the TE VSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width Minimum VSYNC pulse width. Number of DSI_CLK cycles times 256 to determine when VSYNC pulse occurs. The value 0 is invalid. The value shall be greater than MIN_HSYNC_PULSE_WIDTH when DSI_TE_HSY.." group.long 0x100++0x3 line.long 0x00 "DSI_VC_CTRL_i_0,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x11C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_0,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x118++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_0,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x108++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_0,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x10C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_0,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x110++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_0,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x104++0x3 line.long 0x00 "DSI_VC_TE_i_0,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_1" width 32. group.long 0xB4++0x3 line.long 0x00 "DSI_TE_HSYNC_NUMBER_j_1,The register configures the number of HSYNC to synchronize the beginning of the transfer on DSI link based on the number of HSYNC pulse received on the TE line. The input TE signal is asynchronous and needs to be resynchronizred.." hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number Line number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer. Any HSYNC before VSYNC is ignored." group.long 0xAC++0x3 line.long 0x00 "DSI_TE_HSYNC_WIDTH_j_1,The register configures the TE HSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width Minimum HSYNC pulse width. Number of DSI_CLK clock cycles times 256 to determine when HSYNC pulse occurs. The value 0 is invalid." group.long 0xB0++0x3 line.long 0x00 "DSI_TE_VSYNC_WIDTH_j_1,The register configures the TE VSYNC minimum pulse width for TE0 and TE1 CMOS signals The input TE signal is asynchronous and needs to be resynchronizred to DSI_CLK clock domain." hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width Minimum VSYNC pulse width. Number of DSI_CLK cycles times 256 to determine when VSYNC pulse occurs. The value 0 is invalid. The value shall be greater than MIN_HSYNC_PULSE_WIDTH when DSI_TE_HSY.." group.long 0x120++0x3 line.long 0x00 "DSI_VC_CTRL_i_1,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x13C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_1,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x138++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_1,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x128++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_1,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x12C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_1,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x130++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_1,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x124++0x3 line.long 0x00 "DSI_VC_TE_i_1,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_2" width 32. group.long 0x140++0x3 line.long 0x00 "DSI_VC_CTRL_i_2,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x15C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_2,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x158++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_2,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x148++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_2,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x14C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_2,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x150++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_2,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x144++0x3 line.long 0x00 "DSI_VC_TE_i_2,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end tree "Channel_3" width 32. group.long 0x160++0x3 line.long 0x00 "DSI_VC_CTRL_i_3,CONTROL REGISTER - Virtual channel This register controls the virtual channel." bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or Interface slave data when enabled by DCS_CMD_ENABLE (only when TE mechanism is not used otherwise the bit field DCS_CMD_CODE is ignored by DSI protocol engine). -.." "DCS_Continue,DCS_Start" bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port. - . - ." "DCS_Disable,DCS_Enable" bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request (associated to the RX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" textline " " bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the RX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request (associated to the TX FIFO) - . - . - . - . - ." "DMA_REQ0,DMA_REQ1,DMA_REQ2,DMA_REQ3,NO_DMA_REQ,5,6,7" bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request (associated to the TX FIFO) - . - . - . - . - . - ." "f1,f2,f4,f8,f16,f32,6,7" bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status in command mode. Otherwise, this bit can be ignored. - . - ." "Not_Full,Full" bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (packets, BTA) are still being processed. Forced to 1 if VC is enabled. Software should check this bit is 0 before changing channel configuration. - . - ." "Completed,Busy" textline " " bitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status. - . - ." "PP_Free,PP_Busy" bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2. If DSI_GNQ[24] NB_VIDEO_PORTS = 0, the bit field is ignored since only video port 1 is present. - . - . Note: This selection applies only to DSI1. For DSI2 to work properl.." "VIDEO_PORT_1,VIDEO_PORT_2" bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565 - . - ." "RGB565_DBI2,RGB565_Video" textline " " bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the Interface data bus - . - . - . - ." "f16,f24,f1616,f32" bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode. The information is used by hardware only if MODE=COMMAND_MODE otherwise it is ignored. - . - ." "LP,HS" bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header (short and long packets). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload (long packet only). - . - ." "Disable,Enable" bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral. It can be used when the automatic mode is enabled (BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that case only one BTA is sent to the peripheral. The manual mode is used to allow t.." "Disable,Enable" bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status - . - ." "Empty,Not_Empty" textline " " bitfld.long 0x00 4. " MODE ,Selection of the mode - . - ." "COMMAND_MODE,VIDEO_MODE" bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission. - . - ." "Disable,Enable" bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " SOURCE ,Selection of the source between Interface and the Video port(s) (used by the hardware only if MODE=COMMAND MODE (0x0) otherwise it is ignored). The number of available video ports is defined in DSI_GNQ[24] NB_VIDEO_PORTS bit. - .." "OCP_SLAVE_PORT,VIDEO_PORT" bitfld.long 0x00 0. " VC_EN ,Enables the virtual channel. - . - ." "Disable,Enable" group.long 0x17C++0x3 line.long 0x00 "DSI_VC_IRQENABLE_i_3,INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video Port ping-pong buffer busy status. - . - ." "Disable,Enable" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow enable. The FIFO used for buffering the data received on the L3 interface slave port for the virtual channel has underflowed which means that the data for the current packet have not been received in time .." "Disable,Enable" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel -Bus turn around reception - . - ." "Disable,Enable" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "Disable,Enable" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow enable. The FIFO used on the L3 interconnect slave port for buffering the data received on the Interface slave port for the virtual channel has overflowed. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "Disable,Enable" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to correct the only 1-bit error (short and long packet). - . - ." "Disable,Enable" bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - checksum of the payload mismatch detection - . - ." "Disable,Enable" group.long 0x178++0x3 line.long 0x00 "DSI_VC_IRQSTATUS_i_3,INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the virtual channel." bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video Port ping-pong buffer busy status. PP_BUSY has changed from 1 to 0. - . - ." "False,True" bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has underflowed which means that the data for the current packet have not been received in time sinc.." "False,True" bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. - . - ." "False,True" textline " " bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status. - . - ." "False,True" bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data received on the DSI link for the virtual channel has overflowed. - . - ." "False,True" bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status. The FIFO used on the L3 interconnect slave port for buffering the data for the virtual channel has overflowed. - . - ." "False,True" textline " " bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent. It is used when BTA manual mode is used. - . - ." "False,True" bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status (short and long packet). - . - ." "False,True" bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - checksum mismatch status. - . - ." "False,True" wgroup.long 0x168++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_HEADER_i_3,LONG PACKET HEADER INFORMATION -Virtual channel This register sets the 32-bit DATA_ID + Word count + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. DATA_ID is loca.." hexmask.long 0x00 0.--31. 1. " HEADER ,Packet header information: DATA ID + WORD COUNT +ECC" wgroup.long 0x16C++0x3 line.long 0x00 "DSI_VC_LONG_PACKET_PAYLOAD_i_3,LONG PACKET PAYLOAD INFORMATION -Virtual channel This register sets the payload information (excluding checksum). The hardware shall capture the word count in the packet header (in DSI_VC_LONG_PACKET_HEADER) in order to d.." hexmask.long 0x00 0.--31. 1. " PAYLOAD ,Packet payload information (excluding checksum)" group.long 0x170++0x3 line.long 0x00 "DSI_VC_SHORT_PACKET_HEADER_i_3,SHORT PACKET HEADER INFORMATION -Virtual channel This register sets the 24-bit DATA_ID + Short Packet Data Field + ECC (the virtual channel id can be different than VC). The ECC will be computed if ECC_TX_EN is set to 1. .." hexmask.long 0x00 0.--31. 1. " HEADER ,WRITES: Packet header information: DATA ID + DATA FIELD +ECC written into the TX FIFO READS: 32-bit values read from the RX FIFO" group.long 0x164++0x3 line.long 0x00 "DSI_VC_TE_i_3,CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size of the transfer when TE occurs and enables the automatic TE mode." bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer. The user can use the TE interrupt in order to know that the TE trigger has been received prior to set the TE_START bit field. It is not mandatory to use the TE interrupt. - . - ." "Disable,Enable" bitfld.long 0x00 30. " TE_EN ,Tearing Effect Control - . - ." "Disable,Enable" bitfld.long 0x00 29. " TE_LINE ,- . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 CMOS signals. - . - ." "TE0,TE1" hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte (payload data excluding the check -sum) to be sent. The write into the registerDSI_VC_LONG_PACKET_HEADER_i shall be performed by the user before sending data from the register DSI_VC_LONG_P.." tree.end textline "" width 26. rgroup.long 0x0++0x3 line.long 0x00 "DSI_REVISION,IP Revision" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "DSI_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period - . - . - . - ." "OCPFuncOff,FuncOff,OCPOff,OCPFuncOn" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, Idle req/ack control - . - . - . - ." "fIdle,nIdle,sIdle,Res" bitfld.long 0x00 2. " ENWAKEUP ,Wake-up mode enable bit - . - ." "WakeUpDis,WakeUpEnb" textline " " bitfld.long 0x00 1. " SOFT_RESET ,Software reset. Set the bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads return 0. - . - ." "Normal,Reset" bitfld.long 0x00 0. " AUTO_IDLE ,Internal interface gating strategy - . - ." "Free,Gated" rgroup.long 0x14++0x3 line.long 0x00 "DSI_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module, excluding the interrupt status register." bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring - . - ." "ResetOngoing,ResetCompleted" group.long 0x18++0x3 line.long 0x00 "DSI_IRQSTATUS,INTERRUPT STATUS REGISTER - All virtual channels + Complex I/O + PLL This register associates one bit for each virtual channel in order to determine which virtual channel has generated the interrupt. The virtual channel shall be enabled f.." bitfld.long 0x00 22. " TE1_LINE_IRQ ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE1 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . - ." "False,True" bitfld.long 0x00 21. " TE0_LINE_IRQ ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE0 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - ..." "False,True" bitfld.long 0x00 20. " TA_TO_IRQ ,Turn-around Time out. - . - ." "False,True" textline " " bitfld.long 0x00 18. " SYNC_LOST_IRQ ,Synchronization with Video port is lost (Video mode only) - . - ." "False,True" bitfld.long 0x00 17. " ACK_TRIGGER_IRQ ,Acknowledge Trigger - . - ." "False,True" bitfld.long 0x00 16. " TE_TRIGGER_IRQ ,Tearing Effect Trigger - . - ." "False,True" textline " " bitfld.long 0x00 15. " LP_RX_TO_IRQ ,Interrupt for Low Power Rx Time out - . - ." "False,True" bitfld.long 0x00 14. " HS_TX_TO_IRQ ,Interrupt for High Speed Tx Time out. - . - ." "False,True" bitfld.long 0x00 10. " COMPLEXIO_ERR_IRQ ,Error signaling from Complex I/O: status of the complex I/O errors received from the complex I/O (events are defined inDSI_COMPLEXIO_IRQSTATUS). - . - ." "False,True" textline " " bitfld.long 0x00 9. " PLL_RECAL_IRQ ,PLL recal event (assertion of DSIRecal signal from the DSI PLL Control module) - . - ." "False,True" bitfld.long 0x00 8. " PLL_UNLOCK_IRQ ,PLL un-clock event (de-assertion of DSILock signal from the DSI PLL Control module) - . - ." "False,True" bitfld.long 0x00 7. " PLL_LOCK_IRQ ,PLL clock event (assertion of DSILock signal from the DSI PLL Control module) - . - ." "False,True" textline " " bitfld.long 0x00 5. " RESYNCHRONIZATION_IRQ ,Video mode resynchronization indicates to the software users that the video port works but the configuration of the timings for the display controller (DISPC) and for DSI Protocol engine may need to be modified to avoid the .." "False,True" bitfld.long 0x00 4. " WAKEUP_IRQ ,Wakeup - . - ." "False,True" bitfld.long 0x00 3. " VIRTUAL_CHANNEL3_IRQ ,Virtual channel 3 - . - ." "False,True" textline " " bitfld.long 0x00 2. " VIRTUAL_CHANNEL2_IRQ ,Virtual channel 2 - . - ." "False,True" bitfld.long 0x00 1. " VIRTUAL_CHANNEL1_IRQ ,Virtual channel 1 - . - ." "False,True" bitfld.long 0x00 0. " VIRTUAL_CHANNEL0_IRQ ,Virtual channel 0 - . - ." "False,True" group.long 0x1C++0x3 line.long 0x00 "DSI_IRQENABLE,INTERRUPT ENABLE REGISTER - This register associates one bit for each virtual channel in order to enable/disable each virtual channel individually." bitfld.long 0x00 22. " TE1_LINE_IRQ_EN ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE1 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . - ." "Disable,Enable" bitfld.long 0x00 21. " TE0_LINE_IRQ_EN ,The VSYNC and corresponding HSYNC pulses defined in DSI_TE_HSYNC_NUMBER for the line TE0 have been received by the DSI protocol engine and have trigger the start of the data transfer to the peripheral. - . -.." "Disable,Enable" bitfld.long 0x00 20. " TA_TO_IRQ_EN ,Turn-around Time out. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 18. " SYNC_LOST_IRQ_EN ,Synchronization with Video port is lost (Video mode only) - . - ." "Disable,Enable" bitfld.long 0x00 17. " ACK_TRIGGER_IRQ_EN ,Acknowledge trigger - . - ." "Disable,Enable" bitfld.long 0x00 16. " TE_TRIGGER_IRQ_EN ,Tearing Effect trigger - . - ." "Disable,Enable" textline " " bitfld.long 0x00 15. " LP_RX_TO_IRQ_EN ,Interrupt for Low Power Rx Time out. - . - ." "Disable,Enable" bitfld.long 0x00 14. " HS_TX_TO_IRQ_EN ,Interrupt for High Speed Tx Time out. - . - ." "Disable,Enable" bitfld.long 0x00 9. " PLL_RECAL_IRQ_EN ,PLL recal event (assertion of DSIRecal signal from the DSI PLL Control module) - . - ." "Disable,Enable" textline " " bitfld.long 0x00 8. " PLL_UNLOCK_IRQ_EN ,PLL un-clock event (de-assertion of DSILock signal from the DSI PLL Control module) - . - ." "Disable,Enable" bitfld.long 0x00 7. " PLL_LOCK_IRQ_EN ,PLL clock event (assertion of DSILock signal from the DSI PLL Control module) - . - ." "Disable,Enable" bitfld.long 0x00 5. " RESYNCHRONIZATION_IRQ_EN ,Video mode resynchronization - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " WAKEUP_IRQ_EN ,Wakeup - . - ." "Disable,Enable" group.long 0x40++0x3 line.long 0x00 "DSI_CTRL,GLOBAL CONTROL REGISTER This register controls the DSI Protocol Engine module. This register shall not be modified dynamically (except IF_EN bit fields)." bitfld.long 0x00 24. " DISPC_UPDATE_SYNC ,Determines if the Dispc_Update_Sync signal from the display controller is used. - . - ." "Disable,Enable" bitfld.long 0x00 23. " HSA_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" bitfld.long 0x00 22. " HBP_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" textline " " bitfld.long 0x00 21. " HFP_BLANKING_MODE ,Blanking mode - . - ." "COMMAND_PACKET_TX_FIFO,HS_BLANKING_PACKET_ONLY" bitfld.long 0x00 20. " BLANKING_MODE ,Blanking mode - . - ." "LPS,HS" bitfld.long 0x00 19. " EOT_ENABLE ,Enable EOT packets at the end of HS transmission. - . - ." "EOT_OFF,EOT_ON" textline " " bitfld.long 0x00 18. " VP_HSYNC_END ,HSYNC end pulse. - . - ." "Disable,Enable" bitfld.long 0x00 17. " VP_HSYNC_START ,HSYNC start pulse. - . - ." "Disable,Enable" bitfld.long 0x00 16. " VP_VSYNC_END ,VSYNC end pulse. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 15. " VP_VSYNC_START ,VSYNC start pulse. - . - ." "Disable,Enable" bitfld.long 0x00 14. " TRIGGER_RESET_MODE ,Selection of the trigger reset mode - . - ." "Synchronized,Immediate" bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port. The valid values are from 0 toDSI_GNQ[17:16] VP1_NB_LINE_BUFFER. - . - . - ." "f0,f1,f2,3" textline " " bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity - . - ." "Low,High" textline " " bitfld.long 0x00 8. " VP_CLK_POL ,VP pixel clock polarity - . - ." "Falling,Rising" bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus - . - . - ." "f16,f18,f24,3" bitfld.long 0x00 5. " TRIGGER_RESET ,Send the reset trigger to the peripheral. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP_CLK and VP_PCLK. The clock VP_PCLK is generated from VP_CLK. It is divided down. The information is only used when the video port is used to provide data in command mode. In the.." "RATIO2,RATIO3ANDHIGHER" bitfld.long 0x00 3. " TX_FIFO_ARBITRATION ,Defines the arbitration scheme for granting the virtual channel pending ready requests in the TX FIFO - . - ." "RoundRobin,Sequential" bitfld.long 0x00 2. " ECC_RX_EN ,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids). - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " CS_RX_EN ,Enables the checksum check for the received payload (long packet only for all virtual channel ids). - . - ." "Disable,Enable" bitfld.long 0x00 0. " IF_EN ,Enables the module. When the module is disabled the signals from the complex I/O are gated (no updates of the interrupt status register). It is not possible to change the bit fields in the register DSI_CTRL .." "Disable,Enable" rgroup.long 0x44++0x3 line.long 0x00 "DSI_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design." bitfld.long 0x00 24. " NB_VIDEO_PORTS ,Number of video ports - . - ." "Single_VP,Dual_VP" bitfld.long 0x00 22.--23. " VP2_NB_LINE_BUFFER ,Determines the number of video buffer lines associated to video port 2. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 18.--20. " VP2_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 2 . - . - . - . - . - . - ." "0,f1,f2,f3,f4,f5,f6,7" textline " " bitfld.long 0x00 16.--17. " VP1_NB_LINE_BUFFER ,Determines the number of video buffer lines associated to video port 1. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 12.--14. " VP1_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 1 . - . - . - . - . - . - ." "0,f1,f2,f3,f4,f5,f6,7" bitfld.long 0x00 9.--11. " NB_DATA_LANES ,Determines the number of data lanes supported by the DSI protocol engine . - . - . - . - ." "0,f1,f2,f3,f4,5,6,7" textline " " bitfld.long 0x00 6.--8. " NB_DMA_REQUEST ,Determines the number of DMA_REQ signals. - . - . - . - . - ." "f0,f1,f2,f3,f4,5,6,7" bitfld.long 0x00 3.--5. " RX_FIFODEPTH ,Determines the data RX FIFO depth (32-bit words) on the slave port. - . - . - . - ." "0,1,2,3,f32,f64,f128,f256" bitfld.long 0x00 0.--2. " TX_FIFODEPTH ,Determines the data TX FIFO depth (33-bit words) on the slave port. - . - . - . - ." "0,1,2,3,f32,f64,f128,f256" group.long 0x48++0x3 line.long 0x00 "DSI_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in add.." bitfld.long 0x00 31. " SHADOWING ,Shadowing configuration. - . - ." "Disable,Enable" bitfld.long 0x00 30. " GOBIT ,Allows the synchronized update of the shadow registers when the signal DISPCUpdateSync is active. - . - ." "Reset,Set" bitfld.long 0x00 29. " RESET_DONE ,Internal reset monitoring of the power domain using the TXBYTECLKHS clock from the complex I/O - . - ." "ResetOngoing,ResetCompleted" textline " " bitfld.long 0x00 27.--28. " PWR_CMD ,Command for power control of the complex I/O - . - . - ." "STATE_OFF,STATE_ON,STATE_ULP,3" bitfld.long 0x00 25.--26. " PWR_STATUS ,Status of the power control of the complex I/O - . - . - ." "STATE_OFF,STATE_ON,STATE_ULP,3" bitfld.long 0x00 19. " DATA4_POL ,+/- differential pin order of DATA lane 4. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "PlusMinus,MinusPlus" textline " " bitfld.long 0x00 16.--18. " DATA4_POSITION ,Position and order of the DATA lane 4. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" bitfld.long 0x00 15. " DATA3_POL ,+/- differential pin order of DATA lane 3. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 12.--14. " DATA3_POSITION ,Position and order of the DATA lane 3. Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" textline " " bitfld.long 0x00 11. " DATA2_POL ,+/- differential pin order of DATA lane 2. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 8.--10. " DATA2_POSITION ,Position and order of the DATA lane 2. - . - . - . - . - . - ." "Not_used,Position_1,2,3,4,5,6,7" bitfld.long 0x00 7. " DATA1_POL ,+/- pin differential pin order of DATA lane 1 - . - ." "PlusMinus,MinusPlus" textline " " bitfld.long 0x00 4.--6. " DATA1_POSITION ,Position and order of the DATA lane 1. The data lane 1 is always present. - . - . - . - . - . - ." "0,Position_1,Position_2,Position_3,Position_4,Position_5,6,7" bitfld.long 0x00 3. " CLOCK_POL ,+/- differential pin order of CLOCK lane. - . - ." "PlusMinus,MinusPlus" bitfld.long 0x00 0.--2. " CLOCK_POSITION ,Position and order of the CLOCK lane. 0, 5, 6 and 7 are reserved. The clock lane is always present but cannot be at the position 5 even if the COMPLEX I/O consists of 5 lanes. - . - . - . - . - . - . - . - ." "0,Position_1,Position_2,Position_3,Position_4,5,6,7" group.long 0x4C++0x3 line.long 0x00 "DSI_COMPLEXIO_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex I/O" bitfld.long 0x00 31. " ULPSACTIVENOT_ALL1_IRQ ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high. - . - ." "False,True" bitfld.long 0x00 30. " ULPSACTIVENOT_ALL0_IRQ ,All signals ULPSActiveNOT are 0 - . - ." "False,True" bitfld.long 0x00 29. " ERRCONTENTIONLP1_5_IRQ ,Contention LP1 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 28. " ERRCONTENTIONLP0_5_IRQ ,Contention LP0 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 27. " ERRCONTENTIONLP1_4_IRQ ,Contention LP1 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 26. " ERRCONTENTIONLP0_4_IRQ ,Contention LP0 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 25. " ERRCONTENTIONLP1_3_IRQ ,Contention LP1 error for lane 3 - . - ." "False,True" bitfld.long 0x00 24. " ERRCONTENTIONLP0_3_IRQ ,Contention LP0 error for lane 3 - . - ." "False,True" bitfld.long 0x00 23. " ERRCONTENTIONLP1_2_IRQ ,Contention LP1 error for lane 2 - . - ." "False,True" textline " " bitfld.long 0x00 22. " ERRCONTENTIONLP0_2_IRQ ,Contention LP0 error for lane 2 - . - ." "False,True" bitfld.long 0x00 21. " ERRCONTENTIONLP1_1_IRQ ,Contention LP1 error for lane 1 - . - ." "False,True" bitfld.long 0x00 20. " ERRCONTENTIONLP0_1_IRQ ,Contention LP0 error for lane 1 - . - ." "False,True" textline " " bitfld.long 0x00 19. " STATEULPS5_IRQ ,lane 5 in ULTRALOW-POWER State Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 18. " STATEULPS4_IRQ ,lane 4 in ultralow-power mode Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 17. " STATEULPS3_IRQ ,lane 3 in ULTRALOW-POWER state - . - ." "False,True" textline " " bitfld.long 0x00 16. " STATEULPS2_IRQ ,lane 2 in ULTRALOW-POWER state - . - ." "False,True" bitfld.long 0x00 15. " STATEULPS1_IRQ ,lane 1 in ULTRALOW-POWER state - . - ." "False,True" bitfld.long 0x00 14. " ERRCONTROL5_IRQ ,Control error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 13. " ERRCONTROL4_IRQ ,Control error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 12. " ERRCONTROL3_IRQ ,Control error for lane 3 - . - ." "False,True" bitfld.long 0x00 11. " ERRCONTROL2_IRQ ,Control error for lane 2 - . - ." "False,True" textline " " bitfld.long 0x00 10. " ERRCONTROL1_IRQ ,Control error for lane 1 - . - ." "False,True" bitfld.long 0x00 9. " ERRESC5_IRQ ,Escape entry error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 8. " ERRESC4_IRQ ,Escape entry error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" textline " " bitfld.long 0x00 7. " ERRESC3_IRQ ,Escape entry error for lane 3 - . - ." "False,True" bitfld.long 0x00 6. " ERRESC2_IRQ ,Escape entry error for lane 2 - . - ." "False,True" bitfld.long 0x00 5. " ERRESC1_IRQ ,Escape entry error for lane 1 - . - ." "False,True" textline " " bitfld.long 0x00 4. " ERRSYNCESC5_IRQ ,Low power Data transmission synchronization error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 3. " ERRSYNCESC4_IRQ ,Low power Data transmission synchronization error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "False,True" bitfld.long 0x00 2. " ERRSYNCESC3_IRQ ,Low power Data transmission synchronization error for lane 3 - . - ." "False,True" textline " " bitfld.long 0x00 1. " ERRSYNCESC2_IRQ ,Low power Data transmission synchronization error for lane 2 - . - ." "False,True" bitfld.long 0x00 0. " ERRSYNCESC1_IRQ ,Low power Data transmission synchronization error for lane 1 - . - ." "False,True" group.long 0x50++0x3 line.long 0x00 "DSI_COMPLEXIO_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex I/O" bitfld.long 0x00 31. " ULPSACTIVENOT_ALL1_IRQ_EN ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high. - . - ." "Disable,Enable" bitfld.long 0x00 30. " ULPSACTIVENOT_ALL0_IRQ_EN ,All signals ULPSActiveNOT are 0 - . - ." "Disable,Enable" bitfld.long 0x00 29. " ERRCONTENTIONLP1_5_IRQ_EN ,Contention LP1 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " ERRCONTENTIONLP0_5_IRQ_EN ,Contention LP0 error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 27. " ERRCONTENTIONLP1_4_IRQ_EN ,Contention LP1 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 26. " ERRCONTENTIONLP0_4_IRQ_EN ,Contention LP0 error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 25. " ERRCONTENTIONLP1_3_IRQ_EN ,Contention LP1 error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 24. " ERRCONTENTIONLP0_3_IRQ_EN ,Contention LP0 error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 23. " ERRCONTENTIONLP1_2_IRQ_EN ,Contention LP1 error for lane 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 22. " ERRCONTENTIONLP0_2_IRQ_EN ,Contention LP0 error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 21. " ERRCONTENTIONLP1_1_IRQ_EN ,Contention LP1 error for lane 1 - . - ." "Disable,Enable" bitfld.long 0x00 20. " ERRCONTENTIONLP0_1_IRQ_EN ,Contention LP0 error for lane 1 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 19. " STATEULPS5_IRQ_EN ,lane 5 in ULTRALOW-POWER state Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 18. " STATEULPS4_IRQ_EN ,lane 4 in ULTRALOW-POWER state Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 17. " STATEULPS3_IRQ_EN ,lane 3 in ULTRALOW-POWER state - . - ." "Disable,Enable" textline " " bitfld.long 0x00 16. " STATEULPS2_IRQ_EN ,lane 2 in ULTRALOW-POWER state - . - ." "Disable,Enable" bitfld.long 0x00 15. " STATEULPS1_IRQ_EN ,lane 1 in ULTRALOW-POWER state - . - ." "Disable,Enable" bitfld.long 0x00 14. " ERRCONTROL5_IRQ_EN ,Control error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " ERRCONTROL4_IRQ_EN ,Control error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 12. " ERRCONTROL3_IRQ_EN ,Control error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 11. " ERRCONTROL2_IRQ_EN ,Control error for lane 2 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 10. " ERRCONTROL1_IRQ_EN ,Control error for lane 1 - . - ." "Disable,Enable" bitfld.long 0x00 9. " ERRESC5_IRQ_EN ,Escape entry error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 8. " ERRESC4_IRQ_EN ,Escape entry error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 7. " ERRESC3_IRQ_EN ,Escape entry error for lane 3 - . - ." "Disable,Enable" bitfld.long 0x00 6. " ERRESC2_IRQ_EN ,Escape entry error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 5. " ERRESC1_IRQ_EN ,Escape entry error for lane 1 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 4. " ERRSYNCSESC5_IRQ_EN ,Low power Data transmission synchronization error for lane 5 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 3. " ERRSYNCSESC4_IRQ_EN ,Low power Data transmission synchronization error for lane 4 Applicable only to DS1. For DSI2 this bit field is RESERVED. - . - ." "Disable,Enable" bitfld.long 0x00 2. " ERRSYNCSESC3_IRQ_EN ,Low power Data transmission synchronization error for lane 3 - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " ERRSYNCSESC2_IRQ_EN ,Low power Data transmission synchronization error for lane 2 - . - ." "Disable,Enable" bitfld.long 0x00 0. " ERRSYNCSESC1_IRQ_EN ,Low power Data transmission synchronization error for lane 1 - . - ." "Disable,Enable" group.long 0x54++0x3 line.long 0x00 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION. The register can be modified only when IF_EN is reset." bitfld.long 0x00 30.--31. " PLL_PWR_CMD ,Command for power control of the DSI PLL Control module - . - . - . - ." "STATE_OFF,STATE_ON_HSCLK,STATE_ON_ALL,STATE_ON_DIV" bitfld.long 0x00 28.--29. " PLL_PWR_STATUS ,Status of the power control of the DSI PLL Control module - . - . - . - ." "STATE_OFF,STATE_ON_HSCLK,STATE_ON_ALL,STATE_ON_DIV" bitfld.long 0x00 21. " LP_RX_SYNCHRO_ENABLE ,Defines if the functional is higher or lower than 30 MHz. The information is used to define synchronization to be used for RxValidEsc. - . - ." "LowSpeed,HighSpeed" textline " " bitfld.long 0x00 20. " LP_CLK_ENABLE ,Controls the gating of the TXCLKESC clock. - . - ." "Disable,Enable" bitfld.long 0x00 19. " HS_MANUAL_STOP_CTRL ,In case HS_AUTO_STOP_ENABLE=0, the bit field allows manual control of the assertion/de-assertion of the signal DSIStopClk by the user. - . - ." "Deassertion,Assertion" bitfld.long 0x00 18. " HS_AUTO_STOP_ENABLE ,Enables the automatic assertion/de-assertion of DSIStopClk signal. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 16.--17. " LP_CLK_NULL_PACKET_SIZE ,Indicates the size of LP NULL Packets to be sent automatically when after the last LP packet transfer. It is used by the receiver to drain its internal pipeline. The valid values are from 0 to 3 bytes for the payload size." "0,1,2,3" bitfld.long 0x00 15. " LP_CLK_NULL_PACKET_ENABLE ,Enables the generation of NULL packet in low speed. - . - ." "Disable,Enable" bitfld.long 0x00 14. " CIO_CLK_ICG ,Gates SCPClk clock provided to DSI_PHY and PLL-CTRL module. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " DDR_CLK_ALWAYS_ON ,Defines if the DDR clock is also sent when there is no HS packets sent to the peripheral (low-power mode). So TXRequest for the clock lane is not de-asserted. - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " LP_CLK_DIVISOR ,Defines the ratio to be used for the generation of the low-power mode clock from DSI functional clock. The supported values are from 1 to 8191(the value 0 is invalid). The output frequency shall be in the ra.." group.long 0x58++0x3 line.long 0x00 "DSI_TIMING1,TIMING1 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be modified while [0] IF_EN is set to '1'. It is used to indicate the number of DSI1_CLK and DSI2_CLK functional clocks cycles for the timers F.." bitfld.long 0x00 31. " TA_TO ,Enables the turn-around timer - . - ." "Deassertion,Assertion" bitfld.long 0x00 30. " TA_TO_X16 ,Multiplication factor for the number of DSI_CLK functional clocks cycles defined in TA_TO_COUNTER bit field - . - ." "Disable,Enable" bitfld.long 0x00 29. " TA_TO_X8 ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in TA_TO_COUNTER bit field - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 16.--28. 1. " TA_TO_COUNTER ,Turn around counter. It indicates the number of DSI_CLK function clock to wait for the change of the Direction PPI signal according to the TurnRequest signal The value is from 0 to 8191." bitfld.long 0x00 15. " FORCE_TX_STOP_MODE_IO ,Control of ForceTxStopMode signal - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " STOP_STATE_X16_IO ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit field - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " STOP_STATE_X4_IO ,Multiplication factor for the number of DSI_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit field - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " STOP_STATE_COUNTER_IO ,Stop state counter. It indicates the number of DSI_CLK function clock to assert ForceTXStopMode signal. The value is from 0 to 8191." group.long 0x5C++0x3 line.long 0x00 "DSI_TIMING2,TIMING2 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be modified while [0] IF_EN is set to '1'. It is used to indicate the number of DSI_FCLK clock cycles for the timer LP_RX_TIMER and the number .." bitfld.long 0x00 31. " HS_TX_TO ,Enables the HS TX timer. - . - ." "Deassertion,Assertion" bitfld.long 0x00 30. " HS_TX_TO_X64 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit field. BYTE_CLK is a high speed transmit byte clock signal generated by the DSI_PHY. - . - ." "Disable,Enable" bitfld.long 0x00 29. " HS_TX_TO_X16 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit - . - ." "Disable,Enable" textline " " hexmask.long.word 0x00 16.--28. 1. " HS_TX_TO_COUNTER ,HS_TX_TIMER counter. It indicates the number of BYTE_CLK function clock for the HS TX timer. The value is from 0 to 8191." bitfld.long 0x00 15. " LP_RX_TO ,Enables the LP RX timer. - . - ." "Deassertion,Assertion" bitfld.long 0x00 14. " LP_RX_TO_X16 ,Multiplication factor for the number of DSI_FCLK clock cycles defined in LP_RX_COUNTER bit field - . - ." "Disable,Enable" textline " " bitfld.long 0x00 13. " LP_RX_TO_X4 ,Multiplication factor for the number of DSI_FCLK clock cycles defined in LP_RX_COUNTER bit - . - ." "Disable,Enable" hexmask.long.word 0x00 0.--12. 1. " LP_RX_TO_COUNTER ,LP_RX_TIMER counter. It indicates the number of DSI_FCLK clock for the LP RX timer. The value is from 0 to 8191." group.long 0x60++0x3 line.long 0x00 "DSI_VM_TIMING1,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 24.--31. 1. " HSA ,Defines the horizontal Sync active period used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 255." hexmask.long.word 0x00 12.--23. 1. " HFP ,Defines the horizontal front porch used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 4095" hexmask.long.word 0x00 0.--11. 1. " HBP ,Defines the horizontal back porch used in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 4095" group.long 0x64++0x3 line.long 0x00 "DSI_VM_TIMING2,VIDEO MODE TIMING REGISTER This register defines the video mode timing." bitfld.long 0x00 24.--27. " WINDOW_SYNC ,Number of BYTE clock cycles for the synchronization window. An interrupt for synchronization lost is generated when the received synchornization on video port is not inside the window. DSI does not change its own timings if .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " VSA ,Defines the vertical Sync active period used in video mode in number of lines. The supported values are from 0 to 255 It is used to generate the short packet for End of Vertical synchronization." hexmask.long.byte 0x00 8.--15. 1. " VFP ,Defines the vertical front porch used in video mode in number of lines. The supported values are from 0 to 255" textline " " hexmask.long.byte 0x00 0.--7. 1. " VBP ,Defines the vertical back porch used in video mode in number of lines. The supported values are from 0 to 255" group.long 0x68++0x3 line.long 0x00 "DSI_VM_TIMING3,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.word 0x00 16.--31. 1. " TL ,Defines the number of length of the line in video mode in number of byte clock cycles (TXBYTECLKHS clock) The supported values are from 0 to 8192. The values from 8193 to 65535 are not supported." hexmask.long.word 0x00 0.--15. 1. " VACT ,Defines the number of active lines used in video mode. The supported values are from 0 to 65535" group.long 0x6C++0x3 line.long 0x00 "DSI_CLK_TIMING,CLOCK TIMING REGISTER This register controls the DSI Protocol Engine module timers. This register shall not be modified while .IF_EN is set to '1'." hexmask.long.byte 0x00 8.--15. 1. " DDR_CLK_PRE ,Indicates the number of TXBYTECLKHS clock cycles between the start of the DDR clock and the assertion of the data request signal. The values from 1 to 255 are valid. The value 0 is reserved. The value is not used ifDSI_CLK_C.." hexmask.long.byte 0x00 0.--7. 1. " DDR_CLK_POST ,Indicates the number of TXBYTECLKHS clock cycles after the de-assertion of the data request signal and the stop of the DDR clock. The values from 1 to 255 are valid. The value 0 is reserved. The value i.." group.long 0x70++0x3 line.long 0x00 "DSI_TX_FIFO_VC_SIZE,Defines the corresponding memory entries allocated for each virtual channel. The virtual channel shall be disabled in order to allocate/un-allocate some entries in the TX FIFO." bitfld.long 0x00 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7" group.long 0x74++0x3 line.long 0x00 "DSI_RX_FIFO_VC_SIZE,Defines the corresponding memory entries allocated for each virtual channel and the addresses. The virtual channel shall be disabled in order to allocate/un-allocate some entries in the RX FIFO." bitfld.long 0x00 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2. For a complete description, refer to," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1. For a complete description, refer to," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0. For a complete description, refer to," "0,1,2,3,4,5,6,7" group.long 0x78++0x3 line.long 0x00 "DSI_COMPLEXIO_CFG2,COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane configuration for the ULPS for each lane." bitfld.long 0x00 17. " LP_BUSY ,Indicates when there are still pending operations for VCs configured for LP mode. Forced to 1 when at least one VC is enabled and configured for LP mode. - . - ." "False,True" bitfld.long 0x00 16. " HS_BUSY ,Indicates when there are still pending operations for VCs configured for HS mode. Forced to 1 when at least one VC is enabled and configured for HS mode. - . - ." "False,True" bitfld.long 0x00 9. " LANE5_ULPS_SIG2 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 5. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pend.." "Inactive,Active" textline " " bitfld.long 0x00 8. " LANE4_ULPS_SIG2 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 4. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI .." "Inactive,Active" bitfld.long 0x00 7. " LANE3_ULPS_SIG2 ,Enables the ULPS for the lane 3. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" bitfld.long 0x00 6. " LANE2_ULPS_SIG2 ,Enables the ULPS for the lane 2. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" textline " " bitfld.long 0x00 5. " LANE1_ULPS_SIG2 ,Enables the ULPS for the lane 1. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine has control of th.." "Inactive,Active" bitfld.long 0x00 4. " LANE5_ULPS_SIG1 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 5. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending.." "Inactive,Active" bitfld.long 0x00 3. " LANE4_ULPS_SIG1 ,Applicable only to DS1. For DSI2 this bit field is RESERVED. Enables the ULPS for the lane 4. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending.." "Inactive,Active" textline " " bitfld.long 0x00 2. " LANE3_ULPS_SIG1 ,Enables the ULPS for the lane 3. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine has control of th.." "Inactive,Active" bitfld.long 0x00 1. " LANE2_ULPS_SIG1 ,Enables the ULPS for the lane 2. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" bitfld.long 0x00 0. " LANE1_ULPS_SIG1 ,Enables the ULPS for the lane 1. The hardware shall change the state of the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine h.." "Inactive,Active" rgroup.long 0x7C++0x3 line.long 0x00 "DSI_RX_FIFO_VC_FULLNESS,Defines the fullness of each space allocated for each virtual channel." hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 3.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 2.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 1.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." textline " " hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 0.The valid values are from 0 toDSI_GNQ[5:3] RX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[5:3] RX_FIFODEPTH x33-bit." group.long 0x80++0x3 line.long 0x00 "DSI_VM_TIMING4,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 16.--23. 1. " HSA_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HSA blanking period. The supported values are from 0 to 255." hexmask.long.byte 0x00 8.--15. 1. " HFP_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HFP blanking period. The supported values are from 0 to 255" hexmask.long.byte 0x00 0.--7. 1. " HBP_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during HBP blanking period. The supported values are from 0 to 255" rgroup.long 0x84++0x3 line.long 0x00 "DSI_TX_FIFO_VC_EMPTINESS,Defines the emptiness of each space allocated for each virtual channel." hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 3.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 2.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 1.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." textline " " hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 0.The valid values are from 0 toDSI_GNQ[2:0] TX_FIFODEPTH-1 corresponding to 1x33-bit,...up to DSI_GNQ[2:0] TX_FIFODEPTH x33-bit." group.long 0x88++0x3 line.long 0x00 "DSI_VM_TIMING5,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.byte 0x00 16.--23. 1. " HSA_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HSA blanking period. The supported values are from 0 to 255." hexmask.long.byte 0x00 8.--15. 1. " HFP_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HFP blanking period. The supported values are from 0 to 255" hexmask.long.byte 0x00 0.--7. 1. " HBP_LP_INTERLEAVING ,Defines the number of bytes of Low Power command mode packets that can be sent on PPI link during HBP blanking period. The supported values are from 0 to 255" group.long 0x8C++0x3 line.long 0x00 "DSI_VM_TIMING6,VIDEO MODE TIMING REGISTER This register defines the video mode timing." hexmask.long.word 0x00 16.--31. 1. " BL_HS_INTERLEAVING ,Defines the number of TXBYTECLKHS clock cycles that can be used for interleaving High Speed command mode packet into Video Mode stream during blanking periods during VSA, VBP, VFP periods inside one video frame on PPI link. .." hexmask.long.word 0x00 0.--15. 1. " BL_LP_INTERLEAVING ,Defines the maximum number of bytes of Low Power command mode packets that can be sent on PPI link during blanking periods during VSA, VBP or VFP periods inside one video frame on PPI link. The supported .." group.long 0x90++0x3 line.long 0x00 "DSI_VM_TIMING7,Defines the minimum number of HS bytes clock cycles that are required to allow for the delays in entering and exiting HS mode. The supported values are from 0 to 65535" hexmask.long.word 0x00 16.--31. 1. " ENTER_HS_MODE_LATENCY ,Defines the number of TXBYTECLKHS clock cycles necessary for entering to HS mode. It corresponds to the delay in number of HS clock cycles from assertion of TxRequestHS signal to 1 until assertion of TxReadyHS signal to 1. T.." hexmask.long.word 0x00 0.--15. 1. " EXIT_HS_MODE_LATENCY ,Defines the number of TXBYTECLKHS clock cycles necessary for exiting from HS mode. It corresponds to the maximum delay in number of TXBYTECLKHS clock from de-assertion of TxRequestHS signal until PPI link.." group.long 0x94++0x3 line.long 0x00 "DSI_STOPCLK_TIMING,Number of functional clock cycles to wait for TXBYTECLKHS to stop/start after change in DSIStopClk signal" hexmask.long.byte 0x00 0.--7. 1. " DSI_STOPCLK_LATENCY ,Clock gating latency from DSI Protocol to TXBYTECLKHS" group.long 0x98++0x3 line.long 0x00 "DSI_CTRL2,Additional control bits for use with Video Port 2" bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port. The valid values are from 0 toDSI_GNQ[23:22] VP2_NB_LINE_BUFFER. - . - . - ." "f0,f1,f2,3" bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity - . - ." "Low,High" bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity - . - ." "Low,High" textline " " bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity - . - ." "Low,High" bitfld.long 0x00 8. " VP_CLK_POL ,VP pixel clock polarity - . - ." "Falling,Rising" bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus - . - . - ." "f16,f18,f24,3" textline " " bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP_CLK and VP_PCLK. The clock VP_PCLK is generated from VP_CLK. It is divided down. The information is only used when the video port is used to provide data in command mode. In the.." "RATIO2,RATIO3ANDHIGHER" group.long 0x9C++0x3 line.long 0x00 "DSI_VM_TIMING8,VIDEO MODE TIMING REGISTER This register defines the video mode timing." bitfld.long 0x00 0.--1. " HFPX ,Extension to the HFP register. Additional bits added to MSB." "0,1,2,3" tree.end tree.end tree.end tree.open "Remote_Frame_Buffer_Interface" tree.open "RFBI_L4_PER" tree "RFBI_L4_PER" base ad:0x48042000 tree "Channel_0" width 20. group.long 0x6C++0x3 line.long 0x00 "RFBI_DATA_CYCLEi_0,The control register configures the RFBI data format for ith cycle (i = 1 for firstcycle, i = 2 for second cycle, i = 3 for thrid cycle)." bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x70++0x3 line.long 0x00 "RFBI_DATA_CYCLEi_1,The control register configures the RFBI data format for ith cycle (i = 1 for firstcycle, i = 2 for second cycle, i = 3 for thrid cycle)." bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x74++0x3 line.long 0x00 "RFBI_DATA_CYCLEi_2,The control register configures the RFBI data format for ith cycle (i = 1 for firstcycle, i = 2 for second cycle, i = 3 for thrid cycle)." bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end textline "" width 18. rgroup.long 0x0++0x3 line.long 0x00 "RFBI_REVISION,This register contains the IP revision." hexmask.long 0x00 0.--31. 1. " REVISON ,IP revision" group.long 0x10++0x3 line.long 0x00 "RFBI_SYSCONFIG,This register controls various parameters of the slave port interface." bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, Idle req/ack control. - . - . - ." "ForceIdle,NoIdle,SmartIdle,3" bitfld.long 0x00 1. " SOFTRESET ,Software reset Sets this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "NormalMode,ResetDone" bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy (RFBI_ICLK clock and DISPC clock) - . - ." "Freerunning,Gating" rgroup.long 0x14++0x3 line.long 0x00 "RFBI_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information." bitfld.long 0x00 9. " BUSYRFBIDATA ,Data are pending to be processed from interconnect FIFO. - . - ." "NothingPending,PendingData" bitfld.long 0x00 8. " BUSY ,Slave port busy status bit - . - ." "NoStall,Stall" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring. It can be used to determine when a hardware reset is completed or when a software reset is completed (software has setRFBI_SYSCONFIG[0] SOFTRESET to 1). - . - ." "ongoing,Completed" group.long 0x40++0x3 line.long 0x00 "RFBI_CONTROL,The register configures the RFBI module." bitfld.long 0x00 8. " SMART_DMA_REQ ,Smart DMA request - . - ." "Disable,Enable" bitfld.long 0x00 7. " DISABLE_DMA_REQ ,Disable DMA request - . - ." "Enable,Disable" bitfld.long 0x00 5.--6. " HIGHTHRESHOLD ,Defines the FIFO high threshold used by hardware to assert DMA request. Used only if data written toRFBI_DATA are sent using system DMA. - . - . - ." "f4x32,f8x32,f16x32,3" textline " " bitfld.long 0x00 4. " ITE ,Internal Trigger - . - ." "Reset,Set" bitfld.long 0x00 2.--3. " CONFIGSELECT ,Select the CS and configuration - . - . - . - ." "NoCSSelected,CS0Selected,CS1Selected,CS0andCSi1Selected" bitfld.long 0x00 1. " RFBIMODE ,RFBI Mode - . - ." "0,1" textline " " bitfld.long 0x00 0. " ENABLE ,Enable/Disable flag - . - ." "Disable,Enable" group.long 0x44++0x3 line.long 0x00 "RFBI_PIXEL_CNT,The register configures the RFBI pixel count value." hexmask.long 0x00 0.--31. 1. " PIXELCNT ,Pixel counter value The software indicates the number of pixels to transfer to the LCD panel frame buffer. The value is set when the module is disabled. During the transfer the hardware decrements the register when a pixel has been.." group.long 0x48++0x3 line.long 0x00 "RFBI_LINE_NUMBER,The register configures the number of lines to synchronize the beginning of the transfer." hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,Programmable line numberLine number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer." wgroup.long 0x4C++0x3 line.long 0x00 "RFBI_CMD,The register configures the RFBI command." hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command Value" wgroup.long 0x50++0x3 line.long 0x00 "RFBI_PARAM,The register configures the RFBI parameter." hexmask.long.byte 0x00 0.--7. 1. " PARAM ,Parameter value" wgroup.long 0x54++0x3 line.long 0x00 "RFBI_DATA,The register configures the RFBI data." hexmask.long 0x00 0.--31. 1. " DATA ,Data value 12/16/18/24/2x16 bit value depending on:DataType [11:0] 12-bit DataType [15:0] 16-bit DataType [17:0] 18-bit DataType [23:0] 24-bit DataType [31:0] 2x16-bit" group.long 0x58++0x3 line.long 0x00 "RFBI_READ,The register configures the RFBI read." hexmask.long.byte 0x00 0.--7. 1. " READ ,Read value" group.long 0x5C++0x3 line.long 0x00 "RFBI_STATUS,The register configures the RFBI status." hexmask.long.byte 0x00 0.--7. 1. " STATUS ,Status value" group.long 0x60++0x3 line.long 0x00 "RFBI_CONFIG,The control register sets the configuration for the LCD 0 and LCD 1." bitfld.long 0x00 21. " HSYNCPOLARITY ,HSYNC polarity - . - ." "HSYNCactivelow,HSYNCactivehigh" bitfld.long 0x00 20. " TE_VSYNC_POLARITY ,TE or VSYNC polarity - . - ." "activelow,activehigh" bitfld.long 0x00 19. " CSPOLARITY ,CS polarity - . - ." "CSactivelow,CSactivehigh" textline " " bitfld.long 0x00 18. " WEPOLARITY ,WE polarity - . - ." "activelow,activehigh" bitfld.long 0x00 17. " REPOLARITY ,RE polarity - . - ." "activelow,activehigh" bitfld.long 0x00 16. " A0POLARITY ,A0 polarity - . - ." "A0activelow,A0activehigh" textline " " bitfld.long 0x00 11.--12. " UNUSEDBITS ,State of unused bits - . - . - ." "lowlevel,highlevel,unchanged,3" bitfld.long 0x00 9.--10. " CYCLEFORMAT ,Cycle format - . - . - . - ." "1cyclefor1pixel,2cyclesfor1pixel,3cyclesfor1pixel,3cyclesfor2pixels" bitfld.long 0x00 7.--8. " PORTFORMAT ,Slave port write access format - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 5.--6. " DATATYPE ,Data type from the DISPC and slave port - . - . - . - ." "12bit,16bit,18bit,24bit" bitfld.long 0x00 4. " TIMEGRANULARITY ,Multiplies signal timing latencies by 2 - . - ." "disabled,enabled" bitfld.long 0x00 2.--3. " TRIGGERMODE ,Trigger mode - . - . - ." "Internal,External,External2,3" textline " " bitfld.long 0x00 0.--1. " PARALLELMODE ,Parallel mode - . - . - . - ." "8bitparalle,9bitparallel,12bitparallel,16bitparallel" group.long 0x64++0x3 line.long 0x00 "RFBI_ONOFF_TIME,The control register configures the RFBI timings for the LCD 0 and LCD 1." bitfld.long 0x00 24.--29. " REOFFTIME ,Read enable deassertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--23. " REONTIME ,Read enable assertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--19. " WEOFFTIME ,Write enable deassertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 10.--13. " WEONTIME ,Write enable assertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--9. " CSOFFTIME ,CS deassertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " CSONTIME ,CS assertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x68++0x3 line.long 0x00 "RFBI_CYCLE_TIME,The control register configures the RFBI timings for the LCD 0 and LCD 1." bitfld.long 0x00 22.--27. " ACCESSTIME ,Access time number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21. " WRENABLE ,Write-to-read pulse width enable (same CS) - . - ." "WRDisable,WREnable" bitfld.long 0x00 20. " WWENABLE ,Write-to-write pulse width enable (same CS) - . - ." "WWDisable,WWEnable" textline " " bitfld.long 0x00 19. " RRENABLE ,Read-to-read pulse width enable (same CS) - . - ." "RRDisable,RREnable" bitfld.long 0x00 18. " RWENABLE ,Read-to-write pulse width enable (same CS):0x0: CSPULSEWIDTH does not apply on Read-to-Write access 0x1: CSPULSEWIDTH applies on Read-to-Write access" "0,1" bitfld.long 0x00 12.--17. " CSPULSEWIDTH ,CS pulse width number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6.--11. " RECYCLETIME ,RE cycle time number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " WECYCLETIME ,WE cycle time number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x90++0x3 line.long 0x00 "RFBI_VSYNC_WIDTH,The register configures the RFBI VSYNC minimum pulse width." hexmask.long.word 0x00 0.--15. 1. " MINVSYNCPULSEWIDTH ,Programmable minimum VSYNC pulse width Minimum VSYNC pulse width from 0 to 65535. Number of RFBI_ICLK clock cycles to determine when VSYNC pulse occurs. The values 0 and 1 are invalid." group.long 0x94++0x3 line.long 0x00 "RFBI_HSYNC_WIDTH,The register configures the RFBI HSYNC minimum pulse width." hexmask.long.word 0x00 0.--15. 1. " MINHSYNCPULSEWIDTH ,Programmable minimum HSYNC pulse width minimum HSYNC pulse width from 0 to 65535. Number of RFBI_ICLK clock cycles to determine when HSYNC pulse occurs.The values 0 and 1 are invalid." tree.end tree "RFBI_L3" base ad:0x58002000 tree "Channel_0" width 20. group.long 0x6C++0x3 line.long 0x00 "RFBI_DATA_CYCLEi_0,The control register configures the RFBI data format for ith cycle (i = 1 for firstcycle, i = 2 for second cycle, i = 3 for thrid cycle)." bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x70++0x3 line.long 0x00 "RFBI_DATA_CYCLEi_1,The control register configures the RFBI data format for ith cycle (i = 1 for firstcycle, i = 2 for second cycle, i = 3 for thrid cycle)." bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x74++0x3 line.long 0x00 "RFBI_DATA_CYCLEi_2,The control register configures the RFBI data format for ith cycle (i = 1 for firstcycle, i = 2 for second cycle, i = 3 for thrid cycle)." bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end textline "" width 18. rgroup.long 0x0++0x3 line.long 0x00 "RFBI_REVISION,This register contains the IP revision." hexmask.long 0x00 0.--31. 1. " REVISON ,IP revision" group.long 0x10++0x3 line.long 0x00 "RFBI_SYSCONFIG,This register controls various parameters of the slave port interface." bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, Idle req/ack control. - . - . - ." "ForceIdle,NoIdle,SmartIdle,3" bitfld.long 0x00 1. " SOFTRESET ,Software reset Sets this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "NormalMode,ResetDone" bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy (RFBI_ICLK clock and DISPC clock) - . - ." "Freerunning,Gating" rgroup.long 0x14++0x3 line.long 0x00 "RFBI_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information." bitfld.long 0x00 9. " BUSYRFBIDATA ,Data are pending to be processed from interconnect FIFO. - . - ." "NothingPending,PendingData" bitfld.long 0x00 8. " BUSY ,Slave port busy status bit - . - ." "NoStall,Stall" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring. It can be used to determine when a hardware reset is completed or when a software reset is completed (software has setRFBI_SYSCONFIG[0] SOFTRESET to 1). - . - ." "ongoing,Completed" group.long 0x40++0x3 line.long 0x00 "RFBI_CONTROL,The register configures the RFBI module." bitfld.long 0x00 8. " SMART_DMA_REQ ,Smart DMA request - . - ." "Disable,Enable" bitfld.long 0x00 7. " DISABLE_DMA_REQ ,Disable DMA request - . - ." "Enable,Disable" bitfld.long 0x00 5.--6. " HIGHTHRESHOLD ,Defines the FIFO high threshold used by hardware to assert DMA request. Used only if data written toRFBI_DATA are sent using system DMA. - . - . - ." "f4x32,f8x32,f16x32,3" textline " " bitfld.long 0x00 4. " ITE ,Internal Trigger - . - ." "Reset,Set" bitfld.long 0x00 2.--3. " CONFIGSELECT ,Select the CS and configuration - . - . - . - ." "NoCSSelected,CS0Selected,CS1Selected,CS0andCSi1Selected" bitfld.long 0x00 1. " RFBIMODE ,RFBI Mode - . - ." "0,1" textline " " bitfld.long 0x00 0. " ENABLE ,Enable/Disable flag - . - ." "Disable,Enable" group.long 0x44++0x3 line.long 0x00 "RFBI_PIXEL_CNT,The register configures the RFBI pixel count value." hexmask.long 0x00 0.--31. 1. " PIXELCNT ,Pixel counter value The software indicates the number of pixels to transfer to the LCD panel frame buffer. The value is set when the module is disabled. During the transfer the hardware decrements the register when a pixel has been.." group.long 0x48++0x3 line.long 0x00 "RFBI_LINE_NUMBER,The register configures the number of lines to synchronize the beginning of the transfer." hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,Programmable line numberLine number from 0 to 2047. Number of HSYNC after the VSYNC occurs before the beginning of the transfer." wgroup.long 0x4C++0x3 line.long 0x00 "RFBI_CMD,The register configures the RFBI command." hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command Value" wgroup.long 0x50++0x3 line.long 0x00 "RFBI_PARAM,The register configures the RFBI parameter." hexmask.long.byte 0x00 0.--7. 1. " PARAM ,Parameter value" wgroup.long 0x54++0x3 line.long 0x00 "RFBI_DATA,The register configures the RFBI data." hexmask.long 0x00 0.--31. 1. " DATA ,Data value 12/16/18/24/2x16 bit value depending on:DataType [11:0] 12-bit DataType [15:0] 16-bit DataType [17:0] 18-bit DataType [23:0] 24-bit DataType [31:0] 2x16-bit" group.long 0x58++0x3 line.long 0x00 "RFBI_READ,The register configures the RFBI read." hexmask.long.byte 0x00 0.--7. 1. " READ ,Read value" group.long 0x5C++0x3 line.long 0x00 "RFBI_STATUS,The register configures the RFBI status." hexmask.long.byte 0x00 0.--7. 1. " STATUS ,Status value" group.long 0x60++0x3 line.long 0x00 "RFBI_CONFIG,The control register sets the configuration for the LCD 0 and LCD 1." bitfld.long 0x00 21. " HSYNCPOLARITY ,HSYNC polarity - . - ." "HSYNCactivelow,HSYNCactivehigh" bitfld.long 0x00 20. " TE_VSYNC_POLARITY ,TE or VSYNC polarity - . - ." "activelow,activehigh" bitfld.long 0x00 19. " CSPOLARITY ,CS polarity - . - ." "CSactivelow,CSactivehigh" textline " " bitfld.long 0x00 18. " WEPOLARITY ,WE polarity - . - ." "activelow,activehigh" bitfld.long 0x00 17. " REPOLARITY ,RE polarity - . - ." "activelow,activehigh" bitfld.long 0x00 16. " A0POLARITY ,A0 polarity - . - ." "A0activelow,A0activehigh" textline " " bitfld.long 0x00 11.--12. " UNUSEDBITS ,State of unused bits - . - . - ." "lowlevel,highlevel,unchanged,3" bitfld.long 0x00 9.--10. " CYCLEFORMAT ,Cycle format - . - . - . - ." "1cyclefor1pixel,2cyclesfor1pixel,3cyclesfor1pixel,3cyclesfor2pixels" bitfld.long 0x00 7.--8. " PORTFORMAT ,Slave port write access format - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 5.--6. " DATATYPE ,Data type from the DISPC and slave port - . - . - . - ." "12bit,16bit,18bit,24bit" bitfld.long 0x00 4. " TIMEGRANULARITY ,Multiplies signal timing latencies by 2 - . - ." "disabled,enabled" bitfld.long 0x00 2.--3. " TRIGGERMODE ,Trigger mode - . - . - ." "Internal,External,External2,3" textline " " bitfld.long 0x00 0.--1. " PARALLELMODE ,Parallel mode - . - . - . - ." "8bitparalle,9bitparallel,12bitparallel,16bitparallel" group.long 0x64++0x3 line.long 0x00 "RFBI_ONOFF_TIME,The control register configures the RFBI timings for the LCD 0 and LCD 1." bitfld.long 0x00 24.--29. " REOFFTIME ,Read enable deassertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--23. " REONTIME ,Read enable assertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--19. " WEOFFTIME ,Write enable deassertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 10.--13. " WEONTIME ,Write enable assertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--9. " CSOFFTIME ,CS deassertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " CSONTIME ,CS assertion time from start access time. Number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x68++0x3 line.long 0x00 "RFBI_CYCLE_TIME,The control register configures the RFBI timings for the LCD 0 and LCD 1." bitfld.long 0x00 22.--27. " ACCESSTIME ,Access time number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21. " WRENABLE ,Write-to-read pulse width enable (same CS) - . - ." "WRDisable,WREnable" bitfld.long 0x00 20. " WWENABLE ,Write-to-write pulse width enable (same CS) - . - ." "WWDisable,WWEnable" textline " " bitfld.long 0x00 19. " RRENABLE ,Read-to-read pulse width enable (same CS) - . - ." "RRDisable,RREnable" bitfld.long 0x00 18. " RWENABLE ,Read-to-write pulse width enable (same CS):0x0: CSPULSEWIDTH does not apply on Read-to-Write access 0x1: CSPULSEWIDTH applies on Read-to-Write access" "0,1" bitfld.long 0x00 12.--17. " CSPULSEWIDTH ,CS pulse width number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6.--11. " RECYCLETIME ,RE cycle time number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " WECYCLETIME ,WE cycle time number of RFBI_ICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x90++0x3 line.long 0x00 "RFBI_VSYNC_WIDTH,The register configures the RFBI VSYNC minimum pulse width." hexmask.long.word 0x00 0.--15. 1. " MINVSYNCPULSEWIDTH ,Programmable minimum VSYNC pulse width Minimum VSYNC pulse width from 0 to 65535. Number of RFBI_ICLK clock cycles to determine when VSYNC pulse occurs. The values 0 and 1 are invalid." group.long 0x94++0x3 line.long 0x00 "RFBI_HSYNC_WIDTH,The register configures the RFBI HSYNC minimum pulse width." hexmask.long.word 0x00 0.--15. 1. " MINHSYNCPULSEWIDTH ,Programmable minimum HSYNC pulse width minimum HSYNC pulse width from 0 to 65535. Number of RFBI_ICLK clock cycles to determine when HSYNC pulse occurs.The values 0 and 1 are invalid." tree.end tree.end tree.end tree.open "Video_Encoder" tree.open "VENC_L4_PER" tree "VENC_L4_PER" base ad:0x48043000 width 39. rgroup.long 0x0++0x3 line.long 0x00 "VENC_REV_ID,Revision ID for the encoder" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "VENC_STATUS,STATUS" bitfld.long 0x00 4. " CCE ,Closed Caption Status for Even Field. This bit is set immediately after the data in registers LINE21_E0 and LINE21_E1 have been encoded to closed caption. This bit is reset when both of these registers are written." "0,1" bitfld.long 0x00 3. " CCO ,Closed Caption Status for Odd Field. This bit is set immediately after the data in registers LINE21_O0 and LINE21_O1 have been encoded to closed caption. This bit is reset when both of these registers are wri.." "0,1" bitfld.long 0x00 0.--2. " FSQ ,Field Sequence ID. For PAL, all three FSQ[2:0] are used whereas for NTSC only FSQ[1:0] is meaningful. Furthermore, FSQ[0] represents ODD field when it is '0' and EVEN field when it is '1'. - . - ." "ODD_field,EVEN_field,2,3,4,5,6,7" group.long 0x8++0x3 line.long 0x00 "VENC_F_CONTROL,This register specifies the input video source and format" bitfld.long 0x00 8. " RESET ,RESET the encoder - . - ." "No_effect,1" bitfld.long 0x00 6.--7. " SVDS ,Select Video Data Source. - . - . - . - ." "0,1,Use_background_color,?..." bitfld.long 0x00 5. " RGBF ,RGB /YCrCb input coding range - . - ." "0,1" textline " " bitfld.long 0x00 2.--4. " BCOLOR ,Background color select - . - . - . - . - . - . - . - ." "UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 0.--1. " FMT ,These two bits specify the video input data stream format and timing - . - . - . - ." "24-bit_4:4:4_RGB,24-bit_4:4:4,16-bit_4:2:2,3" group.long 0x10++0x3 line.long 0x00 "VENC_VIDOUT_CTRL,Encoder output clock" bitfld.long 0x00 0. " MHZ_27_54 ,Encoder output clock - . - ." "0,1" group.long 0x14++0x3 line.long 0x00 "VENC_SYNC_CTRL,SYNC Control register" bitfld.long 0x00 15. " FREE ,Free running - . - ." "Free_running_disabled,1" bitfld.long 0x00 14. " ESAV ,Enable to detect F and V bits only on EAV in ITU-R 656 input mode - . - ." "0,1" bitfld.long 0x00 13. " IGNP ,Ignore protection bits in ITU-R 656 input mode - . - ." "0,1" textline " " bitfld.long 0x00 12. " NBLNKS ,Blank shaping - . - ." "Blank_shaping_enabled,Blank_shaping_disabled" bitfld.long 0x00 10.--11. " VBLKM ,Vertical blanking mode - . - . - . - ." "Internal_default_blanking,1,?..." bitfld.long 0x00 8.--9. " HBLKM ,Horizontal blanking mode - . - . - . - ." "Internal_default_blanking,1,2,?..." textline " " bitfld.long 0x00 7. " M_S ,Encoder is master or slave of external sync - . - ." "0,1" bitfld.long 0x00 6. " FID_POL ,FID output polarity - . - ." "0,1" bitfld.long 0x00 3. " VS_POL ,VS input polarity - . - ." "0,1" textline " " bitfld.long 0x00 2. " HS_POL ,HS input polarity - . - ." "0,1" bitfld.long 0x00 0. " FHVMOD ,FID extracted from external FID or HSYNC and VSYNC - . - ." "External_FID,1" group.long 0x1C++0x3 line.long 0x00 "VENC_LLEN,LLEN" bitfld.long 0x00 15. " LLEN_EN ,LLEN_EN - . - ." "disable,enable" hexmask.long.word 0x00 0.--10. 1. " LLEN ,LLEN[10:0] Line length or total number of pixels in a scan line including active video and blanking. Total number of pixels in a scan line = LLEN NOTE: A write to bit 11 of this bit field is illegal." group.long 0x20++0x3 line.long 0x00 "VENC_FLENS,FLENS" hexmask.long.word 0x00 0.--10. 1. " FLENS ,The frame length or total number of lines in a frame including active video and blanking from the source image. Total number of lines in a frame from the source image = FLENS + 1" group.long 0x24++0x3 line.long 0x00 "VENC_HFLTR_CTRL,HFLTR_CTRL" bitfld.long 0x00 1.--2. " CINTP ,Chrominance interpolation filter control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0. " YINTP ,Luminance interpolation filter control - . - ." "0,1" group.long 0x28++0x3 line.long 0x00 "VENC_CC_CARR_WSS_CARR,Frequencie code control" hexmask.long.word 0x00 16.--31. 1. " FWSS ,Wide screen signaling run-in code frequency control. For 50-Hz systems, FWSS = 2 * 5 * 10/(LLEN * Fh), where LLEN = total number of pixels in a scan line Fh = line frequency." hexmask.long.word 0x00 0.--15. 1. " FCC ,Close caption run-in code frequency control. For 60-Hz system, FCC = 2 * 0.5035 * 10/(LLEN * Fh) For 50-Hz systems, FCC = 2* 0.500 * 10/(LLEN * Fh), where LLEN = total number of pixels in a scan line Fh = line f.." group.long 0x2C++0x3 line.long 0x00 "VENC_C_PHASE,C_PHASE" hexmask.long.byte 0x00 0.--7. 1. " CPHS ,Phase of the encoded video color subcarrier (including the color burst) relative to H-sync. The adjustable step is 360/256 degrees." group.long 0x30++0x3 line.long 0x00 "VENC_GAIN_U,Gain control for Cb signal" hexmask.long.word 0x00 0.--8. 1. " GU ,Gain control for Cb signal. Following are typical programming examples for NTSC and PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GU = 0x102 NTSC with no pedestal: WHITE - BLACK = 100 IRE GU = 0x117 PAL with n.." group.long 0x34++0x3 line.long 0x00 "VENC_GAIN_V,Gain control of Cr signal" hexmask.long.word 0x00 0.--8. 1. " GV ,Gain control of Cr signal. Following are typical programming examples for NTSC and PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GV = 0x16C NTSC with no pedestal: WHITE - BLACK = 100 IRE GV = 0x189 PAL with no.." group.long 0x38++0x3 line.long 0x00 "VENC_GAIN_Y,Gain control of Y signal" hexmask.long.word 0x00 0.--8. 1. " GY ,Gain control of Y signal. Following are typical programming examples for NTSC/PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GY = 0x12F NTSC with no pedestal: WHITE - BLACK = 100 IRE GY = 0x147 PAL with no pede.." group.long 0x3C++0x3 line.long 0x00 "VENC_BLACK_LEVEL,BLACK LEVEL" hexmask.long.byte 0x00 0.--6. 1. " BLACK ,Black level setting. Following are typical programming examples for NTSC/PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE BLACK_LEVEL = 0x43 NTSC with no pedestal: WHITE - BLACK = 100 IRE BLACK_LEVEL = 0x38 PAL w.." group.long 0x40++0x3 line.long 0x00 "VENC_BLANK_LEVEL,BLANK LEVEL" hexmask.long.byte 0x00 0.--6. 1. " BLANK ,Blank level setting. Following are typical programming examples for NTSC/PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE BLANK_LEVEL = 0x38 NTSC with no pedestal: WHITE - BLACK = 100 IRE BLANK_LEVEL = 0x38 PAL w.." group.long 0x44++0x3 line.long 0x00 "VENC_X_COLOR,Cross-Colour Control register" bitfld.long 0x00 6. " XCE ,Cross color reduction enable for composite video output. Cross color does not affect S-video output - . - ." "0,1" bitfld.long 0x00 3.--4. " XCBW ,Cross color reduction filter selection - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--2. " LCD ,These three bits can be used for chroma channel delay compensation. Delay on Luma channel. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x00 "VENC_M_CONTROL,M_CONTROL" bitfld.long 0x00 7. " PALI ,PAL I enable - . - ." "Normal_oeration,PAL_I_Enable" bitfld.long 0x00 6. " PALN ,PAL N Enable - . - ." "Normal_operation,PAL_N_enable" bitfld.long 0x00 5. " PALPHS ,PAL switch phase setting - . - ." "0,1" textline " " bitfld.long 0x00 2.--4. " CBW ,Chrominance lowpass filter bandwidth control - . - . - . - . - . - . - . - ." "0,1,2,Reserved,Reserved,5,6,7" bitfld.long 0x00 1. " PAL ,Phase alternation line encoding selection - . - ." "0,1" bitfld.long 0x00 0. " FFRQ ,The value of this field and the SQP bit in the BSTAMP_WSS_DATA register control the number of horizontal pixels displayed per scan line # OF MODE SQP FFRQ PIXEL PER LINE ITU-R 601 NTSC 0 1 858 Square pixel NTSC 1.." "0,1" group.long 0x4C++0x3 line.long 0x00 "VENC_BSTAMP_WSS_DATA,BSTAMP and WSS_DATA" hexmask.long.tbyte 0x00 8.--27. 1. " WSS_D ,Wide Screen Signaling data NTSC: WORD 0 D0, D1 WORD 1 D2, D3, D4, D5 WORD 2 D6, D7, D8, D9, D10, D11, D12, D13 CRC D14, D15, D16, D17, D18, D19 PAL: GROUP A D0, D1, D2, D3 GROUP B D4, D5, D6, D7 GROUP C D8, D9 ,D10 GROUP D D11, D12.." bitfld.long 0x00 7. " SQP ,Square-pixel sampling rate. See FFRQ in M_CONTROL register for programming information. - . - ." "0,1" hexmask.long.byte 0x00 0.--6. 1. " BSTAP ,Setting of amplitude of color burst." group.long 0x50++0x3 line.long 0x00 "VENC_S_CARR,Color Subcarrier Frequency Registers." hexmask.long 0x00 0.--31. 1. " FSC ,These four bytes' data are used to program color subcarrier frequency. These four bytes are determined by the following formula. S_CARR = ROUND((Fsc/Fclkenc) * 232) Where Fsc = Frequency of the subcarrier Fclkenc = Frequency of the.." group.long 0x54++0x3 line.long 0x00 "VENC_LINE21,LINE 21" hexmask.long.word 0x00 16.--31. 1. " L21E ,The two bytes of the closed caption data in the even field. - For the data stream content, see. . - . [31:24] First byte of data. - . [23:16] Second byte of data. - ." hexmask.long.word 0x00 0.--15. 1. " L21O ,The two bytes of the closed caption data in the odd field - For the data stream content, see. . - . [15:8] First byte of data. - . [7:0] Second byte of data. - ." group.long 0x58++0x3 line.long 0x00 "VENC_LN_SEL,LN_SEL" hexmask.long.word 0x00 16.--25. 1. " LN21_RUNIN ,The two Bytes of the closed caption runin code position from the HSYNC" bitfld.long 0x00 0.--4. " SLINE ,Selects the line where closed caption or extended service data are encoded.PAL mode: Because there is a one-line offset, program the desired line number ? 1.. - . NTSC mode: Because there is a four-line offset, .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x3 line.long 0x00 "VENC_L21_WC_CTL,L21 and WC_CTL registers" bitfld.long 0x00 15. " INV ,WSS inverter - . - ." "no_effect,invert_WSS_data" bitfld.long 0x00 13.--14. " EVEN_ODD_EN ,This bit controls the WSS encoding. - . - . - . - ." "WSS_encoding_OFF,1,2,3" bitfld.long 0x00 8.--12. " LINE ,Selects the line where WSS data are encoded.PAL mode: Because there is a one-line offset, program the desired line number ? 1.. - . NTSC mode: Because there is a four-line offset, program the desired line number ? 4.. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " L21EN ,Those bits controls the Line21 closed caption encoding according to the mode. - . - . - . - ." "Line21_encoding_OFF,1,2,3" group.long 0x60++0x3 line.long 0x00 "VENC_HTRIGGER_VTRIGGER,HTRIGGER and VTRIGGER" hexmask.long.word 0x00 16.--25. 1. " VTRIG ,Vertical trigger reference for VSYNC. These bits specify the phase between VSYNC input and the lines in a field. The VTRIG field is expressed in units of half-line." hexmask.long.word 0x00 0.--10. 1. " HTRIG ,Horizontal trigger phase, which sets HSYNC. HTRIG is expressed in half-pixels or clk2x (27 MHz) periods" group.long 0x64++0x3 line.long 0x00 "VENC_SAVID_EAVID,SAVID and EAVID" hexmask.long.word 0x00 16.--26. 1. " EAVID ,End of active video. These bits define the ending pixel position on a horizontal display line where active video will be displayed." hexmask.long.word 0x00 0.--10. 1. " SAVID ,Start of active video. These bits define the starting pixel position on a horizontal line where active video will be displayed." group.long 0x68++0x3 line.long 0x00 "VENC_FLEN_FAL,FLEN and FAL" hexmask.long.word 0x00 16.--24. 1. " FAL ,First Active Line of Field. These bits define the first active line of a field" hexmask.long.word 0x00 0.--9. 1. " FLEN ,Field length. These bits define the number of half_lines in each field. Length of field = (FLEN + 1) half_lines" group.long 0x6C++0x3 line.long 0x00 "VENC_LAL_PHASE_RESET,LAL and PHASE_RESET" bitfld.long 0x00 17.--18. " PRES ,Phase reset mode. - . - . - . - ." "No_reset,1,2,3" bitfld.long 0x00 16. " SBLANK ,Vertical blanking setting - . - ." "0,1" hexmask.long.word 0x00 0.--8. 1. " LAL ,Last Active Line of Field. These bits define the last active line of a field" group.long 0x70++0x3 line.long 0x00 "VENC_HS_INT_START_STOP_X,HS_INT_START_STOP_X" hexmask.long.word 0x00 16.--25. 1. " HS_INT_STOP_X ,HSYNC internal stop. These bits define HSYNC internal stop pixel value" hexmask.long.word 0x00 0.--9. 1. " HS_INT_START_X ,HSYNC internal start. These bits define HSYNC internal start pixel value" group.long 0x74++0x3 line.long 0x00 "VENC_HS_EXT_START_STOP_X,HS_EXT_START_STOP_X" hexmask.long.word 0x00 16.--25. 1. " HS_EXT_STOP_X ,HSYNC external stop. These bits define HSYNC external stop pixel value" hexmask.long.word 0x00 0.--9. 1. " HS_EXT_START_X ,HSYNC external start. These bits define HSYNC external start pixel value" group.long 0x78++0x3 line.long 0x00 "VENC_VS_INT_START_X,VS_INT_START_X" hexmask.long.word 0x00 16.--25. 1. " VS_INT_START_X ,VSYNC internal start. These bits define VSYNC internal start pixel value." group.long 0x7C++0x3 line.long 0x00 "VENC_VS_INT_STOP_X_VS_INT_START_Y,VS_INT_STOP_X and VS_INT_START_Y" hexmask.long.word 0x00 16.--25. 1. " VS_INT_START_Y ,VSYNC internal start. These bits define VSYNC internal start line value" hexmask.long.word 0x00 0.--9. 1. " VS_INT_STOP_X ,VSYNC internal stop. These bits define VSYNC internal stop pixel value" group.long 0x80++0x3 line.long 0x00 "VENC_VS_INT_STOP_Y_VS_EXT_START_X,VS_INT_STOP_Y and VS_EXT_START_X" hexmask.long.word 0x00 16.--25. 1. " VS_EXT_START_X ,VSYNC external start. These bits define VSYNC external start pixel value." hexmask.long.word 0x00 0.--9. 1. " VS_INT_STOP_Y ,VSYNC internal stop. These bits define VSYNC internal stop line value." group.long 0x84++0x3 line.long 0x00 "VENC_VS_EXT_STOP_X_VS_EXT_START_Y,VS_EXT_STOP_X and VS_EXT_START_Y" hexmask.long.word 0x00 16.--25. 1. " VS_EXT_START_Y ,VSYNC external start. These bits define VSYNC external start line value." hexmask.long.word 0x00 0.--9. 1. " VS_EXT_STOP_X ,VSYNC external stop. These bits define VSYNC external stop pixel value." group.long 0x88++0x3 line.long 0x00 "VENC_VS_EXT_STOP_Y,VS_EXT_STOP_Y" hexmask.long.word 0x00 0.--9. 1. " VS_EXT_STOP_Y ,VSYNC external stop. These bits define VSYNC external stop line value." group.long 0x90++0x3 line.long 0x00 "VENC_AVID_START_STOP_X,AVID_START_STOP_X" hexmask.long.word 0x00 16.--25. 1. " AVID_STOP_X ,AVID stop. These bits define AVID stop pixel value" hexmask.long.word 0x00 0.--9. 1. " AVID_START_X ,AVID start. These bits define AVID start pixel value" group.long 0x94++0x3 line.long 0x00 "VENC_AVID_START_STOP_Y,AVID_START_STOP_Y" hexmask.long.word 0x00 16.--25. 1. " AVID_STOP_Y ,AVID stop. These bits define AVID stop line value." hexmask.long.word 0x00 0.--9. 1. " AVID_START_Y ,AVID start. These bits define AVID start line value" group.long 0xA0++0x3 line.long 0x00 "VENC_FID_INT_START_X_FID_INT_START_Y,FID_INT_START_X and FID_INT_START_Y" hexmask.long.word 0x00 16.--25. 1. " FID_INT_START_Y ,FID internal stop. These bits define FID internal start line value" hexmask.long.word 0x00 0.--9. 1. " FID_INT_START_X ,FID internal start. These bits define FID internal start pixel value" group.long 0xA4++0x3 line.long 0x00 "VENC_FID_INT_OFFSET_Y_FID_EXT_START_X,FID_INT_OFFSET_Y and FID_EXT_START_X" hexmask.long.word 0x00 16.--25. 1. " FID_EXT_START_X ,FID external start. These bits define FID external start pixel value" hexmask.long.word 0x00 0.--9. 1. " FID_INT_OFFSET_Y ,FID internal offset. These bits define FID internal offset linel value" group.long 0xA8++0x3 line.long 0x00 "VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y,FID_EXT_START_Y and FID_EXT_OFFSET_Y" hexmask.long.word 0x00 16.--25. 1. " FID_EXT_OFFSET_Y ,FID external offset. These bits define FID external offset line value" hexmask.long.word 0x00 0.--9. 1. " FID_EXT_START_Y ,FID external start. These bits define FID external start line value." group.long 0xB0++0x3 line.long 0x00 "VENC_TVDETGP_INT_START_STOP_X,TVDETGP_INT_START_STOP_X" hexmask.long.word 0x00 16.--25. 1. " TVDETGP_INT_STOP_X ,TVDETGP internal stop. These bits define TVDETGP internal stop pixel value." hexmask.long.word 0x00 0.--9. 1. " TVDETGP_INT_START_X ,TVDETGP internal start. These bits define TVDETGP internal start pixel value" group.long 0xB4++0x3 line.long 0x00 "VENC_TVDETGP_INT_START_STOP_Y,TVDETGP_INT_START_STOP_Y" hexmask.long.word 0x00 16.--25. 1. " TVDETGP_INT_STOP_Y ,TVDETGP internal stop. These bits define TVDETGP internal stop line value." hexmask.long.word 0x00 0.--9. 1. " TVDETGP_INT_START_Y ,TVDETGP internal start. These bits define TVDETGP internal start line value" group.long 0xB8++0x3 line.long 0x00 "VENC_GEN_CTRL,TVDETGP enable and SYNC_POLARITY and UVPHASE_POL" bitfld.long 0x00 26. " MS ,UVPHASE_POL MS mode UV phase - . - ." "CbCr,CrCb" bitfld.long 0x00 25. " UVPHASE_POL_656 ,UVPHASE_POL 656 input mode UV phase - . - ." "CbCr,CrCb" bitfld.long 0x00 24. " CBAR ,UVPHASE_POL CBAR mode UV phase - . - ." "CbCr,CrCb" textline " " bitfld.long 0x00 23. " HIP ,HSYNC internal polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 22. " VIP ,VSYNC internal polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 21. " HEP ,HSYNC external polarity - . - ." "Active_Low,Active_High" textline " " bitfld.long 0x00 20. " VEP ,VSYNC externall polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 19. " AVIDP ,AVID polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 18. " FIP ,FID internal polarity - . - ." "Active_Low,Active_High" textline " " bitfld.long 0x00 17. " FEP ,FID external polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 16. " TVDP ,TVDETGP polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 0. " EN ,TVDETGP generation enable - . - ." "Disabled,Enabled" group.long 0xC4++0x3 line.long 0x00 "VENC_OUTPUT_CONTROL,Output channel control register Also contains some test control features" bitfld.long 0x00 6. " COMPOSITE_SOURCE ,Source of composite video data in test mode - . - ." "0,1" bitfld.long 0x00 4. " TEST_MODE ,This enables the video DACs to be tested. The values sent to the DACs comes from a register for each output channel (Luma, Composite or Chroma) or from the display controller video port bits G[1:0], B[7:0], d.." "0,1" bitfld.long 0x00 3. " VIDEO_INVERT ,Controls the video output polarity. This may be used to correct for inversion in an external video amplifier. - . - ." "0,1" textline " " bitfld.long 0x00 1. " COMPOSITE_ENABLE ,Enable the Composite output channel - . - ." "0,1" group.long 0xC8++0x3 line.long 0x00 "VENC_OUTPUT_TEST,Test values for the Luma/Composite Video DAC" hexmask.long.word 0x00 0.--9. 1. " COMPOSITE_TEST ,In test mode, DAC input value (if composite video is selected)" tree.end tree "VENC_L3" base ad:0x58003000 width 39. rgroup.long 0x0++0x3 line.long 0x00 "VENC_REV_ID,Revision ID for the encoder" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "VENC_STATUS,STATUS" bitfld.long 0x00 4. " CCE ,Closed Caption Status for Even Field. This bit is set immediately after the data in registers LINE21_E0 and LINE21_E1 have been encoded to closed caption. This bit is reset when both of these registers are written." "0,1" bitfld.long 0x00 3. " CCO ,Closed Caption Status for Odd Field. This bit is set immediately after the data in registers LINE21_O0 and LINE21_O1 have been encoded to closed caption. This bit is reset when both of these registers are wri.." "0,1" bitfld.long 0x00 0.--2. " FSQ ,Field Sequence ID. For PAL, all three FSQ[2:0] are used whereas for NTSC only FSQ[1:0] is meaningful. Furthermore, FSQ[0] represents ODD field when it is '0' and EVEN field when it is '1'. - . - ." "ODD_field,EVEN_field,2,3,4,5,6,7" group.long 0x8++0x3 line.long 0x00 "VENC_F_CONTROL,This register specifies the input video source and format" bitfld.long 0x00 8. " RESET ,RESET the encoder - . - ." "No_effect,1" bitfld.long 0x00 6.--7. " SVDS ,Select Video Data Source. - . - . - . - ." "0,1,Use_background_color,?..." bitfld.long 0x00 5. " RGBF ,RGB /YCrCb input coding range - . - ." "0,1" textline " " bitfld.long 0x00 2.--4. " BCOLOR ,Background color select - . - . - . - . - . - . - . - ." "UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 0.--1. " FMT ,These two bits specify the video input data stream format and timing - . - . - . - ." "24-bit_4:4:4_RGB,24-bit_4:4:4,16-bit_4:2:2,3" group.long 0x10++0x3 line.long 0x00 "VENC_VIDOUT_CTRL,Encoder output clock" bitfld.long 0x00 0. " MHZ_27_54 ,Encoder output clock - . - ." "0,1" group.long 0x14++0x3 line.long 0x00 "VENC_SYNC_CTRL,SYNC Control register" bitfld.long 0x00 15. " FREE ,Free running - . - ." "Free_running_disabled,1" bitfld.long 0x00 14. " ESAV ,Enable to detect F and V bits only on EAV in ITU-R 656 input mode - . - ." "0,1" bitfld.long 0x00 13. " IGNP ,Ignore protection bits in ITU-R 656 input mode - . - ." "0,1" textline " " bitfld.long 0x00 12. " NBLNKS ,Blank shaping - . - ." "Blank_shaping_enabled,Blank_shaping_disabled" bitfld.long 0x00 10.--11. " VBLKM ,Vertical blanking mode - . - . - . - ." "Internal_default_blanking,1,?..." bitfld.long 0x00 8.--9. " HBLKM ,Horizontal blanking mode - . - . - . - ." "Internal_default_blanking,1,2,?..." textline " " bitfld.long 0x00 7. " M_S ,Encoder is master or slave of external sync - . - ." "0,1" bitfld.long 0x00 6. " FID_POL ,FID output polarity - . - ." "0,1" bitfld.long 0x00 3. " VS_POL ,VS input polarity - . - ." "0,1" textline " " bitfld.long 0x00 2. " HS_POL ,HS input polarity - . - ." "0,1" bitfld.long 0x00 0. " FHVMOD ,FID extracted from external FID or HSYNC and VSYNC - . - ." "External_FID,1" group.long 0x1C++0x3 line.long 0x00 "VENC_LLEN,LLEN" bitfld.long 0x00 15. " LLEN_EN ,LLEN_EN - . - ." "disable,enable" hexmask.long.word 0x00 0.--10. 1. " LLEN ,LLEN[10:0] Line length or total number of pixels in a scan line including active video and blanking. Total number of pixels in a scan line = LLEN NOTE: A write to bit 11 of this bit field is illegal." group.long 0x20++0x3 line.long 0x00 "VENC_FLENS,FLENS" hexmask.long.word 0x00 0.--10. 1. " FLENS ,The frame length or total number of lines in a frame including active video and blanking from the source image. Total number of lines in a frame from the source image = FLENS + 1" group.long 0x24++0x3 line.long 0x00 "VENC_HFLTR_CTRL,HFLTR_CTRL" bitfld.long 0x00 1.--2. " CINTP ,Chrominance interpolation filter control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0. " YINTP ,Luminance interpolation filter control - . - ." "0,1" group.long 0x28++0x3 line.long 0x00 "VENC_CC_CARR_WSS_CARR,Frequencie code control" hexmask.long.word 0x00 16.--31. 1. " FWSS ,Wide screen signaling run-in code frequency control. For 50-Hz systems, FWSS = 2 * 5 * 10/(LLEN * Fh), where LLEN = total number of pixels in a scan line Fh = line frequency." hexmask.long.word 0x00 0.--15. 1. " FCC ,Close caption run-in code frequency control. For 60-Hz system, FCC = 2 * 0.5035 * 10/(LLEN * Fh) For 50-Hz systems, FCC = 2* 0.500 * 10/(LLEN * Fh), where LLEN = total number of pixels in a scan line Fh = line f.." group.long 0x2C++0x3 line.long 0x00 "VENC_C_PHASE,C_PHASE" hexmask.long.byte 0x00 0.--7. 1. " CPHS ,Phase of the encoded video color subcarrier (including the color burst) relative to H-sync. The adjustable step is 360/256 degrees." group.long 0x30++0x3 line.long 0x00 "VENC_GAIN_U,Gain control for Cb signal" hexmask.long.word 0x00 0.--8. 1. " GU ,Gain control for Cb signal. Following are typical programming examples for NTSC and PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GU = 0x102 NTSC with no pedestal: WHITE - BLACK = 100 IRE GU = 0x117 PAL with n.." group.long 0x34++0x3 line.long 0x00 "VENC_GAIN_V,Gain control of Cr signal" hexmask.long.word 0x00 0.--8. 1. " GV ,Gain control of Cr signal. Following are typical programming examples for NTSC and PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GV = 0x16C NTSC with no pedestal: WHITE - BLACK = 100 IRE GV = 0x189 PAL with no.." group.long 0x38++0x3 line.long 0x00 "VENC_GAIN_Y,Gain control of Y signal" hexmask.long.word 0x00 0.--8. 1. " GY ,Gain control of Y signal. Following are typical programming examples for NTSC/PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GY = 0x12F NTSC with no pedestal: WHITE - BLACK = 100 IRE GY = 0x147 PAL with no pede.." group.long 0x3C++0x3 line.long 0x00 "VENC_BLACK_LEVEL,BLACK LEVEL" hexmask.long.byte 0x00 0.--6. 1. " BLACK ,Black level setting. Following are typical programming examples for NTSC/PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE BLACK_LEVEL = 0x43 NTSC with no pedestal: WHITE - BLACK = 100 IRE BLACK_LEVEL = 0x38 PAL w.." group.long 0x40++0x3 line.long 0x00 "VENC_BLANK_LEVEL,BLANK LEVEL" hexmask.long.byte 0x00 0.--6. 1. " BLANK ,Blank level setting. Following are typical programming examples for NTSC/PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE BLANK_LEVEL = 0x38 NTSC with no pedestal: WHITE - BLACK = 100 IRE BLANK_LEVEL = 0x38 PAL w.." group.long 0x44++0x3 line.long 0x00 "VENC_X_COLOR,Cross-Colour Control register" bitfld.long 0x00 6. " XCE ,Cross color reduction enable for composite video output. Cross color does not affect S-video output - . - ." "0,1" bitfld.long 0x00 3.--4. " XCBW ,Cross color reduction filter selection - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--2. " LCD ,These three bits can be used for chroma channel delay compensation. Delay on Luma channel. - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x00 "VENC_M_CONTROL,M_CONTROL" bitfld.long 0x00 7. " PALI ,PAL I enable - . - ." "Normal_oeration,PAL_I_Enable" bitfld.long 0x00 6. " PALN ,PAL N Enable - . - ." "Normal_operation,PAL_N_enable" bitfld.long 0x00 5. " PALPHS ,PAL switch phase setting - . - ." "0,1" textline " " bitfld.long 0x00 2.--4. " CBW ,Chrominance lowpass filter bandwidth control - . - . - . - . - . - . - . - ." "0,1,2,Reserved,Reserved,5,6,7" bitfld.long 0x00 1. " PAL ,Phase alternation line encoding selection - . - ." "0,1" bitfld.long 0x00 0. " FFRQ ,The value of this field and the SQP bit in the BSTAMP_WSS_DATA register control the number of horizontal pixels displayed per scan line # OF MODE SQP FFRQ PIXEL PER LINE ITU-R 601 NTSC 0 1 858 Square pixel NTSC 1.." "0,1" group.long 0x4C++0x3 line.long 0x00 "VENC_BSTAMP_WSS_DATA,BSTAMP and WSS_DATA" hexmask.long.tbyte 0x00 8.--27. 1. " WSS_D ,Wide Screen Signaling data NTSC: WORD 0 D0, D1 WORD 1 D2, D3, D4, D5 WORD 2 D6, D7, D8, D9, D10, D11, D12, D13 CRC D14, D15, D16, D17, D18, D19 PAL: GROUP A D0, D1, D2, D3 GROUP B D4, D5, D6, D7 GROUP C D8, D9 ,D10 GROUP D D11, D12.." bitfld.long 0x00 7. " SQP ,Square-pixel sampling rate. See FFRQ in M_CONTROL register for programming information. - . - ." "0,1" hexmask.long.byte 0x00 0.--6. 1. " BSTAP ,Setting of amplitude of color burst." group.long 0x50++0x3 line.long 0x00 "VENC_S_CARR,Color Subcarrier Frequency Registers." hexmask.long 0x00 0.--31. 1. " FSC ,These four bytes' data are used to program color subcarrier frequency. These four bytes are determined by the following formula. S_CARR = ROUND((Fsc/Fclkenc) * 232) Where Fsc = Frequency of the subcarrier Fclkenc = Frequency of the.." group.long 0x54++0x3 line.long 0x00 "VENC_LINE21,LINE 21" hexmask.long.word 0x00 16.--31. 1. " L21E ,The two bytes of the closed caption data in the even field. - For the data stream content, see. . - . [31:24] First byte of data. - . [23:16] Second byte of data. - ." hexmask.long.word 0x00 0.--15. 1. " L21O ,The two bytes of the closed caption data in the odd field - For the data stream content, see. . - . [15:8] First byte of data. - . [7:0] Second byte of data. - ." group.long 0x58++0x3 line.long 0x00 "VENC_LN_SEL,LN_SEL" hexmask.long.word 0x00 16.--25. 1. " LN21_RUNIN ,The two Bytes of the closed caption runin code position from the HSYNC" bitfld.long 0x00 0.--4. " SLINE ,Selects the line where closed caption or extended service data are encoded.PAL mode: Because there is a one-line offset, program the desired line number ? 1.. - . NTSC mode: Because there is a four-line offset, .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x3 line.long 0x00 "VENC_L21_WC_CTL,L21 and WC_CTL registers" bitfld.long 0x00 15. " INV ,WSS inverter - . - ." "no_effect,invert_WSS_data" bitfld.long 0x00 13.--14. " EVEN_ODD_EN ,This bit controls the WSS encoding. - . - . - . - ." "WSS_encoding_OFF,1,2,3" bitfld.long 0x00 8.--12. " LINE ,Selects the line where WSS data are encoded.PAL mode: Because there is a one-line offset, program the desired line number ? 1.. - . NTSC mode: Because there is a four-line offset, program the desired line number ? 4.. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " L21EN ,Those bits controls the Line21 closed caption encoding according to the mode. - . - . - . - ." "Line21_encoding_OFF,1,2,3" group.long 0x60++0x3 line.long 0x00 "VENC_HTRIGGER_VTRIGGER,HTRIGGER and VTRIGGER" hexmask.long.word 0x00 16.--25. 1. " VTRIG ,Vertical trigger reference for VSYNC. These bits specify the phase between VSYNC input and the lines in a field. The VTRIG field is expressed in units of half-line." hexmask.long.word 0x00 0.--10. 1. " HTRIG ,Horizontal trigger phase, which sets HSYNC. HTRIG is expressed in half-pixels or clk2x (27 MHz) periods" group.long 0x64++0x3 line.long 0x00 "VENC_SAVID_EAVID,SAVID and EAVID" hexmask.long.word 0x00 16.--26. 1. " EAVID ,End of active video. These bits define the ending pixel position on a horizontal display line where active video will be displayed." hexmask.long.word 0x00 0.--10. 1. " SAVID ,Start of active video. These bits define the starting pixel position on a horizontal line where active video will be displayed." group.long 0x68++0x3 line.long 0x00 "VENC_FLEN_FAL,FLEN and FAL" hexmask.long.word 0x00 16.--24. 1. " FAL ,First Active Line of Field. These bits define the first active line of a field" hexmask.long.word 0x00 0.--9. 1. " FLEN ,Field length. These bits define the number of half_lines in each field. Length of field = (FLEN + 1) half_lines" group.long 0x6C++0x3 line.long 0x00 "VENC_LAL_PHASE_RESET,LAL and PHASE_RESET" bitfld.long 0x00 17.--18. " PRES ,Phase reset mode. - . - . - . - ." "No_reset,1,2,3" bitfld.long 0x00 16. " SBLANK ,Vertical blanking setting - . - ." "0,1" hexmask.long.word 0x00 0.--8. 1. " LAL ,Last Active Line of Field. These bits define the last active line of a field" group.long 0x70++0x3 line.long 0x00 "VENC_HS_INT_START_STOP_X,HS_INT_START_STOP_X" hexmask.long.word 0x00 16.--25. 1. " HS_INT_STOP_X ,HSYNC internal stop. These bits define HSYNC internal stop pixel value" hexmask.long.word 0x00 0.--9. 1. " HS_INT_START_X ,HSYNC internal start. These bits define HSYNC internal start pixel value" group.long 0x74++0x3 line.long 0x00 "VENC_HS_EXT_START_STOP_X,HS_EXT_START_STOP_X" hexmask.long.word 0x00 16.--25. 1. " HS_EXT_STOP_X ,HSYNC external stop. These bits define HSYNC external stop pixel value" hexmask.long.word 0x00 0.--9. 1. " HS_EXT_START_X ,HSYNC external start. These bits define HSYNC external start pixel value" group.long 0x78++0x3 line.long 0x00 "VENC_VS_INT_START_X,VS_INT_START_X" hexmask.long.word 0x00 16.--25. 1. " VS_INT_START_X ,VSYNC internal start. These bits define VSYNC internal start pixel value." group.long 0x7C++0x3 line.long 0x00 "VENC_VS_INT_STOP_X_VS_INT_START_Y,VS_INT_STOP_X and VS_INT_START_Y" hexmask.long.word 0x00 16.--25. 1. " VS_INT_START_Y ,VSYNC internal start. These bits define VSYNC internal start line value" hexmask.long.word 0x00 0.--9. 1. " VS_INT_STOP_X ,VSYNC internal stop. These bits define VSYNC internal stop pixel value" group.long 0x80++0x3 line.long 0x00 "VENC_VS_INT_STOP_Y_VS_EXT_START_X,VS_INT_STOP_Y and VS_EXT_START_X" hexmask.long.word 0x00 16.--25. 1. " VS_EXT_START_X ,VSYNC external start. These bits define VSYNC external start pixel value." hexmask.long.word 0x00 0.--9. 1. " VS_INT_STOP_Y ,VSYNC internal stop. These bits define VSYNC internal stop line value." group.long 0x84++0x3 line.long 0x00 "VENC_VS_EXT_STOP_X_VS_EXT_START_Y,VS_EXT_STOP_X and VS_EXT_START_Y" hexmask.long.word 0x00 16.--25. 1. " VS_EXT_START_Y ,VSYNC external start. These bits define VSYNC external start line value." hexmask.long.word 0x00 0.--9. 1. " VS_EXT_STOP_X ,VSYNC external stop. These bits define VSYNC external stop pixel value." group.long 0x88++0x3 line.long 0x00 "VENC_VS_EXT_STOP_Y,VS_EXT_STOP_Y" hexmask.long.word 0x00 0.--9. 1. " VS_EXT_STOP_Y ,VSYNC external stop. These bits define VSYNC external stop line value." group.long 0x90++0x3 line.long 0x00 "VENC_AVID_START_STOP_X,AVID_START_STOP_X" hexmask.long.word 0x00 16.--25. 1. " AVID_STOP_X ,AVID stop. These bits define AVID stop pixel value" hexmask.long.word 0x00 0.--9. 1. " AVID_START_X ,AVID start. These bits define AVID start pixel value" group.long 0x94++0x3 line.long 0x00 "VENC_AVID_START_STOP_Y,AVID_START_STOP_Y" hexmask.long.word 0x00 16.--25. 1. " AVID_STOP_Y ,AVID stop. These bits define AVID stop line value." hexmask.long.word 0x00 0.--9. 1. " AVID_START_Y ,AVID start. These bits define AVID start line value" group.long 0xA0++0x3 line.long 0x00 "VENC_FID_INT_START_X_FID_INT_START_Y,FID_INT_START_X and FID_INT_START_Y" hexmask.long.word 0x00 16.--25. 1. " FID_INT_START_Y ,FID internal stop. These bits define FID internal start line value" hexmask.long.word 0x00 0.--9. 1. " FID_INT_START_X ,FID internal start. These bits define FID internal start pixel value" group.long 0xA4++0x3 line.long 0x00 "VENC_FID_INT_OFFSET_Y_FID_EXT_START_X,FID_INT_OFFSET_Y and FID_EXT_START_X" hexmask.long.word 0x00 16.--25. 1. " FID_EXT_START_X ,FID external start. These bits define FID external start pixel value" hexmask.long.word 0x00 0.--9. 1. " FID_INT_OFFSET_Y ,FID internal offset. These bits define FID internal offset linel value" group.long 0xA8++0x3 line.long 0x00 "VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y,FID_EXT_START_Y and FID_EXT_OFFSET_Y" hexmask.long.word 0x00 16.--25. 1. " FID_EXT_OFFSET_Y ,FID external offset. These bits define FID external offset line value" hexmask.long.word 0x00 0.--9. 1. " FID_EXT_START_Y ,FID external start. These bits define FID external start line value." group.long 0xB0++0x3 line.long 0x00 "VENC_TVDETGP_INT_START_STOP_X,TVDETGP_INT_START_STOP_X" hexmask.long.word 0x00 16.--25. 1. " TVDETGP_INT_STOP_X ,TVDETGP internal stop. These bits define TVDETGP internal stop pixel value." hexmask.long.word 0x00 0.--9. 1. " TVDETGP_INT_START_X ,TVDETGP internal start. These bits define TVDETGP internal start pixel value" group.long 0xB4++0x3 line.long 0x00 "VENC_TVDETGP_INT_START_STOP_Y,TVDETGP_INT_START_STOP_Y" hexmask.long.word 0x00 16.--25. 1. " TVDETGP_INT_STOP_Y ,TVDETGP internal stop. These bits define TVDETGP internal stop line value." hexmask.long.word 0x00 0.--9. 1. " TVDETGP_INT_START_Y ,TVDETGP internal start. These bits define TVDETGP internal start line value" group.long 0xB8++0x3 line.long 0x00 "VENC_GEN_CTRL,TVDETGP enable and SYNC_POLARITY and UVPHASE_POL" bitfld.long 0x00 26. " MS ,UVPHASE_POL MS mode UV phase - . - ." "CbCr,CrCb" bitfld.long 0x00 25. " UVPHASE_POL_656 ,UVPHASE_POL 656 input mode UV phase - . - ." "CbCr,CrCb" bitfld.long 0x00 24. " CBAR ,UVPHASE_POL CBAR mode UV phase - . - ." "CbCr,CrCb" textline " " bitfld.long 0x00 23. " HIP ,HSYNC internal polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 22. " VIP ,VSYNC internal polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 21. " HEP ,HSYNC external polarity - . - ." "Active_Low,Active_High" textline " " bitfld.long 0x00 20. " VEP ,VSYNC externall polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 19. " AVIDP ,AVID polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 18. " FIP ,FID internal polarity - . - ." "Active_Low,Active_High" textline " " bitfld.long 0x00 17. " FEP ,FID external polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 16. " TVDP ,TVDETGP polarity - . - ." "Active_Low,Active_High" bitfld.long 0x00 0. " EN ,TVDETGP generation enable - . - ." "Disabled,Enabled" group.long 0xC4++0x3 line.long 0x00 "VENC_OUTPUT_CONTROL,Output channel control register Also contains some test control features" bitfld.long 0x00 6. " COMPOSITE_SOURCE ,Source of composite video data in test mode - . - ." "0,1" bitfld.long 0x00 4. " TEST_MODE ,This enables the video DACs to be tested. The values sent to the DACs comes from a register for each output channel (Luma, Composite or Chroma) or from the display controller video port bits G[1:0], B[7:0], d.." "0,1" bitfld.long 0x00 3. " VIDEO_INVERT ,Controls the video output polarity. This may be used to correct for inversion in an external video amplifier. - . - ." "0,1" textline " " bitfld.long 0x00 1. " COMPOSITE_ENABLE ,Enable the Composite output channel - . - ." "0,1" group.long 0xC8++0x3 line.long 0x00 "VENC_OUTPUT_TEST,Test values for the Luma/Composite Video DAC" hexmask.long.word 0x00 0.--9. 1. " COMPOSITE_TEST ,In test mode, DAC input value (if composite video is selected)" tree.end tree.end tree.end tree.open "SGX_Overview" tree "SGX" base ad:0x56000000 width 21. rgroup.long 0xFE00++0x3 line.long 0x00 "OCP_REVISION,OCP Revision Register." hexmask.long 0x00 0.--31. 1. " REVISIONID ,Revision value." rgroup.long 0xFE04++0x3 line.long 0x00 "OCP_HWINFO,Hardware implementation information" bitfld.long 0x00 2. " MEM_BUS_WIDTH ,Memory bus width: - . - ." "0,1" bitfld.long 0x00 0.--1. " SYS_BUS_WIDTH ,System bus width: - . - . - . - ." "0,1,2,?..." group.long 0xFE10++0x3 line.long 0x00 "OCP_SYSCONFIG,System Configuration register" bitfld.long 0x00 4.--5. " STANDBY_MODE ,Clock standby mode: - . - . 0x2, 0x3: Smart-standby mode. - ." "Force-standby_mode,No-standby_mode,2,3" bitfld.long 0x00 2.--3. " IDLE_MODE ,Clock Idle mode: - . - . 0x2, 0x3: Smart-idle mode. - ." "Force-idle_mode,No-idle_mode,2,3" group.long 0xFE24++0x3 line.long 0x00 "OCP_IRQSTATUS_RAW_0,Raw IRQ 0 Status" bitfld.long 0x00 0. " INIT_MINTERRUPT_RAW ,Interrupt 0 - Master port raw event: - . - . - . - ." "No_action.,Event_pending." group.long 0xFE28++0x3 line.long 0x00 "OCP_IRQSTATUS_RAW_1,Raw IRQ 1 Status. Slave port interrupt." bitfld.long 0x00 0. " TARGET_SINTERRUPT_RAW ,Interrupt 1- Slave port raw event - . - . - . - ." "No_action.,Event_pending." group.long 0xFE2C++0x3 line.long 0x00 "OCP_IRQSTATUS_RAW_2,Raw IRQ 2 Status. Core interrupt." bitfld.long 0x00 0. " CORE_IRQ_RAW ,Interrupt 2 - Core raw event - . - . - . - ." "No_action.,Event_pending." group.long 0xFE30++0x3 line.long 0x00 "OCP_IRQSTATUS_0,Interrupt 0 Status event. Master port interrupt." bitfld.long 0x00 0. " INIT_MINTERRUPT_STATUS ,Interrupt 0 - Master port status event - . - . - . - ." "No_action.,Clear_event." group.long 0xFE34++0x3 line.long 0x00 "OCP_IRQSTATUS_1,Interrupt 1 - slave port status event" bitfld.long 0x00 0. " TARGET_SINTERRUPT_STATUS ,Interrupt 1 - Slave port status event - . - . - . - ." "No_action.,Clear_event." group.long 0xFE38++0x3 line.long 0x00 "OCP_IRQSTATUS_2,Interrupt 2 - Core status event" bitfld.long 0x00 0. " CORE_IRQ_STATUS ,Interrupt 2 - Core status event - . - . - . - ." "No_action.,Clear_event." group.long 0xFE3C++0x3 line.long 0x00 "OCP_IRQENABLE_SET_0,Enable Interrupt 0 - Master port" bitfld.long 0x00 0. " INIT_MINTERRUPT_ENABLE ,Enable interrupt 0 - Master port - . - . - . - ." "No_action.,Interrupt_is_disabled." group.long 0xFE40++0x3 line.long 0x00 "OCP_IRQENABLE_SET_1,Enable Interrupt 1. Target port interrupt." bitfld.long 0x00 0. " TARGET_SINTERRUPT_ENABLE ,Enable interrupt 1 - Slave port interrupt - . - . - . - ." "No_action.,Interrupt_is_disabled." group.long 0xFE44++0x3 line.long 0x00 "OCP_IRQENABLE_SET_2,Enable Interrupt 2. Core interrupt." bitfld.long 0x00 0. " CORE_IRQ_ENABLE ,Enable interrupt 2 - Core interrupt - . - . - . - ." "No_action.,Interrupt_is_disabled." group.long 0xFE48++0x3 line.long 0x00 "OCP_IRQENABLE_CLR_0,Disable Interrupt 0 - Master port" bitfld.long 0x00 0. " INIT_MINTERRUPT_DISABLE ,Disable interrupt 0 - Master port - . - . - . - ." "No_action.,Interrupt_is_disabled." group.long 0xFE4C++0x3 line.long 0x00 "OCP_IRQENABLE_CLR_1,Disable Interrupt 1 - slave port" bitfld.long 0x00 0. " TARGET_SINTERRUPT_DISABLE ,Disable interrupt 1 - Slave port - . - . - . - ." "No_action.,Interrupt_is_disabled." group.long 0xFE50++0x3 line.long 0x00 "OCP_IRQENABLE_CLR_2,Disable Interrupt 2 - Core interrupt" bitfld.long 0x00 0. " CORE_IRQ_DISABLE ,Disable interrupt 2 - Core interrupt - . - . - . - ." "No_action.,Interrupt_is_disabled." group.long 0xFF00++0x3 line.long 0x00 "OCP_PAGE_CONFIG,Configure memory pages.." bitfld.long 0x00 3.--4. " OCP_PAGE_SIZE ,Defines the page size on OCP memory interface - . - . - . - ." "0,1,2,3" bitfld.long 0x00 2. " MEM_PAGE_CHECK_EN ,Enable page boundary checking. - . - ." "0,1" bitfld.long 0x00 0.--1. " MEM_PAGE_SIZE ,Defines the page size on internal memory interface - . - . - . - ." "0,1,2,3" group.long 0xFF04++0x3 line.long 0x00 "OCP_INTERRUPT_EVENT,Interrupt events" bitfld.long 0x00 10. " TARGET_INVALID_OCP_CMD ,Invalid command from OCP - . - . - . - ." "Clear_the_event.,Event_pending." bitfld.long 0x00 9. " TARGET_CMD_FIFO_FULL ,Command FIFO full - . - . - . - ." "0,1" bitfld.long 0x00 8. " TARGET_RESP_FIFO_FULL ,Response FIFO full. - . - . - . - ." "Clear_the_event.,Event_pending." textline " " bitfld.long 0x00 5. " INIT_MEM_REQ_FIFO_OVERRUN ,Memory request FIFO overrun. - . - . - . - ." "Clear_the_event.,Event_pending." bitfld.long 0x00 4. " INIT_READ_TAG_FIFO_OVERRUN ,Read tag FIFO overrun. - . - . - . - ." "Clear_the_event.,Event_pending." bitfld.long 0x00 3. " INIT_PAGE_CROSS_ERROR ,Memory page had been crossed during a burst. - . - . - . - ." "Clear_the_event.,Event_pending." textline " " bitfld.long 0x00 2. " INIT_RESP_ERROR ,Receiving error response - . - . - . - ." "Clear_the_event.,Event_pending." bitfld.long 0x00 1. " INIT_RESP_UNUSED_TAG ,Receiving response on an unused tag - . - . - . - ." "Clear_the_event.,Event_pending." bitfld.long 0x00 0. " INIT_RESP_UNEXPECTED ,Receiving response when not expected - . - . - . - ." "Clear_the_event.,Event_pending." group.long 0xFF08++0x3 line.long 0x00 "OCP_DEBUG_CONFIG,Configuration of debug modes." bitfld.long 0x00 31. " CORE_INT_BYPASS ,Bypass OCP IPG interrupt logic. - . - ." "Don't_Bypass.,1" bitfld.long 0x00 5. " SELECT_INIT_IDLE ,To select which idle the disconnect protocol should act on 0 - . - ." "Whole_SGX_Idle.,1" bitfld.long 0x00 4. " FORCE_PASS_DATA ,Forces the initiator to pass data independent of disconnect protocol - . - ." "0,1" textline " " bitfld.long 0x00 2.--3. " FORCE_INIT_IDLE ,Forces the OCP master port to idle. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0.--1. " FORCE_TARGET_IDLE ,Forces the OCP target port to idle. - . - . - . - ." "0,1,2,3" group.long 0xFF0C++0x3 line.long 0x00 "OCP_DEBUG_STATUS,Status of debug." bitfld.long 0x00 31. " CMD_DEBUG_STATE ,Target command state-machine - . - ." "Idle,Accept_command." bitfld.long 0x00 30. " CMD_RESP_DEBUG_STATE ,Target response state-machine - . - ." "Send_accept.,Wait_accept." bitfld.long 0x00 29. " TARGET_IDLE ,Target idle" "0,1" textline " " bitfld.long 0x00 28. " RESP_FIFO_FULL ,Target response FIFO full" "0,1" bitfld.long 0x00 27. " CMD_FIFO_FULL ,Target command FIFO full" "0,1" bitfld.long 0x00 26. " RESP_ERROR ,Respond to OCP with error, which could be caused by either address misalignment or invalid byte enable." "0,1" textline " " bitfld.long 0x00 21.--25. " WHICH_TARGET_REGISTER ,Indicates which OCP target registers to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18.--20. " TARGET_CMD_OUT ,Command received from OCP - . - . - . - . - . - . - . - ." "Command_WRSYS_received,Command_RDSYS_received,Command_WR_ERROR_received,Command_RD_ERROR_received,4,5,6,7" bitfld.long 0x00 17. " INIT_MSTANDBY ,Status of init_MStandby signal" "0,1" textline " " bitfld.long 0x00 16. " INIT_MWAIT ,Status of init_MWait signal" "0,1" bitfld.long 0x00 14.--15. " INIT_MDISCREQ ,Disconnect status of the OCP interface - . - . - . - ." "State_is_FUNCT,1,Reserved,State_is_IDLE." bitfld.long 0x00 13. " INIT_MDISCACK ,Memory request FIFO full - . - . - . - ." "Clear_the_event.,Event_pending" textline " " bitfld.long 0x00 12. " INIT_SCONNECT2 ,Defines whether to wait in M_WAIT state for MConnect FSM - . - ." "Skip_M_WAIT_state.,1" bitfld.long 0x00 11. " INIT_SCONNECT1 ,Defines the busy-ness state of the slave - . - ." "Slave_is_drained.,Slave_is_loaded." bitfld.long 0x00 10. " INIT_SCONNECT0 ,Disconnect from slave - . - ." "0,1" textline " " bitfld.long 0x00 8.--9. " INIT_MCONNECT ,Initiator MConnect state - . - . - . - ." "State_is_M_OFF.,State_is_M_WAIT.,State_is_M_DISC.,State_is_M_CON." bitfld.long 0x00 6.--7. " TARGET_SIDLEACK ,Acknowledge the SIdleAck state machine - . - . - . - ." "State_is_FUNCT.,1,Reserved,State_is_IDLE." bitfld.long 0x00 4.--5. " TARGET_SDISCACK ,Acknowledge the SDiscAck state-machine - . - . - . - ." "State_is_FUNCT.,State_is_TRANS.,Reserved,State_is_IDLE." textline " " bitfld.long 0x00 3. " TARGET_SIDLEREQ ,Request the target to go idle. - . - ." "0,Go_idle." bitfld.long 0x00 2. " TARGET_SCONNECT ,Target SConnect state - . - ." "Disconnect_interface.,Connect_OCP_interface." bitfld.long 0x00 0.--1. " TARGET_MCONNECT ,Target MConnect state - . - . - . - ." "0,1,2,3" tree.end tree.end tree.open "L3_Interconnect" tree "EMIF_Firewall" base ad:0x4A20C000 tree "Channel_0" width 32. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k_0,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" width 32. group.long 0x94++0x3 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0x10++0x3 line.long 0x00 "ERROR_LOG_k_1,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x14++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x9C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x90++0x3 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_2" width 32. group.long 0xA4++0x3 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0x20++0x3 line.long 0x00 "ERROR_LOG_k_2,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x24++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k_2,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0xAC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x3 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_3" width 32. group.long 0xB4++0x3 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xBC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x3 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_4" width 32. group.long 0xC4++0x3 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xCC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x3 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_5" width 32. group.long 0xD4++0x3 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xDC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x3 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_6" width 32. group.long 0xE4++0x3 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xEC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x3 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_7" width 32. group.long 0xF4++0x3 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xFC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x3 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end textline "" width 19. group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" tree.end tree "C2C_Slave_NIU_Firewall" base ad:0x4A206000 tree "REG_Bundle_0" width 32. group.long 0x2008C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x20088++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" width 32. group.long 0x2009C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x20098++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_2" width 32. group.long 0x200AC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x200A8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_3" width 32. group.long 0x200BC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x200B8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" tree.end textline "" width 23. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x20004++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x20040++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" tree.end tree.open "CLK1_HOST_CLK1" tree "CLK1_HOST_CLK1" base ad:0x44000000 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x1A." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." rgroup.long 0x8++0x3 line.long 0x00 "L3_HOST_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemente.." "0,1" group.long 0x40++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x0. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x0. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_HOST_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_HOST_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_WR," bitfld.long 0x00 0. " STDERRLOG_CUSTOMINFO_WR ,Type: Status. Reset value: X." "0,1" rgroup.long 0x70++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.tbyte 0x00 0.--20. 1. " STDERRLOG_CUSTOMINFO_ADDR ,Type: Status. Reset value: X." rgroup.long 0x74++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," bitfld.long 0x00 0. " STDERRLOG_CUSTOMINFO_DECERR ,Type: Status. Reset value: X." "0,1" tree.end tree "CLK2_HOST_CLK2" base ad:0x44800000 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x1A." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." rgroup.long 0x8++0x3 line.long 0x00 "L3_HOST_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemente.." "0,1" group.long 0x40++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x0. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x0. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_HOST_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_HOST_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_WR," bitfld.long 0x00 0. " STDERRLOG_CUSTOMINFO_WR ,Type: Status. Reset value: X." "0,1" rgroup.long 0x70++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.tbyte 0x00 0.--20. 1. " STDERRLOG_CUSTOMINFO_ADDR ,Type: Status. Reset value: X." rgroup.long 0x74++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," bitfld.long 0x00 0. " STDERRLOG_CUSTOMINFO_DECERR ,Type: Status. Reset value: X." "0,1" tree.end tree "CLK3_HOST_CLK3" base ad:0x45000000 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x1A." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." rgroup.long 0x8++0x3 line.long 0x00 "L3_HOST_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemente.." "0,1" group.long 0x40++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x0. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x0. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_HOST_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_HOST_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_HOST_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_WR," bitfld.long 0x00 0. " STDERRLOG_CUSTOMINFO_WR ,Type: Status. Reset value: X." "0,1" rgroup.long 0x70++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.tbyte 0x00 0.--20. 1. " STDERRLOG_CUSTOMINFO_ADDR ,Type: Status. Reset value: X." rgroup.long 0x74++0x3 line.long 0x00 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," bitfld.long 0x00 0. " STDERRLOG_CUSTOMINFO_DECERR ,Type: Status. Reset value: X." "0,1" tree.end tree.end tree "Debug_Firewall" base ad:0x4A226000 tree "REG_Bundle_0" width 32. group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" width 32. group.long 0x94++0x3 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0x9C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x90++0x3 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end textline "" width 23. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" tree.end tree.open "SGX_Firewall" tree "SGX_Firewall" base ad:0x4A214000 width 30. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "ISS_Firewall" base ad:0x4A216000 width 30. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "Dual_Cortex_M3_Firewall" base ad:0x4A218000 width 30. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "DSS_Firewall" base ad:0x4A21C000 width 30. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "SL2_Firewall" base ad:0x4A21E000 width 30. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "IVA_HD_Firewall" base ad:0x4A220000 width 30. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "L4_ABE_Firewall" base ad:0x4A228000 width 30. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" tree.end tree.end tree "L3_RAM_Firewall" base ad:0x4A212000 tree "REG_Bundle_0" width 32. group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" width 32. group.long 0x94++0x3 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0x9C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x90++0x3 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_2" width 32. group.long 0xA4++0x3 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xAC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x3 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_3" width 32. group.long 0xB4++0x3 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xBC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x3 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_4" width 32. group.long 0xC4++0x3 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xCC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x3 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_5" width 32. group.long 0xD4++0x3 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xDC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x3 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_6" width 32. group.long 0xE4++0x3 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xEC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x3 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_7" width 32. group.long 0xF4++0x3 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xFC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x3 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_8" width 32. group.long 0x104++0x3 line.long 0x00 "END_REGION_i_8,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0x10C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x108++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x100++0x3 line.long 0x00 "START_REGION_i_8,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_9" width 32. group.long 0x114++0x3 line.long 0x00 "END_REGION_i_9,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0x11C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x118++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x110++0x3 line.long 0x00 "START_REGION_i_9,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end textline "" width 23. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" tree.end tree.open "CLK1_FLAGMUX_CLK1" tree "CLK1_FLAGMUX_CLK1" base ad:0x44000500 width 34. rgroup.long 0x0++0x3 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_FLAGMUX_MASK0," hexmask.long.tbyte 0x00 0.--17. 1. " MASK0 ,Mask flag inputs 0 Type: Control. Reset value: 0x3FFFF." rgroup.long 0xC++0x3 line.long 0x00 "L3_FLAGMUX_REGERR0," hexmask.long.tbyte 0x00 0.--17. 1. " REGERR0 ,Flag inputs 0 Type: Status. Reset value: X." group.long 0x10++0x3 line.long 0x00 "L3_FLAGMUX_MASK1," hexmask.long.tbyte 0x00 0.--17. 1. " MASK1 ,Mask flag inputs 1 Type: Control. Reset value: 0x3FFFF." rgroup.long 0x14++0x3 line.long 0x00 "L3_FLAGMUX_REGERR1," hexmask.long.tbyte 0x00 0.--17. 1. " REGERR1 ,Flag inputs 1 Type: Status. Reset value: X." tree.end tree "CLK2_FLAGMUX_CLK2" base ad:0x44801000 width 34. rgroup.long 0x0++0x3 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_FLAGMUX_MASK0," hexmask.long.tbyte 0x00 0.--17. 1. " MASK0 ,Mask flag inputs 0 Type: Control. Reset value: 0x3FFFF." rgroup.long 0xC++0x3 line.long 0x00 "L3_FLAGMUX_REGERR0," hexmask.long.tbyte 0x00 0.--17. 1. " REGERR0 ,Flag inputs 0 Type: Status. Reset value: X." group.long 0x10++0x3 line.long 0x00 "L3_FLAGMUX_MASK1," hexmask.long.tbyte 0x00 0.--17. 1. " MASK1 ,Mask flag inputs 1 Type: Control. Reset value: 0x3FFFF." rgroup.long 0x14++0x3 line.long 0x00 "L3_FLAGMUX_REGERR1," hexmask.long.tbyte 0x00 0.--17. 1. " REGERR1 ,Flag inputs 1 Type: Status. Reset value: X." tree.end tree "CLK3_FLAGMUX_CLK3" base ad:0x45000200 width 34. rgroup.long 0x0++0x3 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_FLAGMUX_MASK0," hexmask.long.tbyte 0x00 0.--17. 1. " MASK0 ,Mask flag inputs 0 Type: Control. Reset value: 0x3FFFF." rgroup.long 0xC++0x3 line.long 0x00 "L3_FLAGMUX_REGERR0," hexmask.long.tbyte 0x00 0.--17. 1. " REGERR0 ,Flag inputs 0 Type: Status. Reset value: X." group.long 0x10++0x3 line.long 0x00 "L3_FLAGMUX_MASK1," hexmask.long.tbyte 0x00 0.--17. 1. " MASK1 ,Mask flag inputs 1 Type: Control. Reset value: 0x3FFFF." rgroup.long 0x14++0x3 line.long 0x00 "L3_FLAGMUX_REGERR1," hexmask.long.tbyte 0x00 0.--17. 1. " REGERR1 ,Flag inputs 1 Type: Status. Reset value: X." tree.end tree.end tree "CLK3_STATCOLL_SDRAM" base ad:0x45000400 width 36. rgroup.long 0x0++0x3 line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_STCOL_EN," bitfld.long 0x00 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" group.long 0xC++0x3 line.long 0x00 "L3_STCOL_SOFTEN," bitfld.long 0x00 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" group.long 0x10++0x3 line.long 0x00 "L3_STCOL_TRIGEN," bitfld.long 0x00 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" group.long 0x14++0x3 line.long 0x00 "L3_STCOL_REQEVT," bitfld.long 0x00 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0. - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x00 "L3_STCOL_RSPEVT," bitfld.long 0x00 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0. - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x00 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x00 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x00 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x00 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x2C++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL4," bitfld.long 0x00 0.--2. " EVTMUX_SEL4 ,The select of the mux 4 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" rgroup.long 0x30++0x3 line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--1. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "L3_STCOL_DUMP_COLLECTTIME," hexmask.long.word 0x00 0.--15. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." rgroup.long 0x38++0x3 line.long 0x00 "L3_STCOL_DUMP_SLVADDR," bitfld.long 0x00 0.--4. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x3C++0x3 line.long 0x00 "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." group.long 0x40++0x3 line.long 0x00 "L3_STCOL_DUMP_SLVOFS," hexmask.long 0x00 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.long 0x44++0x3 line.long 0x00 "L3_STCOL_DUMP_MANUAL," bitfld.long 0x00 0. " DUMP_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" group.long 0x48++0x3 line.long 0x00 "L3_STCOL_DUMP_SEND," bitfld.long 0x00 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.long 0x4C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN," bitfld.long 0x00 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" group.long 0x50++0x3 line.long 0x00 "L3_STCOL_FILTER_i_EN_k," bitfld.long 0x00 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" group.long 0x54++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." group.long 0x58++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD," bitfld.long 0x00 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" group.long 0x5C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR," bitfld.long 0x00 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" group.long 0x60++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR," bitfld.long 0x00 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" group.long 0x68++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO," hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_i_MASK_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." group.long 0x6C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." group.long 0x70++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD," bitfld.long 0x00 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" group.long 0x74++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR," bitfld.long 0x00 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" group.long 0x78++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR," bitfld.long 0x00 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" group.long 0x80++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO," hexmask.long.tbyte 0x00 0.--17. 1. " FILTER_i_MATCH_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." group.long 0xB8++0x3 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL," hexmask.long.word 0x00 0.--11. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." group.long 0xBC++0x3 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL," hexmask.long.word 0x00 0.--11. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." group.long 0xC0++0x3 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL," bitfld.long 0x00 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0. - . - . - ." "0,1,2,3" group.long 0xC4++0x3 line.long 0x00 "L3_STCOL_OP_i_SEL," bitfld.long 0x00 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0. - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.open "CLK1_DMM1_TARG" tree "CLK1_DMM1_TARG" base ad:0x44000100 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK1_DMM2_TARG" base ad:0x44000200 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK1_ABE_TARG" base ad:0x44000300 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK1_L4CFG_TARG" base ad:0x44000400 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_GPMC_TARG" base ad:0x44800100 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_OCMRAM_TARG" base ad:0x44800200 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_DSS_TARG" base ad:0x44800300 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_ISS_TARG" base ad:0x44800400 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_CORTEXM3_TARG" base ad:0x44800500 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_SGX_TARG" base ad:0x44800600 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_IVAHD_TARG" base ad:0x44800700 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_SL2_TARG" base ad:0x44800800 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_L4PER0_TARG" base ad:0x44800900 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_L4PER1_TARG" base ad:0x44800A00 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_L4PER2_TARG" base ad:0x44800B00 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_L4PER3_TARG" base ad:0x44800C00 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK2_C2C_TARG" base ad:0x44801600 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "CLK3_L4EMU_TARG" base ad:0x45000100 width 38. rgroup.long 0x0++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG__CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG__VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" bitfld.long 0x00 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" rgroup.long 0x10++0x3 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," bitfld.long 0x00 0.--4. " STDHOSTHDR_NTTPADDR_0 ,Sets the RX port address. Type: Control. Reset value: 0x15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet (see). Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" rgroup.long 0x64++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." rgroup.long 0x68++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet (see). Type: Status. Reset value: X." rgroup.long 0x6C++0x3 line.long 0x00 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x00 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree.open "CLK1_RATE_ADAPT_RESP_32TO128_CLK1" tree "CLK1_RATE_ADAPT_RESP_32TO128_CLK1" base ad:0x44000800 width 29. rgroup.long 0x0++0x3 line.long 0x00 "L3_RA_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2D." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_RA_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_RA_CNF," bitfld.long 0x00 1.--4. " CNF_RATE ,Indicates the throughput ratio between input and output (Rate = [16 x (Incoming_Throughput/Outgoing_Throuput)] - 1), when bit StAndFwd bit is reset. Ignored when StAndFwd bit is set. Type: Control. Reset value: 0x3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CNF_STANDFWD ,When this bit is set, the Packet Transport Unit stores the entire NTTP packet, then forwards it on TX port. Type: Control. Reset value: 0x0." "0,1" tree.end tree "CLK2_RATE_ADAPT_RESP_32TO128_CLK2" base ad:0x44801200 width 29. rgroup.long 0x0++0x3 line.long 0x00 "L3_RA_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2D." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_RA_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_RA_CNF," bitfld.long 0x00 1.--4. " CNF_RATE ,Indicates the throughput ratio between input and output (Rate = [16 x (Incoming_Throughput/Outgoing_Throuput)] - 1), when bit StAndFwd bit is reset. Ignored when StAndFwd bit is set. Type: Control. Reset value: 0x3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CNF_STANDFWD ,When this bit is set, the Packet Transport Unit stores the entire NTTP packet, then forwards it on TX port. Type: Control. Reset value: 0x0." "0,1" tree.end tree.end tree "CLK3_STATCOLL_LAT0" base ad:0x45000600 width 35. rgroup.long 0x0++0x3 line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_STCOL_EN," bitfld.long 0x00 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" group.long 0xC++0x3 line.long 0x00 "L3_STCOL_SOFTEN," bitfld.long 0x00 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" group.long 0x10++0x3 line.long 0x00 "L3_STCOL_TRIGEN," bitfld.long 0x00 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" group.long 0x14++0x3 line.long 0x00 "L3_STCOL_REQEVT," bitfld.long 0x00 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0. - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x00 "L3_STCOL_RSPEVT," bitfld.long 0x00 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0. - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x00 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x00 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x00 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x00 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" rgroup.long 0x2C++0x3 line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--1. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3" group.long 0x30++0x3 line.long 0x00 "L3_STCOL_DUMP_COLLECTTIME," hexmask.long.word 0x00 0.--15. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." rgroup.long 0x34++0x3 line.long 0x00 "L3_STCOL_DUMP_SLVADDR," bitfld.long 0x00 0.--4. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x38++0x3 line.long 0x00 "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." group.long 0x3C++0x3 line.long 0x00 "L3_STCOL_DUMP_SLVOFS," hexmask.long 0x00 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.long 0x40++0x3 line.long 0x00 "L3_STCOL_DUMP_MANUAL," bitfld.long 0x00 0. " DUMP_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" group.long 0x44++0x3 line.long 0x00 "L3_STCOL_DUMP_SEND," bitfld.long 0x00 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.long 0x48++0x3 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN," bitfld.long 0x00 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" group.long 0x4C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_EN_k," bitfld.long 0x00 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" group.long 0x50++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." group.long 0x5C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD," bitfld.long 0x00 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" group.long 0x60++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR," bitfld.long 0x00 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" group.long 0x64++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR," bitfld.long 0x00 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" group.long 0x6C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." group.long 0x78++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD," bitfld.long 0x00 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" group.long 0x7C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR," bitfld.long 0x00 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" group.long 0x80++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR," bitfld.long 0x00 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" group.long 0x88++0x3 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL," hexmask.long.word 0x00 0.--11. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." group.long 0x8C++0x3 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL," hexmask.long.word 0x00 0.--11. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." group.long 0x90++0x3 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL," bitfld.long 0x00 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0. - . - . - ." "0,1,2,3" group.long 0x94++0x3 line.long 0x00 "L3_STCOL_OP_i_SEL," bitfld.long 0x00 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0. - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "CLK3_STATCOLL_LAT1" base ad:0x45000800 width 35. rgroup.long 0x0++0x3 line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_STCOL_EN," bitfld.long 0x00 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" group.long 0xC++0x3 line.long 0x00 "L3_STCOL_SOFTEN," bitfld.long 0x00 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" group.long 0x10++0x3 line.long 0x00 "L3_STCOL_TRIGEN," bitfld.long 0x00 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" group.long 0x14++0x3 line.long 0x00 "L3_STCOL_REQEVT," bitfld.long 0x00 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0. - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x00 "L3_STCOL_RSPEVT," bitfld.long 0x00 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0. - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x00 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x00 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x00 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x00 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" rgroup.long 0x2C++0x3 line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--1. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3" group.long 0x30++0x3 line.long 0x00 "L3_STCOL_DUMP_COLLECTTIME," hexmask.long.word 0x00 0.--15. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." rgroup.long 0x34++0x3 line.long 0x00 "L3_STCOL_DUMP_SLVADDR," bitfld.long 0x00 0.--4. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x38++0x3 line.long 0x00 "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." group.long 0x3C++0x3 line.long 0x00 "L3_STCOL_DUMP_SLVOFS," hexmask.long 0x00 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.long 0x40++0x3 line.long 0x00 "L3_STCOL_DUMP_MANUAL," bitfld.long 0x00 0. " DUMP_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" group.long 0x44++0x3 line.long 0x00 "L3_STCOL_DUMP_SEND," bitfld.long 0x00 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.long 0x48++0x3 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN," bitfld.long 0x00 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" group.long 0x4C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_EN_k," bitfld.long 0x00 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" group.long 0x50++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." group.long 0x5C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD," bitfld.long 0x00 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" group.long 0x60++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR," bitfld.long 0x00 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" group.long 0x64++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR," bitfld.long 0x00 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" group.long 0x6C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." group.long 0x78++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD," bitfld.long 0x00 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" group.long 0x7C++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR," bitfld.long 0x00 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" group.long 0x80++0x3 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR," bitfld.long 0x00 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" group.long 0x80++0x3 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL," hexmask.long.word 0x00 0.--11. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." group.long 0x8C++0x3 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL," hexmask.long.word 0x00 0.--11. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." group.long 0x90++0x3 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL," bitfld.long 0x00 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0. - . - . - ." "0,1,2,3" group.long 0x94++0x3 line.long 0x00 "L3_STCOL_OP_i_SEL," bitfld.long 0x00 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0. - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "C2C_Master_NIU_Firewall" base ad:0x4A204000 tree "REG_Bundle_1" width 18. group.long 0x94++0x3 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0x90++0x3 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_2" width 18. group.long 0xA4++0x3 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xA0++0x3 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_3" width 18. group.long 0xB4++0x3 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xB0++0x3 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end textline "" width 30. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" tree.end tree.open "CLK1_DSS_BW_REGULATOR" tree "CLK1_DSS_BW_REGULATOR" base ad:0x44000700 width 31. rgroup.long 0x0++0x3 line.long 0x00 "L3_BW_R_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_BW_R_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_BW_R_BANDWIDTH," hexmask.long.word 0x00 0.--15. 1. " BANDWIDTH ,Bandwidth, in bytes per second. Type: Control. Reset value: 0x0." group.long 0xC++0x3 line.long 0x00 "L3_BW_R_WATERMARK," hexmask.long.word 0x00 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." rgroup.long 0x10++0x3 line.long 0x00 "L3_BW_R_PRESS," bitfld.long 0x00 1. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 0. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1" group.long 0x14++0x3 line.long 0x00 "L3_BW_R_CLEARHISTORY," bitfld.long 0x00 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" tree.end tree "CLK2_ISS_BW_REGULATOR" base ad:0x44801300 width 31. rgroup.long 0x0++0x3 line.long 0x00 "L3_BW_R_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_BW_R_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_BW_R_BANDWIDTH," hexmask.long.word 0x00 0.--15. 1. " BANDWIDTH ,Bandwidth, in bytes per second. Type: Control. Reset value: 0x0." group.long 0xC++0x3 line.long 0x00 "L3_BW_R_WATERMARK," hexmask.long.word 0x00 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." rgroup.long 0x10++0x3 line.long 0x00 "L3_BW_R_PRESS," bitfld.long 0x00 1. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 0. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1" group.long 0x14++0x3 line.long 0x00 "L3_BW_R_CLEARHISTORY," bitfld.long 0x00 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" tree.end tree "CLK2_IVAHD_BW_REGULATOR" base ad:0x44801400 width 31. rgroup.long 0x0++0x3 line.long 0x00 "L3_BW_R_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_BW_R_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_BW_R_BANDWIDTH," hexmask.long.word 0x00 0.--15. 1. " BANDWIDTH ,Bandwidth, in bytes per second. Type: Control. Reset value: 0x0." group.long 0xC++0x3 line.long 0x00 "L3_BW_R_WATERMARK," hexmask.long.word 0x00 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." rgroup.long 0x10++0x3 line.long 0x00 "L3_BW_R_PRESS," bitfld.long 0x00 1. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 0. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1" group.long 0x14++0x3 line.long 0x00 "L3_BW_R_CLEARHISTORY," bitfld.long 0x00 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" tree.end tree "CLK2_SGX_BW_REGULATOR" base ad:0x44801500 width 31. rgroup.long 0x0++0x3 line.long 0x00 "L3_BW_R_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_BW_R_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." group.long 0x8++0x3 line.long 0x00 "L3_BW_R_BANDWIDTH," hexmask.long.word 0x00 0.--15. 1. " BANDWIDTH ,Bandwidth, in bytes per second. Type: Control. Reset value: 0x0." group.long 0xC++0x3 line.long 0x00 "L3_BW_R_WATERMARK," hexmask.long.word 0x00 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." rgroup.long 0x10++0x3 line.long 0x00 "L3_BW_R_PRESS," bitfld.long 0x00 1. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 0. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1" group.long 0x14++0x3 line.long 0x00 "L3_BW_R_CLEARHISTORY," bitfld.long 0x00 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" tree.end tree.end tree "GPMC_Firewall" base ad:0x4A210000 tree "REG_Bundle_0" width 32. group.long 0x8C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" width 32. group.long 0x94++0x3 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0x9C++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0x90++0x3 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_2" width 32. group.long 0xA4++0x3 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xAC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x3 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_3" width 32. group.long 0xB4++0x3 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xBC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x3 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_4" width 32. group.long 0xC4++0x3 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xCC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x3 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_5" width 32. group.long 0xD4++0x3 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xDC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x3 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_6" width 32. group.long 0xE4++0x3 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xEC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x3 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end tree "REG_Bundle_7" width 32. group.long 0xF4++0x3 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." bitfld.long 0x00 2. " REGION_ENABLE_PORT2 ,Enable this region for port 2." "0,1" bitfld.long 0x00 1. " REGION_ENABLE_PORT1 ,Enable this region for port 1." "0,1" textline " " bitfld.long 0x00 0. " REGION_ENABLE_PORT0 ,Enable this region for port 0." "0,1" group.long 0xFC++0x3 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x00 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" textline " " bitfld.long 0x00 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x00 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" textline " " bitfld.long 0x00 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x00 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" textline " " bitfld.long 0x00 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x00 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x3 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x00 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x00 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x3 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See." tree.end textline "" width 23. group.long 0x0++0x3 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" bitfld.long 0x00 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x4++0x3 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x00 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.long 0x40++0x3 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. " FW_LOAD_REQ ,Hadrdware set/Software clear" "0,1" bitfld.long 0x00 0. " BUSY_REQ ,Busy request" "0,1" tree.end tree.open "CLK1_CLK1_TARG_PWR_DISC_CLK2" tree "CLK1_CLK1_TARG_PWR_DISC_CLK2" base ad:0x44000600 width 35. rgroup.long 0x0++0x3 line.long 0x00 "L3_PWR_DISC_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x38." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_PWR_DISC_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." rgroup.long 0x8++0x3 line.long 0x00 "L3_PWR_DISC_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" group.long 0x40++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" tree.end tree "CLK2_CLK2_TARG_PWR_DISC_CLK1" base ad:0x44801100 width 35. rgroup.long 0x0++0x3 line.long 0x00 "L3_PWR_DISC_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x38." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. - . - ." "Third-party_vendor.,UNKN_MNEMO" rgroup.long 0x4++0x3 line.long 0x00 "L3_PWR_DISC_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x00 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." hexmask.long.tbyte 0x00 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." rgroup.long 0x8++0x3 line.long 0x00 "L3_PWR_DISC_STDHOSTHDR_MAINCTLREG," bitfld.long 0x00 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x00 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Loggi.." "0,1" group.long 0x40++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2. - . - . - ." "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_MAIN," bitfld.long 0x00 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" bitfld.long 0x00 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" bitfld.long 0x00 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x00 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X. - . - ." "0,1" bitfld.long 0x00 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" rgroup.long 0x4C++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_HDR," bitfld.long 0x00 18.--23. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" textline " " bitfld.long 0x00 6. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x00 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x54++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_SLVADDR," bitfld.long 0x00 0.--4. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x58++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_INFO," hexmask.long.byte 0x00 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x5C++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_SLVOFSLSB," hexmask.long 0x00 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." rgroup.long 0x60++0x3 line.long 0x00 "L3_PWR_DISC_STDERRLOG_SLVOFSMSB," bitfld.long 0x00 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" tree.end tree.end tree.end tree.open "L4_Interconnects" tree "CFG_AP" base ad:0x4A000000 tree "Channel_0" width 32. rgroup.long 0x204++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x200++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x284++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x280++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x304++0x3 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x300++0x3 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." rgroup.long 0x104++0x3 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" hexmask.long 0x00 5.--31. 1. " Reserved ,Read returns 0." bitfld.long 0x00 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x3 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." tree.end tree "Channel_1" width 32. rgroup.long 0x20C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x208++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x28C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x288++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x30C++0x3 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x308++0x3 line.long 0x00 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." rgroup.long 0x10C++0x3 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Define the size of each segments" hexmask.long 0x00 5.--31. 1. " Reserved ,Read returns 0." bitfld.long 0x00 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x108++0x3 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Define the base address of each segments" hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." tree.end tree "Channel_2" width 32. rgroup.long 0x214++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x210++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x294++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x290++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x314++0x3 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x310++0x3 line.long 0x00 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." rgroup.long 0x114++0x3 line.long 0x00 "L4_AP_SEGMENT_i_H_2,Define the size of each segments" hexmask.long 0x00 5.--31. 1. " Reserved ,Read returns 0." bitfld.long 0x00 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x110++0x3 line.long 0x00 "L4_AP_SEGMENT_i_L_2,Define the base address of each segments" hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." tree.end tree "Channel_3" width 32. rgroup.long 0x21C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x218++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x29C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x298++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x31C++0x3 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x318++0x3 line.long 0x00 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." rgroup.long 0x11C++0x3 line.long 0x00 "L4_AP_SEGMENT_i_H_3,Define the size of each segments" hexmask.long 0x00 5.--31. 1. " Reserved ,Read returns 0." bitfld.long 0x00 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x118++0x3 line.long 0x00 "L4_AP_SEGMENT_i_L_3,Define the base address of each segments" hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." tree.end tree "Channel_4" width 32. rgroup.long 0x224++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x220++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x2A4++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x2A0++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x324++0x3 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x320++0x3 line.long 0x00 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." rgroup.long 0x124++0x3 line.long 0x00 "L4_AP_SEGMENT_i_H_4,Define the size of each segments" hexmask.long 0x00 5.--31. 1. " Reserved ,Read returns 0." bitfld.long 0x00 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x120++0x3 line.long 0x00 "L4_AP_SEGMENT_i_L_4,Define the base address of each segments" hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." tree.end tree "Channel_5" width 32. rgroup.long 0x22C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x228++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x2AC++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x2A8++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x32C++0x3 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x328++0x3 line.long 0x00 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." rgroup.long 0x12C++0x3 line.long 0x00 "L4_AP_SEGMENT_i_H_5,Define the size of each segments" hexmask.long 0x00 5.--31. 1. " Reserved ,Read returns 0." bitfld.long 0x00 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x128++0x3 line.long 0x00 "L4_AP_SEGMENT_i_L_5,Define the base address of each segments" hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." tree.end tree "Channel_6" width 32. rgroup.long 0x234++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x230++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x2B4++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x2B0++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x334++0x3 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x330++0x3 line.long 0x00 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." rgroup.long 0x134++0x3 line.long 0x00 "L4_AP_SEGMENT_i_H_6,Define the size of each segments" hexmask.long 0x00 5.--31. 1. " Reserved ,Read returns 0." bitfld.long 0x00 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x130++0x3 line.long 0x00 "L4_AP_SEGMENT_i_L_6,Define the base address of each segments" hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." tree.end tree "Channel_7" width 32. rgroup.long 0x23C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x238++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x2BC++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x2B8++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x33C++0x3 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x338++0x3 line.long 0x00 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_8" width 20. group.long 0x344++0x3 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x340++0x3 line.long 0x00 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_9" width 20. group.long 0x34C++0x3 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x348++0x3 line.long 0x00 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_10" width 21. group.long 0x354++0x3 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x350++0x3 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_11" width 21. group.long 0x35C++0x3 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x358++0x3 line.long 0x00 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_12" width 21. group.long 0x364++0x3 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x360++0x3 line.long 0x00 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_13" width 21. group.long 0x36C++0x3 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x368++0x3 line.long 0x00 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_14" width 21. group.long 0x374++0x3 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x370++0x3 line.long 0x00 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_15" width 21. group.long 0x37C++0x3 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x378++0x3 line.long 0x00 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_16" width 21. group.long 0x384++0x3 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x380++0x3 line.long 0x00 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_17" width 21. group.long 0x38C++0x3 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x388++0x3 line.long 0x00 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_18" width 21. group.long 0x394++0x3 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x390++0x3 line.long 0x00 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_19" width 21. group.long 0x39C++0x3 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x398++0x3 line.long 0x00 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_20" width 21. group.long 0x3A4++0x3 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3A0++0x3 line.long 0x00 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_21" width 21. group.long 0x3AC++0x3 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3A8++0x3 line.long 0x00 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_22" width 21. group.long 0x3B4++0x3 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3B0++0x3 line.long 0x00 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_23" width 21. group.long 0x3BC++0x3 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3B8++0x3 line.long 0x00 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_24" width 21. group.long 0x3C4++0x3 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3C0++0x3 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_25" width 21. group.long 0x3CC++0x3 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3C8++0x3 line.long 0x00 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_26" width 21. group.long 0x3D4++0x3 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3D0++0x3 line.long 0x00 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_27" width 21. group.long 0x3DC++0x3 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3D8++0x3 line.long 0x00 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_28" width 21. group.long 0x3E4++0x3 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3E0++0x3 line.long 0x00 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_29" width 21. group.long 0x3EC++0x3 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3E8++0x3 line.long 0x00 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_30" width 21. group.long 0x3F4++0x3 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3F0++0x3 line.long 0x00 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_31" width 21. group.long 0x3FC++0x3 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3F8++0x3 line.long 0x00 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_32" width 21. group.long 0x404++0x3 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x400++0x3 line.long 0x00 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_33" width 21. group.long 0x40C++0x3 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x408++0x3 line.long 0x00 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_34" width 21. group.long 0x414++0x3 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x410++0x3 line.long 0x00 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_35" width 21. group.long 0x41C++0x3 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x418++0x3 line.long 0x00 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_36" width 21. group.long 0x424++0x3 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x420++0x3 line.long 0x00 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_37" width 21. group.long 0x42C++0x3 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x428++0x3 line.long 0x00 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_38" width 21. group.long 0x434++0x3 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x430++0x3 line.long 0x00 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_39" width 21. group.long 0x43C++0x3 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x438++0x3 line.long 0x00 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_40" width 21. group.long 0x444++0x3 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x440++0x3 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_41" width 21. group.long 0x44C++0x3 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x448++0x3 line.long 0x00 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_42" width 21. group.long 0x454++0x3 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x450++0x3 line.long 0x00 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_43" width 21. group.long 0x45C++0x3 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x458++0x3 line.long 0x00 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_44" width 21. group.long 0x464++0x3 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x460++0x3 line.long 0x00 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_45" width 21. group.long 0x46C++0x3 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x468++0x3 line.long 0x00 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_46" width 21. group.long 0x474++0x3 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x470++0x3 line.long 0x00 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_47" width 21. group.long 0x47C++0x3 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x478++0x3 line.long 0x00 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_48" width 21. group.long 0x484++0x3 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x480++0x3 line.long 0x00 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_49" width 21. group.long 0x48C++0x3 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x488++0x3 line.long 0x00 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_50" width 21. group.long 0x494++0x3 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x490++0x3 line.long 0x00 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_51" width 21. group.long 0x49C++0x3 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x498++0x3 line.long 0x00 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_52" width 21. group.long 0x4A4++0x3 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4A0++0x3 line.long 0x00 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_53" width 21. group.long 0x4AC++0x3 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4A8++0x3 line.long 0x00 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_54" width 21. group.long 0x4B4++0x3 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4B0++0x3 line.long 0x00 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_55" width 21. group.long 0x4BC++0x3 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4B8++0x3 line.long 0x00 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_56" width 21. group.long 0x4C4++0x3 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4C0++0x3 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_57" width 21. group.long 0x4CC++0x3 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4C8++0x3 line.long 0x00 "L4_AP_REGION_l_L_57,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_58" width 21. group.long 0x4D4++0x3 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4D0++0x3 line.long 0x00 "L4_AP_REGION_l_L_58,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_59" width 21. group.long 0x4DC++0x3 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4D8++0x3 line.long 0x00 "L4_AP_REGION_l_L_59,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_60" width 21. group.long 0x4E4++0x3 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4E0++0x3 line.long 0x00 "L4_AP_REGION_l_L_60,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_61" width 21. group.long 0x4EC++0x3 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4E8++0x3 line.long 0x00 "L4_AP_REGION_l_L_61,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_62" width 21. group.long 0x4F4++0x3 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4F0++0x3 line.long 0x00 "L4_AP_REGION_l_L_62,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_63" width 21. group.long 0x4FC++0x3 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4F8++0x3 line.long 0x00 "L4_AP_REGION_l_L_63,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_64" width 21. group.long 0x504++0x3 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x500++0x3 line.long 0x00 "L4_AP_REGION_l_L_64,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_65" width 21. group.long 0x50C++0x3 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x508++0x3 line.long 0x00 "L4_AP_REGION_l_L_65,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_66" width 21. group.long 0x514++0x3 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x510++0x3 line.long 0x00 "L4_AP_REGION_l_L_66,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_67" width 21. group.long 0x51C++0x3 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x518++0x3 line.long 0x00 "L4_AP_REGION_l_L_67,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_68" width 21. group.long 0x524++0x3 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x520++0x3 line.long 0x00 "L4_AP_REGION_l_L_68,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_69" width 21. group.long 0x52C++0x3 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x528++0x3 line.long 0x00 "L4_AP_REGION_l_L_69,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_70" width 21. group.long 0x534++0x3 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x530++0x3 line.long 0x00 "L4_AP_REGION_l_L_70,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_71" width 21. group.long 0x53C++0x3 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x538++0x3 line.long 0x00 "L4_AP_REGION_l_L_71,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_72" width 21. group.long 0x544++0x3 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x540++0x3 line.long 0x00 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_73" width 21. group.long 0x54C++0x3 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x548++0x3 line.long 0x00 "L4_AP_REGION_l_L_73,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_74" width 21. group.long 0x554++0x3 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x550++0x3 line.long 0x00 "L4_AP_REGION_l_L_74,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_75" width 21. group.long 0x55C++0x3 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x558++0x3 line.long 0x00 "L4_AP_REGION_l_L_75,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_76" width 21. group.long 0x564++0x3 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x560++0x3 line.long 0x00 "L4_AP_REGION_l_L_76,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_77" width 21. group.long 0x56C++0x3 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x568++0x3 line.long 0x00 "L4_AP_REGION_l_L_77,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_78" width 21. group.long 0x574++0x3 line.long 0x00 "L4_AP_REGION_l_H_78,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x570++0x3 line.long 0x00 "L4_AP_REGION_l_L_78,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_79" width 21. group.long 0x57C++0x3 line.long 0x00 "L4_AP_REGION_l_H_79,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x578++0x3 line.long 0x00 "L4_AP_REGION_l_L_79,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_80" width 21. group.long 0x584++0x3 line.long 0x00 "L4_AP_REGION_l_H_80,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x580++0x3 line.long 0x00 "L4_AP_REGION_l_L_80,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_81" width 21. group.long 0x58C++0x3 line.long 0x00 "L4_AP_REGION_l_H_81,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x588++0x3 line.long 0x00 "L4_AP_REGION_l_L_81,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_82" width 21. group.long 0x594++0x3 line.long 0x00 "L4_AP_REGION_l_H_82,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x590++0x3 line.long 0x00 "L4_AP_REGION_l_L_82,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_83" width 21. group.long 0x59C++0x3 line.long 0x00 "L4_AP_REGION_l_H_83,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x598++0x3 line.long 0x00 "L4_AP_REGION_l_L_83,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_84" width 21. group.long 0x5A4++0x3 line.long 0x00 "L4_AP_REGION_l_H_84,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5A0++0x3 line.long 0x00 "L4_AP_REGION_l_L_84,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_85" width 21. group.long 0x5AC++0x3 line.long 0x00 "L4_AP_REGION_l_H_85,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5A8++0x3 line.long 0x00 "L4_AP_REGION_l_L_85,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_86" width 21. group.long 0x5B4++0x3 line.long 0x00 "L4_AP_REGION_l_H_86,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5B0++0x3 line.long 0x00 "L4_AP_REGION_l_L_86,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_87" width 21. group.long 0x5BC++0x3 line.long 0x00 "L4_AP_REGION_l_H_87,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5B8++0x3 line.long 0x00 "L4_AP_REGION_l_L_87,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_88" width 21. group.long 0x5C4++0x3 line.long 0x00 "L4_AP_REGION_l_H_88,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5C0++0x3 line.long 0x00 "L4_AP_REGION_l_L_88,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_89" width 21. group.long 0x5CC++0x3 line.long 0x00 "L4_AP_REGION_l_H_89,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5C8++0x3 line.long 0x00 "L4_AP_REGION_l_L_89,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_90" width 21. group.long 0x5D4++0x3 line.long 0x00 "L4_AP_REGION_l_H_90,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5D0++0x3 line.long 0x00 "L4_AP_REGION_l_L_90,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_91" width 21. group.long 0x5DC++0x3 line.long 0x00 "L4_AP_REGION_l_H_91,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5D8++0x3 line.long 0x00 "L4_AP_REGION_l_L_91,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_92" width 21. group.long 0x5E4++0x3 line.long 0x00 "L4_AP_REGION_l_H_92,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5E0++0x3 line.long 0x00 "L4_AP_REGION_l_L_92,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_93" width 21. group.long 0x5EC++0x3 line.long 0x00 "L4_AP_REGION_l_H_93,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5E8++0x3 line.long 0x00 "L4_AP_REGION_l_L_93,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_94" width 21. group.long 0x5F4++0x3 line.long 0x00 "L4_AP_REGION_l_H_94,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5F0++0x3 line.long 0x00 "L4_AP_REGION_l_L_94,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_95" width 21. group.long 0x5FC++0x3 line.long 0x00 "L4_AP_REGION_l_H_95,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5F8++0x3 line.long 0x00 "L4_AP_REGION_l_L_95,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_96" width 21. group.long 0x604++0x3 line.long 0x00 "L4_AP_REGION_l_H_96,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x600++0x3 line.long 0x00 "L4_AP_REGION_l_L_96,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_97" width 21. group.long 0x60C++0x3 line.long 0x00 "L4_AP_REGION_l_H_97,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x608++0x3 line.long 0x00 "L4_AP_REGION_l_L_97,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_98" width 21. group.long 0x614++0x3 line.long 0x00 "L4_AP_REGION_l_H_98,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x610++0x3 line.long 0x00 "L4_AP_REGION_l_L_98,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_99" width 21. group.long 0x61C++0x3 line.long 0x00 "L4_AP_REGION_l_H_99,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x618++0x3 line.long 0x00 "L4_AP_REGION_l_L_99,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_100" width 22. group.long 0x624++0x3 line.long 0x00 "L4_AP_REGION_l_H_100,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x620++0x3 line.long 0x00 "L4_AP_REGION_l_L_100,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_101" width 22. group.long 0x62C++0x3 line.long 0x00 "L4_AP_REGION_l_H_101,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x628++0x3 line.long 0x00 "L4_AP_REGION_l_L_101,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_102" width 22. group.long 0x634++0x3 line.long 0x00 "L4_AP_REGION_l_H_102,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x630++0x3 line.long 0x00 "L4_AP_REGION_l_L_102,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_103" width 22. group.long 0x63C++0x3 line.long 0x00 "L4_AP_REGION_l_H_103,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x638++0x3 line.long 0x00 "L4_AP_REGION_l_L_103,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_104" width 22. group.long 0x644++0x3 line.long 0x00 "L4_AP_REGION_l_H_104,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x640++0x3 line.long 0x00 "L4_AP_REGION_l_L_104,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_105" width 22. group.long 0x64C++0x3 line.long 0x00 "L4_AP_REGION_l_H_105,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x648++0x3 line.long 0x00 "L4_AP_REGION_l_L_105,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_106" width 22. group.long 0x654++0x3 line.long 0x00 "L4_AP_REGION_l_H_106,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x650++0x3 line.long 0x00 "L4_AP_REGION_l_L_106,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_107" width 22. group.long 0x65C++0x3 line.long 0x00 "L4_AP_REGION_l_H_107,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x658++0x3 line.long 0x00 "L4_AP_REGION_l_L_107,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_108" width 22. group.long 0x664++0x3 line.long 0x00 "L4_AP_REGION_l_H_108,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x660++0x3 line.long 0x00 "L4_AP_REGION_l_L_108,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_109" width 22. group.long 0x66C++0x3 line.long 0x00 "L4_AP_REGION_l_H_109,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x668++0x3 line.long 0x00 "L4_AP_REGION_l_L_109,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_110" width 22. group.long 0x674++0x3 line.long 0x00 "L4_AP_REGION_l_H_110,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x670++0x3 line.long 0x00 "L4_AP_REGION_l_L_110,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_111" width 22. group.long 0x67C++0x3 line.long 0x00 "L4_AP_REGION_l_H_111,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x678++0x3 line.long 0x00 "L4_AP_REGION_l_L_111,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_112" width 22. group.long 0x684++0x3 line.long 0x00 "L4_AP_REGION_l_H_112,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x680++0x3 line.long 0x00 "L4_AP_REGION_l_L_112,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_113" width 22. group.long 0x68C++0x3 line.long 0x00 "L4_AP_REGION_l_H_113,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x688++0x3 line.long 0x00 "L4_AP_REGION_l_L_113,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end textline "" width 19. rgroup.long 0x0++0x3 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code" hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code" rgroup.long 0x4++0x3 line.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0" tree.end tree.open "PER_TA_UART3" tree "PER_TA_UART3" base ad:0x48021000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPTIMER2" base ad:0x48033000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPTIMER3" base ad:0x48035000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPTIMER4" base ad:0x48037000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPTIMER9" base ad:0x4803F000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_DSS" base ad:0x48050000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPIO2" base ad:0x48056000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPIO3" base ad:0x48058000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPIO4" base ad:0x4805A000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPIO5" base ad:0x4805C000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPIO6" base ad:0x4805E000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_I2C3" base ad:0x48061000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_UART1" base ad:0x4806B000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_UART2" base ad:0x4806D000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_UART4" base ad:0x4806F000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_I2C1" base ad:0x48071000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_I2C2" base ad:0x48073000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_SLIMBUS2" base ad:0x48077000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_ELM" base ad:0x48079000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPTIMER10" base ad:0x48087000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_GPTIMER11" base ad:0x48089000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_MCBSP4" base ad:0x48097000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_MCSPI1" base ad:0x48099000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_MCSPI2" base ad:0x4809B000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_HSMMC1" base ad:0x4809D000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_HSMMC3" base ad:0x480AE000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_HDQ" base ad:0x480B3000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_HSMMC2" base ad:0x480B5000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_MCSPI3" base ad:0x480B9000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_MCSPI4" base ad:0x480BB000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_HSMMC4" base ad:0x480D2000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_HSMMC5" base ad:0x480D6000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER_TA_I2C4" base ad:0x48351000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SYSCTRL_GENERAL_CORE" base ad:0x4A003000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_CM1" base ad:0x4A005000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_CM2" base ad:0x4A00A000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SDMA" base ad:0x4A057000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_HSI" base ad:0x4A05C000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SAR_ROM" base ad:0x4A060000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_HSUSBTLL" base ad:0x4A063000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_USBHOSTHS" base ad:0x4A065000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_DSP" base ad:0x4A067000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_USBFS" base ad:0x4A0AA000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_USBOTGHS" base ad:0x4A0AC000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_USBPHY" base ad:0x4A0AE000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SR1" base ad:0x4A0DA000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SR2" base ad:0x4A0DC000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SR3" base ad:0x4A0DE000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_MAILBOX" base ad:0x4A0F5000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SPINLOCK" base ad:0x4A0F7000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SYSCTRL_PADCONF_CORE" base ad:0x4A101000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_FACEDETECT" base ad:0x4A10B000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_EMIFFW" base ad:0x4A20D000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_GPMCFW" base ad:0x4A211000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_OCMCRAMFW" base ad:0x4A213000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SGXFW" base ad:0x4A215000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_ISSFW" base ad:0x4A217000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_CORTEXM3FW" base ad:0x4A219000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_DSSFW" base ad:0x4A21D000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_SL2FW" base ad:0x4A21F000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_IVAHDFW" base ad:0x4A221000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_EMUSSFW" base ad:0x4A227000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_ABEFW" base ad:0x4A229000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_32KTIMER" base ad:0x4A305000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_PRM" base ad:0x4A308000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_SCRM" base ad:0x4A30B000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_SYSCTRL_GENERAL_WKUP" base ad:0x4A30D000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_GPIO1" base ad:0x4A311000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_WDTIMER2" base ad:0x4A315000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_DM_TIMER1MS_1" base ad:0x4A319000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_KEYBOARD" base ad:0x4A31D000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_SYSCTRL_PADCONF_WKUP" base ad:0x4A31F000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_TA_SAR_RAM" base ad:0x4A32A000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CFG_TA_L4WKUP" base ad:0x4A340000 width 23. group.long 0x0++0x3 line.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision." rgroup.long 0x4++0x3 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." rgroup.long 0x18++0x3 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x00 24. " SERROR_REP ,Enable logging of error" "0,1" bitfld.long 0x00 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are:0 - No time-out1 - 1x base cycles.2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset featur.." "0,1" rgroup.long 0x24++0x3 line.long 0x00 "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" hgroup.long 0x28++0x3 hide.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" in group.long 0x2C++0x3 line.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree.end tree.open "PER_LA" tree "PER_LA" base ad:0x48000800 width 25. rgroup.long 0x0++0x3 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." group.long 0x4++0x3 line.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision, which are used to identify the hardware of the component." group.long 0x10++0x3 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x3 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" hexmask.long 0x00 0.--31. 1. " ID ,The ID field uniquely identifies this interconnect." rgroup.long 0x18++0x3 line.long 0x00 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information." bitfld.long 0x00 24.--27. " PROT_GROUPS ,Number of protection group of in the current L40x0: No protection group0x1: 1 protection group0x2: 2 protection groups....0x8: 8 protection groups0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_REGIONS ,Number of regions in the current L40x0: Reserved0x1: 1 region0x2: 2 regions....Max regions +1 to 0xFF: Reserved, maximum regions is listed in" bitfld.long 0x00 0.--3. " SEGMENTS ,Number of segments in the current L40x0: Reserved0x1: 1 segment0x2: 2 segments....0x8: 8 segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1C++0x3 line.long 0x00 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information." bitfld.long 0x00 16.--18. " THREADS ,The THREADS field specifies the number of initiator threads connected to the interconnect. The field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CONNID_WIDTH ,The initiator subsystem ConnID width. The CONNID_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " BYTE_DATA_WIDTH_EXP ,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem.0x1: 16-bit data width is specified 0x2: 32-bit data width is speci.." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " ADDR_WIDTH ,This field specifies the initiator subsystem address width. The ADDR_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x3 line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values." bitfld.long 0x00 8.--10. " TIMEOUT_BASE ,The TIMEOUT_BASE field indicates the time-out period (that is, base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled. Values for the field are:0.." "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x00 24. " CLOCK_GATE_DISABLE ,When set to 1 this field disables all clock gating." "0,1" bitfld.long 0x00 20. " THREAD0_PRI ,Sets thread priority. If the field is set to 0, the default, all initiator threads are treated the same. Setting the THREAD0_PRI field to 1 assigns a higher arbitration priority to thread 0 of the first initiator OCP interface..." "0,1" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on the initiator subsystem instructs the entire L4 to shut off." "0,1" tree.end tree "CFG_LA" base ad:0x4A000800 width 25. rgroup.long 0x0++0x3 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." group.long 0x4++0x3 line.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision, which are used to identify the hardware of the component." group.long 0x10++0x3 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x3 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" hexmask.long 0x00 0.--31. 1. " ID ,The ID field uniquely identifies this interconnect." rgroup.long 0x18++0x3 line.long 0x00 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information." bitfld.long 0x00 24.--27. " PROT_GROUPS ,Number of protection group of in the current L40x0: No protection group0x1: 1 protection group0x2: 2 protection groups....0x8: 8 protection groups0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_REGIONS ,Number of regions in the current L40x0: Reserved0x1: 1 region0x2: 2 regions....Max regions +1 to 0xFF: Reserved, maximum regions is listed in" bitfld.long 0x00 0.--3. " SEGMENTS ,Number of segments in the current L40x0: Reserved0x1: 1 segment0x2: 2 segments....0x8: 8 segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1C++0x3 line.long 0x00 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information." bitfld.long 0x00 16.--18. " THREADS ,The THREADS field specifies the number of initiator threads connected to the interconnect. The field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CONNID_WIDTH ,The initiator subsystem ConnID width. The CONNID_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " BYTE_DATA_WIDTH_EXP ,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem.0x1: 16-bit data width is specified 0x2: 32-bit data width is speci.." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " ADDR_WIDTH ,This field specifies the initiator subsystem address width. The ADDR_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x3 line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values." bitfld.long 0x00 8.--10. " TIMEOUT_BASE ,The TIMEOUT_BASE field indicates the time-out period (that is, base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled. Values for the field are:0.." "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x00 24. " CLOCK_GATE_DISABLE ,When set to 1 this field disables all clock gating." "0,1" bitfld.long 0x00 20. " THREAD0_PRI ,Sets thread priority. If the field is set to 0, the default, all initiator threads are treated the same. Setting the THREAD0_PRI field to 1 assigns a higher arbitration priority to thread 0 of the first initiator OCP interface..." "0,1" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on the initiator subsystem instructs the entire L4 to shut off." "0,1" tree.end tree "WKUP_LA" base ad:0x4A300800 width 25. rgroup.long 0x0++0x3 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code." hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code." group.long 0x4++0x3 line.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision, which are used to identify the hardware of the component." group.long 0x10++0x3 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x3 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" hexmask.long 0x00 0.--31. 1. " ID ,The ID field uniquely identifies this interconnect." rgroup.long 0x18++0x3 line.long 0x00 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information." bitfld.long 0x00 24.--27. " PROT_GROUPS ,Number of protection group of in the current L40x0: No protection group0x1: 1 protection group0x2: 2 protection groups....0x8: 8 protection groups0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_REGIONS ,Number of regions in the current L40x0: Reserved0x1: 1 region0x2: 2 regions....Max regions +1 to 0xFF: Reserved, maximum regions is listed in" bitfld.long 0x00 0.--3. " SEGMENTS ,Number of segments in the current L40x0: Reserved0x1: 1 segment0x2: 2 segments....0x8: 8 segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1C++0x3 line.long 0x00 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information." bitfld.long 0x00 16.--18. " THREADS ,The THREADS field specifies the number of initiator threads connected to the interconnect. The field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CONNID_WIDTH ,The initiator subsystem ConnID width. The CONNID_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " BYTE_DATA_WIDTH_EXP ,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem.0x1: 16-bit data width is specified 0x2: 32-bit data width is speci.." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--4. " ADDR_WIDTH ,This field specifies the initiator subsystem address width. The ADDR_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x3 line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values." bitfld.long 0x00 8.--10. " TIMEOUT_BASE ,The TIMEOUT_BASE field indicates the time-out period (that is, base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled. Values for the field are:0.." "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x00 24. " CLOCK_GATE_DISABLE ,When set to 1 this field disables all clock gating." "0,1" bitfld.long 0x00 20. " THREAD0_PRI ,Sets thread priority. If the field is set to 0, the default, all initiator threads are treated the same. Setting the THREAD0_PRI field to 1 assigns a higher arbitration priority to thread 0 of the first initiator OCP interface..." "0,1" bitfld.long 0x00 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on the initiator subsystem instructs the entire L4 to shut off." "0,1" tree.end tree.end tree "PER_AP" base ad:0x48000000 tree "Channel_0" width 32. rgroup.long 0x204++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x200++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x284++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x280++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x304++0x3 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x300++0x3 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." rgroup.long 0x104++0x3 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" hexmask.long 0x00 5.--31. 1. " Reserved ,Read returns 0." bitfld.long 0x00 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x3 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." tree.end tree "Channel_1" width 32. rgroup.long 0x20C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x208++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x28C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x288++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x30C++0x3 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x308++0x3 line.long 0x00 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." rgroup.long 0x10C++0x3 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Define the size of each segments" hexmask.long 0x00 5.--31. 1. " Reserved ,Read returns 0." bitfld.long 0x00 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x108++0x3 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Define the base address of each segments" hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." tree.end tree "Channel_2" width 32. rgroup.long 0x214++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x210++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x294++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x290++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x314++0x3 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x310++0x3 line.long 0x00 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "Channel_3" width 32. rgroup.long 0x21C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x218++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x29C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x298++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x31C++0x3 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x318++0x3 line.long 0x00 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "Channel_4" width 32. rgroup.long 0x224++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x220++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x2A4++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x2A0++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x324++0x3 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x320++0x3 line.long 0x00 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "Channel_5" width 32. rgroup.long 0x22C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x228++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x2AC++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x2A8++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x32C++0x3 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x328++0x3 line.long 0x00 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "Channel_6" width 32. rgroup.long 0x234++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x230++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x2B4++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x2B0++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x334++0x3 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x330++0x3 line.long 0x00 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "Channel_7" width 32. rgroup.long 0x23C++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" group.long 0x238++0x3 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,?..." bitfld.long 0x00 15. " DMM_PAGE_TABLE_WALK ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 14. " PERF_PROBE ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 13. " Reserved ,?..." "0,1" bitfld.long 0x00 12. " HS_USB_HOST_USB ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 11. " Reserved ,?..." "0,1" textline " " bitfld.long 0x00 10. " MMC1_MMC2 ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 9. " HSI ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 8. " C2C ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 7. " DSS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 6. " SGX ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 5. " sDMA ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 4. " CAM_CORTEXA9_MPU_SS_FACE_DETECT ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 3. " IVA_HD ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 2. " DSP_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" textline " " bitfld.long 0x00 1. " DAP ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" bitfld.long 0x00 0. " CORTEXM3_MPU_SS ,Included in the protection group k0x0: Not a member0x1: Member" "0,1" rgroup.long 0x2BC++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0's" rgroup.long 0x2B8++0x3 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group." hexmask.long.word 0x00 16.--31. 1. " Reserved ,Read returns 0" hexmask.long.word 0x00 0.--15. 1. " ENABLE ,Setting of type acces allowed for the group of initiators." group.long 0x33C++0x3 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x338++0x3 line.long 0x00 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_8" width 20. group.long 0x344++0x3 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x340++0x3 line.long 0x00 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_9" width 20. group.long 0x34C++0x3 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x348++0x3 line.long 0x00 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_10" width 21. group.long 0x354++0x3 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x350++0x3 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_11" width 21. group.long 0x35C++0x3 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x358++0x3 line.long 0x00 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_12" width 21. group.long 0x364++0x3 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x360++0x3 line.long 0x00 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_13" width 21. group.long 0x36C++0x3 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x368++0x3 line.long 0x00 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_14" width 21. group.long 0x374++0x3 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x370++0x3 line.long 0x00 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_15" width 21. group.long 0x37C++0x3 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x378++0x3 line.long 0x00 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_16" width 21. group.long 0x384++0x3 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x380++0x3 line.long 0x00 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_17" width 21. group.long 0x38C++0x3 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x388++0x3 line.long 0x00 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_18" width 21. group.long 0x394++0x3 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x390++0x3 line.long 0x00 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_19" width 21. group.long 0x39C++0x3 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x398++0x3 line.long 0x00 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_20" width 21. group.long 0x3A4++0x3 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3A0++0x3 line.long 0x00 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_21" width 21. group.long 0x3AC++0x3 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3A8++0x3 line.long 0x00 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_22" width 21. group.long 0x3B4++0x3 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3B0++0x3 line.long 0x00 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_23" width 21. group.long 0x3BC++0x3 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3B8++0x3 line.long 0x00 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_24" width 21. group.long 0x3C4++0x3 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3C0++0x3 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_25" width 21. group.long 0x3CC++0x3 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3C8++0x3 line.long 0x00 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_26" width 21. group.long 0x3D4++0x3 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3D0++0x3 line.long 0x00 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_27" width 21. group.long 0x3DC++0x3 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3D8++0x3 line.long 0x00 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_28" width 21. group.long 0x3E4++0x3 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3E0++0x3 line.long 0x00 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_29" width 21. group.long 0x3EC++0x3 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3E8++0x3 line.long 0x00 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_30" width 21. group.long 0x3F4++0x3 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3F0++0x3 line.long 0x00 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_31" width 21. group.long 0x3FC++0x3 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x3F8++0x3 line.long 0x00 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_32" width 21. group.long 0x404++0x3 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x400++0x3 line.long 0x00 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_33" width 21. group.long 0x40C++0x3 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x408++0x3 line.long 0x00 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_34" width 21. group.long 0x414++0x3 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x410++0x3 line.long 0x00 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_35" width 21. group.long 0x41C++0x3 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x418++0x3 line.long 0x00 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_36" width 21. group.long 0x424++0x3 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x420++0x3 line.long 0x00 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_37" width 21. group.long 0x42C++0x3 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x428++0x3 line.long 0x00 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_38" width 21. group.long 0x434++0x3 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x430++0x3 line.long 0x00 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_39" width 21. group.long 0x43C++0x3 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x438++0x3 line.long 0x00 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_40" width 21. group.long 0x444++0x3 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x440++0x3 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_41" width 21. group.long 0x44C++0x3 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x448++0x3 line.long 0x00 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_42" width 21. group.long 0x454++0x3 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x450++0x3 line.long 0x00 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_43" width 21. group.long 0x45C++0x3 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x458++0x3 line.long 0x00 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_44" width 21. group.long 0x464++0x3 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x460++0x3 line.long 0x00 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_45" width 21. group.long 0x46C++0x3 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x468++0x3 line.long 0x00 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_46" width 21. group.long 0x474++0x3 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x470++0x3 line.long 0x00 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_47" width 21. group.long 0x47C++0x3 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x478++0x3 line.long 0x00 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_48" width 21. group.long 0x484++0x3 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x480++0x3 line.long 0x00 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_49" width 21. group.long 0x48C++0x3 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x488++0x3 line.long 0x00 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_50" width 21. group.long 0x494++0x3 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x490++0x3 line.long 0x00 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_51" width 21. group.long 0x49C++0x3 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x498++0x3 line.long 0x00 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_52" width 21. group.long 0x4A4++0x3 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4A0++0x3 line.long 0x00 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_53" width 21. group.long 0x4AC++0x3 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4A8++0x3 line.long 0x00 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_54" width 21. group.long 0x4B4++0x3 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4B0++0x3 line.long 0x00 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_55" width 21. group.long 0x4BC++0x3 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4B8++0x3 line.long 0x00 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_56" width 21. group.long 0x4C4++0x3 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4C0++0x3 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_57" width 21. group.long 0x4CC++0x3 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4C8++0x3 line.long 0x00 "L4_AP_REGION_l_L_57,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_58" width 21. group.long 0x4D4++0x3 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4D0++0x3 line.long 0x00 "L4_AP_REGION_l_L_58,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_59" width 21. group.long 0x4DC++0x3 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4D8++0x3 line.long 0x00 "L4_AP_REGION_l_L_59,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_60" width 21. group.long 0x4E4++0x3 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4E0++0x3 line.long 0x00 "L4_AP_REGION_l_L_60,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_61" width 21. group.long 0x4EC++0x3 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4E8++0x3 line.long 0x00 "L4_AP_REGION_l_L_61,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_62" width 21. group.long 0x4F4++0x3 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4F0++0x3 line.long 0x00 "L4_AP_REGION_l_L_62,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_63" width 21. group.long 0x4FC++0x3 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x4F8++0x3 line.long 0x00 "L4_AP_REGION_l_L_63,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_64" width 21. group.long 0x504++0x3 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x500++0x3 line.long 0x00 "L4_AP_REGION_l_L_64,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_65" width 21. group.long 0x50C++0x3 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x508++0x3 line.long 0x00 "L4_AP_REGION_l_L_65,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_66" width 21. group.long 0x514++0x3 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x510++0x3 line.long 0x00 "L4_AP_REGION_l_L_66,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_67" width 21. group.long 0x51C++0x3 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x518++0x3 line.long 0x00 "L4_AP_REGION_l_L_67,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_68" width 21. group.long 0x524++0x3 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x520++0x3 line.long 0x00 "L4_AP_REGION_l_L_68,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_69" width 21. group.long 0x52C++0x3 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x528++0x3 line.long 0x00 "L4_AP_REGION_l_L_69,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_70" width 21. group.long 0x534++0x3 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x530++0x3 line.long 0x00 "L4_AP_REGION_l_L_70,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_71" width 21. group.long 0x53C++0x3 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x538++0x3 line.long 0x00 "L4_AP_REGION_l_L_71,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_72" width 21. group.long 0x544++0x3 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x540++0x3 line.long 0x00 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_73" width 21. group.long 0x54C++0x3 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x548++0x3 line.long 0x00 "L4_AP_REGION_l_L_73,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_74" width 21. group.long 0x554++0x3 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x550++0x3 line.long 0x00 "L4_AP_REGION_l_L_74,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_75" width 21. group.long 0x55C++0x3 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x558++0x3 line.long 0x00 "L4_AP_REGION_l_L_75,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_76" width 21. group.long 0x564++0x3 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x560++0x3 line.long 0x00 "L4_AP_REGION_l_L_76,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_77" width 21. group.long 0x56C++0x3 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x568++0x3 line.long 0x00 "L4_AP_REGION_l_L_77,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_78" width 21. group.long 0x574++0x3 line.long 0x00 "L4_AP_REGION_l_H_78,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x570++0x3 line.long 0x00 "L4_AP_REGION_l_L_78,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_79" width 21. group.long 0x57C++0x3 line.long 0x00 "L4_AP_REGION_l_H_79,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x578++0x3 line.long 0x00 "L4_AP_REGION_l_L_79,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_80" width 21. group.long 0x584++0x3 line.long 0x00 "L4_AP_REGION_l_H_80,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x580++0x3 line.long 0x00 "L4_AP_REGION_l_L_80,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_81" width 21. group.long 0x58C++0x3 line.long 0x00 "L4_AP_REGION_l_H_81,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x588++0x3 line.long 0x00 "L4_AP_REGION_l_L_81,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_82" width 21. group.long 0x594++0x3 line.long 0x00 "L4_AP_REGION_l_H_82,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x590++0x3 line.long 0x00 "L4_AP_REGION_l_L_82,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_83" width 21. group.long 0x59C++0x3 line.long 0x00 "L4_AP_REGION_l_H_83,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x598++0x3 line.long 0x00 "L4_AP_REGION_l_L_83,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_84" width 21. group.long 0x5A4++0x3 line.long 0x00 "L4_AP_REGION_l_H_84,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5A0++0x3 line.long 0x00 "L4_AP_REGION_l_L_84,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_85" width 21. group.long 0x5AC++0x3 line.long 0x00 "L4_AP_REGION_l_H_85,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5A8++0x3 line.long 0x00 "L4_AP_REGION_l_L_85,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_86" width 21. group.long 0x5B4++0x3 line.long 0x00 "L4_AP_REGION_l_H_86,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5B0++0x3 line.long 0x00 "L4_AP_REGION_l_L_86,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_87" width 21. group.long 0x5BC++0x3 line.long 0x00 "L4_AP_REGION_l_H_87,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5B8++0x3 line.long 0x00 "L4_AP_REGION_l_L_87,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_88" width 21. group.long 0x5C4++0x3 line.long 0x00 "L4_AP_REGION_l_H_88,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5C0++0x3 line.long 0x00 "L4_AP_REGION_l_L_88,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_89" width 21. group.long 0x5CC++0x3 line.long 0x00 "L4_AP_REGION_l_H_89,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5C8++0x3 line.long 0x00 "L4_AP_REGION_l_L_89,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_90" width 21. group.long 0x5D4++0x3 line.long 0x00 "L4_AP_REGION_l_H_90,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5D0++0x3 line.long 0x00 "L4_AP_REGION_l_L_90,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_91" width 21. group.long 0x5DC++0x3 line.long 0x00 "L4_AP_REGION_l_H_91,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5D8++0x3 line.long 0x00 "L4_AP_REGION_l_L_91,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_92" width 21. group.long 0x5E4++0x3 line.long 0x00 "L4_AP_REGION_l_H_92,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5E0++0x3 line.long 0x00 "L4_AP_REGION_l_L_92,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_93" width 21. group.long 0x5EC++0x3 line.long 0x00 "L4_AP_REGION_l_H_93,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5E8++0x3 line.long 0x00 "L4_AP_REGION_l_L_93,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_94" width 21. group.long 0x5F4++0x3 line.long 0x00 "L4_AP_REGION_l_H_94,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5F0++0x3 line.long 0x00 "L4_AP_REGION_l_L_94,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_95" width 21. group.long 0x5FC++0x3 line.long 0x00 "L4_AP_REGION_l_H_95,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x5F8++0x3 line.long 0x00 "L4_AP_REGION_l_L_95,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end tree "REG_Bundle_96" width 21. group.long 0x604++0x3 line.long 0x00 "L4_AP_REGION_l_H_96,Define the size, protection group and segment ID of the region" bitfld.long 0x00 28.--31. " Reserved ,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " SEGMENT_ID ,The segment associated to the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " Reserved ,Read returns 0." "0,1" textline " " bitfld.long 0x00 20.--22. " PROT_GROUP_ID ,The protection group associated to the region." "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " BYTE_DATA_WIDTH_EXP ,The target data byte width is 2 bytes." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 6.--16. 1. " Reserved ,Read returns 0." textline " " bitfld.long 0x00 1.--5. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " ENABLE ,0x0: Disable the region, no access allows0x1: Enable the region, with access as define in registers" "0,1" rgroup.long 0x600++0x3 line.long 0x00 "L4_AP_REGION_l_L_96,Define the base address of the region in respect to the segment it belongs to." hexmask.long.byte 0x00 24.--31. 1. " Reserved ,Read returns 0." hexmask.long.tbyte 0x00 0.--23. 1. " BASE ,Sets the base address of the region relative to its segment base." tree.end textline "" width 19. rgroup.long 0x0++0x3 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code" hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code" rgroup.long 0x4++0x3 line.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x00 0.--31. 1. " Reserved ,Read returns 0" tree.end tree.open "PER_IA_0" tree "PER_IA_0" base ad:0x48001000 width 24. rgroup.long 0x0++0x3 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code" hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code" group.long 0x4++0x3 line.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." rgroup.long 0x18++0x3 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_IA_AGENT_CONTROL_L,Enable error reporting on an initiator interface.The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is .." bitfld.long 0x00 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x00 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x00 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register." "0,1" group.long 0x24++0x3 line.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." group.long 0x28++0x3 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." eventfld.long 0x00 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" eventfld.long 0x00 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" eventfld.long 0x00 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" group.long 0x2C++0x3 line.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." group.long 0x58++0x3 line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." eventfld.long 0x00 31. " MULTI ,Multiple errors detected" "0,1" eventfld.long 0x00 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. " CODE ,The error code of an initiator request.0x00: No errors0x01: Reserved0x10: Address hole0x11: Protection violation" "0,1,2,3" textline " " bitfld.long 0x00 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" rgroup.long 0x5C++0x3 line.long 0x00 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x00 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the errorREQ_INFO[0] = supervisor,REQ_INFO[1] = Debug" rgroup.long 0x60++0x3 line.long 0x00 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x00 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.long 0x64++0x3 line.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" tree.end tree "CFG_IA_0" base ad:0x4A001000 width 24. rgroup.long 0x0++0x3 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code" hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code" group.long 0x4++0x3 line.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." rgroup.long 0x18++0x3 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_IA_AGENT_CONTROL_L,Enable error reporting on an initiator interface.The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is .." bitfld.long 0x00 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x00 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x00 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register." "0,1" group.long 0x24++0x3 line.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." group.long 0x28++0x3 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." eventfld.long 0x00 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" eventfld.long 0x00 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" eventfld.long 0x00 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" group.long 0x2C++0x3 line.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." group.long 0x58++0x3 line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." eventfld.long 0x00 31. " MULTI ,Multiple errors detected" "0,1" eventfld.long 0x00 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. " CODE ,The error code of an initiator request.0x00: No errors0x01: Reserved0x10: Address hole0x11: Protection violation" "0,1,2,3" textline " " bitfld.long 0x00 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" rgroup.long 0x5C++0x3 line.long 0x00 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x00 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the errorREQ_INFO[0] = supervisor,REQ_INFO[1] = Debug" rgroup.long 0x60++0x3 line.long 0x00 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x00 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.long 0x64++0x3 line.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" tree.end tree "WKUP_IA_0" base ad:0x4A301000 width 24. rgroup.long 0x0++0x3 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x00 16.--31. 1. " CODE ,Interconnect code" hexmask.long.word 0x00 0.--15. 1. " REV ,Component revision code" group.long 0x4++0x3 line.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." rgroup.long 0x18++0x3 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. " CORE_CODE ,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. " CORE_REV ,Component revision code code" rgroup.long 0x1C++0x3 line.long 0x00 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x00 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" group.long 0x20++0x3 line.long 0x00 "L4_IA_AGENT_CONTROL_L,Enable error reporting on an initiator interface.The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is .." bitfld.long 0x00 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x00 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x00 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register." "0,1" group.long 0x24++0x3 line.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." group.long 0x28++0x3 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." eventfld.long 0x00 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" eventfld.long 0x00 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" eventfld.long 0x00 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" group.long 0x2C++0x3 line.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." group.long 0x58++0x3 line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." eventfld.long 0x00 31. " MULTI ,Multiple errors detected" "0,1" eventfld.long 0x00 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. " CODE ,The error code of an initiator request.0x00: No errors0x01: Reserved0x10: Address hole0x11: Protection violation" "0,1,2,3" textline " " bitfld.long 0x00 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" rgroup.long 0x5C++0x3 line.long 0x00 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x00 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the errorREQ_INFO[0] = supervisor,REQ_INFO[1] = Debug" rgroup.long 0x60++0x3 line.long 0x00 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x00 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.long 0x64++0x3 line.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" tree.end tree.end tree.end tree.open "C2C" tree.open "ICR_MPU" tree "ICR_MPU" base ad:0x4A0B6000 width 14. rgroup.long 0x0++0x3 line.long 0x00 "ICR_REVISION,This register contains the IP revision code." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "SYS_CONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 3.--4. " IDLEMODE ,Slave interface power management, req/ack control - . - . - . - ." "Force-idle,No-idle,Smart-idle,?..." bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always return 0.0: Normal mode1: The module is reset" "0,1" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating0: OCP clock is free running1: Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x14++0x3 line.long 0x00 "SYS_STATUS,This register provides status information about the module, excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring0: Internal module reset ongoing1: Reset completed - . - ." "0,Reset_completed" group.long 0x18++0x3 line.long 0x00 "M_IRQ_STATUS,The interrupt status register regroups all the status of the module internal events that can generate an interrupt - Write 1 to a given bit resets this bit." bitfld.long 0x00 1. " FLAG_SET ,Flag has been set inG_ICR register. - . - . - . - ." "0,1" bitfld.long 0x00 0. " FLAG_RESET ,Flag has been reset inM_ICR register. - . - . - . - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "G_IRQ_STATUS,The interrupt status register regroups all the status of the module internal events that can generate an interrupt - Write 1 to a given bit resets this bit." eventfld.long 0x00 1. " FLAG_SET ,Flag has been set inM_ICR register. - . - . - . - ." "0,1" eventfld.long 0x00 0. " FLAG_RESET ,Flag has been reset inG_ICR register. - . - . - . - ." "0,1" group.long 0x20++0x3 line.long 0x00 "M_ICR,Flags are used to notify an event to the other subsystem. The meaning of each flag is software dependent." hexmask.long 0x00 0.--31. 1. " FLAGS ,Meaning is software dependent." group.long 0x24++0x3 line.long 0x00 "G_ICR,Flags are used to notify an event to the other subsystem. The meaning of each flag is software dependent." hexmask.long 0x00 0.--31. 1. " FLAGS ,Meaning is software dependent." rgroup.long 0x28++0x3 line.long 0x00 "M_CTL,Enables interrupts to subsystems." bitfld.long 0x00 1. " G_ICR_INTEN ,Enable interrupt to MPU-S0: No interrupt is generated1: An interrupt is generated when Modem-S sets a flag to MPU-S" "0,1" bitfld.long 0x00 0. " M_ICR_INTEN ,Enable interrupt to MPU-S0: No interrupt is generated1: An interrupt is generated when Modem-S resets a flag set by MPU-S" "0,1" group.long 0x2C++0x3 line.long 0x00 "G_CTL,Enables interrupts to subsystems." bitfld.long 0x00 1. " M_ICR_INTEN ,Enable interrupt to Modem-S0: No interrupt is generated1: An interrupt is generated when MPU-S sets a flag to Modem-S" "0,1" bitfld.long 0x00 0. " G_ICR_INTEN ,Enable interrupt to Modem-S0: No interrupt is generated1: An interrupt is generated when MPU-S resets a flag set by Modem-S" "0,1" tree.end tree "ICR_MDM" base ad:0x4A0CD000 width 14. rgroup.long 0x0++0x3 line.long 0x00 "ICR_REVISION,This register contains the IP revision code." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "SYS_CONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 3.--4. " IDLEMODE ,Slave interface power management, req/ack control - . - . - . - ." "Force-idle,No-idle,Smart-idle,?..." bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always return 0.0: Normal mode1: The module is reset" "0,1" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating0: OCP clock is free running1: Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x14++0x3 line.long 0x00 "SYS_STATUS,This register provides status information about the module, excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring0: Internal module reset ongoing1: Reset completed - . - ." "0,Reset_completed" group.long 0x18++0x3 line.long 0x00 "M_IRQ_STATUS,The interrupt status register regroups all the status of the module internal events that can generate an interrupt - Write 1 to a given bit resets this bit." bitfld.long 0x00 1. " FLAG_SET ,Flag has been set inG_ICR register. - . - . - . - ." "0,1" bitfld.long 0x00 0. " FLAG_RESET ,Flag has been reset inM_ICR register. - . - . - . - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "G_IRQ_STATUS,The interrupt status register regroups all the status of the module internal events that can generate an interrupt - Write 1 to a given bit resets this bit." eventfld.long 0x00 1. " FLAG_SET ,Flag has been set inM_ICR register. - . - . - . - ." "0,1" eventfld.long 0x00 0. " FLAG_RESET ,Flag has been reset inG_ICR register. - . - . - . - ." "0,1" group.long 0x20++0x3 line.long 0x00 "M_ICR,Flags are used to notify an event to the other subsystem. The meaning of each flag is software dependent." hexmask.long 0x00 0.--31. 1. " FLAGS ,Meaning is software dependent." group.long 0x24++0x3 line.long 0x00 "G_ICR,Flags are used to notify an event to the other subsystem. The meaning of each flag is software dependent." hexmask.long 0x00 0.--31. 1. " FLAGS ,Meaning is software dependent." rgroup.long 0x28++0x3 line.long 0x00 "M_CTL,Enables interrupts to subsystems." bitfld.long 0x00 1. " G_ICR_INTEN ,Enable interrupt to MPU-S0: No interrupt is generated1: An interrupt is generated when Modem-S sets a flag to MPU-S" "0,1" bitfld.long 0x00 0. " M_ICR_INTEN ,Enable interrupt to MPU-S0: No interrupt is generated1: An interrupt is generated when Modem-S resets a flag set by MPU-S" "0,1" group.long 0x2C++0x3 line.long 0x00 "G_CTL,Enables interrupts to subsystems." bitfld.long 0x00 1. " M_ICR_INTEN ,Enable interrupt to Modem-S0: No interrupt is generated1: An interrupt is generated when MPU-S sets a flag to Modem-S" "0,1" bitfld.long 0x00 0. " G_ICR_INTEN ,Enable interrupt to Modem-S0: No interrupt is generated1: An interrupt is generated when MPU-S resets a flag set by Modem-S" "0,1" tree.end tree.end tree "C2C" base ad:0x5C000000 width 25. rgroup.long 0x0++0x3 line.long 0x00 "C2C_REVISION,IP Revision identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x4++0x3 line.long 0x00 "C2C_SYSCONFIG,System configuration register (not used)" group.long 0x8++0x3 line.long 0x00 "C2C_SYSSTATUS,?..." group.long 0xC++0x3 line.long 0x00 "C2C_PORTCONFIG,This register defines the widths of the TX and RX buses on the C2C interface." bitfld.long 0x00 4.--7. " RX_WIDTH ,0000: Bus width is set to 8 bits (default mode). - . - . - Other values are reserved, and should not be used. . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TX_WIDTH ,0000: Bus width is set to 8 bits. - . - . - Other values are reserved, and shall not be used. . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "C2C_MIRRORMODE,This register sets the C2C L3 in mirror mode. See debug section." bitfld.long 0x00 0. " MIRRORMODE ,Mirror mode. - . - ." "Functional_default_mode,1" group.long 0x14++0x3 line.long 0x00 "C2C_IRQ_RAW_STATUS_0,Interrupt status register (OCP-compliant IRQ line) for C2c_Sscm_Irq(0), regardless of enable settings" bitfld.long 0x00 3. " WAIT_IRQ ,Reading 1 indicates WAIT value in WAIT register has been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 2. " WAKE_ACK_IRQ ,Reading 1 indicates WAKE_ACK value in the WAKE_ACK register has been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 1. " RX_MAX_FREQ_ACK_IRQ ,Reading 1 indicates GPI is not turned on OR RX_MAX_FREQ_ACK value in the RX_MAX_FREQ_ACK register equal RX_MAX_FREQ value in the RX_MAX_FREQ register. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . -.." "0,1" textline " " bitfld.long 0x00 0. " TX_FREQ_IRQ ,Reading 1 indicates that the FCLK_FREQ value in the FCLK_FREQ register has been updated AND the SSCM has finished updating the new division for the TX clock. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ..." "0,1" group.long 0x18++0x3 line.long 0x00 "C2C_IRQ_RAW_STATUS_1," bitfld.long 0x00 31. " GENO_IRQ_31 ,Reading 1 indicates C2c_Sscm_GENO (31) signal and GENO_31 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 30. " GENO_IRQ_30 ,Reading 1 indicates C2c_Sscm_GENO (30) signal and GENO_30 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 29. " GENO_IRQ_29 ,Reading 1 indicates C2c_Sscm_GENO (29) signal and GENO_29 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 28. " GENO_IRQ_28 ,Reading 1 indicates C2c_Sscm_GENO (28) signal and GENO_28 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 27. " GENO_IRQ_27 ,Reading 1 indicates C2c_Sscm_GENO (27) signal and GENO_27 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 26. " GENO_IRQ_26 ,Reading 1 indicates C2c_Sscm_GENO (26) signal and GENO_26 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 25. " GENO_IRQ_25 ,Reading 1 indicates C2c_Sscm_GENO (25) signal and GENO_25 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 24. " GENO_IRQ_24 ,Reading 1 indicates C2c_Sscm_GENO (24) signal and GENO_24 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 23. " GENO_IRQ_23 ,Reading 1 indicates C2c_Sscm_GENO (23) signal and GENO_23 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 22. " GENO_IRQ_22 ,Reading 1 indicates C2c_Sscm_GENO (22) signal and GENO_22 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 21. " GENO_IRQ_21 ,Reading 1 indicates C2c_Sscm_GENO (21) signal and GENO_21 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 20. " GENO_IRQ_20 ,Reading 1 indicates C2c_Sscm_GENO (20) signal and GENO_20 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 19. " GENO_IRQ_19 ,Reading 1 indicates C2c_Sscm_GENO (19) signal and GENO_19 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 18. " GENO_IRQ_18 ,Reading 1 indicates C2c_Sscm_GENO (18) signal and GENO_18 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 17. " GENO_IRQ_17 ,Reading 1 indicates C2c_Sscm_GENO (17) signal and GENO_17 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 16. " GENO_IRQ_16 ,Reading 1 indicates C2c_Sscm_GENO (16) signal and GENO_16 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 15. " GENO_IRQ_15 ,Reading 1 indicates C2c_Sscm_GENO (15) signal and GENO_15 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 14. " GENO_IRQ_14 ,Reading 1 indicates C2c_Sscm_GENO (14) signal and GENO_14 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 13. " GENO_IRQ_13 ,Reading 1 indicates C2c_Sscm_GENO (13) signal and GENO_13 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 12. " GENO_IRQ_12 ,Reading 1 indicates C2c_Sscm_GENO (12) signal and GENO_12 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 11. " GENO_IRQ_11 ,Reading 1 indicates C2c_Sscm_GENO (11) signal and GENO_11 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 10. " GENO_IRQ_10 ,Reading 1 indicates C2c_Sscm_GENO (10) signal and GENO_10 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 9. " GENO_IRQ_9 ,Reading 1 indicates C2c_Sscm_GENO (9) signal and GENO_9 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 8. " GENO_IRQ_8 ,Reading 1 indicates C2c_Sscm_GENO (8) signal and GENO_8 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 7. " GENO_IRQ_7 ,Reading 1 indicates C2c_Sscm_GENO (7) signal and GENO_7 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 6. " GENO_IRQ_6 ,Reading 1 indicates C2c_Sscm_GENO (6) signal and GENO_6 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 5. " GENO_IRQ_5 ,Reading 1 indicates C2c_Sscm_GENO (5) signal and GENO_5 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 4. " GENO_IRQ_4 ,Reading 1 indicates C2c_Sscm_GENO (4) signal and GENO_4 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 3. " GENO_IRQ_3 ,Reading 1 indicates C2c_Sscm_GENO (3) signal and GENO_3 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 2. " GENO_IRQ_2 ,Reading 1 indicates C2c_Sscm_GENO (2) signal and GENO_2 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" textline " " bitfld.long 0x00 1. " GENO_IRQ_1 ,Reading 1 indicates C2c_Sscm_GENO (1) signal and GENO_1 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 0. " GENO_IRQ_0 ,Reading 1 indicates C2c_Sscm_GENO (0) signal and GENO_0 value in GENO_STATUS register have been modified by distant C2C. - Writing 1 to this bit sets the bit. . - . - Writing 0 has no effect. . - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "C2C_IRQ_ENABLE_STATUS_0," eventfld.long 0x00 3. " WAIT_IRQ ,Reading 1 indicates WAIT value in WAIT register has been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 2. " WAKE_ACK_IRQ ,Reading 1 indicates WAKE_ACK value in the WAKE_ACK register has been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 1. " RX_MAX_FREQ_ACK_IRQ ,Reading 1 indicates GPI is not turned on OR RX_MAX_FREQ_ACK value in the RX_MAX_FREQ_ACK register equal RX_MAX_FREQ value in the RX_MAX_FREQ register." "0,1" textline " " eventfld.long 0x00 0. " TX_FREQ_IRQ ,Reading 1 indicates that the FCLK_FREQ value in the FCLK_FREQ register has been updated AND the SSCM has finished updating the new division for the Tx clock." "0,1" group.long 0x20++0x3 line.long 0x00 "C2C_IRQ_ENABLE_STATUS_1," eventfld.long 0x00 31. " GENO_IRQ_31 ,Reading 1 indicates C2c_Sscm_GENO (31) signal and GENO_31 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 30. " GENO_IRQ_30 ,Reading 1 indicates C2c_Sscm_GENO (30) signal and GENO_30 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has n.." "0,1" eventfld.long 0x00 29. " GENO_IRQ_29 ,Reading 1 indicates C2c_Sscm_GENO (29) signal and GENO_29 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 28. " GENO_IRQ_28 ,Reading 1 indicates C2c_Sscm_GENO (28) signal and GENO_28 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 27. " GENO_IRQ_27 ,Reading 1 indicates C2c_Sscm_GENO (27) signal and GENO_27 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has n.." "0,1" eventfld.long 0x00 26. " GENO_IRQ_26 ,Reading 1 indicates C2c_Sscm_GENO (26) signal and GENO_26 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 25. " GENO_IRQ_25 ,Reading 1 indicates C2c_Sscm_GENO (25) signal and GENO_25 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 24. " GENO_IRQ_24 ,Reading 1 indicates C2c_Sscm_GENO (24) signal and GENO_24 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has n.." "0,1" eventfld.long 0x00 23. " GENO_IRQ_23 ,Reading 1 indicates C2c_Sscm_GENO (23) signal and GENO_23 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 22. " GENO_IRQ_22 ,Reading 1 indicates C2c_Sscm_GENO (22) signal and GENO_22 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 21. " GENO_IRQ_21 ,Reading 1 indicates C2c_Sscm_GENO (21) signal and GENO_21 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has n.." "0,1" eventfld.long 0x00 20. " GENO_IRQ_20 ,Reading 1 indicates C2c_Sscm_GENO (20) signal and GENO_20 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 19. " GENO_IRQ_19 ,Reading 1 indicates C2c_Sscm_GENO (19) signal and GENO_19 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 18. " GENO_IRQ_18 ,Reading 1 indicates C2c_Sscm_GENO (18) signal and GENO_18 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has n.." "0,1" eventfld.long 0x00 17. " GENO_IRQ_17 ,Reading 1 indicates C2c_Sscm_GENO (17) signal and GENO_17 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 16. " GENO_IRQ_16 ,Reading 1 indicates C2c_Sscm_GENO (16) signal and GENO_16 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 15. " GENO_IRQ_15 ,Reading 1 indicates C2c_Sscm_GENO (15) signal and GENO_15 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has n.." "0,1" eventfld.long 0x00 14. " GENO_IRQ_14 ,Reading 1 indicates C2c_Sscm_GENO (14) signal and GENO_14 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 13. " GENO_IRQ_13 ,Reading 1 indicates C2c_Sscm_GENO (13) signal and GENO_13 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 12. " GENO_IRQ_12 ,Reading 1 indicates C2c_Sscm_GENO (12) signal and GENO_12 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has n.." "0,1" eventfld.long 0x00 11. " GENO_IRQ_11 ,Reading 1 indicates C2c_Sscm_GENO (11) signal and GENO_11 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 10. " GENO_IRQ_10 ,Reading 1 indicates C2c_Sscm_GENO (10) signal and GENO_10 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 9. " GENO_IRQ_9 ,Reading 1 indicates C2c_Sscm_GENO (9) signal and GENO_9 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no .." "0,1" eventfld.long 0x00 8. " GENO_IRQ_8 ,Reading 1 indicates C2c_Sscm_GENO (8) signal and GENO_8 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 7. " GENO_IRQ_7 ,Reading 1 indicates C2c_Sscm_GENO (7) signal and GENO_7 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 6. " GENO_IRQ_6 ,Reading 1 indicates C2c_Sscm_GENO (6) signal and GENO_6 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no .." "0,1" eventfld.long 0x00 5. " GENO_IRQ_5 ,Reading 1 indicates C2c_Sscm_GENO (5) signal and GENO_5 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 4. " GENO_IRQ_4 ,Reading 1 indicates C2c_Sscm_GENO (4) signal and GENO_4 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 3. " GENO_IRQ_3 ,Reading 1 indicates C2c_Sscm_GENO (3) signal and GENO_3 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no .." "0,1" eventfld.long 0x00 2. " GENO_IRQ_2 ,Reading 1 indicates C2c_Sscm_GENO (2) signal and GENO_2 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" textline " " eventfld.long 0x00 1. " GENO_IRQ_1 ,Reading 1 indicates C2c_Sscm_GENO (1) signal and GENO_1 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 0. " GENO_IRQ_0 ,Reading 1 indicates C2c_Sscm_GENO (0) signal and GENO_0 value in GENO_STATUS register have been modified by distant C2C and interrupt source is not masked. Writing 1 to this bit clears the bit. Writing 0 has no .." "0,1" group.long 0x24++0x3 line.long 0x00 "C2C_IRQ_ENABLE_SET_0," bitfld.long 0x00 3. " WAIT_IRQ_EN ,Interrupt enable for WAIT IRQ. Writing 1 to this bit sets the bit. Writing 0 has no effect." "0,1" bitfld.long 0x00 2. " WAKE_ACK_IRQ_EN ,Interrupt enable for WAKE_ACK IRQ. Writing 1 to this bit sets the bit. Writing 0 has no effect." "0,1" bitfld.long 0x00 1. " RX_MAX_FREQ_ACK_IRQ_EN ,Interrupt enable for RX_MAX_FREQ_ACK IRQ. Writing 1 to this bit sets the bit. Writing 0 has no effect." "0,1" textline " " bitfld.long 0x00 0. " TX_FREQ_IRQ_EN ,Interrupt enable for TX_FREQ IRQ. Writing 1 to this bit sets the bit. Writing 0 has no effect." "0,1" group.long 0x28++0x3 line.long 0x00 "C2C_IRQ_ENABLE_SET_1," bitfld.long 0x00 31. " GENO_IRQ_31_EN ,Interrupt enable for GENO_IRQ_31 IRQ." "0,1" bitfld.long 0x00 30. " GENO_IRQ_30_EN ,Interrupt enable for GENO_IRQ_30 IRQ." "0,1" bitfld.long 0x00 29. " GENO_IRQ_29_EN ,Interrupt enable for GENO_IRQ_29 IRQ." "0,1" textline " " bitfld.long 0x00 28. " GENO_IRQ_28_EN ,Interrupt enable for GENO_IRQ_28 IRQ." "0,1" bitfld.long 0x00 27. " GENO_IRQ_27_EN ,Interrupt enable for GENO_IRQ_27 IRQ." "0,1" bitfld.long 0x00 26. " GENO_IRQ_26_EN ,Interrupt enable for GENO_IRQ_26 IRQ." "0,1" textline " " bitfld.long 0x00 25. " GENO_IRQ_25_EN ,Interrupt enable for GENO_IRQ_25 IRQ." "0,1" bitfld.long 0x00 24. " GENO_IRQ_24_EN ,Interrupt enable for GENO_IRQ_24 IRQ." "0,1" bitfld.long 0x00 23. " GENO_IRQ_23_EN ,Interrupt enable for GENO_IRQ_23 IRQ." "0,1" textline " " bitfld.long 0x00 22. " GENO_IRQ_22_EN ,Interrupt enable for GENO_IRQ_22 IRQ." "0,1" bitfld.long 0x00 21. " GENO_IRQ_21_EN ,Interrupt enable for GENO_IRQ_21 IRQ." "0,1" bitfld.long 0x00 20. " GENO_IRQ_20_EN ,Interrupt enable for GENO_IRQ_20 IRQ." "0,1" textline " " bitfld.long 0x00 19. " GENO_IRQ_19_EN ,Interrupt enable for GENO_IRQ_19 IRQ." "0,1" bitfld.long 0x00 18. " GENO_IRQ_18_EN ,Interrupt enable for GENO_IRQ_18 IRQ." "0,1" bitfld.long 0x00 17. " GENO_IRQ_17_EN ,Interrupt enable for GENO_IRQ_17 IRQ." "0,1" textline " " bitfld.long 0x00 16. " GENO_IRQ_16_EN ,Interrupt enable for GENO_IRQ_16 IRQ." "0,1" bitfld.long 0x00 15. " GENO_IRQ_15_EN ,Interrupt enable for GENO_IRQ_15 IRQ." "0,1" bitfld.long 0x00 14. " GENO_IRQ_14_EN ,Interrupt enable for GENO_IRQ_14 IRQ." "0,1" textline " " bitfld.long 0x00 13. " GENO_IRQ_13_EN ,Interrupt enable for GENO_IRQ_13 IRQ." "0,1" bitfld.long 0x00 12. " GENO_IRQ_12_EN ,Interrupt enable for GENO_IRQ_12 IRQ." "0,1" bitfld.long 0x00 11. " GENO_IRQ_11_EN ,Interrupt enable for GENO_IRQ_11 IRQ." "0,1" textline " " bitfld.long 0x00 10. " GENO_IRQ_10_EN ,Interrupt enable for GENO_IRQ_10 IRQ." "0,1" bitfld.long 0x00 9. " GENO_IRQ_9_EN ,Interrupt enable for GENO_IRQ_9 IRQ." "0,1" bitfld.long 0x00 8. " GENO_IRQ_8_EN ,Interrupt enable for GENO_IRQ_8 IRQ." "0,1" textline " " bitfld.long 0x00 7. " GENO_IRQ_7_EN ,Interrupt enable for GENO_IRQ_7 IRQ." "0,1" bitfld.long 0x00 6. " GENO_IRQ_6_EN ,Interrupt enable for GENO_IRQ_6 IRQ." "0,1" bitfld.long 0x00 5. " GENO_IRQ_5_EN ,Interrupt enable for GENO_IRQ_5 IRQ." "0,1" textline " " bitfld.long 0x00 4. " GENO_IRQ_4_EN ,Interrupt enable for GENO_IRQ_4 IRQ." "0,1" bitfld.long 0x00 3. " GENO_IRQ_3_EN ,Interrupt enable for GENO_IRQ_3 IRQ." "0,1" bitfld.long 0x00 2. " GENO_IRQ_2_EN ,Interrupt enable for GENO_IRQ_2 IRQ." "0,1" textline " " bitfld.long 0x00 1. " GENO_IRQ_1_EN ,Interrupt enable for GENO_IRQ_1 IRQ." "0,1" bitfld.long 0x00 0. " GENO_IRQ_0_EN ,Interrupt enable for GENO_IRQ_0 IRQ." "0,1" group.long 0x2C++0x3 line.long 0x00 "C2C_IRQ_ENABLE_CLEAR_0," eventfld.long 0x00 3. " WAIT_IRQ_EN ,Interrupt enable for WAIT IRQ." "0,1" eventfld.long 0x00 2. " WAKE_ACK_IRQ_EN ,Interrupt enable for WAKE_ACK IRQ." "0,1" eventfld.long 0x00 1. " RX_MAX_FREQ_ACK_IRQ_EN ,Interrupt enable for RX_MAX_FREQ_ACK IRQ." "0,1" textline " " eventfld.long 0x00 0. " TX_FREQ_IRQ_EN ,Interrupt enable for TX_FREQ IRQ." "0,1" group.long 0x30++0x3 line.long 0x00 "C2C_IRQ_ENABLE_CLEAR_1," eventfld.long 0x00 31. " GENO_IRQ_31_EN ,Interrupt enable for GENO_IRQ_31 IRQ. Writing 1 to this bit clears the bit. Writing 0 has no effect." "0,1" eventfld.long 0x00 30. " GENO_IRQ_30_EN ,Interrupt enable for GENO_IRQ_30 IRQ." "0,1" eventfld.long 0x00 29. " GENO_IRQ_29_EN ,Interrupt enable for GENO_IRQ_29 IRQ." "0,1" textline " " eventfld.long 0x00 28. " GENO_IRQ_28_EN ,Interrupt enable for GENO_IRQ_28 IRQ." "0,1" eventfld.long 0x00 27. " GENO_IRQ_27_EN ,Interrupt enable for GENO_IRQ_27 IRQ." "0,1" eventfld.long 0x00 26. " GENO_IRQ_26_EN ,Interrupt enable for GENO_IRQ_26 IRQ." "0,1" textline " " eventfld.long 0x00 25. " GENO_IRQ_25_EN ,Interrupt enable for GENO_IRQ_25 IRQ." "0,1" eventfld.long 0x00 24. " GENO_IRQ_24_EN ,Interrupt enable for GENO_IRQ_24 IRQ." "0,1" eventfld.long 0x00 23. " GENO_IRQ_23_EN ,Interrupt enable for GENO_IRQ_23 IRQ." "0,1" textline " " eventfld.long 0x00 22. " GENO_IRQ_22_EN ,Interrupt enable for GENO_IRQ_22 IRQ." "0,1" eventfld.long 0x00 21. " GENO_IRQ_21_EN ,Interrupt enable for GENO_IRQ_21 IRQ." "0,1" eventfld.long 0x00 20. " GENO_IRQ_20_EN ,Interrupt enable for GENO_IRQ_20 IRQ." "0,1" textline " " eventfld.long 0x00 19. " GENO_IRQ_19_EN ,Interrupt enable for GENO_IRQ_19 IRQ." "0,1" eventfld.long 0x00 18. " GENO_IRQ_18_EN ,Interrupt enable for GENO_IRQ_18 IRQ." "0,1" eventfld.long 0x00 17. " GENO_IRQ_17_EN ,Interrupt enable for GENO_IRQ_17 IRQ." "0,1" textline " " eventfld.long 0x00 16. " GENO_IRQ_16_EN ,Interrupt enable for GENO_IRQ_16 IRQ." "0,1" eventfld.long 0x00 15. " GENO_IRQ_15_EN ,Interrupt enable for GENO_IRQ_15 IRQ." "0,1" eventfld.long 0x00 14. " GENO_IRQ_14_EN ,Interrupt enable for GENO_IRQ_14 IRQ." "0,1" textline " " eventfld.long 0x00 13. " GENO_IRQ_13_EN ,Interrupt enable for GENO_IRQ_13 IRQ." "0,1" eventfld.long 0x00 12. " GENO_IRQ_12_EN ,Interrupt enable for GENO_IRQ_12 IRQ." "0,1" eventfld.long 0x00 11. " GENO_IRQ_11_EN ,Interrupt enable for GENO_IRQ_11 IRQ." "0,1" textline " " eventfld.long 0x00 10. " GENO_IRQ_10_EN ,Interrupt enable for GENO_IRQ_10 IRQ." "0,1" eventfld.long 0x00 9. " GENO_IRQ_9_EN ,Interrupt enable for GENO_IRQ_9 IRQ." "0,1" eventfld.long 0x00 8. " GENO_IRQ_8_EN ,Interrupt enable for GENO_IRQ_8 IRQ." "0,1" textline " " eventfld.long 0x00 7. " GENO_IRQ_7_EN ,Interrupt enable for GENO_IRQ_7 IRQ." "0,1" eventfld.long 0x00 6. " GENO_IRQ_6_EN ,Interrupt enable for GENO_IRQ_6 IRQ." "0,1" eventfld.long 0x00 5. " GENO_IRQ_5_EN ,Interrupt enable for GENO_IRQ_5 IRQ." "0,1" textline " " eventfld.long 0x00 4. " GENO_IRQ_4_EN ,Interrupt enable for GENO_IRQ_4 IRQ." "0,1" eventfld.long 0x00 3. " GENO_IRQ_3_EN ,Interrupt enable for GENO_IRQ_3 IRQ." "0,1" eventfld.long 0x00 2. " GENO_IRQ_2_EN ,Interrupt enable for GENO_IRQ_2 IRQ." "0,1" textline " " eventfld.long 0x00 1. " GENO_IRQ_1_EN ,Interrupt enable for GENO_IRQ_1 IRQ." "0,1" eventfld.long 0x00 0. " GENO_IRQ_0_EN ,Interrupt enable for GENO_IRQ_0 IRQ." "0,1" group.long 0x40++0x3 line.long 0x00 "C2C_FCLK_FREQ," hexmask.long.word 0x00 0.--9. 1. " FCLK_FREQ ,Value of the Functional clock frequency according to OPP written by software. Default value is 400 (MHz)." group.long 0x44++0x3 line.long 0x00 "C2C_RX_MAX_FREQ," hexmask.long.word 0x00 0.--9. 1. " RX_MAX_FREQ ,Value of the requested RX maximum clock frequency according to OPP written by software. Default value is 50 (MHz)." group.long 0x48++0x3 line.long 0x00 "C2C_TX_MAX_FREQ," hexmask.long.word 0x00 0.--9. 1. " TX_MAX_FREQ ,Value of the requested TX maximum clock frequency set by distant C2C. Default value is 50 (MHz)." group.long 0x4C++0x3 line.long 0x00 "C2C_RX_MAX_FREQ_ACK," hexmask.long.word 0x00 0.--9. 1. " RX_MAX_FREQ_ACK ,Acknowledged maximum Rx clock frequency. Set by distant C2C. Default value is 50 (MHz)." group.long 0x50++0x3 line.long 0x00 "C2C_WAKE_REQ," bitfld.long 0x00 0. " WAKE_REQ ,Value of the WAKE_REQ set by software" "0,1" group.long 0x54++0x3 line.long 0x00 "C2C_WAKE_ACK," bitfld.long 0x00 0. " WAKE_ACK ,Value of the WAKE_ACK set by distant C2C" "0,1" group.long 0x60++0x3 line.long 0x00 "C2C_STANDBY," bitfld.long 0x00 0. " STANDBY ,Value of the STANDBY set by software" "0,1" group.long 0x64++0x3 line.long 0x00 "C2C_STANDBY_IN," bitfld.long 0x00 0. " STANDBY ,Value of the STANDBY set by distant C2C" "0,1" group.long 0x68++0x3 line.long 0x00 "C2C_WAIT," bitfld.long 0x00 0. " WAIT ,Value of the WAIT set by distant C2C" "0,1" group.long 0x70++0x3 line.long 0x00 "C2C_GENI_CONTROL," bitfld.long 0x00 31. " GENI_31 ,If GENI_MASK_31 in GENI_MASK register is reset, GENI_31 is the value of C2C_Sscm_GenI_31 and cannot be modified by software. (signal is not masked)If GENI_MASK_31 is set (signal is masked), GENI_31 can be modified by software." "0,1" bitfld.long 0x00 30. " GENI_30 ,f GENI_MASK_30 in GENI_MASK register is reset, GENI_30 is the value of C2C_Sscm_GenI_30 and cannot be modified by software. (signal is not masked)If GENI_MASK_30 is set (signal is masked), GENI_30 can be modifie.." "0,1" bitfld.long 0x00 29. " GENI_29 ,f GENI_MASK_29 in GENI_MASK register is reset, GENI_29 is the value of C2C_Sscm_GenI_29 and cannot be modified by software. (signal is not masked)If GENI_MASK_29 is set (signal is masked), GENI_29 can be modified by software..." "0,1" textline " " bitfld.long 0x00 28. " GENI_28 ,f GENI_MASK_28 in GENI_MASK register is reset, GENI_28 is the value of C2C_Sscm_GenI_28 and cannot be modified by software. (signal is not masked)If GENI_MASK_28 is set (signal is masked), GENI_28 can be modified by software." "0,1" bitfld.long 0x00 27. " GENI_27 ,f GENI_MASK_27 in GENI_MASK register is reset, GENI_27 is the value of C2C_Sscm_GenI_27 and cannot be modified by software. (signal is not masked)If GENI_MASK_27 is set (signal is masked), GENI_27 can be modifie.." "0,1" bitfld.long 0x00 26. " GENI_26 ,f GENI_MASK_26 in GENI_MASK register is reset, GENI_26 is the value of C2C_Sscm_GenI_26 and cannot be modified by software. (signal is not masked)If GENI_MASK_26 is set (signal is masked), GENI_26 can be modified by software..." "0,1" textline " " bitfld.long 0x00 25. " GENI_25 ,f GENI_MASK_25 in GENI_MASK register is reset, GENI_25 is the value of C2C_Sscm_GenI_25 and cannot be modified by software. (signal is not masked)If GENI_MASK_25 is set (signal is masked), GENI_25 can be modified by software." "0,1" bitfld.long 0x00 24. " GENI_24 ,f GENI_MASK_24 in GENI_MASK register is reset, GENI_24 is the value of C2C_Sscm_GenI_24 and cannot be modified by software. (signal is not masked)If GENI_MASK_24 is set (signal is masked), GENI_24 can be modifie.." "0,1" bitfld.long 0x00 23. " GENI_23 ,f GENI_MASK_23 in GENI_MASK register is reset, GENI_23 is the value of C2C_Sscm_GenI_23 and cannot be modified by software. (signal is not masked)If GENI_MASK_23 is set (signal is masked), GENI_23 can be modified by software..." "0,1" textline " " bitfld.long 0x00 22. " GENI_22 ,f GENI_MASK_22 in GENI_MASK register is reset, GENI_22 is the value of C2C_Sscm_GenI_22 and cannot be modified by software. (signal is not masked)If GENI_MASK_22 is set (signal is masked), GENI_22 can be modified by software." "0,1" bitfld.long 0x00 21. " GENI_21 ,f GENI_MASK_21 in GENI_MASK register is reset, GENI_21 is the value of C2C_Sscm_GenI_31 and cannot be modified by software. (signal is not masked)If GENI_MASK_21 is set (signal is masked), GENI_21 can be modifie.." "0,1" bitfld.long 0x00 20. " GENI_20 ,f GENI_MASK_20 in GENI_MASK register is reset, GENI_20 is the value of C2C_Sscm_GenI_20 and cannot be modified by software. (signal is not masked)If GENI_MASK_20 is set (signal is masked), GENI_20 can be modified by software..." "0,1" textline " " bitfld.long 0x00 19. " GENI_19 ,f GENI_MASK_19 in GENI_MASK register is reset, GENI_19 is the value of C2C_Sscm_GenI_19 and cannot be modified by software. (signal is not masked)If GENI_MASK_19 is set (signal is masked), GENI_19 can be modified by software." "0,1" bitfld.long 0x00 18. " GENI_18 ,f GENI_MASK_18 in GENI_MASK register is reset, GENI_18 is the value of C2C_Sscm_GenI_31 and cannot be modified by software. (signal is not masked)If GENI_MASK_18 is set (signal is masked), GENI_18 can be modifie.." "0,1" bitfld.long 0x00 17. " GENI_17 ,f GENI_MASK_17 in GENI_MASK register is reset, GENI_17 is the value of C2C_Sscm_GenI_31 and cannot be modified by software. (signal is not masked)If GENI_MASK_17 is set (signal is masked), GENI_17 can be modified by software..." "0,1" textline " " bitfld.long 0x00 16. " GENI_16 ,f GENI_MASK_16 in GENI_MASK register is reset, GENI_16 is the value of C2C_Sscm_GenI_16 and cannot be modified by software. (signal is not masked)If GENI_MASK_156is set (signal is masked), GENI_16 can be modified by software." "0,1" bitfld.long 0x00 15. " GENI_15 ,f GENI_MASK_15 in GENI_MASK register is reset, GENI_15 is the value of C2C_Sscm_GenI_15 and cannot be modified by software. (signal is not masked)If GENI_MASK_15 is set (signal is masked), GENI_15 can be modifie.." "0,1" bitfld.long 0x00 14. " GENI_14 ,f GENI_MASK_14 in GENI_MASK register is reset, GENI_14 is the value of C2C_Sscm_GenI_14 and cannot be modified by software. (signal is not masked)If GENI_MASK_14 is set (signal is masked), GENI_14 can be modified by software..." "0,1" textline " " bitfld.long 0x00 13. " GENI_13 ,f GENI_MASK_13 in GENI_MASK register is reset, GENI_13 is the value of C2C_Sscm_GenI_13 and cannot be modified by software. (signal is not masked)If GENI_MASK_13 is set (signal is masked), GENI_13 can be modified by software." "0,1" bitfld.long 0x00 12. " GENI_12 ,f GENI_MASK_12 in GENI_MASK register is reset, GENI_12 is the value of C2C_Sscm_GenI_12 and cannot be modified by software. (signal is not masked)If GENI_MASK_12 is set (signal is masked), GENI_12 can be modifie.." "0,1" bitfld.long 0x00 11. " GENI_11 ,f GENI_MASK_11 in GENI_MASK register is reset, GENI_11 is the value of C2C_Sscm_GenI_11 and cannot be modified by software. (signal is not masked)If GENI_MASK_11 is set (signal is masked), GENI_11 can be modified by software..." "0,1" textline " " bitfld.long 0x00 10. " GENI_10 ,f GENI_MASK_10 in GENI_MASK register is reset, GENI_10 is the value of C2C_Sscm_GenI_10 and cannot be modified by software. (signal is not masked)If GENI_MASK_10 is set (signal is masked), GENI_10 can be modified by software." "0,1" bitfld.long 0x00 9. " GENI_9 ,f GENI_MASK_9 in GENI_MASK register is reset, GENI_9 is the value of C2C_Sscm_GenI_9 and cannot be modified by software. (signal is not masked)If GENI_MASK_9 is set (signal is masked), GENI_9 can be modified by .." "0,1" bitfld.long 0x00 8. " GENI_8 ,f GENI_MASK_8 in GENI_MASK register is reset, GENI_8 is the value of C2C_Sscm_GenI_8 and cannot be modified by software. (signal is not masked)If GENI_MASK_8 is set (signal is masked), GENI_8 can be modified by software." "0,1" textline " " bitfld.long 0x00 7. " GENI_7 ,f GENI_MASK_7 in GENI_MASK register is reset, GENI_7 is the value of C2C_Sscm_GenI_7 and cannot be modified by software. (signal is not masked)If GENI_MASK_7 is set (signal is masked), GENI_7 can be modified by software." "0,1" bitfld.long 0x00 6. " GENI_6 ,f GENI_MASK_6 in GENI_MASK register is reset, GENI_6 is the value of C2C_Sscm_GenI_6 and cannot be modified by software. (signal is not masked)If GENI_MASK_6 is set (signal is masked), GENI_6 can be modified by .." "0,1" bitfld.long 0x00 5. " GENI_5 ,f GENI_MASK_5 in GENI_MASK register is reset, GENI_5 is the value of C2C_Sscm_GenI_5 and cannot be modified by software. (signal is not masked)If GENI_MASK_5 is set (signal is masked), GENI_5 can be modified by software." "0,1" textline " " bitfld.long 0x00 4. " GENI_4 ,f GENI_MASK_4 in GENI_MASK register is reset, GENI_4 is the value of C2C_Sscm_GenI_4 and cannot be modified by software. (signal is not masked)If GENI_MASK_4 is set (signal is masked), GENI_4 can be modified by software." "0,1" bitfld.long 0x00 3. " GENI_3 ,f GENI_MASK_3 in GENI_MASK register is reset, GENI_3 is the value of C2C_Sscm_GenI_3 and cannot be modified by software. (signal is not masked)If GENI_MASK_3 is set (signal is masked), GENI_3 can be modified by .." "0,1" bitfld.long 0x00 2. " GENI_2 ,f GENI_MASK_2 in GENI_MASK register is reset, GENI_2 is the value of C2C_Sscm_GenI_2 and cannot be modified by software. (signal is not masked)If GENI_MASK_2 is set (signal is masked), GENI_2 can be modified by software." "0,1" textline " " bitfld.long 0x00 1. " GENI_1 ,f GENI_MASK_1 in GENI_MASK register is reset, GENI_1 is the value of C2C_Sscm_GenI_1 and cannot be modified by software. (signal is not masked)If GENI_MASK_1 is set (signal is masked), GENI_1 can be modified by software." "0,1" bitfld.long 0x00 0. " GENI_0 ,f GENI_MASK_0 in GENI_MASK register is reset, GENI_0 is the value of C2C_Sscm_GenI_0 and cannot be modified by software. (signal is not masked)If GENI_MASK_0 is set (signal is masked), GENI_0 can be modified by .." "0,1" group.long 0x74++0x3 line.long 0x00 "C2C_GENI_MASK," bitfld.long 0x00 31. " GENI_MASK_31 ,If GENI_MASK_31 is reset, C2C_Sscm_GenI_31 signal is not masked If GENI_MASK_31 is set, signal is masked." "0,1" bitfld.long 0x00 30. " GENI_MASK_30 ,If GENI_MASK_30 is reset, C2C_Sscm_GenI_30 signal is not masked If GENI_MASK_30 is set, signal is masked." "0,1" bitfld.long 0x00 29. " GENI_MASK_29 ,If GENI_MASK_29 is reset, C2C_Sscm_GenI_29 signal is not masked If GENI_MASK_29 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 28. " GENI_MASK_28 ,If GENI_MASK_28 is reset, C2C_Sscm_GenI_28 signal is not masked If GENI_MASK_28 is set, signal is masked." "0,1" bitfld.long 0x00 27. " GENI_MASK_27 ,If GENI_MASK_27 is reset, C2C_Sscm_GenI_27 signal is not masked If GENI_MASK_27 is set, signal is masked." "0,1" bitfld.long 0x00 26. " GENI_MASK_26 ,If GENI_MASK_26 is reset, C2C_Sscm_GenI_26 signal is not masked If GENI_MASK_26 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 25. " GENI_MASK_25 ,If GENI_MASK_26 is reset, C2C_Sscm_GenI_25 signal is not masked If GENI_MASK_26 is set, signal is masked." "0,1" bitfld.long 0x00 24. " GENI_MASK_24 ,If GENI_MASK_24 is reset, C2C_Sscm_GenI_24 signal is not masked If GENI_MASK_24 is set, signal is masked." "0,1" bitfld.long 0x00 23. " GENI_MASK_23 ,If GENI_MASK_23 is reset, C2C_Sscm_GenI_23 signal is not masked If GENI_MASK_23 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 22. " GENI_MASK_22 ,If GENI_MASK_22 is reset, C2C_Sscm_GenI_22 signal is not masked If GENI_MASK_22 is set, signal is masked." "0,1" bitfld.long 0x00 21. " GENI_MASK_21 ,If GENI_MASK_21 is reset, C2C_Sscm_GenI_21 signal is not masked If GENI_MASK_21 is set, signal is masked." "0,1" bitfld.long 0x00 20. " GENI_MASK_20 ,If GENI_MASK_20 is reset, C2C_Sscm_GenI_20 signal is not masked If GENI_MASK_20 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 19. " GENI_MASK_19 ,If GENI_MASK_19 is reset, C2C_Sscm_GenI_19 signal is not masked If GENI_MASK_19 is set, signal is masked." "0,1" bitfld.long 0x00 18. " GENI_MASK_18 ,If GENI_MASK_18 is reset, C2C_Sscm_GenI_18 signal is not masked If GENI_MASK_18 is set, signal is masked." "0,1" bitfld.long 0x00 17. " GENI_MASK_17 ,If GENI_MASK_17 is reset, C2C_Sscm_GenI_17 signal is not masked If GENI_MASK_17 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 16. " GENI_MASK_16 ,If GENI_MASK_16 is reset, C2C_Sscm_GenI_16 signal is not masked If GENI_MASK_16 is set, signal is masked." "0,1" bitfld.long 0x00 15. " GENI_MASK_15 ,If GENI_MASK_15 is reset, C2C_Sscm_GenI_15 signal is not masked If GENI_MASK_15 is set, signal is masked." "0,1" bitfld.long 0x00 14. " GENI_MASK_14 ,If GENI_MASK_14 is reset, C2C_Sscm_GenI_14 signal is not masked If GENI_MASK_14 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 13. " GENI_MASK_13 ,If GENI_MASK_13 is reset, C2C_Sscm_GenI_13 signal is not masked If GENI_MASK_13 is set, signal is masked." "0,1" bitfld.long 0x00 12. " GENI_MASK_12 ,If GENI_MASK_12is reset, C2C_Sscm_GenI_12 signal is not masked If GENI_MASK_12 is set, signal is masked." "0,1" bitfld.long 0x00 11. " GENI_MASK_11 ,If GENI_MASK_11 is reset, C2C_Sscm_GenI_11 signal is not masked If GENI_MASK_11 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 10. " GENI_MASK_10 ,If GENI_MASK_10 is reset, C2C_Sscm_GenI_10 signal is not masked If GENI_MASK_10 is set, signal is masked." "0,1" bitfld.long 0x00 9. " GENI_MASK_9 ,If GENI_MASK_9 is reset, C2C_Sscm_GenI_9 signal is not masked If GENI_MASK_9 is set, signal is masked." "0,1" bitfld.long 0x00 8. " GENI_MASK_8 ,If GENI_MASK_8 is reset, C2C_Sscm_GenI_8 signal is not masked If GENI_MASK_8 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 7. " GENI_MASK_7 ,If GENI_MASK_7 is reset, C2C_Sscm_GenI_7 signal is not masked If GENI_MASK_7 is set, signal is masked." "0,1" bitfld.long 0x00 6. " GENI_MASK_6 ,If GENI_MASK_6 is reset, C2C_Sscm_GenI_6 signal is not masked If GENI_MASK_6 is set, signal is masked." "0,1" bitfld.long 0x00 5. " GENI_MASK_5 ,If GENI_MASK_5 is reset, C2C_Sscm_GenI_5 signal is not masked If GENI_MASK_5 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 4. " GENI_MASK_4 ,If GENI_MASK_4 is reset, C2C_Sscm_GenI_4 signal is not masked If GENI_MASK_4 is set, signal is masked." "0,1" bitfld.long 0x00 3. " GENI_MASK_3 ,If GENI_MASK_3 is reset, C2C_Sscm_GenI_3 signal is not masked If GENI_MASK_3 is set, signal is masked." "0,1" bitfld.long 0x00 2. " GENI_MASK_2 ,If GENI_MASK_2 is reset, C2C_Sscm_GenI_2 signal is not masked If GENI_MASK_2 is set, signal is masked." "0,1" textline " " bitfld.long 0x00 1. " GENI_MASK_1 ,If GENI_MASK_1 is reset, C2C_Sscm_GenI_1 signal is not masked If GENI_MASK_1 is set, signal is masked." "0,1" bitfld.long 0x00 0. " GENI_MASK_0 ,If GENI_MASK_0 is reset, C2C_Sscm_GenI_0 signal is not masked If GENI_MASK_0 is set, signal is masked." "0,1" group.long 0x80++0x3 line.long 0x00 "C2C_GENO_STATUS," bitfld.long 0x00 31. " GENO_31 ,GENO_31 is the value of C2C_Sscm_GenO_31 signal." "0,1" bitfld.long 0x00 30. " GENO_30 ,GENO_30 is the value of C2C_Sscm_GenO_30 signal." "0,1" bitfld.long 0x00 29. " GENO_29 ,GENO_29 is the value of C2C_Sscm_GenO_29 signal." "0,1" textline " " bitfld.long 0x00 28. " GENO_28 ,GENO_28 is the value of C2C_Sscm_GenO_28 signal." "0,1" bitfld.long 0x00 27. " GENO_27 ,GENO_27 is the value of C2C_Sscm_GenO_27 signal." "0,1" bitfld.long 0x00 26. " GENO_26 ,GENO_26 is the value of C2C_Sscm_GenO_26 signal." "0,1" textline " " bitfld.long 0x00 25. " GENO_25 ,GENO_25 is the value of C2C_Sscm_GenO_25 signal." "0,1" bitfld.long 0x00 24. " GENO_24 ,GENO_24 is the value of C2C_Sscm_GenO_24 signal." "0,1" bitfld.long 0x00 23. " GENO_23 ,GENO_23 is the value of C2C_Sscm_GenO_23 signal." "0,1" textline " " bitfld.long 0x00 22. " GENO_22 ,GENO_22 is the value of C2C_Sscm_GenO_22 signal." "0,1" bitfld.long 0x00 21. " GENO_21 ,GENO_21 is the value of C2C_Sscm_GenO_21 signal." "0,1" bitfld.long 0x00 20. " GENO_20 ,GENO_20 is the value of C2C_Sscm_GenO_20 signal." "0,1" textline " " bitfld.long 0x00 19. " GENO_19 ,GENO_19 is the value of C2C_Sscm_GenO_19 signal." "0,1" bitfld.long 0x00 18. " GENO_18 ,GENO_18 is the value of C2C_Sscm_GenO_18 signal." "0,1" bitfld.long 0x00 17. " GENO_17 ,GENO_17 is the value of C2C_Sscm_GenO_17 signal." "0,1" textline " " bitfld.long 0x00 16. " GENO_16 ,GENO_16 is the value of C2C_Sscm_GenO_16 signal." "0,1" bitfld.long 0x00 15. " GENO_15 ,GENO_15 is the value of C2C_Sscm_GenO_15 signal." "0,1" bitfld.long 0x00 14. " GENO_14 ,GENO_14 is the value of C2C_Sscm_GenO_14 signal." "0,1" textline " " bitfld.long 0x00 13. " GENO_13 ,GENO_13 is the value of C2C_Sscm_GenO_13 signal." "0,1" bitfld.long 0x00 12. " GENO_12 ,GENO_12 is the value of C2C_Sscm_GenO_12 signal." "0,1" bitfld.long 0x00 11. " GENO_11 ,GENO_11 is the value of C2C_Sscm_GenO_11 signal." "0,1" textline " " bitfld.long 0x00 10. " GENO_10 ,GENO_10 is the value of C2C_Sscm_GenO_10 signal." "0,1" bitfld.long 0x00 9. " GENO_9 ,GENO_9 is the value of C2C_Sscm_GenO_9 signal." "0,1" bitfld.long 0x00 8. " GENO_8 ,GENO_8 is the value of C2C_Sscm_GenO_8 signal." "0,1" textline " " bitfld.long 0x00 7. " GENO_7 ,GENO_7 is the value of C2C_Sscm_GenO_7 signal." "0,1" bitfld.long 0x00 6. " GENO_6 ,GENO_6 is the value of C2C_Sscm_GenO_6 signal." "0,1" bitfld.long 0x00 5. " GENO_5 ,GENO_5 is the value of C2C_Sscm_GenO_5 signal." "0,1" textline " " bitfld.long 0x00 4. " GENO_4 ,GENO_4 is the value of C2C_Sscm_GenO_4 signal." "0,1" bitfld.long 0x00 3. " GENO_3 ,GENO_3 is the value of C2C_Sscm_GenO_3 signal." "0,1" bitfld.long 0x00 2. " GENO_2 ,GENO_2 is the value of C2C_Sscm_GenO_2 signal." "0,1" textline " " bitfld.long 0x00 1. " GENO_1 ,GENO_1 is the value of C2C_Sscm_GenO_1 signal." "0,1" bitfld.long 0x00 0. " GENO_0 ,GENO_0 is the value of C2C_Sscm_GenO_0 signal." "0,1" group.long 0x84++0x3 line.long 0x00 "C2C_GENO_INTERRUPT," bitfld.long 0x00 31. " GENO_INT_31 ,If GENO_INT_31=0, GENO_IRQ_31=1 when GENO_31 toggles; If GENO_INT_31=1: IF GENO_LEVEL_31=0, GENO_IRQ_31 =1 when GENO_31 toggles to 0. IF GENO_LEVEL_31=1, GENO_IRQ_31 =1 when GENO_31 toggles to 1." "0,1" bitfld.long 0x00 30. " GENO_INT_30 ,If GENO_INT_30=0, GENO_IRQ_30=1 when GENO_30 toggles; If GENO_INT_30=1: IF GENO_LEVEL_30=0, GENO_IRQ_30 =1 when GENO_30 toggles to 0. IF GENO_LEVEL_30=1, GENO_IRQ_30 =1 when GENO_30 toggles to 1." "0,1" bitfld.long 0x00 29. " GENO_INT_29 ,If GENO_INT_29=0, GENO_IRQ_29=1 when GENO_29 toggles; If GENO_INT_29=1: IF GENO_LEVEL_29=0, GENO_IRQ_29 =1 when GENO_29 toggles to 0. IF GENO_LEVEL_29=1, GENO_IRQ_29 =1 when GENO_29 toggles to 1." "0,1" textline " " bitfld.long 0x00 28. " GENO_INT_28 ,If GENO_INT_28=0, GENO_IRQ_28=1 when GENO_28 toggles; If GENO_INT_28=1: IF GENO_LEVEL_28=0, GENO_IRQ_28 =1 when GENO_28 toggles to 0. IF GENO_LEVEL_28=1, GENO_IRQ_28 =1 when GENO_28 toggles to 1." "0,1" bitfld.long 0x00 27. " GENO_INT_27 ,If GENO_INT_27=0, GENO_IRQ_27=1 when GENO_27 toggles; If GENO_INT_27=1: IF GENO_LEVEL_27=0, GENO_IRQ_27 =1 when GENO_27 toggles to 0. IF GENO_LEVEL_27=1, GENO_IRQ_27 =1 when GENO_27 toggles to 1." "0,1" bitfld.long 0x00 26. " GENO_INT_26 ,If GENO_INT_26=0, GENO_IRQ_26=1 when GENO_26 toggles; If GENO_INT_26=1: IF GENO_LEVEL_26=0, GENO_IRQ_26 =1 when GENO_26 toggles to 0. IF GENO_LEVEL_26=1, GENO_IRQ_26 =1 when GENO_26 toggles to 1." "0,1" textline " " bitfld.long 0x00 25. " GENO_INT_25 ,If GENO_INT_25=0, GENO_IRQ_25=1 when GENO_25 toggles; If GENO_INT_25=1: IF GENO_LEVEL_25=0, GENO_IRQ_25 =1 when GENO_25 toggles to 0. IF GENO_LEVEL_25=1, GENO_IRQ_25 =1 when GENO_25 toggles to 1." "0,1" bitfld.long 0x00 24. " GENO_INT_24 ,If GENO_INT_24=0, GENO_IRQ_24=1 when GENO_24 toggles; If GENO_INT_24=1: IF GENO_LEVEL_24=0, GENO_IRQ_24 =1 when GENO_24 toggles to 0. IF GENO_LEVEL_24=1, GENO_IRQ_24 =1 when GENO_24 toggles to 1." "0,1" bitfld.long 0x00 23. " GENO_INT_23 ,If GENO_INT_23=0, GENO_IRQ_23=1 when GENO_23 toggles; If GENO_INT_23=1: IF GENO_LEVEL_23=0, GENO_IRQ_23 =1 when GENO_23 toggles to 0. IF GENO_LEVEL_23=1, GENO_IRQ_23 =1 when GENO_23 toggles to 1." "0,1" textline " " bitfld.long 0x00 22. " GENO_INT_22 ,If GENO_INT_22=0, GENO_IRQ_22=1 when GENO_22 toggles; If GENO_INT_22=1: IF GENO_LEVEL_22=0, GENO_IRQ_22 =1 when GENO_22 toggles to 0. IF GENO_LEVEL_22=1, GENO_IRQ_22 =1 when GENO_22 toggles to 1." "0,1" bitfld.long 0x00 21. " GENO_INT_21 ,If GENO_INT_21=0, GENO_IRQ_21=1 when GENO_21 toggles; If GENO_INT_21=1: IF GENO_LEVEL_21=0, GENO_IRQ_21 =1 when GENO_21 toggles to 0. IF GENO_LEVEL_21=1, GENO_IRQ_21 =1 when GENO_21 toggles to 1." "0,1" bitfld.long 0x00 20. " GENO_INT_20 ,If GENO_INT_20=0, GENO_IRQ_20=1 when GENO_20 toggles; If GENO_INT_20=1: IF GENO_LEVEL_20=0, GENO_IRQ_20 =1 when GENO_20 toggles to 0. IF GENO_LEVEL_20=1, GENO_IRQ_20 =1 when GENO_20 toggles to 1." "0,1" textline " " bitfld.long 0x00 19. " GENO_INT_19 ,If GENO_INT_19=0, GENO_IRQ_19=1 when GENO_19 toggles; If GENO_INT_19=1: IF GENO_LEVEL_19=0, GENO_IRQ_19 =1 when GENO_19 toggles to 0. IF GENO_LEVEL_19=1, GENO_IRQ_19 =1 when GENO_19 toggles to 1." "0,1" bitfld.long 0x00 18. " GENO_INT_18 ,If GENO_INT_18=0, GENO_IRQ_18=1 when GENO_18 toggles; If GENO_INT_18=1: IF GENO_LEVEL_18=0, GENO_IRQ_18 =1 when GENO_18 toggles to 0. IF GENO_LEVEL_18=1, GENO_IRQ_18 =1 when GENO_18 toggles to 1." "0,1" bitfld.long 0x00 17. " GENO_INT_17 ,If GENO_INT_17=0, GENO_IRQ_17=1 when GENO_17 toggles; If GENO_INT_17=1: IF GENO_LEVEL_17=0, GENO_IRQ_17 =1 when GENO_17 toggles to 0. IF GENO_LEVEL_17=1, GENO_IRQ_17 =1 when GENO_17 toggles to 1." "0,1" textline " " bitfld.long 0x00 16. " GENO_INT_16 ,If GENO_INT_16=0, GENO_IRQ_16=1 when GENO_16 toggles; If GENO_INT_16=1: IF GENO_LEVEL_16=0, GENO_IRQ_16 =1 when GENO_16 toggles to 0. IF GENO_LEVEL_16=1, GENO_IRQ_16 =1 when GENO_16 toggles to 1." "0,1" bitfld.long 0x00 15. " GENO_INT_15 ,If GENO_INT_15=0, GENO_IRQ_15=1 when GENO_15 toggles; If GENO_INT_15=1: IF GENO_LEVEL_15=0, GENO_IRQ_15 =1 when GENO_15 toggles to 0. IF GENO_LEVEL_15=1, GENO_IRQ_15 =1 when GENO_15 toggles to 1." "0,1" bitfld.long 0x00 14. " GENO_INT_14 ,If GENO_INT_14=0, GENO_IRQ_14=1 when GENO_14 toggles; If GENO_INT_14=1: IF GENO_LEVEL_14=0, GENO_IRQ_14 =1 when GENO_14 toggles to 0. IF GENO_LEVEL_14=1, GENO_IRQ_14 =1 when GENO_14 toggles to 1." "0,1" textline " " bitfld.long 0x00 13. " GENO_INT_13 ,If GENO_INT_13=0, GENO_IRQ_13=1 when GENO_13 toggles; If GENO_INT_13=1: IF GENO_LEVEL_13=0, GENO_IRQ_13 =1 when GENO_13 toggles to 0. IF GENO_LEVEL_13=1, GENO_IRQ_13 =1 when GENO_13 toggles to 1." "0,1" bitfld.long 0x00 12. " GENO_INT_12 ,If GENO_INT_12=0, GENO_IRQ_12=1 when GENO_12 toggles; If GENO_INT_12=1: IF GENO_LEVEL_12=0, GENO_IRQ_12 =1 when GENO_12 toggles to 0. IF GENO_LEVEL_12=1, GENO_IRQ_12 =1 when GENO_12 toggles to 1." "0,1" bitfld.long 0x00 11. " GENO_INT_11 ,If GENO_INT_11=0, GENO_IRQ_11=1 when GENO_11 toggles; If GENO_INT_11=1: IF GENO_LEVEL_11=0, GENO_IRQ_11 =1 when GENO_11 toggles to 0. IF GENO_LEVEL_11=1, GENO_IRQ_11 =1 when GENO_11 toggles to 1." "0,1" textline " " bitfld.long 0x00 10. " GENO_INT_10 ,If GENO_INT_10=0, GENO_IRQ_10=1 when GENO_10 toggles; If GENO_INT_10=1: IF GENO_LEVEL_10=0, GENO_IRQ_10 =1 when GENO_10 toggles to 0. IF GENO_LEVEL_10=1, GENO_IRQ_10 =1 when GENO_10 toggles to 1." "0,1" bitfld.long 0x00 9. " GENO_INT_9 ,If GENO_INT_9=0, GENO_IRQ_9=1 when GENO_9 toggles; If GENO_INT_9=1: IF GENO_LEVEL_9=0, GENO_IRQ_9 =1 when GENO_9 toggles to 0. IF GENO_LEVEL_9=1, GENO_IRQ_9 =1 when GENO_9 toggles to 1." "0,1" bitfld.long 0x00 8. " GENO_INT_8 ,If GENO_INT_8=0, GENO_IRQ_8=1 when GENO_8 toggles; If GENO_INT_8=1: IF GENO_LEVEL_8=0, GENO_IRQ_8 =1 when GENO_8 toggles to 0. IF GENO_LEVEL_8=1, GENO_IRQ_8 =1 when GENO_8 toggles to 1." "0,1" textline " " bitfld.long 0x00 7. " GENO_INT_7 ,If GENO_INT_7=0, GENO_IRQ_7=1 when GENO_7 toggles; If GENO_INT_7=1: IF GENO_LEVEL_7=0, GENO_IRQ_7 =1 when GENO_7 toggles to 0. IF GENO_LEVEL_7=1, GENO_IRQ_7 =1 when GENO_7 toggles to 1." "0,1" bitfld.long 0x00 6. " GENO_INT_6 ,If GENO_INT_6=0, GENO_IRQ_6=1 when GENO_6 toggles; If GENO_INT_6=1: IF GENO_LEVEL_6=0, GENO_IRQ_6 =1 when GENO_6 toggles to 0. IF GENO_LEVEL_6=1, GENO_IRQ_6 =1 when GENO_6 toggles to 1." "0,1" bitfld.long 0x00 5. " GENO_INT_5 ,If GENO_INT_5=0, GENO_IRQ_5=1 when GENO_5 toggles; If GENO_INT_5=1: IF GENO_LEVEL_5=0, GENO_IRQ_5 =1 when GENO_5 toggles to 0. IF GENO_LEVEL_5=1, GENO_IRQ_5 =1 when GENO_5 toggles to 1." "0,1" textline " " bitfld.long 0x00 4. " GENO_INT_4 ,If GENO_INT_4=0, GENO_IRQ_4=1 when GENO_4 toggles; If GENO_INT_4=1: IF GENO_LEVEL_4=0, GENO_IRQ_4 =1 when GENO_4 toggles to 0. IF GENO_LEVEL_4=1, GENO_IRQ_4 =1 when GENO_4 toggles to 1." "0,1" bitfld.long 0x00 3. " GENO_INT_3 ,If GENO_INT_3=0, GENO_IRQ_3=1 when GENO_3 toggles; If GENO_INT_3=1: IF GENO_LEVEL_3=0, GENO_IRQ_3 =1 when GENO_3 toggles to 0. IF GENO_LEVEL_3=1, GENO_IRQ_3 =1 when GENO_3 toggles to 1." "0,1" bitfld.long 0x00 2. " GENO_INT_2 ,If GENO_INT_2=0, GENO_IRQ_2=1 when GENO_2 toggles; If GENO_INT_2=1: IF GENO_LEVEL_2=0, GENO_IRQ_2 =1 when GENO_2 toggles to 0. IF GENO_LEVEL_2=1, GENO_IRQ_2 =1 when GENO_2 toggles to 1." "0,1" textline " " bitfld.long 0x00 1. " GENO_INT_1 ,If GENO_INT_1=0, GENO_IRQ_1=1 when GENO_1 toggles; If GENO_INT_1=1: IF GENO_LEVEL_1=0, GENO_IRQ_1 =1 when GENO_1 toggles to 0. IF GENO_LEVEL_1=1, GENO_IRQ_1 =1 when GENO_1 toggles to 1." "0,1" bitfld.long 0x00 0. " GENO_INT_0 ,If GENO_INT_0=0, GENO_IRQ_0=1 when GENO_0 toggles; If GENO_INT_0=1: IF GENO_LEVEL_0=0, GENO_IRQ_0 =1 when GENO_0 toggles to 0. IF GENO_LEVEL_0=1, GENO_IRQ_0 =1 when GENO_0 toggles to 1." "0,1" group.long 0x88++0x3 line.long 0x00 "C2C_GENO_LEVEL," bitfld.long 0x00 31. " GENO_LEVEL_31 ,IF GENO_LEVEL_31=0, GENO_IRQ_31 =1 when GENO_31 toggles to 0. IF GENO_LEVEL_31=1, GENO_IRQ_31 =1 when GENO_31 toggles to 1." "0,1" bitfld.long 0x00 30. " GENO_LEVEL_30 ,IF GENO_LEVEL_30=0, GENO_IRQ_30 =1 when GENO_30 toggles to 0. IF GENO_LEVEL_30=1, GENO_IRQ_30 =1 when GENO_30 toggles to 1." "0,1" bitfld.long 0x00 29. " GENO_LEVEL_29 ,IF GENO_LEVEL_29=0, GENO_IRQ_29 =1 when GENO_29 toggles to 0. IF GENO_LEVEL_29=1, GENO_IRQ_29 =1 when GENO_29 toggles to 1." "0,1" textline " " bitfld.long 0x00 28. " GENO_LEVEL_28 ,IF GENO_LEVEL_28=0, GENO_IRQ_28 =1 when GENO_28 toggles to 0. IF GENO_LEVEL_28=1, GENO_IRQ_28 =1 when GENO_28 toggles to 1." "0,1" bitfld.long 0x00 27. " GENO_LEVEL_27 ,IF GENO_LEVEL_27=0, GENO_IRQ_27 =1 when GENO_27 toggles to 0. IF GENO_LEVEL_27=1, GENO_IRQ_27 =1 when GENO_27 toggles to 1." "0,1" bitfld.long 0x00 26. " GENO_LEVEL_26 ,IF GENO_LEVEL_26=0, GENO_IRQ_26 =1 when GENO_26 toggles to 0. IF GENO_LEVEL_26=1, GENO_IRQ_26 =1 when GENO_26 toggles to 1." "0,1" textline " " bitfld.long 0x00 25. " GENO_LEVEL_25 ,IF GENO_LEVEL_25=0, GENO_IRQ_25 =1 when GENO_25 toggles to 0. IF GENO_LEVEL_25=1, GENO_IRQ_25 =1 when GENO_25 toggles to 1." "0,1" bitfld.long 0x00 24. " GENO_LEVEL_24 ,IF GENO_LEVEL_24=0, GENO_IRQ_24 =1 when GENO_24 toggles to 0. IF GENO_LEVEL_24=1, GENO_IRQ_24 =1 when GENO_24 toggles to 1." "0,1" bitfld.long 0x00 23. " GENO_LEVEL_23 ,IF GENO_LEVEL_23=0, GENO_IRQ_23 =1 when GENO_23 toggles to 0. IF GENO_LEVEL_23=1, GENO_IRQ_23 =1 when GENO_23 toggles to 1." "0,1" textline " " bitfld.long 0x00 22. " GENO_LEVEL_22 ,IF GENO_LEVEL_22=0, GENO_IRQ_22 =1 when GENO_22 toggles to 0. IF GENO_LEVEL_22=1, GENO_IRQ_22 =1 when GENO_22 toggles to 1." "0,1" bitfld.long 0x00 21. " GENO_LEVEL_21 ,IF GENO_LEVEL_21=0, GENO_IRQ_21 =1 when GENO_21 toggles to 0. IF GENO_LEVEL_21=1, GENO_IRQ_21 =1 when GENO_21 toggles to 1." "0,1" bitfld.long 0x00 20. " GENO_LEVEL_20 ,IF GENO_LEVEL_20=0, GENO_IRQ_20 =1 when GENO_20 toggles to 0. IF GENO_LEVEL_20=1, GENO_IRQ_20 =1 when GENO_20 toggles to 1." "0,1" textline " " bitfld.long 0x00 19. " GENO_LEVEL_19 ,IF GENO_LEVEL_19=0, GENO_IRQ_19 =1 when GENO_19 toggles to 0. IF GENO_LEVEL_19=1, GENO_IRQ_19 =1 when GENO_19 toggles to 1." "0,1" bitfld.long 0x00 18. " GENO_LEVEL_18 ,IF GENO_LEVEL_18=0, GENO_IRQ_18 =1 when GENO_18 toggles to 0. IF GENO_LEVEL_18=1, GENO_IRQ_18 =1 when GENO_18 toggles to 1." "0,1" bitfld.long 0x00 17. " GENO_LEVEL_17 ,IF GENO_LEVEL_17=0, GENO_IRQ_17 =1 when GENO_17 toggles to 0. IF GENO_LEVEL_17=1, GENO_IRQ_17 =1 when GENO_17 toggles to 1." "0,1" textline " " bitfld.long 0x00 16. " GENO_LEVEL_16 ,IF GENO_LEVEL_16=0, GENO_IRQ_16 =1 when GENO_16 toggles to 0. IF GENO_LEVEL_16=1, GENO_IRQ_16 =1 when GENO_16 toggles to 1." "0,1" bitfld.long 0x00 15. " GENO_LEVEL_15 ,IF GENO_LEVEL_15=0, GENO_IRQ_15 =1 when GENO_15 toggles to 0. IF GENO_LEVEL_15=1, GENO_IRQ_15 =1 when GENO_15 toggles to 1." "0,1" bitfld.long 0x00 14. " GENO_LEVEL_14 ,IF GENO_LEVEL_14=0, GENO_IRQ_14 =1 when GENO_14 toggles to 0. IF GENO_LEVEL_14=1, GENO_IRQ_14 =1 when GENO_14 toggles to 1." "0,1" textline " " bitfld.long 0x00 13. " GENO_LEVEL_13 ,IF GENO_LEVEL_13=0, GENO_IRQ_13 =1 when GENO_13 toggles to 0. IF GENO_LEVEL_13=1, GENO_IRQ_13 =1 when GENO_13 toggles to 1." "0,1" bitfld.long 0x00 12. " GENO_LEVEL_12 ,IF GENO_LEVEL_12=0, GENO_IRQ_12 =1 when GENO_12 toggles to 0. IF GENO_LEVEL_12=1, GENO_IRQ_12 =1 when GENO_12 toggles to 1." "0,1" bitfld.long 0x00 11. " GENO_LEVEL_11 ,IF GENO_LEVEL_11=0, GENO_IRQ_11 =1 when GENO_11 toggles to 0. IF GENO_LEVEL_11=1, GENO_IRQ_11 =1 when GENO_11 toggles to 1." "0,1" textline " " bitfld.long 0x00 10. " GENO_LEVEL_10 ,IF GENO_LEVEL_10=0, GENO_IRQ_10 =1 when GENO_10 toggles to 0. IF GENO_LEVEL_10=1, GENO_IRQ_10 =1 when GENO_10 toggles to 1." "0,1" bitfld.long 0x00 9. " GENO_LEVEL_9 ,IF GENO_LEVEL_9=0, GENO_IRQ_9 =1 when GENO_9 toggles to 0. IF GENO_LEVEL_9=1, GENO_IRQ_9 =1 when GENO_9 toggles to 1." "0,1" bitfld.long 0x00 8. " GENO_LEVEL_8 ,IF GENO_LEVEL_8=0, GENO_IRQ_8 =1 when GENO_8 toggles to 0. IF GENO_LEVEL_8=1, GENO_IRQ_8 =1 when GENO_8 toggles to 1." "0,1" textline " " bitfld.long 0x00 7. " GENO_LEVEL_7 ,IF GENO_LEVEL_7=0, GENO_IRQ_7 =1 when GENO_7 toggles to 0. IF GENO_LEVEL_7=1, GENO_IRQ_7 =1 when GENO_7 toggles to 1." "0,1" bitfld.long 0x00 6. " GENO_LEVEL_6 ,IF GENO_LEVEL_6=0, GENO_IRQ_6 =1 when GENO_6 toggles to 0. IF GENO_LEVEL_6=1, GENO_IRQ_6 =1 when GENO_6 toggles to 1." "0,1" bitfld.long 0x00 5. " GENO_LEVEL_5 ,IF GENO_LEVEL_5=0, GENO_IRQ_5 =1 when GENO_5 toggles to 0. IF GENO_LEVEL_5=1, GENO_IRQ_5 =1 when GENO_5 toggles to 1." "0,1" textline " " bitfld.long 0x00 4. " GENO_LEVEL_4 ,IF GENO_LEVEL_4=0, GENO_IRQ_4 =1 when GENO_4 toggles to 0. IF GENO_LEVEL_4=1, GENO_IRQ_4 =1 when GENO_4 toggles to 1." "0,1" bitfld.long 0x00 3. " GENO_LEVEL_3 ,IF GENO_LEVEL_3=0, GENO_IRQ_3 =1 when GENO_3 toggles to 0. IF GENO_LEVEL_3=1, GENO_IRQ_3 =1 when GENO_3 toggles to 1." "0,1" bitfld.long 0x00 2. " GENO_LEVEL_2 ,IF GENO_LEVEL_2=0, GENO_IRQ_2 =1 when GENO_2 toggles to 0. IF GENO_LEVEL_2=1, GENO_IRQ_2 =1 when GENO_2 toggles to 1." "0,1" textline " " bitfld.long 0x00 1. " GENO_LEVEL_1 ,IF GENO_LEVEL_1=0, GENO_IRQ_1 =1 when GENO_1 toggles to 0. IF GENO_LEVEL_1=1, GENO_IRQ_1 =1 when GENO_1 toggles to 1." "0,1" bitfld.long 0x00 0. " GENO_LEVEL_0 ,IF GENO_LEVEL_0=0, GENO_IRQ_0 =1 when GENO_0 toggles to 0. IF GENO_LEVEL_0=1, GENO_IRQ_0 =1 when GENO_0 toggles to 1." "0,1" tree.end tree.end tree.open "Dynamic_Memory_Manager" tree "DMM" base ad:0x4E000000 tree "Channel_0" width 22. group.long 0x40++0x3 line.long 0x00 "DMM_LISA_MAP_i_0,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. " SYS_ADDR ,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. " SYS_SIZE ,DMM system section size for view mapping i - . - . - . - . - . - . - . - ." "16-MiB_section,32-MiB_section,64-MiB_section,128-MiB_section,256-MiB_section,512-MiB_section,1-GiB_section,2-GiB_section" bitfld.long 0x00 18.--19. " SDRC_INTL ,SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled r.." "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " SDRC_ADDRSPC ,SDRAM controller address space for view mapping i" "0,1,2,3" bitfld.long 0x00 8.--9. " SDRC_MAP ,SDRAM controller mapping for view mapping i 0x0: Un-mapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be.." "0,1,2,3" hexmask.long.byte 0x00 0.--7. 1. " SDRC_ADDR ,SDRAM controller address MSB for view mapping i" group.long 0x504++0x3 line.long 0x00 "DMM_PAT_AREA_i_0,Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine..." hexmask.long.byte 0x00 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area for engine n" hexmask.long.byte 0x00 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area for engine n" textline " " hexmask.long.byte 0x00 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area for engine n" group.long 0x508++0x3 line.long 0x00 "DMM_PAT_CTRL_i_0,DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine..." bitfld.long 0x00 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " SYNC ,DMM PAT table reload synchronisation for engine n - . - ." "Not_synchronized,Synchronised" bitfld.long 0x00 4.--6. " DIRECTION ,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " START ,Starting a PAT table refill with engine n" "0,1" group.long 0x50C++0x3 line.long 0x00 "DMM_PAT_DATA_i_0,Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine..." hexmask.long 0x00 4.--31. 1. " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x500++0x3 line.long 0x00 "DMM_PAT_DESCR_i_0,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine... Writing to this register aborts the current ongoing area reload and .." hexmask.long 0x00 4.--31. 1. " ADDR ,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4C0++0x3 line.long 0x00 "DMM_PAT_STATUS_i_0,Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register..." hexmask.long.word 0x00 16.--24. 1. " CNT ,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. " ERROR ,Error happened in engine n - . - . - . - . - . - . - ." "No_error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " BYPASSED ,Engine n is bypassed. Direct access to the LUT is provided." "0,1" textline " " bitfld.long 0x00 4. " LINKED ,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x00 3. " DONE ,Area reloading finished for engine n" "0,1" bitfld.long 0x00 2. " RUN ,Area currently reloading for engine n" "0,1" textline " " bitfld.long 0x00 1. " VALID ,Valid area description for engine n" "0,1" bitfld.long 0x00 0. " READY ,Area registers ready for engine n" "0,1" group.long 0x440++0x3 line.long 0x00 "DMM_PAT_VIEW_MAP_i_0,PAT view mapping register" bitfld.long 0x00 31. " ACCESS_PAGE ,Kind of access for this page mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 24.--27. " CONT_PAGE ,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " ACCESS_32 ,Kind of access for this 32-bit mode container in view mapping i - . - ." "0,1" textline " " bitfld.long 0x00 16.--19. " CONT_32 ,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " ACCESS_16 ,Kind of access for this 16-bit mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 8.--11. " CONT_16 ,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " ACCESS_8 ,Kind of access for this 8-bit mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 0.--3. " CONT_8 ,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x620++0x3 line.long 0x00 "DMM_PEG_PRIO_k_0,DMM PEG Priority register" bitfld.long 0x00 31. " W7 ,Write-enable for P7 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " P7 ,Priority for initiator 8.k+7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W6 ,Write-enable for P6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " P6 ,Priority for initiator 8.k+6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W5 ,Write-enable for P5 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " P5 ,Priority for initiator 8.k+5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for P4 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " P4 ,Priority for initiator 8.k+4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W3 ,Write-enable for P3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " P3 ,Priority for initiator 8.k+3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W2 ,Write-enable for P2 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " P2 ,Priority for initiator 8.k+2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for P1 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " P1 ,Priority for initiator 8.k+1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W0 ,Write-enable for P0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " P0 ,Priority for initiator 8.k" "0,1,2,3,4,5,6,7" tree.end tree "Channel_1" width 22. group.long 0x44++0x3 line.long 0x00 "DMM_LISA_MAP_i_1,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. " SYS_ADDR ,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. " SYS_SIZE ,DMM system section size for view mapping i - . - . - . - . - . - . - . - ." "16-MiB_section,32-MiB_section,64-MiB_section,128-MiB_section,256-MiB_section,512-MiB_section,1-GiB_section,2-GiB_section" bitfld.long 0x00 18.--19. " SDRC_INTL ,SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled r.." "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " SDRC_ADDRSPC ,SDRAM controller address space for view mapping i" "0,1,2,3" bitfld.long 0x00 8.--9. " SDRC_MAP ,SDRAM controller mapping for view mapping i 0x0: Un-mapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be.." "0,1,2,3" hexmask.long.byte 0x00 0.--7. 1. " SDRC_ADDR ,SDRAM controller address MSB for view mapping i" group.long 0x514++0x3 line.long 0x00 "DMM_PAT_AREA_i_1,Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine..." hexmask.long.byte 0x00 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area for engine n" hexmask.long.byte 0x00 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area for engine n" textline " " hexmask.long.byte 0x00 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area for engine n" group.long 0x518++0x3 line.long 0x00 "DMM_PAT_CTRL_i_1,DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine..." bitfld.long 0x00 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " SYNC ,DMM PAT table reload synchronisation for engine n - . - ." "Not_synchronized,Synchronised" bitfld.long 0x00 4.--6. " DIRECTION ,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " START ,Starting a PAT table refill with engine n" "0,1" group.long 0x51C++0x3 line.long 0x00 "DMM_PAT_DATA_i_1,Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine..." hexmask.long 0x00 4.--31. 1. " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x510++0x3 line.long 0x00 "DMM_PAT_DESCR_i_1,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine... Writing to this register aborts the current ongoing area reload and .." hexmask.long 0x00 4.--31. 1. " ADDR ,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4C4++0x3 line.long 0x00 "DMM_PAT_STATUS_i_1,Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register..." hexmask.long.word 0x00 16.--24. 1. " CNT ,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. " ERROR ,Error happened in engine n - . - . - . - . - . - . - ." "No_error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " BYPASSED ,Engine n is bypassed. Direct access to the LUT is provided." "0,1" textline " " bitfld.long 0x00 4. " LINKED ,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x00 3. " DONE ,Area reloading finished for engine n" "0,1" bitfld.long 0x00 2. " RUN ,Area currently reloading for engine n" "0,1" textline " " bitfld.long 0x00 1. " VALID ,Valid area description for engine n" "0,1" bitfld.long 0x00 0. " READY ,Area registers ready for engine n" "0,1" group.long 0x444++0x3 line.long 0x00 "DMM_PAT_VIEW_MAP_i_1,PAT view mapping register" bitfld.long 0x00 31. " ACCESS_PAGE ,Kind of access for this page mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 24.--27. " CONT_PAGE ,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " ACCESS_32 ,Kind of access for this 32-bit mode container in view mapping i - . - ." "0,1" textline " " bitfld.long 0x00 16.--19. " CONT_32 ,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " ACCESS_16 ,Kind of access for this 16-bit mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 8.--11. " CONT_16 ,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " ACCESS_8 ,Kind of access for this 8-bit mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 0.--3. " CONT_8 ,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x624++0x3 line.long 0x00 "DMM_PEG_PRIO_k_1,DMM PEG Priority register" bitfld.long 0x00 31. " W7 ,Write-enable for P7 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " P7 ,Priority for initiator 8.k+7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W6 ,Write-enable for P6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " P6 ,Priority for initiator 8.k+6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W5 ,Write-enable for P5 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " P5 ,Priority for initiator 8.k+5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for P4 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " P4 ,Priority for initiator 8.k+4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W3 ,Write-enable for P3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " P3 ,Priority for initiator 8.k+3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W2 ,Write-enable for P2 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " P2 ,Priority for initiator 8.k+2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for P1 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " P1 ,Priority for initiator 8.k+1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W0 ,Write-enable for P0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " P0 ,Priority for initiator 8.k" "0,1,2,3,4,5,6,7" tree.end tree "Channel_2" width 22. group.long 0x48++0x3 line.long 0x00 "DMM_LISA_MAP_i_2,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. " SYS_ADDR ,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. " SYS_SIZE ,DMM system section size for view mapping i - . - . - . - . - . - . - . - ." "16-MiB_section,32-MiB_section,64-MiB_section,128-MiB_section,256-MiB_section,512-MiB_section,1-GiB_section,2-GiB_section" bitfld.long 0x00 18.--19. " SDRC_INTL ,SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled r.." "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " SDRC_ADDRSPC ,SDRAM controller address space for view mapping i" "0,1,2,3" bitfld.long 0x00 8.--9. " SDRC_MAP ,SDRAM controller mapping for view mapping i 0x0: Un-mapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be.." "0,1,2,3" hexmask.long.byte 0x00 0.--7. 1. " SDRC_ADDR ,SDRAM controller address MSB for view mapping i" group.long 0x524++0x3 line.long 0x00 "DMM_PAT_AREA_i_2,Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine..." hexmask.long.byte 0x00 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area for engine n" hexmask.long.byte 0x00 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area for engine n" textline " " hexmask.long.byte 0x00 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area for engine n" group.long 0x528++0x3 line.long 0x00 "DMM_PAT_CTRL_i_2,DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine..." bitfld.long 0x00 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " SYNC ,DMM PAT table reload synchronisation for engine n - . - ." "Not_synchronized,Synchronised" bitfld.long 0x00 4.--6. " DIRECTION ,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " START ,Starting a PAT table refill with engine n" "0,1" group.long 0x52C++0x3 line.long 0x00 "DMM_PAT_DATA_i_2,Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine..." hexmask.long 0x00 4.--31. 1. " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x520++0x3 line.long 0x00 "DMM_PAT_DESCR_i_2,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine... Writing to this register aborts the current ongoing area reload and .." hexmask.long 0x00 4.--31. 1. " ADDR ,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4C8++0x3 line.long 0x00 "DMM_PAT_STATUS_i_2,Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register..." hexmask.long.word 0x00 16.--24. 1. " CNT ,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. " ERROR ,Error happened in engine n - . - . - . - . - . - . - ." "No_error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " BYPASSED ,Engine n is bypassed. Direct access to the LUT is provided." "0,1" textline " " bitfld.long 0x00 4. " LINKED ,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x00 3. " DONE ,Area reloading finished for engine n" "0,1" bitfld.long 0x00 2. " RUN ,Area currently reloading for engine n" "0,1" textline " " bitfld.long 0x00 1. " VALID ,Valid area description for engine n" "0,1" bitfld.long 0x00 0. " READY ,Area registers ready for engine n" "0,1" group.long 0x448++0x3 line.long 0x00 "DMM_PAT_VIEW_MAP_i_2,PAT view mapping register" bitfld.long 0x00 31. " ACCESS_PAGE ,Kind of access for this page mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 24.--27. " CONT_PAGE ,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " ACCESS_32 ,Kind of access for this 32-bit mode container in view mapping i - . - ." "0,1" textline " " bitfld.long 0x00 16.--19. " CONT_32 ,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " ACCESS_16 ,Kind of access for this 16-bit mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 8.--11. " CONT_16 ,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " ACCESS_8 ,Kind of access for this 8-bit mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 0.--3. " CONT_8 ,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x628++0x3 line.long 0x00 "DMM_PEG_PRIO_k_2,DMM PEG Priority register" bitfld.long 0x00 31. " W7 ,Write-enable for P7 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " P7 ,Priority for initiator 8.k+7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W6 ,Write-enable for P6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " P6 ,Priority for initiator 8.k+6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W5 ,Write-enable for P5 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " P5 ,Priority for initiator 8.k+5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for P4 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " P4 ,Priority for initiator 8.k+4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W3 ,Write-enable for P3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " P3 ,Priority for initiator 8.k+3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W2 ,Write-enable for P2 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " P2 ,Priority for initiator 8.k+2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for P1 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " P1 ,Priority for initiator 8.k+1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W0 ,Write-enable for P0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " P0 ,Priority for initiator 8.k" "0,1,2,3,4,5,6,7" tree.end tree "Channel_3" width 22. group.long 0x4C++0x3 line.long 0x00 "DMM_LISA_MAP_i_3,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. " SYS_ADDR ,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. " SYS_SIZE ,DMM system section size for view mapping i - . - . - . - . - . - . - . - ." "16-MiB_section,32-MiB_section,64-MiB_section,128-MiB_section,256-MiB_section,512-MiB_section,1-GiB_section,2-GiB_section" bitfld.long 0x00 18.--19. " SDRC_INTL ,SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled r.." "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " SDRC_ADDRSPC ,SDRAM controller address space for view mapping i" "0,1,2,3" bitfld.long 0x00 8.--9. " SDRC_MAP ,SDRAM controller mapping for view mapping i 0x0: Un-mapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be.." "0,1,2,3" hexmask.long.byte 0x00 0.--7. 1. " SDRC_ADDR ,SDRAM controller address MSB for view mapping i" group.long 0x534++0x3 line.long 0x00 "DMM_PAT_AREA_i_3,Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine..." hexmask.long.byte 0x00 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area for engine n" hexmask.long.byte 0x00 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area for engine n" textline " " hexmask.long.byte 0x00 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area for engine n" group.long 0x538++0x3 line.long 0x00 "DMM_PAT_CTRL_i_3,DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine..." bitfld.long 0x00 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " SYNC ,DMM PAT table reload synchronisation for engine n - . - ." "Not_synchronized,Synchronised" bitfld.long 0x00 4.--6. " DIRECTION ,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " START ,Starting a PAT table refill with engine n" "0,1" group.long 0x53C++0x3 line.long 0x00 "DMM_PAT_DATA_i_3,Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine..." hexmask.long 0x00 4.--31. 1. " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x530++0x3 line.long 0x00 "DMM_PAT_DESCR_i_3,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine... Writing to this register aborts the current ongoing area reload and .." hexmask.long 0x00 4.--31. 1. " ADDR ,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4CC++0x3 line.long 0x00 "DMM_PAT_STATUS_i_3,Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register..." hexmask.long.word 0x00 16.--24. 1. " CNT ,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. " ERROR ,Error happened in engine n - . - . - . - . - . - . - ." "No_error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " BYPASSED ,Engine n is bypassed. Direct access to the LUT is provided." "0,1" textline " " bitfld.long 0x00 4. " LINKED ,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x00 3. " DONE ,Area reloading finished for engine n" "0,1" bitfld.long 0x00 2. " RUN ,Area currently reloading for engine n" "0,1" textline " " bitfld.long 0x00 1. " VALID ,Valid area description for engine n" "0,1" bitfld.long 0x00 0. " READY ,Area registers ready for engine n" "0,1" group.long 0x44C++0x3 line.long 0x00 "DMM_PAT_VIEW_MAP_i_3,PAT view mapping register" bitfld.long 0x00 31. " ACCESS_PAGE ,Kind of access for this page mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 24.--27. " CONT_PAGE ,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " ACCESS_32 ,Kind of access for this 32-bit mode container in view mapping i - . - ." "0,1" textline " " bitfld.long 0x00 16.--19. " CONT_32 ,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " ACCESS_16 ,Kind of access for this 16-bit mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 8.--11. " CONT_16 ,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " ACCESS_8 ,Kind of access for this 8-bit mode container in view mapping i - . - ." "0,1" bitfld.long 0x00 0.--3. " CONT_8 ,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x62C++0x3 line.long 0x00 "DMM_PEG_PRIO_k_3,DMM PEG Priority register" bitfld.long 0x00 31. " W7 ,Write-enable for P7 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " P7 ,Priority for initiator 8.k+7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W6 ,Write-enable for P6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " P6 ,Priority for initiator 8.k+6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W5 ,Write-enable for P5 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " P5 ,Priority for initiator 8.k+5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for P4 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " P4 ,Priority for initiator 8.k+4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W3 ,Write-enable for P3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " P3 ,Priority for initiator 8.k+3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W2 ,Write-enable for P2 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " P2 ,Priority for initiator 8.k+2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for P1 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " P1 ,Priority for initiator 8.k+1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W0 ,Write-enable for P0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " P0 ,Priority for initiator 8.k" "0,1,2,3,4,5,6,7" group.long 0x630++0x3 line.long 0x00 "DMM_PEG_PRIO_k_4,DMM PEG Priority register" bitfld.long 0x00 31. " W7 ,Write-enable for P7 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " P7 ,Priority for initiator 8.k+7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W6 ,Write-enable for P6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " P6 ,Priority for initiator 8.k+6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W5 ,Write-enable for P5 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " P5 ,Priority for initiator 8.k+5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for P4 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " P4 ,Priority for initiator 8.k+4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W3 ,Write-enable for P3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " P3 ,Priority for initiator 8.k+3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W2 ,Write-enable for P2 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " P2 ,Priority for initiator 8.k+2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for P1 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " P1 ,Priority for initiator 8.k+1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W0 ,Write-enable for P0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " P0 ,Priority for initiator 8.k" "0,1,2,3,4,5,6,7" group.long 0x634++0x3 line.long 0x00 "DMM_PEG_PRIO_k_5,DMM PEG Priority register" bitfld.long 0x00 31. " W7 ,Write-enable for P7 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " P7 ,Priority for initiator 8.k+7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W6 ,Write-enable for P6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " P6 ,Priority for initiator 8.k+6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W5 ,Write-enable for P5 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " P5 ,Priority for initiator 8.k+5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for P4 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " P4 ,Priority for initiator 8.k+4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W3 ,Write-enable for P3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " P3 ,Priority for initiator 8.k+3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W2 ,Write-enable for P2 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " P2 ,Priority for initiator 8.k+2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for P1 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " P1 ,Priority for initiator 8.k+1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W0 ,Write-enable for P0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " P0 ,Priority for initiator 8.k" "0,1,2,3,4,5,6,7" group.long 0x638++0x3 line.long 0x00 "DMM_PEG_PRIO_k_6,DMM PEG Priority register" bitfld.long 0x00 31. " W7 ,Write-enable for P7 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " P7 ,Priority for initiator 8.k+7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W6 ,Write-enable for P6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " P6 ,Priority for initiator 8.k+6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W5 ,Write-enable for P5 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " P5 ,Priority for initiator 8.k+5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for P4 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " P4 ,Priority for initiator 8.k+4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W3 ,Write-enable for P3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " P3 ,Priority for initiator 8.k+3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W2 ,Write-enable for P2 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " P2 ,Priority for initiator 8.k+2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for P1 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " P1 ,Priority for initiator 8.k+1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W0 ,Write-enable for P0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " P0 ,Priority for initiator 8.k" "0,1,2,3,4,5,6,7" group.long 0x63C++0x3 line.long 0x00 "DMM_PEG_PRIO_k_7,DMM PEG Priority register" bitfld.long 0x00 31. " W7 ,Write-enable for P7 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " P7 ,Priority for initiator 8.k+7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W6 ,Write-enable for P6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " P6 ,Priority for initiator 8.k+6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W5 ,Write-enable for P5 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " P5 ,Priority for initiator 8.k+5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for P4 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " P4 ,Priority for initiator 8.k+4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W3 ,Write-enable for P3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " P3 ,Priority for initiator 8.k+3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W2 ,Write-enable for P2 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " P2 ,Priority for initiator 8.k+2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for P1 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " P1 ,Priority for initiator 8.k+1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W0 ,Write-enable for P0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " P0 ,Priority for initiator 8.k" "0,1,2,3,4,5,6,7" tree.end textline "" width 23. rgroup.long 0x0++0x3 line.long 0x00 "DMM_REVISION,DMM Revision Number" hexmask.long 0x00 0.--31. 1. " REVISION ,Revision Number" rgroup.long 0x4++0x3 line.long 0x00 "DMM_HWINFO,DMM hardware configuration" bitfld.long 0x00 16.--19. " ROBIN_CNT ,Number of ROBIN in the DMM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ELLA_CNT ,Number of ELLA in the DMM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TILER_CNT ,Number of TILER in the DMM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x8++0x3 line.long 0x00 "DMM_LISA_HWINFO,DMM hardware configuration for LISA" bitfld.long 0x00 8.--11. " SDRC_CNT ,Number of attached SDRAM controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " SECTION_CNT ,Number of DMM sections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10++0x3 line.long 0x00 "DMM_SYSCONFIG,DMM clock management configuration" bitfld.long 0x00 2.--3. " IDLE_MODE ,Configuration of the local target state management mode. - . - . - . - ." "0,1,2,?..." group.long 0x1C++0x3 line.long 0x00 "DMM_LISA_LOCK,DMM memory mapping lock" bitfld.long 0x00 0. " LOCK ,DMM lock map - . - . - . - ." "un-locked,locked" rgroup.long 0x208++0x3 line.long 0x00 "DMM_TILER_HWINFO,DMM hardware configuration for TILER" bitfld.long 0x00 0.--4. " OR_CNT ,Number of TILER orientation entries - . - . - . - . - ." "0,One_orientation_entry,Two_orientation_entries,3,Four_orientation_entries,5,6,7,Eight_orientation_entries,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x220++0x3 line.long 0x00 "DMM_TILER_OR0,DMM TILER orientation (initiators 0 to 7)" bitfld.long 0x00 31. " W7 ,Write-enable for OR7 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " OR7 ,Orientation for initiator 7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W6 ,Write-enable for OR6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " OR6 ,Orientation for initiator 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W5 ,Write-enable for OR5 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " OR5 ,Orientation for initiator 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for OR4 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " OR4 ,Orientation for initiator 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W3 ,Write-enable for OR3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " OR3 ,Orientation for initiator 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W2 ,Write-enable for OR2 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " OR2 ,Orientation for initiator 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for OR1 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " OR1 ,Orientation for initiator 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W0 ,Write-enable for OR0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " OR0 ,Orientation for initiator 0" "0,1,2,3,4,5,6,7" group.long 0x224++0x3 line.long 0x00 "DMM_TILER_OR1,DMM TILER orientation (initiators 8 to 15)" bitfld.long 0x00 31. " W15 ,Write-enable for OR15 bit field - . - ." "0,1" bitfld.long 0x00 28.--30. " OR15 ,Orientation for initiator 15" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " W14 ,Write-enable for OR14 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--26. " OR14 ,Orientation for initiator 14" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " W13 ,Write-enable for OR13 bit field - . - ." "0,1" bitfld.long 0x00 20.--22. " OR13 ,Orientation for initiator 13" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 19. " W12 ,Write-enable for OR12 bit field - . - ." "0,1" bitfld.long 0x00 16.--18. " OR12 ,Orientation for initiator 12" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " W11 ,Write-enable for OR11 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--14. " OR11 ,Orientation for initiator 11" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " W10 ,Write-enable for OR10 bit field - . - ." "0,1" bitfld.long 0x00 8.--10. " OR10 ,Orientation for initiator 10" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 7. " W9 ,Write-enable for OR9 bit field - . - ." "0,1" bitfld.long 0x00 4.--6. " OR9 ,Orientation for initiator 9" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " W8 ,Write-enable for OR8 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--2. " OR8 ,Orientation for initiator 8" "0,1,2,3,4,5,6,7" rgroup.long 0x408++0x3 line.long 0x00 "DMM_PAT_HWINFO,DMM hardware configuration for PAT" bitfld.long 0x00 24.--28. " ENGINE_CNT ,Number of PAT refill engines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " LUT_CNT ,Number of PAT LUT for page-grained physical address translation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " VIEW_MAP_CNT ,Number of internal PAT view mappings. - . - . - . - ." "0,One_view_map,Two_view_maps,3,Four_view_maps,5,6,7,Eight_view_maps,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 0.--6. 1. " VIEW_CNT ,Number of PAT view entries - . - . - . - . - . - . - ." rgroup.long 0x40C++0x3 line.long 0x00 "DMM_PAT_GEOMETRY,PAT geometry-related settings" bitfld.long 0x00 24.--26. " CONT_HGHT ,Container height in pages - . - . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " CONT_WDTH ,Container width in pages - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--13. " ADDR_RANGE ,PAT output physical address range - . - . - . - . - . - ." "0,128-MiB_range,256-MiB_range,3,512-MiB_range,5,6,7,1-GiB_range,9,10,11,12,13,14,15,2-GiB_range,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,4-GiB_range,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--4. " PAGE_SZ ,Page size in 4-kiB granularity - . - . - ." "0,4-kiB_page,2,3,16-kiB_page,5,6,7,8,9,10,11,12,13,14,15,64-kiB_page,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x410++0x3 line.long 0x00 "DMM_PAT_CONFIG,This is the PAT configuration register aimed at defining the major PAT configuration of each refill engine." bitfld.long 0x00 3. " MODE3 ,Mode of refill engine 3 - . - ." "Normal_mode,Direct_LUT_access" bitfld.long 0x00 2. " MODE2 ,Mode of refill engine 2 - . - ." "Normal_mode,Direct_LUT_access" bitfld.long 0x00 1. " MODE1 ,Mode of refill engine 1 - . - ." "Normal_mode,Direct_LUT_access" textline " " bitfld.long 0x00 0. " MODE0 ,Mode of refill engine 0 - . - ." "Normal_mode,Direct_LUT_access" group.long 0x420++0x3 line.long 0x00 "DMM_PAT_VIEW0,DMM PAT View register (initiators 0 to 7)" bitfld.long 0x00 31. " W7 ,Write-enable for V7 bit field - . - ." "0,1" bitfld.long 0x00 28.--29. " V7 ,PAT view for initiator 7" "0,1,2,3" bitfld.long 0x00 27. " W6 ,Write-enable for V6 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--25. " V6 ,PAT view for initiator 6" "0,1,2,3" bitfld.long 0x00 23. " W5 ,Write-enable for V5 bit field - . - ." "0,1" bitfld.long 0x00 20.--21. " V5 ,PAT view for initiator 5" "0,1,2,3" textline " " bitfld.long 0x00 19. " W4 ,Write-enable for V4 bit field - . - ." "0,1" bitfld.long 0x00 16.--17. " V4 ,PAT view for initiator 4" "0,1,2,3" bitfld.long 0x00 15. " W3 ,Write-enable for V3 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--13. " V3 ,PAT view for initiator 3" "0,1,2,3" bitfld.long 0x00 11. " W2 ,Write-enable for V2 bit field - . - ." "0,1" bitfld.long 0x00 8.--9. " V2 ,PAT view for initiator 2" "0,1,2,3" textline " " bitfld.long 0x00 7. " W1 ,Write-enable for V1 bit field - . - ." "0,1" bitfld.long 0x00 4.--5. " V1 ,PAT view for initiator 1" "0,1,2,3" bitfld.long 0x00 3. " W0 ,Write-enable for V0 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " V0 ,PAT view for initiator 0" "0,1,2,3" group.long 0x424++0x3 line.long 0x00 "DMM_PAT_VIEW1,DMM PAT view register (initiators 8 to 15)" bitfld.long 0x00 31. " W15 ,Write-enable for V15 bit field - . - ." "0,1" bitfld.long 0x00 28.--29. " V15 ,PAT view for initiator 15" "0,1,2,3" bitfld.long 0x00 27. " W14 ,Write-enable for V14 bit field - . - ." "0,1" textline " " bitfld.long 0x00 24.--25. " V14 ,PAT view for initiator 14" "0,1,2,3" bitfld.long 0x00 23. " W13 ,Write-enable for V13 bit field - . - ." "0,1" bitfld.long 0x00 20.--21. " V13 ,PAT view for initiator 13" "0,1,2,3" textline " " bitfld.long 0x00 19. " W12 ,Write-enable for V12 bit field - . - ." "0,1" bitfld.long 0x00 16.--17. " V12 ,PAT view for initiator 12" "0,1,2,3" bitfld.long 0x00 15. " W11 ,Write-enable for V11 bit field - . - ." "0,1" textline " " bitfld.long 0x00 12.--13. " V11 ,PAT view for initiator 11" "0,1,2,3" bitfld.long 0x00 11. " W10 ,Write-enable for V10 bit field - . - ." "0,1" bitfld.long 0x00 8.--9. " V10 ,PAT view for initiator 10" "0,1,2,3" textline " " bitfld.long 0x00 7. " W9 ,Write-enable for V9 bit field - . - ." "0,1" bitfld.long 0x00 4.--5. " V9 ,PAT view for initiator 9" "0,1,2,3" bitfld.long 0x00 3. " W8 ,Write-enable for V8 bit field - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " V8 ,PAT view for initiator 8" "0,1,2,3" group.long 0x460++0x3 line.long 0x00 "DMM_PAT_VIEW_MAP_BASE,Base address of all view mappings" bitfld.long 0x00 31. " BASE_ADDR ,MSB of the PAT view mapping base address" "0,1" group.long 0x480++0x3 line.long 0x00 "DMM_PAT_IRQSTATUS_RAW,Per-event raw interrupt status vector. Raw status is set even if the related event is not enabled. Write 1 to set the (raw) status, mostly for debug. n = 0 for the first interrupt status raw register, n = 1 for the second interrup.." bitfld.long 0x00 15. " ERR_LUT_MISS1 ,Access to a yet-to-be-refilled area event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" bitfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" bitfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" textline " " bitfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" bitfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" bitfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" textline " " bitfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 4.n+1 - . - . - . - ." "0,1" bitfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 4.n+1 - . - . - . - ." "0,1" bitfld.long 0x00 7. " ERR_LUT_MISS0 ,Access to a yet-to-be-refilled area event in area 4.n - . - . - . - ." "0,Error_event_happened" textline " " bitfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 4.n - . - . - . - ." "0,Error_event_happened" bitfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 4.n - . - . - . - ." "0,Error_event_happened" bitfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 4.n - . - . - . - ." "0,Error_event_happened" textline " " bitfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 4.n - . - . - . - ." "0,Error_event_happened" bitfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 4.n - . - . - . - ." "0,Error_event_happened" bitfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 4.n - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 4.n - . - . - . - ." "0,1" group.long 0x490++0x3 line.long 0x00 "DMM_PAT_IRQSTATUS,Per-event 'enabled' interrupt status vector. Enabled status is not set unless the event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). n = 0 for the f.." eventfld.long 0x00 15. " ERR_LUT_MISS1 ,Access to a yet-to-be-refilled area event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" eventfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" eventfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" textline " " eventfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" eventfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" eventfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 4.n+1 - . - . - . - ." "0,Error_event_happened" textline " " eventfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 4.n+1 - . - . - . - ." "0,1" eventfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 4.n+1 - . - . - . - ." "0,1" eventfld.long 0x00 7. " ERR_LUT_MISS0 ,Access to a yet-to-be-refilled area event in area 4.n - . - . - . - ." "0,Error_event_happened" textline " " eventfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 4.n - . - . - . - ." "0,Error_event_happened" eventfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 4.n - . - . - . - ." "0,Error_event_happened" eventfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 4.n - . - . - . - ." "0,Error_event_happened" textline " " eventfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 4.n - . - . - . - ." "0,Error_event_happened" eventfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 4.n - . - . - . - ." "0,Error_event_happened" eventfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 4.n - . - . - . - ." "0,1" textline " " eventfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 4.n - . - . - . - ." "0,1" group.long 0x4A0++0x3 line.long 0x00 "DMM_PAT_IRQENABLE_SET,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. n = 0 for the first interrupt enable set register, n = 1 for the second interrupt enable set register..." bitfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" bitfld.long 0x00 14. " ERR_UPD_DATA1 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" bitfld.long 0x00 13. " ERR_UPD_CTRL1 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " ERR_UPD_AREA1 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" bitfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" bitfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " FILL_LST1 ,End of refill interrupt source mask for the last descriptior in area 4.n+1 - . - . - . - ." "0,1" bitfld.long 0x00 8. " FILL_DSC1 ,End of refill interrupt source mask for any descriptior in area 4.n+1 - . - . - . - ." "0,1" bitfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " ERR_UPD_DATA0 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n - . - . - . - ." "0,1" bitfld.long 0x00 5. " ERR_UPD_CTRL0 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n - . - . - . - ." "0,1" bitfld.long 0x00 4. " ERR_UPD_AREA0 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer interrupt source mask for area 4.n - . - . - . - ." "0,1" bitfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer interrupt source mask for area 4.n - . - . - . - ." "0,1" bitfld.long 0x00 1. " FILL_LST0 ,End of refill interrupt source mask for the last descriptior in area 4.n - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " FILL_DSC0 ,End of refill interrupt source mask for any descriptior in area 4.n - . - . - . - ." "0,1" group.long 0x4B0++0x3 line.long 0x00 "DMM_PAT_IRQENABLE_CLR,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. n = 0 for the first interrupt enable clear register, n = 1 for the second interrupt enable clear register...." eventfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" eventfld.long 0x00 14. " ERR_UPD_DATA1 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" eventfld.long 0x00 13. " ERR_UPD_CTRL1 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" textline " " eventfld.long 0x00 12. " ERR_UPD_AREA1 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" eventfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" eventfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer interrupt source mask for area 4.n+1 - . - . - . - ." "0,1" textline " " eventfld.long 0x00 9. " FILL_LST1 ,End of refill interrupt source mask for the last descriptior in area 4.n+1 - . - . - . - ." "0,1" eventfld.long 0x00 8. " FILL_DSC1 ,End of refill interrupt source mask for any descriptior in area 4.n+1 - . - . - . - ." "0,1" eventfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n - . - . - . - ." "0,1" textline " " eventfld.long 0x00 6. " ERR_UPD_DATA0 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n - . - . - . - ." "0,1" eventfld.long 0x00 5. " ERR_UPD_CTRL0 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n - . - . - . - ." "0,1" eventfld.long 0x00 4. " ERR_UPD_AREA0 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n - . - . - . - ." "0,1" textline " " eventfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer interrupt source mask for area 4.n - . - . - . - ." "0,1" eventfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer interrupt source mask for area 4.n - . - . - . - ." "0,1" eventfld.long 0x00 1. " FILL_LST0 ,End of refill interrupt source mask for the last descriptior in area 4.n - . - . - . - ." "0,1" textline " " eventfld.long 0x00 0. " FILL_DSC0 ,End of refill interrupt source mask for any descriptior in area 4.n - . - . - . - ." "0,1" rgroup.long 0x608++0x3 line.long 0x00 "DMM_PEG_HWINFO,DMM hardware configuration for PEG" hexmask.long.byte 0x00 0.--6. 1. " PRIO_CNT ,Number of PEG priority entries - . - . - . - . - . - . - ." group.long 0x640++0x3 line.long 0x00 "DMM_PEG_PRIO_PAT,DMM PEG Priority register for the internal PAT engine." bitfld.long 0x00 3. " W_PAT ,Write-enable for P_PAT bit field - . - ." "0,1" bitfld.long 0x00 0.--2. " P_PAT ,Priority for PAT engine" "0,1,2,3,4,5,6,7" tree.end tree.end tree.open "EMIF_Controller" tree.open "EMIF1" tree "EMIF1" base ad:0x4C000000 width 27. group.long 0x0++0x3 line.long 0x00 "EMIF_MOD_ID_REV,Revision number register" rgroup.long 0x4++0x3 line.long 0x00 "EMIF_STATUS,SDRAM Status Register (STATUS)" bitfld.long 0x00 31. " REG_BE ,Big endian mode select for 8 and 16-bit devices, set to 1 for big endian or 0 for little endian operation." "0,1" bitfld.long 0x00 30. " REG_DUAL_CLK_MODE ,Dual Clock mode. Defines whether the L3_clk and EMIF_FCLK are asynchronous. L3_clk and EMIF_FCLK are asynchronous, if set to 1." "0,1" bitfld.long 0x00 29. " REG_FAST_INIT ,Fast Init. Defines whether the EMIF fast initialization mode has been enabled. Fast initialization is enabled if set to 1." "0,1" textline " " bitfld.long 0x00 2. " REG_PHY_DLL_READY ,DDR PHY Ready. Reflects the value on the phy_ready port (active high) that defines whether the DDR PHY is ready for normal operation. The DDR PHY is ready for normal operation, if set to 1." "0,1" group.long 0x8++0x3 line.long 0x00 "EMIF_SDRAM_CONFIG,SDRAM Config Register. A write to this register will cause the EMIF to start the SDRAM initialization sequence if it was not performed previously because [31] REG_INITREF_DIS was a zero." bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection. Set to 4 for LPDDR2-S4, Set to 5 for LPDDR2-S2 All other value are reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position. Set to 0 to assign internal bank address bits from L3 address as shown in and . Set to 1, 2, or 3 to assign internal bank address bits from L3 address as shown in , , and ." "0,1,2,3" bitfld.long 0x00 23. " REG_DDR2_DDQS ,DDR2 differential DQS enable. - Set to 0 for single-ended DQS. . - . - Set to 1 for differential DQS. . - . - This bit is only for DDR2 mode; because the device supports LPDDR2, this bit is don?t care. . - ." "0,1" textline " " bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select. Set to 1 to disable DLL inside SDRAM." "0,1" bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width. Set to 0 for 32-bit and set to 1 for 16-bit. All other values are reserved." "0,1,2,3" bitfld.long 0x00 10.--13. " REG_CL ,CAS Latency (referred to as read latency (RL) in some SDRAM specs). The value of this field defines the CAS latency to be used when accessing connected SDRAM devices. Value of 3, 4, 5, 6, 7, and 8 (CAS latency o.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size. Defines the number of row address bits of connected SDRAM devices. Set to 0 for 9 row bits, Set to 1 for 10 row bits, Set to 2 for 11 row bits, Set to 3 for 12 row bits, Set to 4 for 13 row bits, Set.." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup. Defines number of banks inside connected SDRAM devices. Set to 0 for 1 bank, Set to 1 for 2 banks, Set to 2 for 4 banks, Set to 3 for 8 banks. All other values are reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " REG_EBANK ,External chip-select setup. Defines whether SDRAM accesses will use 1 or 2 chip-select lines. Set to 0 to use pad_cs_o_n[0] only. Set to 1 to use pad_cs_o_n[1:0]. This bit will automaticlly be set to 0 if EMIF_S.." "0,1" textline " " bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size. Defines the internal page size of connected SDRAM devices. Set to 0 for 256-word page (8 column bits), Set to 1 for 512-word page (9 column bits), Set to 2 for 1024-word page (10 column bits), Set t.." "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x00 "EMIF_SDRAM_CONFIG_2," bitfld.long 0x00 30. " REG_CS1NVMEN ,CS1 LPDDR2-NVM enable. Set to 1 if LPDDR2-NVM is connected to CS1. This bit will automatically be set to 0 if reg_sdram_type field in the SDRAM Config register is not set to LPDDR2." "0,1" bitfld.long 0x00 27. " REG_EBANK_POS ,External bank position. Set to 0 to assign external bank address bits from lower OCP address as shown in tables. Set to 1 to assign external bank address bits from higher OCP address bits as shown in ta.." "0,1" bitfld.long 0x00 4.--5. " REG_RDBNUM ,Row Buffer setup. Defines number of row buffers inside connected LPDDR2-NVM devices. Set to 0 for 1 row buffer, set to 1 for 2 row buffers, set to 2 for 4 row buffers, and set to 3 for 8 row buffers. All other v.." "0,1,2,3" textline " " bitfld.long 0x00 0.--2. " REG_RDBSIZE ,Row Data Buffer Size. Defines the row data buffer size of connected LPDDR2-NVM devices. Set to 0 for 32 bytes, set to 1 for 64 bytes, set to 2 for 128 bytes, set to 3 for 256 bytes, set to 4 for 512 bytes, set.." "0,1,2,3,4,5,6,7" group.long 0x10++0x3 line.long 0x00 "EMIF_SDRAM_REF_CTRL,SDRAM Refresh Control Register" bitfld.long 0x00 31. " REG_INITREF_DIS ,Initialization and Refresh disable. When set to 1, EMIF will disable SDRAM initialization and refreshes, but will carry out SDRAM write/read transactions." "0,1" hexmask.long.word 0x00 0.--15. 1. " REG_REFRESH_RATE ,Refresh Rate. Value in this field is used to define the rate at which connected SDRAM devices will be refreshed. SDRAM refresh rate = DDR_PHY_CLK / REG_REFRESH_RATE. If REG_REFRESH_RATE &lt; (8 ? RE.." group.long 0x14++0x3 line.long 0x00 "EMIF_SDRAM_REF_CTRL_SHDW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x00 0.--15. 1. " REG_REFRESH_RATE_SHDW ,Shadow field for REG_REFRESH_RATE. This field is loaded intoEMIF_SDRAM_REF_CTRL[15:0] REG_REFRESH_RATE field when SIdleAck is asserted. This register is not auto corrected when the value is invalid." group.long 0x18++0x3 line.long 0x00 "EMIF_SDRAM_TIM_1,SDRAM Timing 1 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x00 25.--28. " REG_T_RP ,Minimum number of DDR clock cycles from Precharge to Activate or Refresh, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21.--24. " REG_T_RCD ,Minimum number of DDR clock cycles from Activate to Read or Write, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " REG_T_WR ,Minimum number of DDR clock cycles from last Write transfer to Precharge, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--16. " REG_T_RAS ,Minimum number of DDR clock cycles from Activate to Precharge, minus one. reg_t_ras value needs to be bigger than or equal to reg_t_rcd value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--11. " REG_T_RC ,Minimum number of DDR clock cycles from Activate to Activate, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 3.--5. " REG_T_RRD ,Minimum number of DDR clock cycles from Activate to Activate for a different bank, minus one. For an 8-bank, this field must be equal to ((tFAW/(4*tCK))-1)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " REG_T_WTR ,Minimum number of DDR clock cycles from last Write to Read, minus one." "0,1,2,3,4,5,6,7" group.long 0x1C++0x3 line.long 0x00 "EMIF_SDRAM_TIM_1_SHDW,SDRAM Timing 1 Shadow Register" bitfld.long 0x00 25.--28. " REG_T_RP_SHDW ,Shadow field for REG_T_RP. This field is loaded intoEMIF_SDRAM_TIM_1[28:25] REG_T_RP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21.--24. " REG_T_RCD_SHDW ,Shadow field for REG_T_RCD. This field is loaded intoEMIF_SDRAM_TIM_1[24:21] REG_T_RCD field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " REG_T_WR_SHDW ,Shadow field for REG_T_WR. This field is loaded intoEMIF_SDRAM_TIM_1[20:17] REG_T_WR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--16. " REG_T_RAS_SHDW ,Shadow field for REG_T_RAS. This field is loaded intoEMIF_SDRAM_TIM_1[16:12] REG_T_RAS field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--11. " REG_T_RC_SHDW ,Shadow field for REG_T_RC. This field is loaded intoEMIF_SDRAM_TIM_1[11:6] REG_T_RC field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 3.--5. " REG_T_RRD_SHDW ,Shadow field for REG_T_RRD. This field is loaded intoEMIF_SDRAM_TIM_1[5:3] REG_T_RRD field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " REG_T_WTR_SHDW ,Shadow field for REG_T_WTR. This field is loaded intoEMIF_SDRAM_TIM_1[2:0] REG_T_WTR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x00 "EMIF_SDRAM_TIM_2,SDRAM Timing 2 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x00 28.--30. " REG_T_XP ,Minimum number of DDR clock cycles from Powerdown exit to any command other than a Read command, minus one." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--24. 1. " REG_T_XSNR ,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command, minus one. REG_T_XSNR and REG_T_XSRD must be programmed with the same value." hexmask.long.word 0x00 6.--15. 1. " REG_T_XSRD ,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command, minus one. REG_T_XSNR and REG_T_XSRD must be programmed with the same value." textline " " bitfld.long 0x00 3.--5. " REG_T_RTP ,Minimum number of DDR clock cycles for the last read command to a Precharge command, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " REG_T_CKE ,Minimum number of DDR clock cycles between pad_cke_o changes, minus one." "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "EMIF_SDRAM_TIM_2_SHDW,SDRAM Timing 2 Shadow Register" bitfld.long 0x00 28.--30. " REG_T_XP_SHDW ,Shadow field for REG_T_XP. This field is loaded intoEMIF_SDRAM_TIM_2[30:28] REG_T_XP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--24. 1. " REG_T_XSNR_SHDW ,Shadow field for REG_T_XSNR. This field is loaded intoEMIF_SDRAM_TIM_2[24:16] REG_T_XSNR field when SIdleAck is asserted." hexmask.long.word 0x00 6.--15. 1. " REG_T_XSRD_SHDW ,Shadow field for REG_T_XSRD. This field is loaded intoEMIF_SDRAM_TIM_2[15:6] REG_T_XSRD field when SIdleAck is asserted." textline " " bitfld.long 0x00 3.--5. " REG_T_RTP_SHDW ,Shadow field for REG_T_RTP. This field is loaded intoEMIF_SDRAM_TIM_2[5:3] REG_T_RTP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " REG_T_CKE_SHDW ,Shadow field for REG_T_CKE. This field is loaded intoEMIF_SDRAM_TIM_2[2:0] REG_T_CKE field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "EMIF_SDRAM_TIM_3,SDRAM Timing 3 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x00 21.--23. " REG_T_CKESR ,Minimum number of DDR clock cycles for which LPDDR2 must remain in Self Refresh, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--20. " REG_ZQ_ZQCS ,Number of DDR clock clock cycles for a ZQCS command, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--14. " REG_T_TDQSCKMAX ,Number of DDR clock that satisfies tDQSCKmax for LPDDR2, minus one." "0,1,2,3" textline " " hexmask.long.word 0x00 4.--12. 1. " REG_T_RFC ,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate, minus one." bitfld.long 0x00 0.--3. " REG_T_RAS_MAX ,Maximum number of reg_refresh_rate intervals from Activate to Precharge command. This field must be equal to ((tRASmax / tREFI)-1) rounded down to the next lower integer. Value for REG_T_RAS_MAX can be cal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x3 line.long 0x00 "EMIF_SDRAM_TIM_3_SHDW,SDRAM Timing 3 Shadow Register" bitfld.long 0x00 21.--23. " REG_T_CKESR_SHDW ,Shadow field for reg_t_ckesr. This field is loaded into reg_t_ckesr field inEMIF_SDRAM_TIM_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--20. " REG_ZQ_ZQCS_SHDW ,Shadow field for reg_zq_zqcs. This field is loaded into reg_zq_zqcs field inEMIF_SDRAM_TIM_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--14. " REG_T_TDQSCKMAX_SHDW ,Shadow field for REG_T_TDQSCKMAX. This field is loaded intoEMIF_SDRAM_TIM_3[14:13] REG_T_TDQSCKMAX field when SIdleAck is asserted." "0,1,2,3" textline " " hexmask.long.word 0x00 4.--12. 1. " REG_T_RFC_SHDW ,Shadow field for REG_T_RFC. This field is loaded intoEMIF_SDRAM_TIM_3[12:4] REG_T_RFC when SIdleAck is asserted." bitfld.long 0x00 0.--3. " REG_T_RAS_MAX_SHDW ,Shadow field for REG_T_RAS_MAX. This field is loaded intoEMIF_SDRAM_TIM_3[3:0] REG_T_RAS_MAX field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x3 line.long 0x00 "EMIF_LPDDR2_NVM_TIM,LPDDR2-NVM Timing Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the LPDDR2-NVM." bitfld.long 0x00 28.--30. " REG_NVM_T_XP ,Minimum number of DDR clock cycles from Powerdown exit to any command, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " REG_NVM_T_WTR ,Minimum number of DDR clock cycles from last Write to Read, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " REG_NVM_T_RP ,Minimum number of DDR clock cycles from Preactive to Activate, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " REG_NVM_T_WRA ,Minimum number of DDR clock cycles from last Write transfer to Activate, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " REG_NVM_T_RRD ,Minimum number of DDR clock cycles from Activate to Activate for a different bank, minus one." hexmask.long.byte 0x00 0.--7. 1. " REG_NVM_T_RCDMIN ,Minimum number of DDR clock cycles from Activate to Read or Write, minus one." group.long 0x34++0x3 line.long 0x00 "EMIF_LPDDR2_NVM_TIM_SHDW,LPDDR2-NVM Timing Shadow Register" bitfld.long 0x00 28.--30. " REG_NVM_T_XP_SHDW ,Shadow field for REG_NVM_T_XP. This field is loaded intoEMIF_LPDDR2_NVM_TIM[30:28] REG_NVM_T_XP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " REG_NVM_T_WTR_SHDW ,Shadow field for REG_NVM_T_WTR. This field is loaded intoEMIF_LPDDR2_NVM_TIM[26:24] REG_NVM_T_WTR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " REG_NVM_T_RP_SHDW ,Shadow field for REG_NVM_T_RP. This field is loaded intoEMIF_LPDDR2_NVM_TIM[23:20] REG_NVM_T_RP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " REG_NVM_T_WRA_SHDW ,Shadow field for REG_NVM_T_WRA. This field is loaded intoEMIF_LPDDR2_NVM_TIM[19:16] REG_NVM_T_WRA field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " REG_NVM_T_RRD_SHDW ,Shadow field for REG_NVM_T_RRD. This field is loaded intoEMIF_LPDDR2_NVM_TIM[15:8] REG_NVM_T_RRD field when SIdleAck is asserted." hexmask.long.byte 0x00 0.--7. 1. " REG_NVM_T_RCDMIN_SHDW ,Shadow field for . This field is loaded intoEMIF_LPDDR2_NVM_TIM[7:0] REG_NVM_T_RCDMIN field when SIdleAck is asserted." group.long 0x38++0x3 line.long 0x00 "EMIF_PWR_MGMT_CTRL,Power Management Control Register" bitfld.long 0x00 12.--15. " REG_PD_TIM ,Power Mangement timer for Power-Down. The EMIF will put the external SDRAM in Power-Down mode after the EMIF is idle for these number of DDR clock cycles and if reg_lp_mode field is set to 4. Set to 0 to immed.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " REG_DPD_EN ,Deep Power Down enable. Set to 0 for normal operation. Set to 1 to enter deep power-down mode. This mode will override the reg_lp_mode field setting." "0,1" bitfld.long 0x00 8.--10. " REG_LP_MODE ,Automatic Power Management enableSet to 1: Reserved. - . Set to 2: Self-refresh mode. - . Set to 4: Power-down mode. - . - All other values will disable automatic power management. . - ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " REG_SR_TIM ,Power Mangement timer for Self Refresh. The EMIF will put the external SDRAM in Self Refresh mode after the EMIF is idle for these number of DDR clock cycles and if reg_lp_mode field is set to 2. Set to 0 to i.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REG_CS_TIM ,Power Mangement timer for Clock Stop. The EMIF will put the external SDRAM in Clock Stop mode after the EMIF is idle for these number of DDR clock cycles and if reg_lp_mode field is set to 1. Set to 0 to.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x3 line.long 0x00 "EMIF_PWR_MGMT_CTRL_SHDW,Power Management Control Shadow Register" bitfld.long 0x00 12.--15. " REG_PD_TIM_SHDW ,Shadow field for reg_pd_tim. This field is loaded into reg_pd_tim field in Power Management Control register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " REG_SR_TIM_SHDW ,Shadow field for reg_sr_tim. This field is loaded into reg_sr_tim field in Power Management Control register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REG_CS_TIM_SHDW ,Shadow field for reg_cs_tim. This field is loaded into reg_cs_tim field in Power Management Control register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x3 line.long 0x00 "EMIF_LPDDR2_MODE_REG_DATA,LPDDR2 Mode Reg Data Register A write to this register will cause a Mode Register write command to be sent to the LPDDR2 device with write data as specified in the REG_VALUE_0 field. The address and chip-select are taken from .." hexmask.long.byte 0x00 0.--7. 1. " REG_VALUE_0 ,Mode register value." group.long 0x50++0x3 line.long 0x00 "EMIF_LPDDR2_MODE_REG_CFG,LPDDR2 Mode Reg Config Register" bitfld.long 0x00 31. " REG_CS ,Chip-select to issue mode register command. Set to 0 for CS0 and set to 1 for CS1." "0,1" bitfld.long 0x00 30. " REG_REFRESH_EN ,Refresh Enable after MRW write. If a Mode Data register write occurs with this bit set to 1, the refresh operations will commence." "0,1" hexmask.long.byte 0x00 0.--7. 1. " REG_ADDRESS ,Mode register address." group.long 0x54++0x3 line.long 0x00 "EMIF_L3_CONFIG,Config Register" bitfld.long 0x00 24.--27. " REG_SYS_THRESH_MAX ,System L3 Threshold Maximum. The number of commands the system interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for th.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " REG_LL_THRESH_MAX ,Low-latency L3 Threshold Maximum. The number of commands the low latency interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " REG_PR_OLD_COUNT ,Priority Raise Old Counter. Number of memory transfers after which the EMIF momentarily raises the priority of old commands in the L3 Command FIFO." rgroup.long 0x58++0x3 line.long 0x00 "EMIF_L3_CFG_VAL_1,Config Value 1 Register" bitfld.long 0x00 30.--31. " REG_SYS_BUS_WIDTH ,System L3 data bus width 0 = 32-bit wide, 1 = 64-bit wide, 2 = 128-bit wide, 3 = Reserved" "0,1,2,3" bitfld.long 0x00 28.--29. " REG_LL_BUS_WIDTH ,Low-latency L3 data bus width 0 = 32-bit wide, 1 = 64-bit wide, 2 = 128-bit wide, 3 = Reserved" "0,1,2,3" hexmask.long.byte 0x00 8.--15. 1. " REG_WR_FIFO_DEPTH ,Write Data FIFO depth" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_CMD_FIFO_DEPTH ,Command FIFO depth" rgroup.long 0x5C++0x3 line.long 0x00 "EMIF_L3_CFG_VAL_2,Config Value 2 Register" hexmask.long.byte 0x00 16.--23. 1. " REG_RREG_FIFO_DEPTH ,Register Read Data FIFO depth" hexmask.long.byte 0x00 8.--15. 1. " REG_RSD_FIFO_DEPTH ,SDRAM Read Data FIFO depth" hexmask.long.byte 0x00 0.--7. 1. " REG_RCMD_FIFO_DEPTH ,Read Command FIFO depth" rgroup.long 0x80++0x3 line.long 0x00 "EMIF_PERF_CNT_1,Performance Counter 1 Register" hexmask.long 0x00 0.--31. 1. " REG_COUNTER1 ,32-bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register." rgroup.long 0x84++0x3 line.long 0x00 "EMIF_PERF_CNT_2,Performance Counter 2 Register" hexmask.long 0x00 0.--31. 1. " REG_COUNTER2 ,32-bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register." group.long 0x88++0x3 line.long 0x00 "EMIF_PERF_CNT_CFG,Performance Counter Config Register" bitfld.long 0x00 31. " REG_CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register." "0,1" bitfld.long 0x00 30. " REG_CNTR2_REGION_EN ,Chip-select filter enable for Performance Counter 2 register." "0,1" bitfld.long 0x00 16.--19. " REG_CNTR2_CFG ,Filter configuration for Performance Counter 2. Refer to for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 15. " REG_CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register." "0,1" bitfld.long 0x00 14. " REG_CNTR1_REGION_EN ,Chip-select filter enable for Performance Counter 1 register." "0,1" bitfld.long 0x00 0.--3. " REG_CNTR1_CFG ,Filter configuration for Performance Counter 1. Refer to for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8C++0x3 line.long 0x00 "EMIF_PERF_CNT_SEL,Performance Counter Master Region Select Register" hexmask.long.byte 0x00 24.--31. 1. " REG_MCONNID2 ,MConnID for Performance Counter 2 register. The values programmed are those in in , , left-shifted by 2 bits." bitfld.long 0x00 16.--17. " REG_REGION_SEL2 ,MAddrSpace for Performance Counter 2 register." "0,1,2,3" hexmask.long.byte 0x00 8.--15. 1. " REG_MCONNID1 ,MConnID for Performance Counter 1 register. The values programmed are those in in , , left-shifted by 2 bits." textline " " bitfld.long 0x00 0.--1. " REG_REGION_SEL1 ,MAddrSpace for Performance Counter 1 register." "0,1,2,3" rgroup.long 0x90++0x3 line.long 0x00 "EMIF_PERF_CNT_TIM,Performance Counter Time Register. This is a free running counter." hexmask.long 0x00 0.--31. 1. " REG_TOTAL_TIME ,32-bit counter that continuously counts number for EMIF clock cycles elapsed after EMIF is brought out of reset." group.long 0x98++0x3 line.long 0x00 "EMIF_READ_IDLE_CTRL,Read Idle Control Register" bitfld.long 0x00 16.--19. " REG_READ_IDLE_LEN ,The Read Idle Length field determines the minimum size (reg_read_idle_len-1 EMIF_FCLK clock cycles) of Read Idle window for the read idle detection as well as the force read idle time." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--8. 1. " REG_READ_IDLE_INTERVAL ,The Read Idle Interval field determines the maximum interval ((REG_READ_IDLE_INTERVAL - 1) * 64 EMIF_FCLK clock cycles) between read idle detections or force. A value of zero disables the read idle funct.." group.long 0x9C++0x3 line.long 0x00 "EMIF_READ_IDLE_CTRL_SHDW,Read Idle Control Shadow Register" bitfld.long 0x00 16.--19. " REG_READ_IDLE_LEN_SHDW ,Shadow field for REG_READ_IDLE_LEN. This field is loaded intoEMIF_READ_IDLE_CTRL[19:16] REG_READ_IDLE_LEN field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--8. 1. " REG_READ_IDLE_INTERVAL_SHDW ,Shadow field for REG_READ_IDLE_INTERVAL. This field is loaded intoEMIF_READ_IDLE_CTRL[8:0] REG_READ_IDLE_INTERVAL field when SIdleAck is asserted." group.long 0xA4++0x3 line.long 0x00 "EMIF_IRQSTATUS_RAW_SYS,System L3 Interrupt Raw Status Register" bitfld.long 0x00 2. " REG_DNV_SYS ,Raw status of system L3 interrupt for LPDDR2 NVM data not valid. - Write 1 to set the (raw) status, typically for debug. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 1. " REG_TA_SYS ,Raw status of system L3 interrupt for SDRAM temperature alert. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x00 0. " REG_ERR_SYS ,Raw status of system L3 interrupt for command or address error. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" group.long 0xA8++0x3 line.long 0x00 "EMIF_IRQSTATUS_RAW_LL,Low-Latency L3 Interrupt Raw Status Register" bitfld.long 0x00 2. " REG_DNV_LL ,Raw status of low-latency L3 interrupt for LPDDR2 NVM data not valid. - Write 1 to set the (raw) status, typically for debug. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 1. " REG_TA_LL ,Raw status of low-latency L3 interrupt or SDRAM temperature alert. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x00 0. " REG_ERR_LL ,Raw status of low-latency L3 interrupt for command or address error. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" group.long 0xAC++0x3 line.long 0x00 "EMIF_IRQSTATUS_SYS,System L3 Interrupt Status Register" bitfld.long 0x00 2. " REG_DNV_SYS ,Enabled status of system L3 interrupt for LPDDR2 NVM data not valid. - Write 1 to clear the status after interrupt is serviced (raw status is cleared; that is, even if not enabled). . - . - Writing 0 has no ef.." "0,1" bitfld.long 0x00 1. " REG_TA_SYS ,Enabled status of system L3 interrupt for SDRAM temperature alert. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0 has .." "0,1" bitfld.long 0x00 0. " REG_ERR_SYS ,Enabled status of system L3 interrupt interrupt for command or address error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0 ha.." "0,1" group.long 0xB0++0x3 line.long 0x00 "EMIF_IRQSTATUS_LL,Low-Latency L3 Interrupt Status Register" eventfld.long 0x00 2. " REG_DNV_LL ,Enabled status of low-latency L3 interrupt for LPDDR2 NVM data not valid. - Write 1 to clear the status after interrupt is serviced (raw status is cleared; that is, even if not enabled). . - . - Writing 0 has .." "0,1" eventfld.long 0x00 1. " REG_TA_LL ,Enabled status of low-latency L3 interrupt for SDRAM temperature alert. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0.." "0,1" eventfld.long 0x00 0. " REG_ERR_LL ,Enabled status of low-latency L3 interrupt for command or address error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0 has no .." "0,1" group.long 0xB4++0x3 line.long 0x00 "EMIF_IRQENABLE_SET_SYS,System L3 Interrupt Enable Set Register" bitfld.long 0x00 2. " REG_EN_DNV_SYS ,Enable set for system L3 interrupt for LPDDR2 NVM data not valid. - Writing 1 enables the interrupt and sets this bit and the corresponding Interrupt-enable clear register. . - . - Writing 0 has no effect. . -.." "0,1" bitfld.long 0x00 1. " REG_EN_TA_SYS ,Enable set for system L3 interrupt for SDRAM temperature alert. . Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no.." "0,1" bitfld.long 0x00 0. " REG_EN_ERR_SYS ,Enable set for system L3 interrupt for command or address error. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" group.long 0xB8++0x3 line.long 0x00 "EMIF_IRQENABLE_SET_LL,Low-Latency L3 Interrupt Enable Set Register" bitfld.long 0x00 2. " REG_EN_DNV_LL ,Enable set for low-latency L3 interrupt for LPDDR2 NVM data not valid. - Writing 1 enables the interrupt and sets this bit and the corresponding Interrupt-enable clear register. . - . - Writing a 0 has no effe.." "0,1" bitfld.long 0x00 1. " REG_EN_TA_LL ,Enable set for low-latency L3 interrupt for SDRAM temperature alert. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has.." "0,1" bitfld.long 0x00 0. " REG_EN_ERR_LL ,Enable set for low-latency L3 interrupt for command or address error. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effe.." "0,1" group.long 0xBC++0x3 line.long 0x00 "EMIF_IRQENABLE_CLR_SYS,System L3 Interrupt Enable Clear Register" eventfld.long 0x00 2. " REG_EN_DNV_SYS ,Enable clear for system OCP interrupt for LPDDR2 NVM data not valid. - Writing 1 disables the interrupt and clears this bit and the corresponding interrupt-enable set register. . - . - Writing 0 has no effect..." "0,1" eventfld.long 0x00 1. " REG_EN_TA_SYS ,Enable clear for system L3 interrupt for SDRAM temperature alert. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has n.." "0,1" eventfld.long 0x00 0. " REG_EN_ERR_SYS ,Enable clear for system L3 interrupt for command or address error. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.." "0,1" group.long 0xC0++0x3 line.long 0x00 "EMIF_IRQENABLE_CLR_LL,Low-Latency L3 Interrupt Enable Clear Register" eventfld.long 0x00 2. " REG_EN_DNV_LL ,Enable clear for low-latency OCP interrupt for LPDDR2 NVM data not valid. - Writing 1 disables the interrupt and clears this bit and the corresponding interrupt enable set register. . - . - Writing 0 has no ef.." "0,1" eventfld.long 0x00 1. " REG_EN_TA_LL ,Enable clear for low-latency L3 interrupt for SDRAM temperature alert. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 .." "0,1" eventfld.long 0x00 0. " REG_EN_ERR_LL ,Enable clear for low-latency L3 interrupt for command or address error. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no e.." "0,1" group.long 0xC8++0x3 line.long 0x00 "EMIF_ZQ_CONFIG,SDRAM Output Impedance Calibration Config Register" bitfld.long 0x00 31. " REG_ZQ_CS1EN ,Writing a 1 enables ZQ calibration for CS1." "0,1" bitfld.long 0x00 30. " REG_ZQ_CS0EN ,Writing a 1 enables ZQ calibration for CS0." "0,1" bitfld.long 0x00 29. " REG_ZQ_DUALCALEN ,ZQ Dual Calibration enable. Allows both ranks to be ZQ calibrated simultaneously. Setting this bit requires both chip-selects to have a separate calibration resistor per device." "0,1" textline " " bitfld.long 0x00 28. " REG_ZQ_SFEXITEN ,ZQCL on Self-Refresh, Active Power-Down, and Precharge Power-Down exit enable. Writing a 1 enables the issuing of ZQCL on Self-Refresh, Active Power-Down, and Precharge Power-Down exit." "0,1" bitfld.long 0x00 18.--19. " REG_ZQ_ZQINIT_MULT ,Indicates the number of ZQCL durations that make up a ZQINIT duration, minus one." "0,1,2,3" bitfld.long 0x00 16.--17. " REG_ZQ_ZQCL_MULT ,Indicates the number of ZQCS intervals that make up a ZQCL duration, minus one. ZQCS interval is defined by reg_zq_zqcs inEMIF_SDRAM_TIM_3." "0,1,2,3" textline " " hexmask.long.word 0x00 0.--15. 1. " REG_ZQ_REFINTERVAL ,Number of refresh periods between ZQCS commands. This field supports between one refresh period to 256 ms between ZQCS calibration commands. Refresh period is defined by reg_refresh_rate inEMIF_SDRAM_REF_CTRL .." group.long 0xCC++0x3 line.long 0x00 "EMIF_TEMP_ALERT_CONFIG,Temperature Alert Config Register" bitfld.long 0x00 31. " REG_TA_CS1EN ,Writing a 1 enables temperature alert polling for CS1." "0,1" bitfld.long 0x00 30. " REG_TA_CS0EN ,Writing a 1 enables temperature alert polling for CS0." "0,1" bitfld.long 0x00 28. " REG_TA_SFEXITEN ,Temperature Alert Poll on Self-Refresh, Active Power-Down, and Precharge Power-Down exit enable. Writing a 1 enables the issuing of a temperature alert poll on Self-Refresh exit." "0,1" textline " " bitfld.long 0x00 26.--27. " REG_TA_DEVWDT ,This field indicates how wide a physical device is. It is used in conjunction with the reg_ta_devcnt register to determine which byte lanes contain the temperature alert info. A value of 0 = eight bit wide, 1 .." "0,1,2,3" bitfld.long 0x00 24.--25. " REG_TA_DEVCNT ,This field indicates which external byte lanes contain a device for temperature monitoring. A value of 0 = one device, 1 = two devices, 2 = four devices. All other reserved." "0,1,2,3" hexmask.long.tbyte 0x00 0.--21. 1. " REG_TA_REFINTERVAL ,Number of refresh periods between temperature alert polls. This field supports between one refresh period to 10 seconds between temperature alert polls. Refresh period is defined by reg_refresh_rate in SDRAM Ref.." rgroup.long 0xD0++0x3 line.long 0x00 "EMIF_L3_ERR_LOG,Error Log Register" bitfld.long 0x00 14.--15. " REG_MADDRSPACE ,Address space of the first errored transaction. 0x0: SDRAM 0x1: LPDDR2-NVM 0x2: reserved 0x3: internal registers" "0,1,2,3" bitfld.long 0x00 11.--13. " REG_MBURSTSEQ ,Addressing mode of the first errored transaction. (see, for more information)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " REG_MCMD ,Command type of the first errored transaction. (see, for more information)" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_MCONNID ,Connection ID of the first errored transaction." group.long 0xE4++0x3 line.long 0x00 "EMIF_DDR_PHY_CTRL_1,DDR PHY Control 1 Register. This register is used to control the DDR PHY. The bit field definitions are DDR PHY specific." bitfld.long 0x00 30.--31. " DLL_MASTER_SENSITIVITY ,This field defines the level of sensitivity of the DLL master: the lower the value, the more sensitive the DLL is to PVT variation. The recommended setting is 0x2." "0,1,2,3" bitfld.long 0x00 26.--29. " REG_PHY_FREEZE_DELAY_CODE_POSTAMBLE ,Postamble time respected by the DATA PHY freezing the DLL slave code after reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--25. " REG_PHY_FREEZE_DELAY_CODE_PREAMBLE ,Preamble time respected by the DATA PHY before freezing the DLL slave code during reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 12.--21. 1. " REG_DLL_MASTER_SW_CODE_CTRL ,DLL delay code when in software override mode" hexmask.long.byte 0x00 4.--11. 1. " REG_DLL_SLAVE_DLY_CTRL ,DLL slave delay ratio control" bitfld.long 0x00 0.--3. " REG_READ_LATENCY ,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles. This field is used by the EMIF as well as the PHY. The EMIF will expect the first read data to arrive (reg_read_late.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE8++0x3 line.long 0x00 "EMIF_DDR_PHY_CTRL_1_SHDW,DDR PHY Control 1 Shadow Register. Shadow field for." bitfld.long 0x00 26.--29. " REG_PHY_FREEZE_DELAY_CODE_POSTAMBLE_SHDW ,Shadow field for REG_PHY_FREEZE_DELAY_CODE_POSTAMBLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--25. " REG_PHY_FREEZE_DELAY_CODE_PREAMBLE_SHDW ,Shadow field for REG_PHY_FREEZE_DELAY_CODE_PREAMBLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 12.--21. 1. " REG_DLL_MASTER_SW_CODE_CTRL_SHDW ,Shadow field for REG_DLL_MASTER_SW_CODE_CTRL" textline " " hexmask.long.byte 0x00 4.--11. 1. " REG_DLL_SLAVE_DLY_CTRL_SHDW ,Shadow field for REG_DLL_SLAVE_DLY_CTRL" bitfld.long 0x00 0.--3. " REG_READ_LATENCY_SHDW ,Shadow field for REG_READ_LATENCY. This field is loaded intoEMIF_DDR_PHY_CTRL_1[3:0] REG_READ_LATENCY field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEC++0x3 line.long 0x00 "EMIF_DDR_PHY_CTRL_2,DDR PHY Control 2 Register" hexmask.long 0x00 0.--31. 1. " REG_DDR_PHY_CTRL_2 ,This register is used to control the DDR PHY. The bit field definitions are DDR PHY specific." tree.end tree "EMIF2" base ad:0x4D000000 width 27. group.long 0x0++0x3 line.long 0x00 "EMIF_MOD_ID_REV,Revision number register" rgroup.long 0x4++0x3 line.long 0x00 "EMIF_STATUS,SDRAM Status Register (STATUS)" bitfld.long 0x00 31. " REG_BE ,Big endian mode select for 8 and 16-bit devices, set to 1 for big endian or 0 for little endian operation." "0,1" bitfld.long 0x00 30. " REG_DUAL_CLK_MODE ,Dual Clock mode. Defines whether the L3_clk and EMIF_FCLK are asynchronous. L3_clk and EMIF_FCLK are asynchronous, if set to 1." "0,1" bitfld.long 0x00 29. " REG_FAST_INIT ,Fast Init. Defines whether the EMIF fast initialization mode has been enabled. Fast initialization is enabled if set to 1." "0,1" textline " " bitfld.long 0x00 2. " REG_PHY_DLL_READY ,DDR PHY Ready. Reflects the value on the phy_ready port (active high) that defines whether the DDR PHY is ready for normal operation. The DDR PHY is ready for normal operation, if set to 1." "0,1" group.long 0x8++0x3 line.long 0x00 "EMIF_SDRAM_CONFIG,SDRAM Config Register. A write to this register will cause the EMIF to start the SDRAM initialization sequence if it was not performed previously because [31] REG_INITREF_DIS was a zero." bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection. Set to 4 for LPDDR2-S4, Set to 5 for LPDDR2-S2 All other value are reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position. Set to 0 to assign internal bank address bits from L3 address as shown in and . Set to 1, 2, or 3 to assign internal bank address bits from L3 address as shown in , , and ." "0,1,2,3" bitfld.long 0x00 23. " REG_DDR2_DDQS ,DDR2 differential DQS enable. - Set to 0 for single-ended DQS. . - . - Set to 1 for differential DQS. . - . - This bit is only for DDR2 mode; because the device supports LPDDR2, this bit is don?t care. . - ." "0,1" textline " " bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select. Set to 1 to disable DLL inside SDRAM." "0,1" bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width. Set to 0 for 32-bit and set to 1 for 16-bit. All other values are reserved." "0,1,2,3" bitfld.long 0x00 10.--13. " REG_CL ,CAS Latency (referred to as read latency (RL) in some SDRAM specs). The value of this field defines the CAS latency to be used when accessing connected SDRAM devices. Value of 3, 4, 5, 6, 7, and 8 (CAS latency o.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size. Defines the number of row address bits of connected SDRAM devices. Set to 0 for 9 row bits, Set to 1 for 10 row bits, Set to 2 for 11 row bits, Set to 3 for 12 row bits, Set to 4 for 13 row bits, Set.." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup. Defines number of banks inside connected SDRAM devices. Set to 0 for 1 bank, Set to 1 for 2 banks, Set to 2 for 4 banks, Set to 3 for 8 banks. All other values are reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " REG_EBANK ,External chip-select setup. Defines whether SDRAM accesses will use 1 or 2 chip-select lines. Set to 0 to use pad_cs_o_n[0] only. Set to 1 to use pad_cs_o_n[1:0]. This bit will automaticlly be set to 0 if EMIF_S.." "0,1" textline " " bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size. Defines the internal page size of connected SDRAM devices. Set to 0 for 256-word page (8 column bits), Set to 1 for 512-word page (9 column bits), Set to 2 for 1024-word page (10 column bits), Set t.." "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x00 "EMIF_SDRAM_CONFIG_2," bitfld.long 0x00 30. " REG_CS1NVMEN ,CS1 LPDDR2-NVM enable. Set to 1 if LPDDR2-NVM is connected to CS1. This bit will automatically be set to 0 if reg_sdram_type field in the SDRAM Config register is not set to LPDDR2." "0,1" bitfld.long 0x00 27. " REG_EBANK_POS ,External bank position. Set to 0 to assign external bank address bits from lower OCP address as shown in tables. Set to 1 to assign external bank address bits from higher OCP address bits as shown in ta.." "0,1" bitfld.long 0x00 4.--5. " REG_RDBNUM ,Row Buffer setup. Defines number of row buffers inside connected LPDDR2-NVM devices. Set to 0 for 1 row buffer, set to 1 for 2 row buffers, set to 2 for 4 row buffers, and set to 3 for 8 row buffers. All other v.." "0,1,2,3" textline " " bitfld.long 0x00 0.--2. " REG_RDBSIZE ,Row Data Buffer Size. Defines the row data buffer size of connected LPDDR2-NVM devices. Set to 0 for 32 bytes, set to 1 for 64 bytes, set to 2 for 128 bytes, set to 3 for 256 bytes, set to 4 for 512 bytes, set.." "0,1,2,3,4,5,6,7" group.long 0x10++0x3 line.long 0x00 "EMIF_SDRAM_REF_CTRL,SDRAM Refresh Control Register" bitfld.long 0x00 31. " REG_INITREF_DIS ,Initialization and Refresh disable. When set to 1, EMIF will disable SDRAM initialization and refreshes, but will carry out SDRAM write/read transactions." "0,1" hexmask.long.word 0x00 0.--15. 1. " REG_REFRESH_RATE ,Refresh Rate. Value in this field is used to define the rate at which connected SDRAM devices will be refreshed. SDRAM refresh rate = DDR_PHY_CLK / REG_REFRESH_RATE. If REG_REFRESH_RATE &lt; (8 ? RE.." group.long 0x14++0x3 line.long 0x00 "EMIF_SDRAM_REF_CTRL_SHDW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x00 0.--15. 1. " REG_REFRESH_RATE_SHDW ,Shadow field for REG_REFRESH_RATE. This field is loaded intoEMIF_SDRAM_REF_CTRL[15:0] REG_REFRESH_RATE field when SIdleAck is asserted. This register is not auto corrected when the value is invalid." group.long 0x18++0x3 line.long 0x00 "EMIF_SDRAM_TIM_1,SDRAM Timing 1 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x00 25.--28. " REG_T_RP ,Minimum number of DDR clock cycles from Precharge to Activate or Refresh, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21.--24. " REG_T_RCD ,Minimum number of DDR clock cycles from Activate to Read or Write, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " REG_T_WR ,Minimum number of DDR clock cycles from last Write transfer to Precharge, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--16. " REG_T_RAS ,Minimum number of DDR clock cycles from Activate to Precharge, minus one. reg_t_ras value needs to be bigger than or equal to reg_t_rcd value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--11. " REG_T_RC ,Minimum number of DDR clock cycles from Activate to Activate, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 3.--5. " REG_T_RRD ,Minimum number of DDR clock cycles from Activate to Activate for a different bank, minus one. For an 8-bank, this field must be equal to ((tFAW/(4*tCK))-1)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " REG_T_WTR ,Minimum number of DDR clock cycles from last Write to Read, minus one." "0,1,2,3,4,5,6,7" group.long 0x1C++0x3 line.long 0x00 "EMIF_SDRAM_TIM_1_SHDW,SDRAM Timing 1 Shadow Register" bitfld.long 0x00 25.--28. " REG_T_RP_SHDW ,Shadow field for REG_T_RP. This field is loaded intoEMIF_SDRAM_TIM_1[28:25] REG_T_RP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21.--24. " REG_T_RCD_SHDW ,Shadow field for REG_T_RCD. This field is loaded intoEMIF_SDRAM_TIM_1[24:21] REG_T_RCD field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " REG_T_WR_SHDW ,Shadow field for REG_T_WR. This field is loaded intoEMIF_SDRAM_TIM_1[20:17] REG_T_WR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--16. " REG_T_RAS_SHDW ,Shadow field for REG_T_RAS. This field is loaded intoEMIF_SDRAM_TIM_1[16:12] REG_T_RAS field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--11. " REG_T_RC_SHDW ,Shadow field for REG_T_RC. This field is loaded intoEMIF_SDRAM_TIM_1[11:6] REG_T_RC field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 3.--5. " REG_T_RRD_SHDW ,Shadow field for REG_T_RRD. This field is loaded intoEMIF_SDRAM_TIM_1[5:3] REG_T_RRD field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " REG_T_WTR_SHDW ,Shadow field for REG_T_WTR. This field is loaded intoEMIF_SDRAM_TIM_1[2:0] REG_T_WTR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x00 "EMIF_SDRAM_TIM_2,SDRAM Timing 2 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x00 28.--30. " REG_T_XP ,Minimum number of DDR clock cycles from Powerdown exit to any command other than a Read command, minus one." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--24. 1. " REG_T_XSNR ,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command, minus one. REG_T_XSNR and REG_T_XSRD must be programmed with the same value." hexmask.long.word 0x00 6.--15. 1. " REG_T_XSRD ,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command, minus one. REG_T_XSNR and REG_T_XSRD must be programmed with the same value." textline " " bitfld.long 0x00 3.--5. " REG_T_RTP ,Minimum number of DDR clock cycles for the last read command to a Precharge command, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " REG_T_CKE ,Minimum number of DDR clock cycles between pad_cke_o changes, minus one." "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "EMIF_SDRAM_TIM_2_SHDW,SDRAM Timing 2 Shadow Register" bitfld.long 0x00 28.--30. " REG_T_XP_SHDW ,Shadow field for REG_T_XP. This field is loaded intoEMIF_SDRAM_TIM_2[30:28] REG_T_XP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--24. 1. " REG_T_XSNR_SHDW ,Shadow field for REG_T_XSNR. This field is loaded intoEMIF_SDRAM_TIM_2[24:16] REG_T_XSNR field when SIdleAck is asserted." hexmask.long.word 0x00 6.--15. 1. " REG_T_XSRD_SHDW ,Shadow field for REG_T_XSRD. This field is loaded intoEMIF_SDRAM_TIM_2[15:6] REG_T_XSRD field when SIdleAck is asserted." textline " " bitfld.long 0x00 3.--5. " REG_T_RTP_SHDW ,Shadow field for REG_T_RTP. This field is loaded intoEMIF_SDRAM_TIM_2[5:3] REG_T_RTP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " REG_T_CKE_SHDW ,Shadow field for REG_T_CKE. This field is loaded intoEMIF_SDRAM_TIM_2[2:0] REG_T_CKE field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "EMIF_SDRAM_TIM_3,SDRAM Timing 3 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x00 21.--23. " REG_T_CKESR ,Minimum number of DDR clock cycles for which LPDDR2 must remain in Self Refresh, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--20. " REG_ZQ_ZQCS ,Number of DDR clock clock cycles for a ZQCS command, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--14. " REG_T_TDQSCKMAX ,Number of DDR clock that satisfies tDQSCKmax for LPDDR2, minus one." "0,1,2,3" textline " " hexmask.long.word 0x00 4.--12. 1. " REG_T_RFC ,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate, minus one." bitfld.long 0x00 0.--3. " REG_T_RAS_MAX ,Maximum number of reg_refresh_rate intervals from Activate to Precharge command. This field must be equal to ((tRASmax / tREFI)-1) rounded down to the next lower integer. Value for REG_T_RAS_MAX can be cal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x3 line.long 0x00 "EMIF_SDRAM_TIM_3_SHDW,SDRAM Timing 3 Shadow Register" bitfld.long 0x00 21.--23. " REG_T_CKESR_SHDW ,Shadow field for reg_t_ckesr. This field is loaded into reg_t_ckesr field inEMIF_SDRAM_TIM_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--20. " REG_ZQ_ZQCS_SHDW ,Shadow field for reg_zq_zqcs. This field is loaded into reg_zq_zqcs field inEMIF_SDRAM_TIM_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--14. " REG_T_TDQSCKMAX_SHDW ,Shadow field for REG_T_TDQSCKMAX. This field is loaded intoEMIF_SDRAM_TIM_3[14:13] REG_T_TDQSCKMAX field when SIdleAck is asserted." "0,1,2,3" textline " " hexmask.long.word 0x00 4.--12. 1. " REG_T_RFC_SHDW ,Shadow field for REG_T_RFC. This field is loaded intoEMIF_SDRAM_TIM_3[12:4] REG_T_RFC when SIdleAck is asserted." bitfld.long 0x00 0.--3. " REG_T_RAS_MAX_SHDW ,Shadow field for REG_T_RAS_MAX. This field is loaded intoEMIF_SDRAM_TIM_3[3:0] REG_T_RAS_MAX field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x3 line.long 0x00 "EMIF_LPDDR2_NVM_TIM,LPDDR2-NVM Timing Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the LPDDR2-NVM." bitfld.long 0x00 28.--30. " REG_NVM_T_XP ,Minimum number of DDR clock cycles from Powerdown exit to any command, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " REG_NVM_T_WTR ,Minimum number of DDR clock cycles from last Write to Read, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " REG_NVM_T_RP ,Minimum number of DDR clock cycles from Preactive to Activate, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " REG_NVM_T_WRA ,Minimum number of DDR clock cycles from last Write transfer to Activate, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " REG_NVM_T_RRD ,Minimum number of DDR clock cycles from Activate to Activate for a different bank, minus one." hexmask.long.byte 0x00 0.--7. 1. " REG_NVM_T_RCDMIN ,Minimum number of DDR clock cycles from Activate to Read or Write, minus one." group.long 0x34++0x3 line.long 0x00 "EMIF_LPDDR2_NVM_TIM_SHDW,LPDDR2-NVM Timing Shadow Register" bitfld.long 0x00 28.--30. " REG_NVM_T_XP_SHDW ,Shadow field for REG_NVM_T_XP. This field is loaded intoEMIF_LPDDR2_NVM_TIM[30:28] REG_NVM_T_XP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " REG_NVM_T_WTR_SHDW ,Shadow field for REG_NVM_T_WTR. This field is loaded intoEMIF_LPDDR2_NVM_TIM[26:24] REG_NVM_T_WTR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " REG_NVM_T_RP_SHDW ,Shadow field for REG_NVM_T_RP. This field is loaded intoEMIF_LPDDR2_NVM_TIM[23:20] REG_NVM_T_RP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " REG_NVM_T_WRA_SHDW ,Shadow field for REG_NVM_T_WRA. This field is loaded intoEMIF_LPDDR2_NVM_TIM[19:16] REG_NVM_T_WRA field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " REG_NVM_T_RRD_SHDW ,Shadow field for REG_NVM_T_RRD. This field is loaded intoEMIF_LPDDR2_NVM_TIM[15:8] REG_NVM_T_RRD field when SIdleAck is asserted." hexmask.long.byte 0x00 0.--7. 1. " REG_NVM_T_RCDMIN_SHDW ,Shadow field for . This field is loaded intoEMIF_LPDDR2_NVM_TIM[7:0] REG_NVM_T_RCDMIN field when SIdleAck is asserted." group.long 0x38++0x3 line.long 0x00 "EMIF_PWR_MGMT_CTRL,Power Management Control Register" bitfld.long 0x00 12.--15. " REG_PD_TIM ,Power Mangement timer for Power-Down. The EMIF will put the external SDRAM in Power-Down mode after the EMIF is idle for these number of DDR clock cycles and if reg_lp_mode field is set to 4. Set to 0 to immed.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " REG_DPD_EN ,Deep Power Down enable. Set to 0 for normal operation. Set to 1 to enter deep power-down mode. This mode will override the reg_lp_mode field setting." "0,1" bitfld.long 0x00 8.--10. " REG_LP_MODE ,Automatic Power Management enableSet to 1: Reserved. - . Set to 2: Self-refresh mode. - . Set to 4: Power-down mode. - . - All other values will disable automatic power management. . - ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 4.--7. " REG_SR_TIM ,Power Mangement timer for Self Refresh. The EMIF will put the external SDRAM in Self Refresh mode after the EMIF is idle for these number of DDR clock cycles and if reg_lp_mode field is set to 2. Set to 0 to i.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REG_CS_TIM ,Power Mangement timer for Clock Stop. The EMIF will put the external SDRAM in Clock Stop mode after the EMIF is idle for these number of DDR clock cycles and if reg_lp_mode field is set to 1. Set to 0 to.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x3 line.long 0x00 "EMIF_PWR_MGMT_CTRL_SHDW,Power Management Control Shadow Register" bitfld.long 0x00 12.--15. " REG_PD_TIM_SHDW ,Shadow field for reg_pd_tim. This field is loaded into reg_pd_tim field in Power Management Control register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " REG_SR_TIM_SHDW ,Shadow field for reg_sr_tim. This field is loaded into reg_sr_tim field in Power Management Control register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REG_CS_TIM_SHDW ,Shadow field for reg_cs_tim. This field is loaded into reg_cs_tim field in Power Management Control register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x3 line.long 0x00 "EMIF_LPDDR2_MODE_REG_DATA,LPDDR2 Mode Reg Data Register A write to this register will cause a Mode Register write command to be sent to the LPDDR2 device with write data as specified in the REG_VALUE_0 field. The address and chip-select are taken from .." hexmask.long.byte 0x00 0.--7. 1. " REG_VALUE_0 ,Mode register value." group.long 0x50++0x3 line.long 0x00 "EMIF_LPDDR2_MODE_REG_CFG,LPDDR2 Mode Reg Config Register" bitfld.long 0x00 31. " REG_CS ,Chip-select to issue mode register command. Set to 0 for CS0 and set to 1 for CS1." "0,1" bitfld.long 0x00 30. " REG_REFRESH_EN ,Refresh Enable after MRW write. If a Mode Data register write occurs with this bit set to 1, the refresh operations will commence." "0,1" hexmask.long.byte 0x00 0.--7. 1. " REG_ADDRESS ,Mode register address." group.long 0x54++0x3 line.long 0x00 "EMIF_L3_CONFIG,Config Register" bitfld.long 0x00 24.--27. " REG_SYS_THRESH_MAX ,System L3 Threshold Maximum. The number of commands the system interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for th.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " REG_LL_THRESH_MAX ,Low-latency L3 Threshold Maximum. The number of commands the low latency interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " REG_PR_OLD_COUNT ,Priority Raise Old Counter. Number of memory transfers after which the EMIF momentarily raises the priority of old commands in the L3 Command FIFO." rgroup.long 0x58++0x3 line.long 0x00 "EMIF_L3_CFG_VAL_1,Config Value 1 Register" bitfld.long 0x00 30.--31. " REG_SYS_BUS_WIDTH ,System L3 data bus width 0 = 32-bit wide, 1 = 64-bit wide, 2 = 128-bit wide, 3 = Reserved" "0,1,2,3" bitfld.long 0x00 28.--29. " REG_LL_BUS_WIDTH ,Low-latency L3 data bus width 0 = 32-bit wide, 1 = 64-bit wide, 2 = 128-bit wide, 3 = Reserved" "0,1,2,3" hexmask.long.byte 0x00 8.--15. 1. " REG_WR_FIFO_DEPTH ,Write Data FIFO depth" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_CMD_FIFO_DEPTH ,Command FIFO depth" rgroup.long 0x5C++0x3 line.long 0x00 "EMIF_L3_CFG_VAL_2,Config Value 2 Register" hexmask.long.byte 0x00 16.--23. 1. " REG_RREG_FIFO_DEPTH ,Register Read Data FIFO depth" hexmask.long.byte 0x00 8.--15. 1. " REG_RSD_FIFO_DEPTH ,SDRAM Read Data FIFO depth" hexmask.long.byte 0x00 0.--7. 1. " REG_RCMD_FIFO_DEPTH ,Read Command FIFO depth" rgroup.long 0x80++0x3 line.long 0x00 "EMIF_PERF_CNT_1,Performance Counter 1 Register" hexmask.long 0x00 0.--31. 1. " REG_COUNTER1 ,32-bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register." rgroup.long 0x84++0x3 line.long 0x00 "EMIF_PERF_CNT_2,Performance Counter 2 Register" hexmask.long 0x00 0.--31. 1. " REG_COUNTER2 ,32-bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register." group.long 0x88++0x3 line.long 0x00 "EMIF_PERF_CNT_CFG,Performance Counter Config Register" bitfld.long 0x00 31. " REG_CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register." "0,1" bitfld.long 0x00 30. " REG_CNTR2_REGION_EN ,Chip-select filter enable for Performance Counter 2 register." "0,1" bitfld.long 0x00 16.--19. " REG_CNTR2_CFG ,Filter configuration for Performance Counter 2. Refer to for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 15. " REG_CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register." "0,1" bitfld.long 0x00 14. " REG_CNTR1_REGION_EN ,Chip-select filter enable for Performance Counter 1 register." "0,1" bitfld.long 0x00 0.--3. " REG_CNTR1_CFG ,Filter configuration for Performance Counter 1. Refer to for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8C++0x3 line.long 0x00 "EMIF_PERF_CNT_SEL,Performance Counter Master Region Select Register" hexmask.long.byte 0x00 24.--31. 1. " REG_MCONNID2 ,MConnID for Performance Counter 2 register. The values programmed are those in in , , left-shifted by 2 bits." bitfld.long 0x00 16.--17. " REG_REGION_SEL2 ,MAddrSpace for Performance Counter 2 register." "0,1,2,3" hexmask.long.byte 0x00 8.--15. 1. " REG_MCONNID1 ,MConnID for Performance Counter 1 register. The values programmed are those in in , , left-shifted by 2 bits." textline " " bitfld.long 0x00 0.--1. " REG_REGION_SEL1 ,MAddrSpace for Performance Counter 1 register." "0,1,2,3" rgroup.long 0x90++0x3 line.long 0x00 "EMIF_PERF_CNT_TIM,Performance Counter Time Register. This is a free running counter." hexmask.long 0x00 0.--31. 1. " REG_TOTAL_TIME ,32-bit counter that continuously counts number for EMIF clock cycles elapsed after EMIF is brought out of reset." group.long 0x98++0x3 line.long 0x00 "EMIF_READ_IDLE_CTRL,Read Idle Control Register" bitfld.long 0x00 16.--19. " REG_READ_IDLE_LEN ,The Read Idle Length field determines the minimum size (reg_read_idle_len-1 EMIF_FCLK clock cycles) of Read Idle window for the read idle detection as well as the force read idle time." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--8. 1. " REG_READ_IDLE_INTERVAL ,The Read Idle Interval field determines the maximum interval ((REG_READ_IDLE_INTERVAL - 1) * 64 EMIF_FCLK clock cycles) between read idle detections or force. A value of zero disables the read idle funct.." group.long 0x9C++0x3 line.long 0x00 "EMIF_READ_IDLE_CTRL_SHDW,Read Idle Control Shadow Register" bitfld.long 0x00 16.--19. " REG_READ_IDLE_LEN_SHDW ,Shadow field for REG_READ_IDLE_LEN. This field is loaded intoEMIF_READ_IDLE_CTRL[19:16] REG_READ_IDLE_LEN field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--8. 1. " REG_READ_IDLE_INTERVAL_SHDW ,Shadow field for REG_READ_IDLE_INTERVAL. This field is loaded intoEMIF_READ_IDLE_CTRL[8:0] REG_READ_IDLE_INTERVAL field when SIdleAck is asserted." group.long 0xA4++0x3 line.long 0x00 "EMIF_IRQSTATUS_RAW_SYS,System L3 Interrupt Raw Status Register" bitfld.long 0x00 2. " REG_DNV_SYS ,Raw status of system L3 interrupt for LPDDR2 NVM data not valid. - Write 1 to set the (raw) status, typically for debug. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 1. " REG_TA_SYS ,Raw status of system L3 interrupt for SDRAM temperature alert. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x00 0. " REG_ERR_SYS ,Raw status of system L3 interrupt for command or address error. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" group.long 0xA8++0x3 line.long 0x00 "EMIF_IRQSTATUS_RAW_LL,Low-Latency L3 Interrupt Raw Status Register" bitfld.long 0x00 2. " REG_DNV_LL ,Raw status of low-latency L3 interrupt for LPDDR2 NVM data not valid. - Write 1 to set the (raw) status, typically for debug. . - . - Writing 0 has no effect. . - ." "0,1" bitfld.long 0x00 1. " REG_TA_LL ,Raw status of low-latency L3 interrupt or SDRAM temperature alert. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x00 0. " REG_ERR_LL ,Raw status of low-latency L3 interrupt for command or address error. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" group.long 0xAC++0x3 line.long 0x00 "EMIF_IRQSTATUS_SYS,System L3 Interrupt Status Register" bitfld.long 0x00 2. " REG_DNV_SYS ,Enabled status of system L3 interrupt for LPDDR2 NVM data not valid. - Write 1 to clear the status after interrupt is serviced (raw status is cleared; that is, even if not enabled). . - . - Writing 0 has no ef.." "0,1" bitfld.long 0x00 1. " REG_TA_SYS ,Enabled status of system L3 interrupt for SDRAM temperature alert. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0 has .." "0,1" bitfld.long 0x00 0. " REG_ERR_SYS ,Enabled status of system L3 interrupt interrupt for command or address error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0 ha.." "0,1" group.long 0xB0++0x3 line.long 0x00 "EMIF_IRQSTATUS_LL,Low-Latency L3 Interrupt Status Register" eventfld.long 0x00 2. " REG_DNV_LL ,Enabled status of low-latency L3 interrupt for LPDDR2 NVM data not valid. - Write 1 to clear the status after interrupt is serviced (raw status is cleared; that is, even if not enabled). . - . - Writing 0 has .." "0,1" eventfld.long 0x00 1. " REG_TA_LL ,Enabled status of low-latency L3 interrupt for SDRAM temperature alert. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0.." "0,1" eventfld.long 0x00 0. " REG_ERR_LL ,Enabled status of low-latency L3 interrupt for command or address error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0 has no .." "0,1" group.long 0xB4++0x3 line.long 0x00 "EMIF_IRQENABLE_SET_SYS,System L3 Interrupt Enable Set Register" bitfld.long 0x00 2. " REG_EN_DNV_SYS ,Enable set for system L3 interrupt for LPDDR2 NVM data not valid. - Writing 1 enables the interrupt and sets this bit and the corresponding Interrupt-enable clear register. . - . - Writing 0 has no effect. . -.." "0,1" bitfld.long 0x00 1. " REG_EN_TA_SYS ,Enable set for system L3 interrupt for SDRAM temperature alert. . Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no.." "0,1" bitfld.long 0x00 0. " REG_EN_ERR_SYS ,Enable set for system L3 interrupt for command or address error. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" group.long 0xB8++0x3 line.long 0x00 "EMIF_IRQENABLE_SET_LL,Low-Latency L3 Interrupt Enable Set Register" bitfld.long 0x00 2. " REG_EN_DNV_LL ,Enable set for low-latency L3 interrupt for LPDDR2 NVM data not valid. - Writing 1 enables the interrupt and sets this bit and the corresponding Interrupt-enable clear register. . - . - Writing a 0 has no effe.." "0,1" bitfld.long 0x00 1. " REG_EN_TA_LL ,Enable set for low-latency L3 interrupt for SDRAM temperature alert. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has.." "0,1" bitfld.long 0x00 0. " REG_EN_ERR_LL ,Enable set for low-latency L3 interrupt for command or address error. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effe.." "0,1" group.long 0xBC++0x3 line.long 0x00 "EMIF_IRQENABLE_CLR_SYS,System L3 Interrupt Enable Clear Register" eventfld.long 0x00 2. " REG_EN_DNV_SYS ,Enable clear for system OCP interrupt for LPDDR2 NVM data not valid. - Writing 1 disables the interrupt and clears this bit and the corresponding interrupt-enable set register. . - . - Writing 0 has no effect..." "0,1" eventfld.long 0x00 1. " REG_EN_TA_SYS ,Enable clear for system L3 interrupt for SDRAM temperature alert. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has n.." "0,1" eventfld.long 0x00 0. " REG_EN_ERR_SYS ,Enable clear for system L3 interrupt for command or address error. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.." "0,1" group.long 0xC0++0x3 line.long 0x00 "EMIF_IRQENABLE_CLR_LL,Low-Latency L3 Interrupt Enable Clear Register" eventfld.long 0x00 2. " REG_EN_DNV_LL ,Enable clear for low-latency OCP interrupt for LPDDR2 NVM data not valid. - Writing 1 disables the interrupt and clears this bit and the corresponding interrupt enable set register. . - . - Writing 0 has no ef.." "0,1" eventfld.long 0x00 1. " REG_EN_TA_LL ,Enable clear for low-latency L3 interrupt for SDRAM temperature alert. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 .." "0,1" eventfld.long 0x00 0. " REG_EN_ERR_LL ,Enable clear for low-latency L3 interrupt for command or address error. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no e.." "0,1" group.long 0xC8++0x3 line.long 0x00 "EMIF_ZQ_CONFIG,SDRAM Output Impedance Calibration Config Register" bitfld.long 0x00 31. " REG_ZQ_CS1EN ,Writing a 1 enables ZQ calibration for CS1." "0,1" bitfld.long 0x00 30. " REG_ZQ_CS0EN ,Writing a 1 enables ZQ calibration for CS0." "0,1" bitfld.long 0x00 29. " REG_ZQ_DUALCALEN ,ZQ Dual Calibration enable. Allows both ranks to be ZQ calibrated simultaneously. Setting this bit requires both chip-selects to have a separate calibration resistor per device." "0,1" textline " " bitfld.long 0x00 28. " REG_ZQ_SFEXITEN ,ZQCL on Self-Refresh, Active Power-Down, and Precharge Power-Down exit enable. Writing a 1 enables the issuing of ZQCL on Self-Refresh, Active Power-Down, and Precharge Power-Down exit." "0,1" bitfld.long 0x00 18.--19. " REG_ZQ_ZQINIT_MULT ,Indicates the number of ZQCL durations that make up a ZQINIT duration, minus one." "0,1,2,3" bitfld.long 0x00 16.--17. " REG_ZQ_ZQCL_MULT ,Indicates the number of ZQCS intervals that make up a ZQCL duration, minus one. ZQCS interval is defined by reg_zq_zqcs inEMIF_SDRAM_TIM_3." "0,1,2,3" textline " " hexmask.long.word 0x00 0.--15. 1. " REG_ZQ_REFINTERVAL ,Number of refresh periods between ZQCS commands. This field supports between one refresh period to 256 ms between ZQCS calibration commands. Refresh period is defined by reg_refresh_rate inEMIF_SDRAM_REF_CTRL .." group.long 0xCC++0x3 line.long 0x00 "EMIF_TEMP_ALERT_CONFIG,Temperature Alert Config Register" bitfld.long 0x00 31. " REG_TA_CS1EN ,Writing a 1 enables temperature alert polling for CS1." "0,1" bitfld.long 0x00 30. " REG_TA_CS0EN ,Writing a 1 enables temperature alert polling for CS0." "0,1" bitfld.long 0x00 28. " REG_TA_SFEXITEN ,Temperature Alert Poll on Self-Refresh, Active Power-Down, and Precharge Power-Down exit enable. Writing a 1 enables the issuing of a temperature alert poll on Self-Refresh exit." "0,1" textline " " bitfld.long 0x00 26.--27. " REG_TA_DEVWDT ,This field indicates how wide a physical device is. It is used in conjunction with the reg_ta_devcnt register to determine which byte lanes contain the temperature alert info. A value of 0 = eight bit wide, 1 .." "0,1,2,3" bitfld.long 0x00 24.--25. " REG_TA_DEVCNT ,This field indicates which external byte lanes contain a device for temperature monitoring. A value of 0 = one device, 1 = two devices, 2 = four devices. All other reserved." "0,1,2,3" hexmask.long.tbyte 0x00 0.--21. 1. " REG_TA_REFINTERVAL ,Number of refresh periods between temperature alert polls. This field supports between one refresh period to 10 seconds between temperature alert polls. Refresh period is defined by reg_refresh_rate in SDRAM Ref.." rgroup.long 0xD0++0x3 line.long 0x00 "EMIF_L3_ERR_LOG,Error Log Register" bitfld.long 0x00 14.--15. " REG_MADDRSPACE ,Address space of the first errored transaction. 0x0: SDRAM 0x1: LPDDR2-NVM 0x2: reserved 0x3: internal registers" "0,1,2,3" bitfld.long 0x00 11.--13. " REG_MBURSTSEQ ,Addressing mode of the first errored transaction. (see, for more information)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " REG_MCMD ,Command type of the first errored transaction. (see, for more information)" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_MCONNID ,Connection ID of the first errored transaction." group.long 0xE4++0x3 line.long 0x00 "EMIF_DDR_PHY_CTRL_1,DDR PHY Control 1 Register. This register is used to control the DDR PHY. The bit field definitions are DDR PHY specific." bitfld.long 0x00 30.--31. " DLL_MASTER_SENSITIVITY ,This field defines the level of sensitivity of the DLL master: the lower the value, the more sensitive the DLL is to PVT variation. The recommended setting is 0x2." "0,1,2,3" bitfld.long 0x00 26.--29. " REG_PHY_FREEZE_DELAY_CODE_POSTAMBLE ,Postamble time respected by the DATA PHY freezing the DLL slave code after reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--25. " REG_PHY_FREEZE_DELAY_CODE_PREAMBLE ,Preamble time respected by the DATA PHY before freezing the DLL slave code during reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 12.--21. 1. " REG_DLL_MASTER_SW_CODE_CTRL ,DLL delay code when in software override mode" hexmask.long.byte 0x00 4.--11. 1. " REG_DLL_SLAVE_DLY_CTRL ,DLL slave delay ratio control" bitfld.long 0x00 0.--3. " REG_READ_LATENCY ,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles. This field is used by the EMIF as well as the PHY. The EMIF will expect the first read data to arrive (reg_read_late.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE8++0x3 line.long 0x00 "EMIF_DDR_PHY_CTRL_1_SHDW,DDR PHY Control 1 Shadow Register. Shadow field for." bitfld.long 0x00 26.--29. " REG_PHY_FREEZE_DELAY_CODE_POSTAMBLE_SHDW ,Shadow field for REG_PHY_FREEZE_DELAY_CODE_POSTAMBLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--25. " REG_PHY_FREEZE_DELAY_CODE_PREAMBLE_SHDW ,Shadow field for REG_PHY_FREEZE_DELAY_CODE_PREAMBLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 12.--21. 1. " REG_DLL_MASTER_SW_CODE_CTRL_SHDW ,Shadow field for REG_DLL_MASTER_SW_CODE_CTRL" textline " " hexmask.long.byte 0x00 4.--11. 1. " REG_DLL_SLAVE_DLY_CTRL_SHDW ,Shadow field for REG_DLL_SLAVE_DLY_CTRL" bitfld.long 0x00 0.--3. " REG_READ_LATENCY_SHDW ,Shadow field for REG_READ_LATENCY. This field is loaded intoEMIF_DDR_PHY_CTRL_1[3:0] REG_READ_LATENCY field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEC++0x3 line.long 0x00 "EMIF_DDR_PHY_CTRL_2,DDR PHY Control 2 Register" hexmask.long 0x00 0.--31. 1. " REG_DDR_PHY_CTRL_2 ,This register is used to control the DDR PHY. The bit field definitions are DDR PHY specific." tree.end tree.end tree.end tree.open "General_Purpose_Memory_Controller" tree "GPMC" base ad:0x50000000 tree "Channel_0" width 23. group.long 0x240++0x3 line.long 0x00 "GPMC_BCH_RESULT0_i_0,BCH ECC result (bits 0 to 31)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.long 0x244++0x3 line.long 0x00 "GPMC_BCH_RESULT1_i_0,BCH ECC result (bits 32 to 63)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.long 0x248++0x3 line.long 0x00 "GPMC_BCH_RESULT2_i_0,BCH ECC result (bits 64 to 95)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.long 0x24C++0x3 line.long 0x00 "GPMC_BCH_RESULT3_i_0,BCH ECC result (bits 96 to 127)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.long 0x300++0x3 line.long 0x00 "GPMC_BCH_RESULT4_i_0,BCH ECC result (bits 128 to 159)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.long 0x304++0x3 line.long 0x00 "GPMC_BCH_RESULT5_i_0,BCH ECC result (bits 160 to 191)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.long 0x308++0x3 line.long 0x00 "GPMC_BCH_RESULT6_i_0,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" group.long 0x60++0x3 line.long 0x00 "GPMC_CONFIG1_i_0,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst - . - ." "WrapNotSupp,WrapSupp" bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access - . - ." "RdSingle,RdMultiple" bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation - . - ." "RdAsync,RdSync" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access - . - ." "WrSingle,WrMultiple" bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation - . - ." "WrAsync,WrSync" bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time - . - . - . - ." "AtStart,OneClkB4,TwoClkB4,NotDefined" textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGE_LENGTH ,Specifies the attached device page (burst) length - . - . - . - ." "4_Words,8_Words,16_Words,3" bitfld.long 0x00 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at IC reset) - . - ." "WNotMonit,Wmonit" bitfld.long 0x00 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses - . - ." "WNotMonit,Wmonit" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time - . - . - . - ." "AtValid,OneDeviceB4,TwoDeviceB4,NotDefined" bitfld.long 0x00 16.--17. " WAITPINSELECT ,Selects the input WAIT pin for this chip-select (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-7) - . - . - . - ." "W0,W1,W2,W3" bitfld.long 0x00 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value is input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) - . - . - . - ." "EightBits,SixteenBits,ThirtyTwoBits,Res" textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type - . - . - . - ." "NORlike,Res1,NANDlike,Res2" bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-CS7) - . - . - . - ." "NonMux,AADMux,Mux,?..." bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIME.." "x1,x2" textline " " bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock - . - . - . - ." "DivBy1,DivBy2,DivBy3,UNKN_MNEMO" group.long 0x64++0x3 line.long 0x00 "GPMC_CONFIG2_i_0,CS signal timing parameter configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,CS i de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " CSEXTRADELAY ,CS i Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x68++0x3 line.long 0x00 "GPMC_CONFIG3_i_0,nADV signal timing parameter configuration" bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,nADV de-assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " ADVWROFFTIME ,nADV de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,nADV de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " ADVEXTRADELAY ,nADV Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x6C++0x3 line.long 0x00 "GPMC_CONFIG4_i_0,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,nWE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " WEEXTRADELAY ,nWE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " OEAADMUX_OFFTIME ,nOE de-assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " OEOFFTIME ,nOE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " OEEXTRADELAY ,nOE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,1" textline " " bitfld.long 0x00 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x70++0x3 line.long 0x00 "GPMC_CONFIG5_i_0,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x74++0x3 line.long 0x00 "GPMC_CONFIG6_i_0,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FC.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type) - . - ." "NoC2CDelay,C2CDelay" bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type) - . - ." "NoC2CDelay,1" bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x78++0x3 line.long 0x00 "GPMC_CONFIG7_i_0,CS address mapping configuration" bitfld.long 0x00 8.--11. " MASKADDRESS ,CS mask address. 0x1000: Chip-select size of 128 Mbytes 0x1100: Chip-select size of 64 Mbytes 0x1110: Chip-select size of 32 Mbytes 0x1111: Chip-select size of 16 Mbytes Other values must be avoided as they create holes in t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " CSVALID ,CS enable - . - ." "CSDisabled,CSEnabled" bitfld.long 0x00 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16M bytes minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x200++0x3 line.long 0x00 "GPMC_ECCj_RESULT_0,ECC result register" bitfld.long 0x00 27. " P2048o ,Odd row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024o ,Odd row parity bit 1024" "0,1" bitfld.long 0x00 25. " P512o ,Odd row parity bit 512" "0,1" textline " " bitfld.long 0x00 24. " P256o ,Odd row parity bit 256" "0,1" bitfld.long 0x00 23. " P128o ,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. " P64o ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x00 21. " P32o ,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. " P16o ,Odd row parity bit 16" "0,1" bitfld.long 0x00 19. " P8o ,Odd row parity bit 8" "0,1" textline " " bitfld.long 0x00 18. " P4o ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2o ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1o ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048e ,Even row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024e ,Even row parity bit 1024" "0,1" bitfld.long 0x00 9. " P512e ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x00 8. " P256e ,Even row parity bit 256" "0,1" bitfld.long 0x00 7. " P128e ,Even row parity bit 128" "0,1" bitfld.long 0x00 6. " P64e ,Even row parity bit 64" "0,1" textline " " bitfld.long 0x00 5. " P32e ,Even row parity bit 32" "0,1" bitfld.long 0x00 4. " P16e ,Even row parity bit 16" "0,1" bitfld.long 0x00 3. " P8e ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x00 2. " P4e ,Even column parity bit 4" "0,1" bitfld.long 0x00 1. " P2e ,Even column parity bit 2" "0,1" bitfld.long 0x00 0. " P1e ,Even column parity bit 1" "0,1" wgroup.long 0x80++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_i_0,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." wgroup.long 0x7C++0x3 line.long 0x00 "GPMC_NAND_COMMAND_i_0,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." wgroup.long 0x84++0x3 line.long 0x00 "GPMC_NAND_DATA_i_0,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, just an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." tree.end tree "Channel_1" width 23. group.long 0x250++0x3 line.long 0x00 "GPMC_BCH_RESULT0_i_1,BCH ECC result (bits 0 to 31)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.long 0x254++0x3 line.long 0x00 "GPMC_BCH_RESULT1_i_1,BCH ECC result (bits 32 to 63)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.long 0x258++0x3 line.long 0x00 "GPMC_BCH_RESULT2_i_1,BCH ECC result (bits 64 to 95)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.long 0x25C++0x3 line.long 0x00 "GPMC_BCH_RESULT3_i_1,BCH ECC result (bits 96 to 127)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.long 0x310++0x3 line.long 0x00 "GPMC_BCH_RESULT4_i_1,BCH ECC result (bits 128 to 159)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.long 0x314++0x3 line.long 0x00 "GPMC_BCH_RESULT5_i_1,BCH ECC result (bits 160 to 191)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.long 0x318++0x3 line.long 0x00 "GPMC_BCH_RESULT6_i_1,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" group.long 0x90++0x3 line.long 0x00 "GPMC_CONFIG1_i_1,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst - . - ." "WrapNotSupp,WrapSupp" bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access - . - ." "RdSingle,RdMultiple" bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation - . - ." "RdAsync,RdSync" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access - . - ." "WrSingle,WrMultiple" bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation - . - ." "WrAsync,WrSync" bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time - . - . - . - ." "AtStart,OneClkB4,TwoClkB4,NotDefined" textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGE_LENGTH ,Specifies the attached device page (burst) length - . - . - . - ." "4_Words,8_Words,16_Words,3" bitfld.long 0x00 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at IC reset) - . - ." "WNotMonit,Wmonit" bitfld.long 0x00 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses - . - ." "WNotMonit,Wmonit" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time - . - . - . - ." "AtValid,OneDeviceB4,TwoDeviceB4,NotDefined" bitfld.long 0x00 16.--17. " WAITPINSELECT ,Selects the input WAIT pin for this chip-select (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-7) - . - . - . - ." "W0,W1,W2,W3" bitfld.long 0x00 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value is input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) - . - . - . - ." "EightBits,SixteenBits,ThirtyTwoBits,Res" textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type - . - . - . - ." "NORlike,Res1,NANDlike,Res2" bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-CS7) - . - . - . - ." "NonMux,AADMux,Mux,?..." bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIME.." "x1,x2" textline " " bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock - . - . - . - ." "DivBy1,DivBy2,DivBy3,UNKN_MNEMO" group.long 0x94++0x3 line.long 0x00 "GPMC_CONFIG2_i_1,CS signal timing parameter configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,CS i de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " CSEXTRADELAY ,CS i Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x98++0x3 line.long 0x00 "GPMC_CONFIG3_i_1,nADV signal timing parameter configuration" bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,nADV de-assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " ADVWROFFTIME ,nADV de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,nADV de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " ADVEXTRADELAY ,nADV Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9C++0x3 line.long 0x00 "GPMC_CONFIG4_i_1,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,nWE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " WEEXTRADELAY ,nWE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " OEAADMUX_OFFTIME ,nOE de-assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " OEOFFTIME ,nOE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " OEEXTRADELAY ,nOE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,1" textline " " bitfld.long 0x00 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x3 line.long 0x00 "GPMC_CONFIG5_i_1,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA4++0x3 line.long 0x00 "GPMC_CONFIG6_i_1,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FC.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type) - . - ." "NoC2CDelay,C2CDelay" bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type) - . - ." "NoC2CDelay,1" bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA8++0x3 line.long 0x00 "GPMC_CONFIG7_i_1,CS address mapping configuration" bitfld.long 0x00 8.--11. " MASKADDRESS ,CS mask address. 0x1000: Chip-select size of 128 Mbytes 0x1100: Chip-select size of 64 Mbytes 0x1110: Chip-select size of 32 Mbytes 0x1111: Chip-select size of 16 Mbytes Other values must be avoided as they create holes in t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " CSVALID ,CS enable - . - ." "CSDisabled,CSEnabled" bitfld.long 0x00 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16M bytes minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x204++0x3 line.long 0x00 "GPMC_ECCj_RESULT_1,ECC result register" bitfld.long 0x00 27. " P2048o ,Odd row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024o ,Odd row parity bit 1024" "0,1" bitfld.long 0x00 25. " P512o ,Odd row parity bit 512" "0,1" textline " " bitfld.long 0x00 24. " P256o ,Odd row parity bit 256" "0,1" bitfld.long 0x00 23. " P128o ,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. " P64o ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x00 21. " P32o ,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. " P16o ,Odd row parity bit 16" "0,1" bitfld.long 0x00 19. " P8o ,Odd row parity bit 8" "0,1" textline " " bitfld.long 0x00 18. " P4o ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2o ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1o ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048e ,Even row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024e ,Even row parity bit 1024" "0,1" bitfld.long 0x00 9. " P512e ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x00 8. " P256e ,Even row parity bit 256" "0,1" bitfld.long 0x00 7. " P128e ,Even row parity bit 128" "0,1" bitfld.long 0x00 6. " P64e ,Even row parity bit 64" "0,1" textline " " bitfld.long 0x00 5. " P32e ,Even row parity bit 32" "0,1" bitfld.long 0x00 4. " P16e ,Even row parity bit 16" "0,1" bitfld.long 0x00 3. " P8e ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x00 2. " P4e ,Even column parity bit 4" "0,1" bitfld.long 0x00 1. " P2e ,Even column parity bit 2" "0,1" bitfld.long 0x00 0. " P1e ,Even column parity bit 1" "0,1" wgroup.long 0xB0++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_i_1,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." wgroup.long 0xAC++0x3 line.long 0x00 "GPMC_NAND_COMMAND_i_1,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." wgroup.long 0xB4++0x3 line.long 0x00 "GPMC_NAND_DATA_i_1,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, just an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." tree.end tree "Channel_2" width 23. group.long 0x260++0x3 line.long 0x00 "GPMC_BCH_RESULT0_i_2,BCH ECC result (bits 0 to 31)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.long 0x264++0x3 line.long 0x00 "GPMC_BCH_RESULT1_i_2,BCH ECC result (bits 32 to 63)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.long 0x268++0x3 line.long 0x00 "GPMC_BCH_RESULT2_i_2,BCH ECC result (bits 64 to 95)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.long 0x26C++0x3 line.long 0x00 "GPMC_BCH_RESULT3_i_2,BCH ECC result (bits 96 to 127)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.long 0x320++0x3 line.long 0x00 "GPMC_BCH_RESULT4_i_2,BCH ECC result (bits 128 to 159)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.long 0x324++0x3 line.long 0x00 "GPMC_BCH_RESULT5_i_2,BCH ECC result (bits 160 to 191)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.long 0x328++0x3 line.long 0x00 "GPMC_BCH_RESULT6_i_2,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" group.long 0xC0++0x3 line.long 0x00 "GPMC_CONFIG1_i_2,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst - . - ." "WrapNotSupp,WrapSupp" bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access - . - ." "RdSingle,RdMultiple" bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation - . - ." "RdAsync,RdSync" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access - . - ." "WrSingle,WrMultiple" bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation - . - ." "WrAsync,WrSync" bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time - . - . - . - ." "AtStart,OneClkB4,TwoClkB4,NotDefined" textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGE_LENGTH ,Specifies the attached device page (burst) length - . - . - . - ." "4_Words,8_Words,16_Words,3" bitfld.long 0x00 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at IC reset) - . - ." "WNotMonit,Wmonit" bitfld.long 0x00 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses - . - ." "WNotMonit,Wmonit" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time - . - . - . - ." "AtValid,OneDeviceB4,TwoDeviceB4,NotDefined" bitfld.long 0x00 16.--17. " WAITPINSELECT ,Selects the input WAIT pin for this chip-select (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-7) - . - . - . - ." "W0,W1,W2,W3" bitfld.long 0x00 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value is input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) - . - . - . - ." "EightBits,SixteenBits,ThirtyTwoBits,Res" textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type - . - . - . - ." "NORlike,Res1,NANDlike,Res2" bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-CS7) - . - . - . - ." "NonMux,AADMux,Mux,?..." bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIME.." "x1,x2" textline " " bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock - . - . - . - ." "DivBy1,DivBy2,DivBy3,UNKN_MNEMO" group.long 0xC4++0x3 line.long 0x00 "GPMC_CONFIG2_i_2,CS signal timing parameter configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,CS i de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " CSEXTRADELAY ,CS i Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC8++0x3 line.long 0x00 "GPMC_CONFIG3_i_2,nADV signal timing parameter configuration" bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,nADV de-assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " ADVWROFFTIME ,nADV de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,nADV de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " ADVEXTRADELAY ,nADV Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xCC++0x3 line.long 0x00 "GPMC_CONFIG4_i_2,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,nWE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " WEEXTRADELAY ,nWE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " OEAADMUX_OFFTIME ,nOE de-assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " OEOFFTIME ,nOE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " OEEXTRADELAY ,nOE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,1" textline " " bitfld.long 0x00 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD0++0x3 line.long 0x00 "GPMC_CONFIG5_i_2,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD4++0x3 line.long 0x00 "GPMC_CONFIG6_i_2,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FC.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type) - . - ." "NoC2CDelay,C2CDelay" bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type) - . - ." "NoC2CDelay,1" bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD8++0x3 line.long 0x00 "GPMC_CONFIG7_i_2,CS address mapping configuration" bitfld.long 0x00 8.--11. " MASKADDRESS ,CS mask address. 0x1000: Chip-select size of 128 Mbytes 0x1100: Chip-select size of 64 Mbytes 0x1110: Chip-select size of 32 Mbytes 0x1111: Chip-select size of 16 Mbytes Other values must be avoided as they create holes in t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " CSVALID ,CS enable - . - ." "CSDisabled,CSEnabled" bitfld.long 0x00 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16M bytes minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x208++0x3 line.long 0x00 "GPMC_ECCj_RESULT_2,ECC result register" bitfld.long 0x00 27. " P2048o ,Odd row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024o ,Odd row parity bit 1024" "0,1" bitfld.long 0x00 25. " P512o ,Odd row parity bit 512" "0,1" textline " " bitfld.long 0x00 24. " P256o ,Odd row parity bit 256" "0,1" bitfld.long 0x00 23. " P128o ,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. " P64o ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x00 21. " P32o ,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. " P16o ,Odd row parity bit 16" "0,1" bitfld.long 0x00 19. " P8o ,Odd row parity bit 8" "0,1" textline " " bitfld.long 0x00 18. " P4o ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2o ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1o ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048e ,Even row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024e ,Even row parity bit 1024" "0,1" bitfld.long 0x00 9. " P512e ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x00 8. " P256e ,Even row parity bit 256" "0,1" bitfld.long 0x00 7. " P128e ,Even row parity bit 128" "0,1" bitfld.long 0x00 6. " P64e ,Even row parity bit 64" "0,1" textline " " bitfld.long 0x00 5. " P32e ,Even row parity bit 32" "0,1" bitfld.long 0x00 4. " P16e ,Even row parity bit 16" "0,1" bitfld.long 0x00 3. " P8e ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x00 2. " P4e ,Even column parity bit 4" "0,1" bitfld.long 0x00 1. " P2e ,Even column parity bit 2" "0,1" bitfld.long 0x00 0. " P1e ,Even column parity bit 1" "0,1" wgroup.long 0xE0++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_i_2,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." wgroup.long 0xDC++0x3 line.long 0x00 "GPMC_NAND_COMMAND_i_2,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." wgroup.long 0xE4++0x3 line.long 0x00 "GPMC_NAND_DATA_i_2,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, just an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." tree.end tree "Channel_3" width 23. group.long 0x270++0x3 line.long 0x00 "GPMC_BCH_RESULT0_i_3,BCH ECC result (bits 0 to 31)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.long 0x274++0x3 line.long 0x00 "GPMC_BCH_RESULT1_i_3,BCH ECC result (bits 32 to 63)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.long 0x278++0x3 line.long 0x00 "GPMC_BCH_RESULT2_i_3,BCH ECC result (bits 64 to 95)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.long 0x27C++0x3 line.long 0x00 "GPMC_BCH_RESULT3_i_3,BCH ECC result (bits 96 to 127)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.long 0x330++0x3 line.long 0x00 "GPMC_BCH_RESULT4_i_3,BCH ECC result (bits 128 to 159)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.long 0x334++0x3 line.long 0x00 "GPMC_BCH_RESULT5_i_3,BCH ECC result (bits 160 to 191)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.long 0x338++0x3 line.long 0x00 "GPMC_BCH_RESULT6_i_3,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" group.long 0xF0++0x3 line.long 0x00 "GPMC_CONFIG1_i_3,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst - . - ." "WrapNotSupp,WrapSupp" bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access - . - ." "RdSingle,RdMultiple" bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation - . - ." "RdAsync,RdSync" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access - . - ." "WrSingle,WrMultiple" bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation - . - ." "WrAsync,WrSync" bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time - . - . - . - ." "AtStart,OneClkB4,TwoClkB4,NotDefined" textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGE_LENGTH ,Specifies the attached device page (burst) length - . - . - . - ." "4_Words,8_Words,16_Words,3" bitfld.long 0x00 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at IC reset) - . - ." "WNotMonit,Wmonit" bitfld.long 0x00 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses - . - ." "WNotMonit,Wmonit" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time - . - . - . - ." "AtValid,OneDeviceB4,TwoDeviceB4,NotDefined" bitfld.long 0x00 16.--17. " WAITPINSELECT ,Selects the input WAIT pin for this chip-select (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-7) - . - . - . - ." "W0,W1,W2,W3" bitfld.long 0x00 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value is input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) - . - . - . - ." "EightBits,SixteenBits,ThirtyTwoBits,Res" textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type - . - . - . - ." "NORlike,Res1,NANDlike,Res2" bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-CS7) - . - . - . - ." "NonMux,AADMux,Mux,?..." bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIME.." "x1,x2" textline " " bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock - . - . - . - ." "DivBy1,DivBy2,DivBy3,UNKN_MNEMO" group.long 0xF4++0x3 line.long 0x00 "GPMC_CONFIG2_i_3,CS signal timing parameter configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,CS i de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " CSEXTRADELAY ,CS i Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF8++0x3 line.long 0x00 "GPMC_CONFIG3_i_3,nADV signal timing parameter configuration" bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,nADV de-assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " ADVWROFFTIME ,nADV de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,nADV de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " ADVEXTRADELAY ,nADV Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFC++0x3 line.long 0x00 "GPMC_CONFIG4_i_3,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,nWE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " WEEXTRADELAY ,nWE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " OEAADMUX_OFFTIME ,nOE de-assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " OEOFFTIME ,nOE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " OEEXTRADELAY ,nOE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,1" textline " " bitfld.long 0x00 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x3 line.long 0x00 "GPMC_CONFIG5_i_3,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x104++0x3 line.long 0x00 "GPMC_CONFIG6_i_3,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FC.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type) - . - ." "NoC2CDelay,C2CDelay" bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type) - . - ." "NoC2CDelay,1" bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x108++0x3 line.long 0x00 "GPMC_CONFIG7_i_3,CS address mapping configuration" bitfld.long 0x00 8.--11. " MASKADDRESS ,CS mask address. 0x1000: Chip-select size of 128 Mbytes 0x1100: Chip-select size of 64 Mbytes 0x1110: Chip-select size of 32 Mbytes 0x1111: Chip-select size of 16 Mbytes Other values must be avoided as they create holes in t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " CSVALID ,CS enable - . - ." "CSDisabled,CSEnabled" bitfld.long 0x00 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16M bytes minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x20C++0x3 line.long 0x00 "GPMC_ECCj_RESULT_3,ECC result register" bitfld.long 0x00 27. " P2048o ,Odd row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024o ,Odd row parity bit 1024" "0,1" bitfld.long 0x00 25. " P512o ,Odd row parity bit 512" "0,1" textline " " bitfld.long 0x00 24. " P256o ,Odd row parity bit 256" "0,1" bitfld.long 0x00 23. " P128o ,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. " P64o ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x00 21. " P32o ,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. " P16o ,Odd row parity bit 16" "0,1" bitfld.long 0x00 19. " P8o ,Odd row parity bit 8" "0,1" textline " " bitfld.long 0x00 18. " P4o ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2o ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1o ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048e ,Even row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024e ,Even row parity bit 1024" "0,1" bitfld.long 0x00 9. " P512e ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x00 8. " P256e ,Even row parity bit 256" "0,1" bitfld.long 0x00 7. " P128e ,Even row parity bit 128" "0,1" bitfld.long 0x00 6. " P64e ,Even row parity bit 64" "0,1" textline " " bitfld.long 0x00 5. " P32e ,Even row parity bit 32" "0,1" bitfld.long 0x00 4. " P16e ,Even row parity bit 16" "0,1" bitfld.long 0x00 3. " P8e ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x00 2. " P4e ,Even column parity bit 4" "0,1" bitfld.long 0x00 1. " P2e ,Even column parity bit 2" "0,1" bitfld.long 0x00 0. " P1e ,Even column parity bit 1" "0,1" wgroup.long 0x110++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_i_3,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." wgroup.long 0x10C++0x3 line.long 0x00 "GPMC_NAND_COMMAND_i_3,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." wgroup.long 0x114++0x3 line.long 0x00 "GPMC_NAND_DATA_i_3,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, just an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." tree.end tree "Channel_4" width 23. group.long 0x280++0x3 line.long 0x00 "GPMC_BCH_RESULT0_i_4,BCH ECC result (bits 0 to 31)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.long 0x284++0x3 line.long 0x00 "GPMC_BCH_RESULT1_i_4,BCH ECC result (bits 32 to 63)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.long 0x288++0x3 line.long 0x00 "GPMC_BCH_RESULT2_i_4,BCH ECC result (bits 64 to 95)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.long 0x28C++0x3 line.long 0x00 "GPMC_BCH_RESULT3_i_4,BCH ECC result (bits 96 to 127)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.long 0x340++0x3 line.long 0x00 "GPMC_BCH_RESULT4_i_4,BCH ECC result (bits 128 to 159)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.long 0x344++0x3 line.long 0x00 "GPMC_BCH_RESULT5_i_4,BCH ECC result (bits 160 to 191)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.long 0x348++0x3 line.long 0x00 "GPMC_BCH_RESULT6_i_4,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" group.long 0x120++0x3 line.long 0x00 "GPMC_CONFIG1_i_4,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst - . - ." "WrapNotSupp,WrapSupp" bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access - . - ." "RdSingle,RdMultiple" bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation - . - ." "RdAsync,RdSync" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access - . - ." "WrSingle,WrMultiple" bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation - . - ." "WrAsync,WrSync" bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time - . - . - . - ." "AtStart,OneClkB4,TwoClkB4,NotDefined" textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGE_LENGTH ,Specifies the attached device page (burst) length - . - . - . - ." "4_Words,8_Words,16_Words,3" bitfld.long 0x00 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at IC reset) - . - ." "WNotMonit,Wmonit" bitfld.long 0x00 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses - . - ." "WNotMonit,Wmonit" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time - . - . - . - ." "AtValid,OneDeviceB4,TwoDeviceB4,NotDefined" bitfld.long 0x00 16.--17. " WAITPINSELECT ,Selects the input WAIT pin for this chip-select (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-7) - . - . - . - ." "W0,W1,W2,W3" bitfld.long 0x00 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value is input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) - . - . - . - ." "EightBits,SixteenBits,ThirtyTwoBits,Res" textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type - . - . - . - ." "NORlike,Res1,NANDlike,Res2" bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-CS7) - . - . - . - ." "NonMux,AADMux,Mux,?..." bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIME.." "x1,x2" textline " " bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock - . - . - . - ." "DivBy1,DivBy2,DivBy3,UNKN_MNEMO" group.long 0x124++0x3 line.long 0x00 "GPMC_CONFIG2_i_4,CS signal timing parameter configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,CS i de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " CSEXTRADELAY ,CS i Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x128++0x3 line.long 0x00 "GPMC_CONFIG3_i_4,nADV signal timing parameter configuration" bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,nADV de-assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " ADVWROFFTIME ,nADV de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,nADV de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " ADVEXTRADELAY ,nADV Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x12C++0x3 line.long 0x00 "GPMC_CONFIG4_i_4,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,nWE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " WEEXTRADELAY ,nWE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " OEAADMUX_OFFTIME ,nOE de-assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " OEOFFTIME ,nOE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " OEEXTRADELAY ,nOE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,1" textline " " bitfld.long 0x00 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x3 line.long 0x00 "GPMC_CONFIG5_i_4,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x3 line.long 0x00 "GPMC_CONFIG6_i_4,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FC.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type) - . - ." "NoC2CDelay,C2CDelay" bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type) - . - ." "NoC2CDelay,1" bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x138++0x3 line.long 0x00 "GPMC_CONFIG7_i_4,CS address mapping configuration" bitfld.long 0x00 8.--11. " MASKADDRESS ,CS mask address. 0x1000: Chip-select size of 128 Mbytes 0x1100: Chip-select size of 64 Mbytes 0x1110: Chip-select size of 32 Mbytes 0x1111: Chip-select size of 16 Mbytes Other values must be avoided as they create holes in t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " CSVALID ,CS enable - . - ." "CSDisabled,CSEnabled" bitfld.long 0x00 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16M bytes minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x210++0x3 line.long 0x00 "GPMC_ECCj_RESULT_4,ECC result register" bitfld.long 0x00 27. " P2048o ,Odd row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024o ,Odd row parity bit 1024" "0,1" bitfld.long 0x00 25. " P512o ,Odd row parity bit 512" "0,1" textline " " bitfld.long 0x00 24. " P256o ,Odd row parity bit 256" "0,1" bitfld.long 0x00 23. " P128o ,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. " P64o ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x00 21. " P32o ,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. " P16o ,Odd row parity bit 16" "0,1" bitfld.long 0x00 19. " P8o ,Odd row parity bit 8" "0,1" textline " " bitfld.long 0x00 18. " P4o ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2o ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1o ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048e ,Even row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024e ,Even row parity bit 1024" "0,1" bitfld.long 0x00 9. " P512e ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x00 8. " P256e ,Even row parity bit 256" "0,1" bitfld.long 0x00 7. " P128e ,Even row parity bit 128" "0,1" bitfld.long 0x00 6. " P64e ,Even row parity bit 64" "0,1" textline " " bitfld.long 0x00 5. " P32e ,Even row parity bit 32" "0,1" bitfld.long 0x00 4. " P16e ,Even row parity bit 16" "0,1" bitfld.long 0x00 3. " P8e ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x00 2. " P4e ,Even column parity bit 4" "0,1" bitfld.long 0x00 1. " P2e ,Even column parity bit 2" "0,1" bitfld.long 0x00 0. " P1e ,Even column parity bit 1" "0,1" wgroup.long 0x140++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_i_4,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." wgroup.long 0x13C++0x3 line.long 0x00 "GPMC_NAND_COMMAND_i_4,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." wgroup.long 0x144++0x3 line.long 0x00 "GPMC_NAND_DATA_i_4,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, just an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." tree.end tree "Channel_5" width 23. group.long 0x290++0x3 line.long 0x00 "GPMC_BCH_RESULT0_i_5,BCH ECC result (bits 0 to 31)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.long 0x294++0x3 line.long 0x00 "GPMC_BCH_RESULT1_i_5,BCH ECC result (bits 32 to 63)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.long 0x298++0x3 line.long 0x00 "GPMC_BCH_RESULT2_i_5,BCH ECC result (bits 64 to 95)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.long 0x29C++0x3 line.long 0x00 "GPMC_BCH_RESULT3_i_5,BCH ECC result (bits 96 to 127)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.long 0x350++0x3 line.long 0x00 "GPMC_BCH_RESULT4_i_5,BCH ECC result (bits 128 to 159)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.long 0x354++0x3 line.long 0x00 "GPMC_BCH_RESULT5_i_5,BCH ECC result (bits 160 to 191)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.long 0x358++0x3 line.long 0x00 "GPMC_BCH_RESULT6_i_5,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" group.long 0x150++0x3 line.long 0x00 "GPMC_CONFIG1_i_5,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst - . - ." "WrapNotSupp,WrapSupp" bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access - . - ." "RdSingle,RdMultiple" bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation - . - ." "RdAsync,RdSync" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access - . - ." "WrSingle,WrMultiple" bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation - . - ." "WrAsync,WrSync" bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time - . - . - . - ." "AtStart,OneClkB4,TwoClkB4,NotDefined" textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGE_LENGTH ,Specifies the attached device page (burst) length - . - . - . - ." "4_Words,8_Words,16_Words,3" bitfld.long 0x00 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at IC reset) - . - ." "WNotMonit,Wmonit" bitfld.long 0x00 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses - . - ." "WNotMonit,Wmonit" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time - . - . - . - ." "AtValid,OneDeviceB4,TwoDeviceB4,NotDefined" bitfld.long 0x00 16.--17. " WAITPINSELECT ,Selects the input WAIT pin for this chip-select (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-7) - . - . - . - ." "W0,W1,W2,W3" bitfld.long 0x00 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value is input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) - . - . - . - ." "EightBits,SixteenBits,ThirtyTwoBits,Res" textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type - . - . - . - ." "NORlike,Res1,NANDlike,Res2" bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-CS7) - . - . - . - ." "NonMux,AADMux,Mux,?..." bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIME.." "x1,x2" textline " " bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock - . - . - . - ." "DivBy1,DivBy2,DivBy3,UNKN_MNEMO" group.long 0x154++0x3 line.long 0x00 "GPMC_CONFIG2_i_5,CS signal timing parameter configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,CS i de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " CSEXTRADELAY ,CS i Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x158++0x3 line.long 0x00 "GPMC_CONFIG3_i_5,nADV signal timing parameter configuration" bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,nADV de-assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " ADVWROFFTIME ,nADV de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,nADV de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " ADVEXTRADELAY ,nADV Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x15C++0x3 line.long 0x00 "GPMC_CONFIG4_i_5,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,nWE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " WEEXTRADELAY ,nWE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " OEAADMUX_OFFTIME ,nOE de-assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " OEOFFTIME ,nOE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " OEEXTRADELAY ,nOE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,1" textline " " bitfld.long 0x00 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x160++0x3 line.long 0x00 "GPMC_CONFIG5_i_5,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x164++0x3 line.long 0x00 "GPMC_CONFIG6_i_5,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FC.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type) - . - ." "NoC2CDelay,C2CDelay" bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type) - . - ." "NoC2CDelay,1" bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x168++0x3 line.long 0x00 "GPMC_CONFIG7_i_5,CS address mapping configuration" bitfld.long 0x00 8.--11. " MASKADDRESS ,CS mask address. 0x1000: Chip-select size of 128 Mbytes 0x1100: Chip-select size of 64 Mbytes 0x1110: Chip-select size of 32 Mbytes 0x1111: Chip-select size of 16 Mbytes Other values must be avoided as they create holes in t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " CSVALID ,CS enable - . - ." "CSDisabled,CSEnabled" bitfld.long 0x00 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16M bytes minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x214++0x3 line.long 0x00 "GPMC_ECCj_RESULT_5,ECC result register" bitfld.long 0x00 27. " P2048o ,Odd row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024o ,Odd row parity bit 1024" "0,1" bitfld.long 0x00 25. " P512o ,Odd row parity bit 512" "0,1" textline " " bitfld.long 0x00 24. " P256o ,Odd row parity bit 256" "0,1" bitfld.long 0x00 23. " P128o ,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. " P64o ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x00 21. " P32o ,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. " P16o ,Odd row parity bit 16" "0,1" bitfld.long 0x00 19. " P8o ,Odd row parity bit 8" "0,1" textline " " bitfld.long 0x00 18. " P4o ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2o ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1o ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048e ,Even row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024e ,Even row parity bit 1024" "0,1" bitfld.long 0x00 9. " P512e ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x00 8. " P256e ,Even row parity bit 256" "0,1" bitfld.long 0x00 7. " P128e ,Even row parity bit 128" "0,1" bitfld.long 0x00 6. " P64e ,Even row parity bit 64" "0,1" textline " " bitfld.long 0x00 5. " P32e ,Even row parity bit 32" "0,1" bitfld.long 0x00 4. " P16e ,Even row parity bit 16" "0,1" bitfld.long 0x00 3. " P8e ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x00 2. " P4e ,Even column parity bit 4" "0,1" bitfld.long 0x00 1. " P2e ,Even column parity bit 2" "0,1" bitfld.long 0x00 0. " P1e ,Even column parity bit 1" "0,1" wgroup.long 0x170++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_i_5,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." wgroup.long 0x16C++0x3 line.long 0x00 "GPMC_NAND_COMMAND_i_5,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." wgroup.long 0x174++0x3 line.long 0x00 "GPMC_NAND_DATA_i_5,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, just an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." tree.end tree "Channel_6" width 23. group.long 0x2A0++0x3 line.long 0x00 "GPMC_BCH_RESULT0_i_6,BCH ECC result (bits 0 to 31)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.long 0x2A4++0x3 line.long 0x00 "GPMC_BCH_RESULT1_i_6,BCH ECC result (bits 32 to 63)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.long 0x2A8++0x3 line.long 0x00 "GPMC_BCH_RESULT2_i_6,BCH ECC result (bits 64 to 95)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.long 0x2AC++0x3 line.long 0x00 "GPMC_BCH_RESULT3_i_6,BCH ECC result (bits 96 to 127)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.long 0x360++0x3 line.long 0x00 "GPMC_BCH_RESULT4_i_6,BCH ECC result (bits 128 to 159)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.long 0x364++0x3 line.long 0x00 "GPMC_BCH_RESULT5_i_6,BCH ECC result (bits 160 to 191)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.long 0x368++0x3 line.long 0x00 "GPMC_BCH_RESULT6_i_6,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" group.long 0x180++0x3 line.long 0x00 "GPMC_CONFIG1_i_6,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst - . - ." "WrapNotSupp,WrapSupp" bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access - . - ." "RdSingle,RdMultiple" bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation - . - ." "RdAsync,RdSync" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access - . - ." "WrSingle,WrMultiple" bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation - . - ." "WrAsync,WrSync" bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time - . - . - . - ." "AtStart,OneClkB4,TwoClkB4,NotDefined" textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGE_LENGTH ,Specifies the attached device page (burst) length - . - . - . - ." "4_Words,8_Words,16_Words,3" bitfld.long 0x00 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at IC reset) - . - ." "WNotMonit,Wmonit" bitfld.long 0x00 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses - . - ." "WNotMonit,Wmonit" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time - . - . - . - ." "AtValid,OneDeviceB4,TwoDeviceB4,NotDefined" bitfld.long 0x00 16.--17. " WAITPINSELECT ,Selects the input WAIT pin for this chip-select (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-7) - . - . - . - ." "W0,W1,W2,W3" bitfld.long 0x00 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value is input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) - . - . - . - ." "EightBits,SixteenBits,ThirtyTwoBits,Res" textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type - . - . - . - ." "NORlike,Res1,NANDlike,Res2" bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-CS7) - . - . - . - ." "NonMux,AADMux,Mux,?..." bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIME.." "x1,x2" textline " " bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock - . - . - . - ." "DivBy1,DivBy2,DivBy3,UNKN_MNEMO" group.long 0x184++0x3 line.long 0x00 "GPMC_CONFIG2_i_6,CS signal timing parameter configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,CS i de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " CSEXTRADELAY ,CS i Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x188++0x3 line.long 0x00 "GPMC_CONFIG3_i_6,nADV signal timing parameter configuration" bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,nADV de-assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " ADVWROFFTIME ,nADV de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,nADV de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " ADVEXTRADELAY ,nADV Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18C++0x3 line.long 0x00 "GPMC_CONFIG4_i_6,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,nWE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " WEEXTRADELAY ,nWE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " OEAADMUX_OFFTIME ,nOE de-assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " OEOFFTIME ,nOE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " OEEXTRADELAY ,nOE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,1" textline " " bitfld.long 0x00 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x190++0x3 line.long 0x00 "GPMC_CONFIG5_i_6,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x194++0x3 line.long 0x00 "GPMC_CONFIG6_i_6,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FC.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type) - . - ." "NoC2CDelay,C2CDelay" bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type) - . - ." "NoC2CDelay,1" bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x198++0x3 line.long 0x00 "GPMC_CONFIG7_i_6,CS address mapping configuration" bitfld.long 0x00 8.--11. " MASKADDRESS ,CS mask address. 0x1000: Chip-select size of 128 Mbytes 0x1100: Chip-select size of 64 Mbytes 0x1110: Chip-select size of 32 Mbytes 0x1111: Chip-select size of 16 Mbytes Other values must be avoided as they create holes in t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " CSVALID ,CS enable - . - ." "CSDisabled,CSEnabled" bitfld.long 0x00 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16M bytes minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x218++0x3 line.long 0x00 "GPMC_ECCj_RESULT_6,ECC result register" bitfld.long 0x00 27. " P2048o ,Odd row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024o ,Odd row parity bit 1024" "0,1" bitfld.long 0x00 25. " P512o ,Odd row parity bit 512" "0,1" textline " " bitfld.long 0x00 24. " P256o ,Odd row parity bit 256" "0,1" bitfld.long 0x00 23. " P128o ,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. " P64o ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x00 21. " P32o ,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. " P16o ,Odd row parity bit 16" "0,1" bitfld.long 0x00 19. " P8o ,Odd row parity bit 8" "0,1" textline " " bitfld.long 0x00 18. " P4o ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2o ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1o ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048e ,Even row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024e ,Even row parity bit 1024" "0,1" bitfld.long 0x00 9. " P512e ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x00 8. " P256e ,Even row parity bit 256" "0,1" bitfld.long 0x00 7. " P128e ,Even row parity bit 128" "0,1" bitfld.long 0x00 6. " P64e ,Even row parity bit 64" "0,1" textline " " bitfld.long 0x00 5. " P32e ,Even row parity bit 32" "0,1" bitfld.long 0x00 4. " P16e ,Even row parity bit 16" "0,1" bitfld.long 0x00 3. " P8e ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x00 2. " P4e ,Even column parity bit 4" "0,1" bitfld.long 0x00 1. " P2e ,Even column parity bit 2" "0,1" bitfld.long 0x00 0. " P1e ,Even column parity bit 1" "0,1" wgroup.long 0x1A0++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_i_6,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." wgroup.long 0x19C++0x3 line.long 0x00 "GPMC_NAND_COMMAND_i_6,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." wgroup.long 0x1A4++0x3 line.long 0x00 "GPMC_NAND_DATA_i_6,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, just an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." tree.end tree "Channel_7" width 23. group.long 0x2B0++0x3 line.long 0x00 "GPMC_BCH_RESULT0_i_7,BCH ECC result (bits 0 to 31)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.long 0x2B4++0x3 line.long 0x00 "GPMC_BCH_RESULT1_i_7,BCH ECC result (bits 32 to 63)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.long 0x2B8++0x3 line.long 0x00 "GPMC_BCH_RESULT2_i_7,BCH ECC result (bits 64 to 95)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.long 0x2BC++0x3 line.long 0x00 "GPMC_BCH_RESULT3_i_7,BCH ECC result (bits 96 to 127)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.long 0x370++0x3 line.long 0x00 "GPMC_BCH_RESULT4_i_7,BCH ECC result (bits 128 to 159)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.long 0x374++0x3 line.long 0x00 "GPMC_BCH_RESULT5_i_7,BCH ECC result (bits 160 to 191)" hexmask.long 0x00 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.long 0x378++0x3 line.long 0x00 "GPMC_BCH_RESULT6_i_7,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" group.long 0x1B0++0x3 line.long 0x00 "GPMC_CONFIG1_i_7,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst - . - ." "WrapNotSupp,WrapSupp" bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access - . - ." "RdSingle,RdMultiple" bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation - . - ." "RdAsync,RdSync" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access - . - ." "WrSingle,WrMultiple" bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation - . - ." "WrAsync,WrSync" bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time - . - . - . - ." "AtStart,OneClkB4,TwoClkB4,NotDefined" textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGE_LENGTH ,Specifies the attached device page (burst) length - . - . - . - ." "4_Words,8_Words,16_Words,3" bitfld.long 0x00 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at IC reset) - . - ." "WNotMonit,Wmonit" bitfld.long 0x00 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses - . - ." "WNotMonit,Wmonit" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time - . - . - . - ." "AtValid,OneDeviceB4,TwoDeviceB4,NotDefined" bitfld.long 0x00 16.--17. " WAITPINSELECT ,Selects the input WAIT pin for this chip-select (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-7) - . - . - . - ." "W0,W1,W2,W3" bitfld.long 0x00 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value is input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) - . - . - . - ." "EightBits,SixteenBits,ThirtyTwoBits,Res" textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type - . - . - . - ." "NORlike,Res1,NANDlike,Res2" bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value is input pin sampled at IC reset for CS0 and 0 for CS1-CS7) - . - . - . - ." "NonMux,AADMux,Mux,?..." bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIME.." "x1,x2" textline " " bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock - . - . - . - ." "DivBy1,DivBy2,DivBy3,UNKN_MNEMO" group.long 0x1B4++0x3 line.long 0x00 "GPMC_CONFIG2_i_7,CS signal timing parameter configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,CS i de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " CSEXTRADELAY ,CS i Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1B8++0x3 line.long 0x00 "GPMC_CONFIG3_i_7,nADV signal timing parameter configuration" bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,nADV de-assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " ADVWROFFTIME ,nADV de-assertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,nADV de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " ADVEXTRADELAY ,nADV Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-mux protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1BC++0x3 line.long 0x00 "GPMC_CONFIG4_i_7,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,nWE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " WEEXTRADELAY ,nWE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,0x01" bitfld.long 0x00 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " OEAADMUX_OFFTIME ,nOE de-assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " OEOFFTIME ,nOE de-assertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " OEEXTRADELAY ,nOE Add Extra Half GPMC_FCLK cycle - . - ." "NotDelayed,1" textline " " bitfld.long 0x00 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C0++0x3 line.long 0x00 "GPMC_CONFIG5_i_7,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C4++0x3 line.long 0x00 "GPMC_CONFIG6_i_7,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FC.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type) - . - ." "NoC2CDelay,C2CDelay" bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type) - . - ." "NoC2CDelay,1" bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C8++0x3 line.long 0x00 "GPMC_CONFIG7_i_7,CS address mapping configuration" bitfld.long 0x00 8.--11. " MASKADDRESS ,CS mask address. 0x1000: Chip-select size of 128 Mbytes 0x1100: Chip-select size of 64 Mbytes 0x1110: Chip-select size of 32 Mbytes 0x1111: Chip-select size of 16 Mbytes Other values must be avoided as they create holes in t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " CSVALID ,CS enable - . - ." "CSDisabled,CSEnabled" bitfld.long 0x00 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16M bytes minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x21C++0x3 line.long 0x00 "GPMC_ECCj_RESULT_7,ECC result register" bitfld.long 0x00 27. " P2048o ,Odd row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024o ,Odd row parity bit 1024" "0,1" bitfld.long 0x00 25. " P512o ,Odd row parity bit 512" "0,1" textline " " bitfld.long 0x00 24. " P256o ,Odd row parity bit 256" "0,1" bitfld.long 0x00 23. " P128o ,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. " P64o ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x00 21. " P32o ,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. " P16o ,Odd row parity bit 16" "0,1" bitfld.long 0x00 19. " P8o ,Odd row parity bit 8" "0,1" textline " " bitfld.long 0x00 18. " P4o ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2o ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1o ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048e ,Even row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024e ,Even row parity bit 1024" "0,1" bitfld.long 0x00 9. " P512e ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x00 8. " P256e ,Even row parity bit 256" "0,1" bitfld.long 0x00 7. " P128e ,Even row parity bit 128" "0,1" bitfld.long 0x00 6. " P64e ,Even row parity bit 64" "0,1" textline " " bitfld.long 0x00 5. " P32e ,Even row parity bit 32" "0,1" bitfld.long 0x00 4. " P16e ,Even row parity bit 16" "0,1" bitfld.long 0x00 3. " P8e ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x00 2. " P4e ,Even column parity bit 4" "0,1" bitfld.long 0x00 1. " P2e ,Even column parity bit 2" "0,1" bitfld.long 0x00 0. " P1e ,Even column parity bit 1" "0,1" wgroup.long 0x1D0++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_i_7,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." wgroup.long 0x1CC++0x3 line.long 0x00 "GPMC_NAND_COMMAND_i_7,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, just an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." wgroup.long 0x1D4++0x3 line.long 0x00 "GPMC_NAND_DATA_i_7,This register is not a true register, just an address location." hexmask.long 0x00 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, just an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." rgroup.long 0x220++0x3 line.long 0x00 "GPMC_ECCj_RESULT_8,ECC result register" bitfld.long 0x00 27. " P2048o ,Odd row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024o ,Odd row parity bit 1024" "0,1" bitfld.long 0x00 25. " P512o ,Odd row parity bit 512" "0,1" textline " " bitfld.long 0x00 24. " P256o ,Odd row parity bit 256" "0,1" bitfld.long 0x00 23. " P128o ,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. " P64o ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x00 21. " P32o ,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. " P16o ,Odd row parity bit 16" "0,1" bitfld.long 0x00 19. " P8o ,Odd row parity bit 8" "0,1" textline " " bitfld.long 0x00 18. " P4o ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2o ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1o ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048e ,Even row parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024e ,Even row parity bit 1024" "0,1" bitfld.long 0x00 9. " P512e ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x00 8. " P256e ,Even row parity bit 256" "0,1" bitfld.long 0x00 7. " P128e ,Even row parity bit 128" "0,1" bitfld.long 0x00 6. " P64e ,Even row parity bit 64" "0,1" textline " " bitfld.long 0x00 5. " P32e ,Even row parity bit 32" "0,1" bitfld.long 0x00 4. " P16e ,Even row parity bit 16" "0,1" bitfld.long 0x00 3. " P8e ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x00 2. " P4e ,Even column parity bit 4" "0,1" bitfld.long 0x00 1. " P2e ,Even column parity bit 2" "0,1" bitfld.long 0x00 0. " P1e ,Even column parity bit 1" "0,1" tree.end textline "" width 23. rgroup.long 0x0++0x3 line.long 0x00 "GPMC_REVISION,This register contains the IP revision code." hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "GPMC_SYSCONFIG,This register controls the various parameters of the Interconnect." bitfld.long 0x00 3.--4. " SIDLEMODE ,0x0: Force-idle. An idle request is acknowledged unconditionally - . - . - ." "0,1,2,Do_not_use" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 triggers a module reset. This bit is automatically reset by hardware. During reads, it always returns 0. - . - ." "Normal,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal Interface clock gating strategy - . - ." "FreeRun,AutoRun" rgroup.long 0x14++0x3 line.long 0x00 "GPMC_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "RstOnGoing,RstDone" group.long 0x18++0x3 line.long 0x00 "GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x00 10. " WAIT2EDGEDETECTION_STATUS ,Status of the Wait2 Edge Detection interrupt - . - . - . - ." "0,1" bitfld.long 0x00 9. " WAIT1EDGEDETECTION_STATUS ,Status of the Wait1 Edge Detection interrupt - . - . - . - ." "0,1" bitfld.long 0x00 8. " WAIT0EDGEDETECTION_STATUS ,Status of the Wait0 Edge Detection interrupt - . - . - . - ." "0,1" textline " " bitfld.long 0x00 1. " TERMINALCOUNTSTATUS ,Status of the TerminalCountEvent interrupt - . - . - . - ." "TCStat0_R_/_TCStat0_W,TCStat1_R_/_TCStat1_W" bitfld.long 0x00 0. " FIFOEVENTSTATUS ,Status of the FIFOEvent interrupt - . - . - . - ." "FIFOStat0_R_/_FIFOStat0_W,FIFOStat1_R_/_FIFOStat1_W" group.long 0x1C++0x3 line.long 0x00 "GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x00 10. " WAIT2EDGEDETECTION_ENABLE ,Enables the Wait2 Edge Detection interrupt - . - ." "0,1" bitfld.long 0x00 9. " WAIT1EDGEDETECTION_ENABLE ,Enables the Wait1 Edge Detection interrupt - . - ." "0,1" bitfld.long 0x00 8. " WAIT0EDGEDETECTION_ENABLE ,Enables the Wait0 Edge Detection interrupt - . - ." "0,1" textline " " bitfld.long 0x00 1. " TERMINALCOUNTEVENT_ENABLE ,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode - . - ." "0,1" bitfld.long 0x00 0. " FIFOEVENTENABLE ,Enables the FIFOEvent interrupt - . - ." "FIFOMasked,FIFOEnabled" group.long 0x40++0x3 line.long 0x00 "GPMC_TIMEOUT_CONTROL,The register allows the user to set the start value of the timeout counter" hexmask.long.word 0x00 4.--12. 1. " TIMEOUTSTARTVALUE ,Start value of the time-out counter 0x000: Zero GPMC_FCLK cycle 0x001: One GPMC_FCLK cycle ... 0x1FF: 511 GPMC_FCLK cycles" bitfld.long 0x00 0. " TIMEOUTENABLE ,Enable bit of the TimeOut feature - . - ." "TODisabled,TOEnabled" rgroup.long 0x44++0x3 line.long 0x00 "GPMC_ERR_ADDRESS,The register stores the address of the illegal access when an error occurs" hexmask.long 0x00 0.--30. 1. " ILLEGALADD ,Address of illegal access A30: 0 for memory region, 1 for GPMC register region A29-A0: 1 GBytes max" group.long 0x48++0x3 line.long 0x00 "GPMC_ERR_TYPE,The register stores the type of error when an error occurs" bitfld.long 0x00 8.--10. " ILLEGALMCMD ,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " ERRORNOTSUPPADD ,Not supported Address error - . - ." "NoErr,Err" bitfld.long 0x00 3. " ERRORNOTSUPPMCMD ,Not supported Command error - . - ." "NoErr,Err" textline " " bitfld.long 0x00 2. " ERRORTIMEOUT ,Time-out error - . - ." "NoErr,Err" bitfld.long 0x00 0. " ERRORVALID ,Error validity status - Must be explicitly cleared with a write 1 transaction - . - ." "NotValid,ErrDetect" group.long 0x50++0x3 line.long 0x00 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC" bitfld.long 0x00 10. " WAIT2PINPOLARITY ,Selects the polarity of input pin WAIT2 - . - ." "W2ActiveL,W2ActiveH" bitfld.long 0x00 9. " WAIT1PINPOLARITY ,Selects the polarity of input pin WAIT1 - . - ." "W1ActiveL,W1ActiveH" bitfld.long 0x00 8. " WAIT0PINPOLARITY ,Selects the polarity of input pin WAIT0 - . - ." "W0ActiveL,W0ActiveH" textline " " bitfld.long 0x00 4. " WRITEPROTECT ,Controls the WP output pin level - . - ." "WPLow,WPHigh" bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support - . - ." "NoLimited,Limited" bitfld.long 0x00 0. " NANDFORCEPOSTEDWRITE ,Enables the Force Posted Write feature to NAND Cmd/Add/Data location - . - ." "NoForcePWr,ForcePWr" rgroup.long 0x54++0x3 line.long 0x00 "GPMC_STATUS,The status register provides global status bits of the GPMC" bitfld.long 0x00 10. " WAIT2STATUS ,Is a copy of input pin WAIT2. (Reset value is WAIT2 input pin sampled at IC reset) - . - ." "W2ActiveL,W2ActiveH" bitfld.long 0x00 9. " WAIT1STATUS ,Is a copy of input pin WAIT1. (Reset value is WAIT1 input pin sampled at IC reset) - . - ." "W1ActiveL,W1ActiveH" bitfld.long 0x00 8. " WAIT0STATUS ,Is a copy of input pin WAIT0. (Reset value is WAIT0 input pin sampled at IC reset) - . - ." "W0ActiveL,W0ActiveH" textline " " bitfld.long 0x00 0. " EMPTYWRITEBUFFERSTATUS ,Stores the empty status of the write buffer - . - ." "b0,b1" group.long 0x1E0++0x3 line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1" bitfld.long 0x00 28.--30. " CYCLEOPTIMIZATION ,Define the number of GPMC_FCLK cycles to be subtracted from RDCYCLETIME, WRCYCLETIME, ACCESSTIME, CSRDOFFTIME, CSWROFFTIME, ADVRDOFFTIME, ADVWROFFTIME, OEOFFTIME, WEOFFTIME 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0.." "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " ENABLEOPTIMIZEDACCESS ,Enables access cycle optimization - . - ." "OptDisabled,OptEnabled" bitfld.long 0x00 24.--26. " ENGINECSSELECTOR ,Selects the CS where Prefetch Postwrite engine is active 0x0: CS0 0x1: CS1 0x2: CS2 0x3: CS3 0x4: CS4 0x5: CS5 0x6: CS6 0x7: CS7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 23. " PFPWENROUNDROBIN ,Enables the PFPW RoundRobin arbitration - . - ." "RRDisabled,RREnabled" bitfld.long 0x00 16.--19. " PFPWWEIGHTEDPRIO ,When an arbitration occurs between a DMA and a PFPW engine access, the DMA is always serviced. If the PFPWEnRoundRobin is enabled, 0x0: the next access is granted to the PFPW engine, 0x1: the two next accesses ar.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--14. 1. " FIFOTHRESHOLD ,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request 0x00: 0 byte 0x01: 1 byte ... 0x40: 64 bytes" textline " " bitfld.long 0x00 7. " ENABLEENGINE ,Enables the Prefetch Postwite engine - . - ." "PPDisabled,PPEnabled" bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Select which wait pin edge detector should start the engine in synchronized mode - . - . - . - ." "W0,W1,W2,W3" bitfld.long 0x00 3. " SYNCHROMODE ,Selects when the engine starts the access to CS - . - ." "AtStart,AtStartAndWait" textline " " bitfld.long 0x00 2. " DMAMODE ,Selects interrupt synchronization or DMA request synchronization - . - ." "InterruptSync,DMAReqSync" bitfld.long 0x00 0. " ACCESSMODE ,Selects prefetch read or write-posting accesses - . - ." "PrefetchRead,WritePosting" group.long 0x1E4++0x3 line.long 0x00 "GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2" hexmask.long.word 0x00 0.--13. 1. " TRANSFERCOUNT ,Selects the number of bytes to be read or written by the engine to the selected CS 0x0000: 0 byte 0x0001: 1 byte ... 0x2000: 8 Kbytes" group.long 0x1EC++0x3 line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch engine control" bitfld.long 0x00 0. " STARTENGINE ,Resets the FIFO pointer and starts the engine - . - Write 0x0 stops the engine . - . - . - Write 0x1 resets the FIFO pointer to 0x0 in prefetch mode and 0x40 in postwrite mode and starts the engine . - ." "Stop,Start" rgroup.long 0x1F0++0x3 line.long 0x00 "GPMC_PREFETCH_STATUS,Prefetch engine status" hexmask.long.byte 0x00 24.--30. 1. " FIFOPOINTER ,Number of available bytes to be read or number of free empty byte places to be written 0x00: 0 byte available to be read or 0 free empty place to be written ... 0x40: 64 bytes available to be read or 64 empty places to be wr.." bitfld.long 0x00 16. " FIFOTHRESHOLDSTATUS ,Set when FIFOPointer exceeds FIFOThreshold value - . - ." "SmallerThanThres,GreaterThanThres" hexmask.long.word 0x00 0.--13. 1. " COUNTVALUE ,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value 0x0000: 0 byte remaining to be read or to be written 0x0001: 1 byte remaining to be read or to be written ....." group.long 0x1F4++0x3 line.long 0x00 "GPMC_ECC_CONFIG,ECC configuration" bitfld.long 0x00 16. " ECCALGORITHM ,ECC algorithm used - . - ." "0,1" bitfld.long 0x00 12.--13. " ECCBCHTSEL ,Error correction capability used for BCH - . - . - . - ." "0,1,2,3" bitfld.long 0x00 8.--11. " ECCWRAPMODE ,Spare area organization definition for the BCH algorithm. See the BCH syndrome/parity calculator module functional specification for more details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " ECC16B ,Selects an ECC calculated on 16 columns - . - ." "EightCol,SixteenCol" bitfld.long 0x00 4.--6. " ECCTOPSECTOR ,Number of sectors to process with the BCH algorithm 0x0: 1 sector (512kB page) 0x1: 2 sectors ... 0x3: 4 sectors (2kB page) ... 0x7: 8 sectors (4kB page)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " ECCCS ,Selects the CS where ECC is computed - . - . - . - . Other: Reserved. - ." "CS0,CS1,CS2,CS3,4,5,6,7" textline " " bitfld.long 0x00 0. " ECCENABLE ,Enables the ECC feature - . - ." "ECCDisabled,ECCEnabled" group.long 0x1F8++0x3 line.long 0x00 "GPMC_ECC_CONTROL,ECC control" bitfld.long 0x00 8. " ECCCLEAR ,Clear all ECC result registers Reads returns 0 Write 0x1 to this field clear all ECC result registers Write 0x0 is ignored" "0,1" bitfld.long 0x00 0.--3. " ECCPOINTER ,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored); Other .." "NoEffect1,ECCRes1,ECCRes2,ECCRes3,ECCRes4,ECCRes5,ECCRes6,ECCRes7,ECCRes8,ECCRes9,10,11,12,13,14,15" group.long 0x1FC++0x3 line.long 0x00 "GPMC_ECC_SIZE_CONFIG,ECC size" hexmask.long.byte 0x00 22.--29. 1. " ECCSIZE1 ,Defines Hamming code ECC size 1 in bytes 0x00: 2 Bytes 0x01: 4 Bytes 0x02: 6 Bytes 0x03: 8 Bytes ... 0xFF: 512 Bytes For BCH code ECC, the size 1 is programmed directly with the number of nibbles (see , )." hexmask.long.byte 0x00 12.--19. 1. " ECCSIZE0 ,Defines Hamming code ECC size 0 in bytes 0x00: 2 Bytes 0x01: 4 Bytes 0x02: 6 Bytes 0x03: 8 Bytes ... 0xFF: 512 Bytes For BCH code ECC, the size 0 is programmed directly with the number of nibbles (see , ).." bitfld.long 0x00 8. " ECC9RESULTSIZE ,Selects ECC size for ECC 9 result register - . - ." "Size0Sel,Size1Sel" textline " " bitfld.long 0x00 7. " ECC8RESULTSIZE ,Selects ECC size for ECC 8 result register - . - ." "Size0Sel,Size1Sel" bitfld.long 0x00 6. " ECC7RESULTSIZE ,Selects ECC size for ECC 7 result register - . - ." "Size0Sel,Size1Sel" bitfld.long 0x00 5. " ECC6RESULTSIZE ,Selects ECC size for ECC 6 result register - . - ." "Size0Sel,Size1Sel" textline " " bitfld.long 0x00 4. " ECC5RESULTSIZE ,Selects ECC size for ECC 5 result register - . - ." "Size0Sel,Size1Sel" bitfld.long 0x00 3. " ECC4RESULTSIZE ,Selects ECC size for ECC 4 result register - . - ." "Size0Sel,Size1Sel" bitfld.long 0x00 2. " ECC3RESULTSIZE ,Selects ECC size for ECC 3 result register - . - ." "Size0Sel,Size1Sel" textline " " bitfld.long 0x00 1. " ECC2RESULTSIZE ,Selects ECC size for ECC 2 result register - . - ." "Size0Sel,Size1Sel" bitfld.long 0x00 0. " ECC1RESULTSIZE ,Selects ECC size for ECC 1 result register - . - ." "Size0Sel,Size1Sel" group.long 0x2D0++0x3 line.long 0x00 "GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface." hexmask.long.word 0x00 0.--15. 1. " BCH_DATA ,Data to be included in the BCH calculation. Only bits 0 to 7 are taken into account if the calculator is configured to use 8 bits data (GPMC_ECC_CONFIG[7] ECC16B = 0)" tree.end tree.end tree.open "Error_Location_Module" tree "ELM" base ad:0x48078000 tree "Channel_0" width 29. rgroup.long 0x880++0x3 line.long 0x00 "ELM_ERROR_LOCATION_0_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x8A8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_10_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x8AC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_11_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x8B0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_12_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x8B4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_13_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x8B8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_14_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x8BC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_15_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x884++0x3 line.long 0x00 "ELM_ERROR_LOCATION_1_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x888++0x3 line.long 0x00 "ELM_ERROR_LOCATION_2_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x88C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_3_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x890++0x3 line.long 0x00 "ELM_ERROR_LOCATION_4_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x894++0x3 line.long 0x00 "ELM_ERROR_LOCATION_5_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x898++0x3 line.long 0x00 "ELM_ERROR_LOCATION_6_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x89C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_7_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x8A0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_8_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x8A4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_9_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x800++0x3 line.long 0x00 "ELM_LOCATION_STATUS_i_0,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error-location process exit status0x0: ECC error-location process failed. Number of errors and error locations are invalid.0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x400++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_0,Input syndrome polynomial bits 0 to 31." hexmask.long 0x00 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.long 0x404++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_0,Input syndrome polynomial bits 32 to 63." hexmask.long 0x00 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.long 0x408++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_0,Input syndrome polynomial bits 64 to 95." hexmask.long 0x00 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.long 0x40C++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_0,Input syndrome polynomial bits 96 to 127" hexmask.long 0x00 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.long 0x410++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_0,Input syndrome polynomial bits 128 to 159." hexmask.long 0x00 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.long 0x414++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_0,Input syndrome polynomial bits 160 to 191." hexmask.long 0x00 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.long 0x418++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_0,Input syndrome polynomial bits 192 to 207." bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit0x0: This syndrome polynomial should not be processed.0x1: This syndrome polynomial must be processed." "0,1" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" tree.end tree "Channel_1" width 29. rgroup.long 0x980++0x3 line.long 0x00 "ELM_ERROR_LOCATION_0_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x9A8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_10_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x9AC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_11_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x9B0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_12_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x9B4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_13_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x9B8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_14_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x9BC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_15_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x984++0x3 line.long 0x00 "ELM_ERROR_LOCATION_1_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x988++0x3 line.long 0x00 "ELM_ERROR_LOCATION_2_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x98C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_3_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x990++0x3 line.long 0x00 "ELM_ERROR_LOCATION_4_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x994++0x3 line.long 0x00 "ELM_ERROR_LOCATION_5_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x998++0x3 line.long 0x00 "ELM_ERROR_LOCATION_6_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x99C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_7_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x9A0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_8_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x9A4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_9_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0x900++0x3 line.long 0x00 "ELM_LOCATION_STATUS_i_1,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error-location process exit status0x0: ECC error-location process failed. Number of errors and error locations are invalid.0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x440++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_1,Input syndrome polynomial bits 0 to 31." hexmask.long 0x00 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.long 0x444++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_1,Input syndrome polynomial bits 32 to 63." hexmask.long 0x00 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.long 0x448++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_1,Input syndrome polynomial bits 64 to 95." hexmask.long 0x00 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.long 0x44C++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_1,Input syndrome polynomial bits 96 to 127" hexmask.long 0x00 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.long 0x450++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_1,Input syndrome polynomial bits 128 to 159." hexmask.long 0x00 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.long 0x454++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_1,Input syndrome polynomial bits 160 to 191." hexmask.long 0x00 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.long 0x458++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_1,Input syndrome polynomial bits 192 to 207." bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit0x0: This syndrome polynomial should not be processed.0x1: This syndrome polynomial must be processed." "0,1" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" tree.end tree "Channel_2" width 29. rgroup.long 0xA80++0x3 line.long 0x00 "ELM_ERROR_LOCATION_0_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xAA8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_10_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xAAC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_11_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xAB0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_12_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xAB4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_13_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xAB8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_14_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xABC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_15_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xA84++0x3 line.long 0x00 "ELM_ERROR_LOCATION_1_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xA88++0x3 line.long 0x00 "ELM_ERROR_LOCATION_2_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xA8C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_3_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xA90++0x3 line.long 0x00 "ELM_ERROR_LOCATION_4_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xA94++0x3 line.long 0x00 "ELM_ERROR_LOCATION_5_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xA98++0x3 line.long 0x00 "ELM_ERROR_LOCATION_6_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xA9C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_7_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xAA0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_8_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xAA4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_9_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xA00++0x3 line.long 0x00 "ELM_LOCATION_STATUS_i_2,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error-location process exit status0x0: ECC error-location process failed. Number of errors and error locations are invalid.0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x480++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_2,Input syndrome polynomial bits 0 to 31." hexmask.long 0x00 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.long 0x484++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_2,Input syndrome polynomial bits 32 to 63." hexmask.long 0x00 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.long 0x488++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_2,Input syndrome polynomial bits 64 to 95." hexmask.long 0x00 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.long 0x48C++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_2,Input syndrome polynomial bits 96 to 127" hexmask.long 0x00 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.long 0x490++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_2,Input syndrome polynomial bits 128 to 159." hexmask.long 0x00 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.long 0x494++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_2,Input syndrome polynomial bits 160 to 191." hexmask.long 0x00 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.long 0x498++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_2,Input syndrome polynomial bits 192 to 207." bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit0x0: This syndrome polynomial should not be processed.0x1: This syndrome polynomial must be processed." "0,1" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" tree.end tree "Channel_3" width 29. rgroup.long 0xB80++0x3 line.long 0x00 "ELM_ERROR_LOCATION_0_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xBA8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_10_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xBAC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_11_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xBB0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_12_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xBB4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_13_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xBB8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_14_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xBBC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_15_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xB84++0x3 line.long 0x00 "ELM_ERROR_LOCATION_1_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xB88++0x3 line.long 0x00 "ELM_ERROR_LOCATION_2_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xB8C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_3_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xB90++0x3 line.long 0x00 "ELM_ERROR_LOCATION_4_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xB94++0x3 line.long 0x00 "ELM_ERROR_LOCATION_5_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xB98++0x3 line.long 0x00 "ELM_ERROR_LOCATION_6_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xB9C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_7_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xBA0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_8_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xBA4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_9_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xB00++0x3 line.long 0x00 "ELM_LOCATION_STATUS_i_3,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error-location process exit status0x0: ECC error-location process failed. Number of errors and error locations are invalid.0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C0++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_3,Input syndrome polynomial bits 0 to 31." hexmask.long 0x00 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.long 0x4C4++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_3,Input syndrome polynomial bits 32 to 63." hexmask.long 0x00 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.long 0x4C8++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_3,Input syndrome polynomial bits 64 to 95." hexmask.long 0x00 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.long 0x4CC++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_3,Input syndrome polynomial bits 96 to 127" hexmask.long 0x00 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.long 0x4D0++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_3,Input syndrome polynomial bits 128 to 159." hexmask.long 0x00 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.long 0x4D4++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_3,Input syndrome polynomial bits 160 to 191." hexmask.long 0x00 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.long 0x4D8++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_3,Input syndrome polynomial bits 192 to 207." bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit0x0: This syndrome polynomial should not be processed.0x1: This syndrome polynomial must be processed." "0,1" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" tree.end tree "Channel_4" width 29. rgroup.long 0xC80++0x3 line.long 0x00 "ELM_ERROR_LOCATION_0_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xCA8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_10_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xCAC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_11_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xCB0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_12_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xCB4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_13_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xCB8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_14_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xCBC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_15_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xC84++0x3 line.long 0x00 "ELM_ERROR_LOCATION_1_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xC88++0x3 line.long 0x00 "ELM_ERROR_LOCATION_2_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xC8C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_3_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xC90++0x3 line.long 0x00 "ELM_ERROR_LOCATION_4_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xC94++0x3 line.long 0x00 "ELM_ERROR_LOCATION_5_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xC98++0x3 line.long 0x00 "ELM_ERROR_LOCATION_6_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xC9C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_7_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xCA0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_8_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xCA4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_9_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xC00++0x3 line.long 0x00 "ELM_LOCATION_STATUS_i_4,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error-location process exit status0x0: ECC error-location process failed. Number of errors and error locations are invalid.0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x500++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_4,Input syndrome polynomial bits 0 to 31." hexmask.long 0x00 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.long 0x504++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_4,Input syndrome polynomial bits 32 to 63." hexmask.long 0x00 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.long 0x508++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_4,Input syndrome polynomial bits 64 to 95." hexmask.long 0x00 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.long 0x50C++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_4,Input syndrome polynomial bits 96 to 127" hexmask.long 0x00 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.long 0x510++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_4,Input syndrome polynomial bits 128 to 159." hexmask.long 0x00 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.long 0x514++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_4,Input syndrome polynomial bits 160 to 191." hexmask.long 0x00 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.long 0x518++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_4,Input syndrome polynomial bits 192 to 207." bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit0x0: This syndrome polynomial should not be processed.0x1: This syndrome polynomial must be processed." "0,1" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" tree.end tree "Channel_5" width 29. rgroup.long 0xD80++0x3 line.long 0x00 "ELM_ERROR_LOCATION_0_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xDA8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_10_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xDAC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_11_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xDB0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_12_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xDB4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_13_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xDB8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_14_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xDBC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_15_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xD84++0x3 line.long 0x00 "ELM_ERROR_LOCATION_1_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xD88++0x3 line.long 0x00 "ELM_ERROR_LOCATION_2_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xD8C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_3_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xD90++0x3 line.long 0x00 "ELM_ERROR_LOCATION_4_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xD94++0x3 line.long 0x00 "ELM_ERROR_LOCATION_5_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xD98++0x3 line.long 0x00 "ELM_ERROR_LOCATION_6_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xD9C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_7_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xDA0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_8_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xDA4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_9_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xD00++0x3 line.long 0x00 "ELM_LOCATION_STATUS_i_5,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error-location process exit status0x0: ECC error-location process failed. Number of errors and error locations are invalid.0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x540++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_5,Input syndrome polynomial bits 0 to 31." hexmask.long 0x00 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.long 0x544++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_5,Input syndrome polynomial bits 32 to 63." hexmask.long 0x00 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.long 0x548++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_5,Input syndrome polynomial bits 64 to 95." hexmask.long 0x00 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.long 0x54C++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_5,Input syndrome polynomial bits 96 to 127" hexmask.long 0x00 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.long 0x550++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_5,Input syndrome polynomial bits 128 to 159." hexmask.long 0x00 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.long 0x554++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_5,Input syndrome polynomial bits 160 to 191." hexmask.long 0x00 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.long 0x558++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_5,Input syndrome polynomial bits 192 to 207." bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit0x0: This syndrome polynomial should not be processed.0x1: This syndrome polynomial must be processed." "0,1" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" tree.end tree "Channel_6" width 29. rgroup.long 0xE80++0x3 line.long 0x00 "ELM_ERROR_LOCATION_0_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xEA8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_10_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xEAC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_11_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xEB0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_12_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xEB4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_13_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xEB8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_14_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xEBC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_15_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xE84++0x3 line.long 0x00 "ELM_ERROR_LOCATION_1_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xE88++0x3 line.long 0x00 "ELM_ERROR_LOCATION_2_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xE8C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_3_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xE90++0x3 line.long 0x00 "ELM_ERROR_LOCATION_4_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xE94++0x3 line.long 0x00 "ELM_ERROR_LOCATION_5_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xE98++0x3 line.long 0x00 "ELM_ERROR_LOCATION_6_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xE9C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_7_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xEA0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_8_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xEA4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_9_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xE00++0x3 line.long 0x00 "ELM_LOCATION_STATUS_i_6,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error-location process exit status0x0: ECC error-location process failed. Number of errors and error locations are invalid.0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x580++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_6,Input syndrome polynomial bits 0 to 31." hexmask.long 0x00 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.long 0x584++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_6,Input syndrome polynomial bits 32 to 63." hexmask.long 0x00 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.long 0x588++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_6,Input syndrome polynomial bits 64 to 95." hexmask.long 0x00 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.long 0x58C++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_6,Input syndrome polynomial bits 96 to 127" hexmask.long 0x00 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.long 0x590++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_6,Input syndrome polynomial bits 128 to 159." hexmask.long 0x00 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.long 0x594++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_6,Input syndrome polynomial bits 160 to 191." hexmask.long 0x00 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.long 0x598++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_6,Input syndrome polynomial bits 192 to 207." bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit0x0: This syndrome polynomial should not be processed.0x1: This syndrome polynomial must be processed." "0,1" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" tree.end tree "Channel_7" width 29. rgroup.long 0xF80++0x3 line.long 0x00 "ELM_ERROR_LOCATION_0_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xFA8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_10_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xFAC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_11_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xFB0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_12_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xFB4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_13_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xFB8++0x3 line.long 0x00 "ELM_ERROR_LOCATION_14_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xFBC++0x3 line.long 0x00 "ELM_ERROR_LOCATION_15_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xF84++0x3 line.long 0x00 "ELM_ERROR_LOCATION_1_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xF88++0x3 line.long 0x00 "ELM_ERROR_LOCATION_2_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xF8C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_3_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xF90++0x3 line.long 0x00 "ELM_ERROR_LOCATION_4_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xF94++0x3 line.long 0x00 "ELM_ERROR_LOCATION_5_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xF98++0x3 line.long 0x00 "ELM_ERROR_LOCATION_6_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xF9C++0x3 line.long 0x00 "ELM_ERROR_LOCATION_7_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xFA0++0x3 line.long 0x00 "ELM_ERROR_LOCATION_8_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xFA4++0x3 line.long 0x00 "ELM_ERROR_LOCATION_9_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" rgroup.long 0xF00++0x3 line.long 0x00 "ELM_LOCATION_STATUS_i_7,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error-location process exit status0x0: ECC error-location process failed. Number of errors and error locations are invalid.0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C0++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_7,Input syndrome polynomial bits 0 to 31." hexmask.long 0x00 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.long 0x5C4++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_7,Input syndrome polynomial bits 32 to 63." hexmask.long 0x00 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.long 0x5C8++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_7,Input syndrome polynomial bits 64 to 95." hexmask.long 0x00 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.long 0x5CC++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_7,Input syndrome polynomial bits 96 to 127" hexmask.long 0x00 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.long 0x5D0++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_7,Input syndrome polynomial bits 128 to 159." hexmask.long 0x00 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.long 0x5D4++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_7,Input syndrome polynomial bits 160 to 191." hexmask.long 0x00 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.long 0x5D8++0x3 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_7,Input syndrome polynomial bits 192 to 207." bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit0x0: This syndrome polynomial should not be processed.0x1: This syndrome polynomial must be processed." "0,1" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" tree.end textline "" width 21. rgroup.long 0x0++0x3 line.long 0x00 "ELM_REVISION,This register contains the IP revision code.(A write or reset of to this register has no effect.)" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 8. " CLOCKACTIVITYOCP ,OCP Clock activity when module is in IDLE mode (during wake up mode period) - . - ." "OCP_OFF,OCP_ON" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management (IDLE req/ack control) - . - . - . - ." "FORCE_IDLE,NO_IDLE,SMART_IDLE,?..." bitfld.long 0x00 1. " SOFTRESET ,Module software resetThis bit is automatically reset by hardware (During reads, it always returns 0.)It has same effect as the OCP hardware reset. - . - ." "NORMAL,RESET" textline " " bitfld.long 0x00 0. " AUTOGATING ,Internal OCP clock gating strategy(no module visible impact other than saving power) - . - ." "OCP_FREE,OCP_GATING" rgroup.long 0x14++0x3 line.long 0x00 "ELM_SYSSTATUS,Internal reset monitoring (OCP domain)Undefined since:From hardware perspective, the reset state is 0.From software user perspective, when the accessible module is 1." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring (OCP domain)Undefined since:From hardware perspective, the reset state is 0.From software user perspective, when the accessible module is 1. - . - ." "RST_ONGOING,RST_DONE" group.long 0x18++0x3 line.long 0x00 "ELM_IRQSTATUS,Interrupt status. This register doubles as a status register for the error-location processes." bitfld.long 0x00 8. " PAGE_VALID ,Error-location status for a full page, based on the mask definitionRead 0x0: Error locations invalid for all polynomials enabled in the ECC_INTERRUPT_MASK registerRead 0x1: All error locations validWrite 0x0: No effectWrite 0x1: Clea.." "0,1" eventfld.long 0x00 7. " LOC_VALID_7 ,Error-location status for syndrome polynomial 7Read 0x0: No syndrome processed or process in progressRead 0x1: Error-location process completedWrite 0x0: No effectWrite 0x1: Clear interrupt" "0,1" eventfld.long 0x00 6. " LOC_VALID_6 ,Error-location status for syndrome polynomial 6" "0,1" textline " " eventfld.long 0x00 5. " LOC_VALID_5 ,Error-location status for syndrome polynomial 5" "0,1" eventfld.long 0x00 4. " LOC_VALID_4 ,Error-location status for syndrome polynomial 4" "0,1" eventfld.long 0x00 3. " LOC_VALID_3 ,Error-location status for syndrome polynomial 3" "0,1" textline " " eventfld.long 0x00 2. " LOC_VALID_2 ,Error-location status for syndrome polynomial 2" "0,1" eventfld.long 0x00 1. " LOC_VALID_1 ,Error-location status for syndrome polynomial 1" "0,1" eventfld.long 0x00 0. " LOC_VALID_0 ,Error-location status for syndrome polynomial 0" "0,1" group.long 0x1C++0x3 line.long 0x00 "ELM_IRQENABLE,Interrupt enable" bitfld.long 0x00 8. " PAGE_MASK ,Page interrupt mask bit0: Disable interrupt1: Enable interrupt" "0,1" bitfld.long 0x00 7. " LOCATION_MASK_7 ,Error-location interrupt mask bit for syndrome polynomial 7" "0,1" bitfld.long 0x00 6. " LOCATION_MASK_6 ,Error-location interrupt mask bit for syndrome polynomial 6" "0,1" textline " " bitfld.long 0x00 5. " LOCATION_MASK_5 ,Error-location interrupt mask bit for syndrome polynomial 5" "0,1" bitfld.long 0x00 4. " LOCATION_MASK_4 ,Error-location interrupt mask bit for syndrome polynomial 4" "0,1" bitfld.long 0x00 3. " LOCATION_MASK_3 ,Error-location interrupt mask bit for syndrome polynomial 3" "0,1" textline " " bitfld.long 0x00 2. " LOCATION_MASK_2 ,Error-location interrupt mask bit for syndrome polynomial 2" "0,1" bitfld.long 0x00 1. " LOCATION_MASK_1 ,Error-location interrupt mask bit for syndrome polynomial 1" "0,1" bitfld.long 0x00 0. " LOCATION_MASK_0 ,Error-location interrupt mask bit for syndrome polynomial 00: Disable interrupt1: Enable interrupt" "0,1" group.long 0x20++0x3 line.long 0x00 "ELM_LOCATION_CONFIG,ECC algorithm parameters" hexmask.long.word 0x00 16.--26. 1. " ECC_SIZE ,Maximum size of the buffers for which the error-location engine is used, in number of nibbles (4-bits entities)" bitfld.long 0x00 0.--1. " ECC_BCH_LEVEL ,Error correction level0x0: 4 bits0x1: 8 bits0x2: 16 bits0x3: Reserved" "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "ELM_PAGE_CTRL,Page definition" bitfld.long 0x00 7. " SECTOR_7 ,Set to 1 if syndrome polynomial 7 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x00 6. " SECTOR_6 ,Set to 1 if syndrome polynomial 6 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x00 5. " SECTOR_5 ,Set to 1 if syndrome polynomial 5 is part of the page in page mode. Must be 0 in continuous mode." "0,1" textline " " bitfld.long 0x00 4. " SECTOR_4 ,Set to 1 if syndrome polynomial 4 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x00 3. " SECTOR_3 ,Set to 1 if syndrome polynomial 3 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x00 2. " SECTOR_2 ,Set to 1 if syndrome polynomial 2 is part of the page in page mode. Must be 0 in continuous mode." "0,1" textline " " bitfld.long 0x00 1. " SECTOR_1 ,Set to 1 if syndrome polynomial 1 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x00 0. " SECTOR_0 ,Set to 1 if syndrome polynomial 0 is part of the page in page mode. Must be 0 in continuous mode." "0,1" tree.end tree.end tree.open "sDMA_Module" tree "sDMA" base ad:0x4A056000 tree "DMA_Channel_0" width 21. group.long 0xD8++0x3 line.long 0x00 "DMA4_CCDNi_0," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0xBC++0x3 line.long 0x00 "DMA4_CCENi_0,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0xC0++0x3 line.long 0x00 "DMA4_CCFNi_0,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x80++0x3 line.long 0x00 "DMA4_CCRi_0,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB8++0x3 line.long 0x00 "DMA4_CDACi_0,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0xAC++0x3 line.long 0x00 "DMA4_CDEIi_0,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0xB0++0x3 line.long 0x00 "DMA4_CDFIi_0,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0xD0++0x3 line.long 0x00 "DMA4_CDPi_0,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0xA0++0x3 line.long 0x00 "DMA4_CDSAi_0,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x94++0x3 line.long 0x00 "DMA4_CENi_0,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x98++0x3 line.long 0x00 "DMA4_CFNi_0,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x88++0x3 line.long 0x00 "DMA4_CICRi_0,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x84++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_0,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD4++0x3 line.long 0x00 "DMA4_CNDPi_0,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xC4++0x3 line.long 0x00 "DMA4_COLORi_0,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0xB4++0x3 line.long 0x00 "DMA4_CSACi_0,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x90++0x3 line.long 0x00 "DMA4_CSDPi_0,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0xA4++0x3 line.long 0x00 "DMA4_CSEIi_0,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0xA8++0x3 line.long 0x00 "DMA4_CSFIi_0,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x8C++0x3 line.long 0x00 "DMA4_CSRi_0,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x9C++0x3 line.long 0x00 "DMA4_CSSAi_0,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.long 0x18++0x3 line.long 0x00 "DMA4_IRQENABLE_Lj_0,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line Lj" hexmask.long 0x00 0.--31. 1. " CH_31_0_Lj_EN ,Channel Interrupt on Lj mask/unmask : to Mask/Unmask a channel i interrupt on Lj the user writes 0/1 on the bit field i. - . - ." group.long 0x8++0x3 line.long 0x00 "DMA4_IRQSTATUS_Lj_0,The interrupt status register regroups all the status of the DMA4 channels that can generate an interrupt over line Lj." hexmask.long 0x00 0.--31. 1. " CH_31_0_Lj ,Channel 31 Interrupt on Lj: When an interrupt is seen on the line Lj the status of a interrupting channel i is read in the bit field i. - . - . - . - ." tree.end tree "DMA_Channel_1" width 21. group.long 0x138++0x3 line.long 0x00 "DMA4_CCDNi_1," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x11C++0x3 line.long 0x00 "DMA4_CCENi_1,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x120++0x3 line.long 0x00 "DMA4_CCFNi_1,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0xE0++0x3 line.long 0x00 "DMA4_CCRi_1,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x118++0x3 line.long 0x00 "DMA4_CDACi_1,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x10C++0x3 line.long 0x00 "DMA4_CDEIi_1,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x110++0x3 line.long 0x00 "DMA4_CDFIi_1,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x130++0x3 line.long 0x00 "DMA4_CDPi_1,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x100++0x3 line.long 0x00 "DMA4_CDSAi_1,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0xF4++0x3 line.long 0x00 "DMA4_CENi_1,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0xF8++0x3 line.long 0x00 "DMA4_CFNi_1,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0xE8++0x3 line.long 0x00 "DMA4_CICRi_1,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0xE4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_1,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x3 line.long 0x00 "DMA4_CNDPi_1,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x124++0x3 line.long 0x00 "DMA4_COLORi_1,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x114++0x3 line.long 0x00 "DMA4_CSACi_1,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0xF0++0x3 line.long 0x00 "DMA4_CSDPi_1,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x104++0x3 line.long 0x00 "DMA4_CSEIi_1,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x108++0x3 line.long 0x00 "DMA4_CSFIi_1,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0xEC++0x3 line.long 0x00 "DMA4_CSRi_1,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0xFC++0x3 line.long 0x00 "DMA4_CSSAi_1,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.long 0x1C++0x3 line.long 0x00 "DMA4_IRQENABLE_Lj_1,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line Lj" hexmask.long 0x00 0.--31. 1. " CH_31_0_Lj_EN ,Channel Interrupt on Lj mask/unmask : to Mask/Unmask a channel i interrupt on Lj the user writes 0/1 on the bit field i. - . - ." group.long 0xC++0x3 line.long 0x00 "DMA4_IRQSTATUS_Lj_1,The interrupt status register regroups all the status of the DMA4 channels that can generate an interrupt over line Lj." hexmask.long 0x00 0.--31. 1. " CH_31_0_Lj ,Channel 31 Interrupt on Lj: When an interrupt is seen on the line Lj the status of a interrupting channel i is read in the bit field i. - . - . - . - ." tree.end tree "DMA_Channel_2" width 21. group.long 0x198++0x3 line.long 0x00 "DMA4_CCDNi_2," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x17C++0x3 line.long 0x00 "DMA4_CCENi_2,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x180++0x3 line.long 0x00 "DMA4_CCFNi_2,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x140++0x3 line.long 0x00 "DMA4_CCRi_2,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x178++0x3 line.long 0x00 "DMA4_CDACi_2,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x16C++0x3 line.long 0x00 "DMA4_CDEIi_2,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x170++0x3 line.long 0x00 "DMA4_CDFIi_2,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x190++0x3 line.long 0x00 "DMA4_CDPi_2,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x160++0x3 line.long 0x00 "DMA4_CDSAi_2,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x154++0x3 line.long 0x00 "DMA4_CENi_2,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x158++0x3 line.long 0x00 "DMA4_CFNi_2,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x148++0x3 line.long 0x00 "DMA4_CICRi_2,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x144++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_2,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x194++0x3 line.long 0x00 "DMA4_CNDPi_2,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x184++0x3 line.long 0x00 "DMA4_COLORi_2,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x174++0x3 line.long 0x00 "DMA4_CSACi_2,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x150++0x3 line.long 0x00 "DMA4_CSDPi_2,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x164++0x3 line.long 0x00 "DMA4_CSEIi_2,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x168++0x3 line.long 0x00 "DMA4_CSFIi_2,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x14C++0x3 line.long 0x00 "DMA4_CSRi_2,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x15C++0x3 line.long 0x00 "DMA4_CSSAi_2,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.long 0x20++0x3 line.long 0x00 "DMA4_IRQENABLE_Lj_2,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line Lj" hexmask.long 0x00 0.--31. 1. " CH_31_0_Lj_EN ,Channel Interrupt on Lj mask/unmask : to Mask/Unmask a channel i interrupt on Lj the user writes 0/1 on the bit field i. - . - ." group.long 0x10++0x3 line.long 0x00 "DMA4_IRQSTATUS_Lj_2,The interrupt status register regroups all the status of the DMA4 channels that can generate an interrupt over line Lj." hexmask.long 0x00 0.--31. 1. " CH_31_0_Lj ,Channel 31 Interrupt on Lj: When an interrupt is seen on the line Lj the status of a interrupting channel i is read in the bit field i. - . - . - . - ." tree.end tree "DMA_Channel_3" width 21. group.long 0x1F8++0x3 line.long 0x00 "DMA4_CCDNi_3," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x1DC++0x3 line.long 0x00 "DMA4_CCENi_3,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x1E0++0x3 line.long 0x00 "DMA4_CCFNi_3,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x1A0++0x3 line.long 0x00 "DMA4_CCRi_3,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1D8++0x3 line.long 0x00 "DMA4_CDACi_3,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x1CC++0x3 line.long 0x00 "DMA4_CDEIi_3,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x1D0++0x3 line.long 0x00 "DMA4_CDFIi_3,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x1F0++0x3 line.long 0x00 "DMA4_CDPi_3,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x1C0++0x3 line.long 0x00 "DMA4_CDSAi_3,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x1B4++0x3 line.long 0x00 "DMA4_CENi_3,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x1B8++0x3 line.long 0x00 "DMA4_CFNi_3,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x1A8++0x3 line.long 0x00 "DMA4_CICRi_3,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x1A4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_3,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1F4++0x3 line.long 0x00 "DMA4_CNDPi_3,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x1E4++0x3 line.long 0x00 "DMA4_COLORi_3,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x1D4++0x3 line.long 0x00 "DMA4_CSACi_3,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x1B0++0x3 line.long 0x00 "DMA4_CSDPi_3,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x1C4++0x3 line.long 0x00 "DMA4_CSEIi_3,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x1C8++0x3 line.long 0x00 "DMA4_CSFIi_3,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x1AC++0x3 line.long 0x00 "DMA4_CSRi_3,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x1BC++0x3 line.long 0x00 "DMA4_CSSAi_3,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.long 0x24++0x3 line.long 0x00 "DMA4_IRQENABLE_Lj_3,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line Lj" hexmask.long 0x00 0.--31. 1. " CH_31_0_Lj_EN ,Channel Interrupt on Lj mask/unmask : to Mask/Unmask a channel i interrupt on Lj the user writes 0/1 on the bit field i. - . - ." group.long 0x14++0x3 line.long 0x00 "DMA4_IRQSTATUS_Lj_3,The interrupt status register regroups all the status of the DMA4 channels that can generate an interrupt over line Lj." hexmask.long 0x00 0.--31. 1. " CH_31_0_Lj ,Channel 31 Interrupt on Lj: When an interrupt is seen on the line Lj the status of a interrupting channel i is read in the bit field i. - . - . - . - ." tree.end tree "DMA_Channel_4" width 19. group.long 0x258++0x3 line.long 0x00 "DMA4_CCDNi_4," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x23C++0x3 line.long 0x00 "DMA4_CCENi_4,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x240++0x3 line.long 0x00 "DMA4_CCFNi_4,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x200++0x3 line.long 0x00 "DMA4_CCRi_4,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x238++0x3 line.long 0x00 "DMA4_CDACi_4,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x22C++0x3 line.long 0x00 "DMA4_CDEIi_4,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x230++0x3 line.long 0x00 "DMA4_CDFIi_4,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x250++0x3 line.long 0x00 "DMA4_CDPi_4,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x220++0x3 line.long 0x00 "DMA4_CDSAi_4,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x214++0x3 line.long 0x00 "DMA4_CENi_4,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x218++0x3 line.long 0x00 "DMA4_CFNi_4,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x208++0x3 line.long 0x00 "DMA4_CICRi_4,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x204++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_4,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x254++0x3 line.long 0x00 "DMA4_CNDPi_4,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x244++0x3 line.long 0x00 "DMA4_COLORi_4,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x234++0x3 line.long 0x00 "DMA4_CSACi_4,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x210++0x3 line.long 0x00 "DMA4_CSDPi_4,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x224++0x3 line.long 0x00 "DMA4_CSEIi_4,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x228++0x3 line.long 0x00 "DMA4_CSFIi_4,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x20C++0x3 line.long 0x00 "DMA4_CSRi_4,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x21C++0x3 line.long 0x00 "DMA4_CSSAi_4,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_5" width 19. group.long 0x2B8++0x3 line.long 0x00 "DMA4_CCDNi_5," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x29C++0x3 line.long 0x00 "DMA4_CCENi_5,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x2A0++0x3 line.long 0x00 "DMA4_CCFNi_5,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x260++0x3 line.long 0x00 "DMA4_CCRi_5,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x298++0x3 line.long 0x00 "DMA4_CDACi_5,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x28C++0x3 line.long 0x00 "DMA4_CDEIi_5,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x290++0x3 line.long 0x00 "DMA4_CDFIi_5,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x2B0++0x3 line.long 0x00 "DMA4_CDPi_5,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x280++0x3 line.long 0x00 "DMA4_CDSAi_5,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x274++0x3 line.long 0x00 "DMA4_CENi_5,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x278++0x3 line.long 0x00 "DMA4_CFNi_5,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x268++0x3 line.long 0x00 "DMA4_CICRi_5,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x264++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_5,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2B4++0x3 line.long 0x00 "DMA4_CNDPi_5,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x2A4++0x3 line.long 0x00 "DMA4_COLORi_5,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x294++0x3 line.long 0x00 "DMA4_CSACi_5,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x270++0x3 line.long 0x00 "DMA4_CSDPi_5,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x284++0x3 line.long 0x00 "DMA4_CSEIi_5,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x288++0x3 line.long 0x00 "DMA4_CSFIi_5,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x26C++0x3 line.long 0x00 "DMA4_CSRi_5,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x27C++0x3 line.long 0x00 "DMA4_CSSAi_5,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_6" width 19. group.long 0x318++0x3 line.long 0x00 "DMA4_CCDNi_6," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x2FC++0x3 line.long 0x00 "DMA4_CCENi_6,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x300++0x3 line.long 0x00 "DMA4_CCFNi_6,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x2C0++0x3 line.long 0x00 "DMA4_CCRi_6,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2F8++0x3 line.long 0x00 "DMA4_CDACi_6,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x2EC++0x3 line.long 0x00 "DMA4_CDEIi_6,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x2F0++0x3 line.long 0x00 "DMA4_CDFIi_6,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x310++0x3 line.long 0x00 "DMA4_CDPi_6,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x2E0++0x3 line.long 0x00 "DMA4_CDSAi_6,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x2D4++0x3 line.long 0x00 "DMA4_CENi_6,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x2D8++0x3 line.long 0x00 "DMA4_CFNi_6,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x2C8++0x3 line.long 0x00 "DMA4_CICRi_6,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x2C4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_6,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x314++0x3 line.long 0x00 "DMA4_CNDPi_6,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x304++0x3 line.long 0x00 "DMA4_COLORi_6,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x2F4++0x3 line.long 0x00 "DMA4_CSACi_6,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x2D0++0x3 line.long 0x00 "DMA4_CSDPi_6,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x2E4++0x3 line.long 0x00 "DMA4_CSEIi_6,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x2E8++0x3 line.long 0x00 "DMA4_CSFIi_6,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x2CC++0x3 line.long 0x00 "DMA4_CSRi_6,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x2DC++0x3 line.long 0x00 "DMA4_CSSAi_6,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_7" width 19. group.long 0x378++0x3 line.long 0x00 "DMA4_CCDNi_7," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x35C++0x3 line.long 0x00 "DMA4_CCENi_7,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x360++0x3 line.long 0x00 "DMA4_CCFNi_7,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x320++0x3 line.long 0x00 "DMA4_CCRi_7,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x358++0x3 line.long 0x00 "DMA4_CDACi_7,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x34C++0x3 line.long 0x00 "DMA4_CDEIi_7,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x350++0x3 line.long 0x00 "DMA4_CDFIi_7,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x370++0x3 line.long 0x00 "DMA4_CDPi_7,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x340++0x3 line.long 0x00 "DMA4_CDSAi_7,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x334++0x3 line.long 0x00 "DMA4_CENi_7,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x338++0x3 line.long 0x00 "DMA4_CFNi_7,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x328++0x3 line.long 0x00 "DMA4_CICRi_7,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x324++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_7,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x374++0x3 line.long 0x00 "DMA4_CNDPi_7,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x364++0x3 line.long 0x00 "DMA4_COLORi_7,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x354++0x3 line.long 0x00 "DMA4_CSACi_7,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x330++0x3 line.long 0x00 "DMA4_CSDPi_7,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x344++0x3 line.long 0x00 "DMA4_CSEIi_7,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x348++0x3 line.long 0x00 "DMA4_CSFIi_7,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x32C++0x3 line.long 0x00 "DMA4_CSRi_7,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x33C++0x3 line.long 0x00 "DMA4_CSSAi_7,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_8" width 19. group.long 0x3D8++0x3 line.long 0x00 "DMA4_CCDNi_8," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x3BC++0x3 line.long 0x00 "DMA4_CCENi_8,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x3C0++0x3 line.long 0x00 "DMA4_CCFNi_8,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x380++0x3 line.long 0x00 "DMA4_CCRi_8,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3B8++0x3 line.long 0x00 "DMA4_CDACi_8,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x3AC++0x3 line.long 0x00 "DMA4_CDEIi_8,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x3B0++0x3 line.long 0x00 "DMA4_CDFIi_8,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x3D0++0x3 line.long 0x00 "DMA4_CDPi_8,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x3A0++0x3 line.long 0x00 "DMA4_CDSAi_8,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x394++0x3 line.long 0x00 "DMA4_CENi_8,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x398++0x3 line.long 0x00 "DMA4_CFNi_8,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x388++0x3 line.long 0x00 "DMA4_CICRi_8,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x384++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_8,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3D4++0x3 line.long 0x00 "DMA4_CNDPi_8,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x3C4++0x3 line.long 0x00 "DMA4_COLORi_8,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x3B4++0x3 line.long 0x00 "DMA4_CSACi_8,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x390++0x3 line.long 0x00 "DMA4_CSDPi_8,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x3A4++0x3 line.long 0x00 "DMA4_CSEIi_8,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x3A8++0x3 line.long 0x00 "DMA4_CSFIi_8,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x38C++0x3 line.long 0x00 "DMA4_CSRi_8,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x39C++0x3 line.long 0x00 "DMA4_CSSAi_8,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_9" width 19. group.long 0x438++0x3 line.long 0x00 "DMA4_CCDNi_9," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x41C++0x3 line.long 0x00 "DMA4_CCENi_9,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x420++0x3 line.long 0x00 "DMA4_CCFNi_9,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x3E0++0x3 line.long 0x00 "DMA4_CCRi_9,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x418++0x3 line.long 0x00 "DMA4_CDACi_9,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x40C++0x3 line.long 0x00 "DMA4_CDEIi_9,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x410++0x3 line.long 0x00 "DMA4_CDFIi_9,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x430++0x3 line.long 0x00 "DMA4_CDPi_9,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x400++0x3 line.long 0x00 "DMA4_CDSAi_9,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x3F4++0x3 line.long 0x00 "DMA4_CENi_9,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x3F8++0x3 line.long 0x00 "DMA4_CFNi_9,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x3E8++0x3 line.long 0x00 "DMA4_CICRi_9,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x3E4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_9,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x434++0x3 line.long 0x00 "DMA4_CNDPi_9,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x424++0x3 line.long 0x00 "DMA4_COLORi_9,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x414++0x3 line.long 0x00 "DMA4_CSACi_9,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x3F0++0x3 line.long 0x00 "DMA4_CSDPi_9,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x404++0x3 line.long 0x00 "DMA4_CSEIi_9,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x408++0x3 line.long 0x00 "DMA4_CSFIi_9,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x3EC++0x3 line.long 0x00 "DMA4_CSRi_9,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x3FC++0x3 line.long 0x00 "DMA4_CSSAi_9,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_10" width 20. group.long 0x498++0x3 line.long 0x00 "DMA4_CCDNi_10," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x47C++0x3 line.long 0x00 "DMA4_CCENi_10,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x480++0x3 line.long 0x00 "DMA4_CCFNi_10,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x440++0x3 line.long 0x00 "DMA4_CCRi_10,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x478++0x3 line.long 0x00 "DMA4_CDACi_10,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x46C++0x3 line.long 0x00 "DMA4_CDEIi_10,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x470++0x3 line.long 0x00 "DMA4_CDFIi_10,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x490++0x3 line.long 0x00 "DMA4_CDPi_10,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x460++0x3 line.long 0x00 "DMA4_CDSAi_10,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x454++0x3 line.long 0x00 "DMA4_CENi_10,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x458++0x3 line.long 0x00 "DMA4_CFNi_10,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x448++0x3 line.long 0x00 "DMA4_CICRi_10,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x444++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_10,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x494++0x3 line.long 0x00 "DMA4_CNDPi_10,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x484++0x3 line.long 0x00 "DMA4_COLORi_10,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x474++0x3 line.long 0x00 "DMA4_CSACi_10,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x450++0x3 line.long 0x00 "DMA4_CSDPi_10,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x464++0x3 line.long 0x00 "DMA4_CSEIi_10,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x468++0x3 line.long 0x00 "DMA4_CSFIi_10,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x44C++0x3 line.long 0x00 "DMA4_CSRi_10,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x45C++0x3 line.long 0x00 "DMA4_CSSAi_10,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_11" width 20. group.long 0x4F8++0x3 line.long 0x00 "DMA4_CCDNi_11," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x4DC++0x3 line.long 0x00 "DMA4_CCENi_11,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x4E0++0x3 line.long 0x00 "DMA4_CCFNi_11,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x4A0++0x3 line.long 0x00 "DMA4_CCRi_11,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4D8++0x3 line.long 0x00 "DMA4_CDACi_11,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x4CC++0x3 line.long 0x00 "DMA4_CDEIi_11,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x4D0++0x3 line.long 0x00 "DMA4_CDFIi_11,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x4F0++0x3 line.long 0x00 "DMA4_CDPi_11,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x4C0++0x3 line.long 0x00 "DMA4_CDSAi_11,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x4B4++0x3 line.long 0x00 "DMA4_CENi_11,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x4B8++0x3 line.long 0x00 "DMA4_CFNi_11,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x4A8++0x3 line.long 0x00 "DMA4_CICRi_11,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x4A4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_11,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4F4++0x3 line.long 0x00 "DMA4_CNDPi_11,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x4E4++0x3 line.long 0x00 "DMA4_COLORi_11,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x4D4++0x3 line.long 0x00 "DMA4_CSACi_11,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x4B0++0x3 line.long 0x00 "DMA4_CSDPi_11,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x4C4++0x3 line.long 0x00 "DMA4_CSEIi_11,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x4C8++0x3 line.long 0x00 "DMA4_CSFIi_11,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x4AC++0x3 line.long 0x00 "DMA4_CSRi_11,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x4BC++0x3 line.long 0x00 "DMA4_CSSAi_11,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_12" width 20. group.long 0x558++0x3 line.long 0x00 "DMA4_CCDNi_12," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x53C++0x3 line.long 0x00 "DMA4_CCENi_12,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x540++0x3 line.long 0x00 "DMA4_CCFNi_12,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x500++0x3 line.long 0x00 "DMA4_CCRi_12,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x538++0x3 line.long 0x00 "DMA4_CDACi_12,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x52C++0x3 line.long 0x00 "DMA4_CDEIi_12,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x530++0x3 line.long 0x00 "DMA4_CDFIi_12,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x550++0x3 line.long 0x00 "DMA4_CDPi_12,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x520++0x3 line.long 0x00 "DMA4_CDSAi_12,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x514++0x3 line.long 0x00 "DMA4_CENi_12,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x518++0x3 line.long 0x00 "DMA4_CFNi_12,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x508++0x3 line.long 0x00 "DMA4_CICRi_12,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x504++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_12,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x554++0x3 line.long 0x00 "DMA4_CNDPi_12,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x544++0x3 line.long 0x00 "DMA4_COLORi_12,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x534++0x3 line.long 0x00 "DMA4_CSACi_12,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x510++0x3 line.long 0x00 "DMA4_CSDPi_12,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x524++0x3 line.long 0x00 "DMA4_CSEIi_12,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x528++0x3 line.long 0x00 "DMA4_CSFIi_12,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x50C++0x3 line.long 0x00 "DMA4_CSRi_12,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x51C++0x3 line.long 0x00 "DMA4_CSSAi_12,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_13" width 20. group.long 0x5B8++0x3 line.long 0x00 "DMA4_CCDNi_13," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x59C++0x3 line.long 0x00 "DMA4_CCENi_13,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x5A0++0x3 line.long 0x00 "DMA4_CCFNi_13,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x560++0x3 line.long 0x00 "DMA4_CCRi_13,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x598++0x3 line.long 0x00 "DMA4_CDACi_13,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x58C++0x3 line.long 0x00 "DMA4_CDEIi_13,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x590++0x3 line.long 0x00 "DMA4_CDFIi_13,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x5B0++0x3 line.long 0x00 "DMA4_CDPi_13,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x580++0x3 line.long 0x00 "DMA4_CDSAi_13,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x574++0x3 line.long 0x00 "DMA4_CENi_13,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x578++0x3 line.long 0x00 "DMA4_CFNi_13,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x568++0x3 line.long 0x00 "DMA4_CICRi_13,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x564++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_13,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5B4++0x3 line.long 0x00 "DMA4_CNDPi_13,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x5A4++0x3 line.long 0x00 "DMA4_COLORi_13,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x594++0x3 line.long 0x00 "DMA4_CSACi_13,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x570++0x3 line.long 0x00 "DMA4_CSDPi_13,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x584++0x3 line.long 0x00 "DMA4_CSEIi_13,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x588++0x3 line.long 0x00 "DMA4_CSFIi_13,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x56C++0x3 line.long 0x00 "DMA4_CSRi_13,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x57C++0x3 line.long 0x00 "DMA4_CSSAi_13,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_14" width 20. group.long 0x618++0x3 line.long 0x00 "DMA4_CCDNi_14," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x5FC++0x3 line.long 0x00 "DMA4_CCENi_14,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x600++0x3 line.long 0x00 "DMA4_CCFNi_14,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x5C0++0x3 line.long 0x00 "DMA4_CCRi_14,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5F8++0x3 line.long 0x00 "DMA4_CDACi_14,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x5EC++0x3 line.long 0x00 "DMA4_CDEIi_14,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x5F0++0x3 line.long 0x00 "DMA4_CDFIi_14,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x610++0x3 line.long 0x00 "DMA4_CDPi_14,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x5E0++0x3 line.long 0x00 "DMA4_CDSAi_14,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x5D4++0x3 line.long 0x00 "DMA4_CENi_14,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x5D8++0x3 line.long 0x00 "DMA4_CFNi_14,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x5C8++0x3 line.long 0x00 "DMA4_CICRi_14,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x5C4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_14,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x614++0x3 line.long 0x00 "DMA4_CNDPi_14,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x604++0x3 line.long 0x00 "DMA4_COLORi_14,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x5F4++0x3 line.long 0x00 "DMA4_CSACi_14,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x5D0++0x3 line.long 0x00 "DMA4_CSDPi_14,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x5E4++0x3 line.long 0x00 "DMA4_CSEIi_14,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x5E8++0x3 line.long 0x00 "DMA4_CSFIi_14,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x5CC++0x3 line.long 0x00 "DMA4_CSRi_14,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x5DC++0x3 line.long 0x00 "DMA4_CSSAi_14,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_15" width 20. group.long 0x678++0x3 line.long 0x00 "DMA4_CCDNi_15," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x65C++0x3 line.long 0x00 "DMA4_CCENi_15,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x660++0x3 line.long 0x00 "DMA4_CCFNi_15,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x620++0x3 line.long 0x00 "DMA4_CCRi_15,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x658++0x3 line.long 0x00 "DMA4_CDACi_15,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x64C++0x3 line.long 0x00 "DMA4_CDEIi_15,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x650++0x3 line.long 0x00 "DMA4_CDFIi_15,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x670++0x3 line.long 0x00 "DMA4_CDPi_15,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x640++0x3 line.long 0x00 "DMA4_CDSAi_15,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x634++0x3 line.long 0x00 "DMA4_CENi_15,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x638++0x3 line.long 0x00 "DMA4_CFNi_15,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x628++0x3 line.long 0x00 "DMA4_CICRi_15,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x624++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_15,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x674++0x3 line.long 0x00 "DMA4_CNDPi_15,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x664++0x3 line.long 0x00 "DMA4_COLORi_15,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x654++0x3 line.long 0x00 "DMA4_CSACi_15,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x630++0x3 line.long 0x00 "DMA4_CSDPi_15,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x644++0x3 line.long 0x00 "DMA4_CSEIi_15,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x648++0x3 line.long 0x00 "DMA4_CSFIi_15,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x62C++0x3 line.long 0x00 "DMA4_CSRi_15,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x63C++0x3 line.long 0x00 "DMA4_CSSAi_15,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_16" width 20. group.long 0x6D8++0x3 line.long 0x00 "DMA4_CCDNi_16," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x6BC++0x3 line.long 0x00 "DMA4_CCENi_16,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x6C0++0x3 line.long 0x00 "DMA4_CCFNi_16,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x680++0x3 line.long 0x00 "DMA4_CCRi_16,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x6B8++0x3 line.long 0x00 "DMA4_CDACi_16,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x6AC++0x3 line.long 0x00 "DMA4_CDEIi_16,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x6B0++0x3 line.long 0x00 "DMA4_CDFIi_16,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x6D0++0x3 line.long 0x00 "DMA4_CDPi_16,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x6A0++0x3 line.long 0x00 "DMA4_CDSAi_16,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x694++0x3 line.long 0x00 "DMA4_CENi_16,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x698++0x3 line.long 0x00 "DMA4_CFNi_16,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x688++0x3 line.long 0x00 "DMA4_CICRi_16,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x684++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_16,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x6D4++0x3 line.long 0x00 "DMA4_CNDPi_16,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x6C4++0x3 line.long 0x00 "DMA4_COLORi_16,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x6B4++0x3 line.long 0x00 "DMA4_CSACi_16,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x690++0x3 line.long 0x00 "DMA4_CSDPi_16,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x6A4++0x3 line.long 0x00 "DMA4_CSEIi_16,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x6A8++0x3 line.long 0x00 "DMA4_CSFIi_16,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x68C++0x3 line.long 0x00 "DMA4_CSRi_16,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x69C++0x3 line.long 0x00 "DMA4_CSSAi_16,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_17" width 20. group.long 0x738++0x3 line.long 0x00 "DMA4_CCDNi_17," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x71C++0x3 line.long 0x00 "DMA4_CCENi_17,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x720++0x3 line.long 0x00 "DMA4_CCFNi_17,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x6E0++0x3 line.long 0x00 "DMA4_CCRi_17,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x718++0x3 line.long 0x00 "DMA4_CDACi_17,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x70C++0x3 line.long 0x00 "DMA4_CDEIi_17,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x710++0x3 line.long 0x00 "DMA4_CDFIi_17,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x730++0x3 line.long 0x00 "DMA4_CDPi_17,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x700++0x3 line.long 0x00 "DMA4_CDSAi_17,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x6F4++0x3 line.long 0x00 "DMA4_CENi_17,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x6F8++0x3 line.long 0x00 "DMA4_CFNi_17,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x6E8++0x3 line.long 0x00 "DMA4_CICRi_17,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x6E4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_17,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x734++0x3 line.long 0x00 "DMA4_CNDPi_17,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x724++0x3 line.long 0x00 "DMA4_COLORi_17,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x714++0x3 line.long 0x00 "DMA4_CSACi_17,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x6F0++0x3 line.long 0x00 "DMA4_CSDPi_17,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x704++0x3 line.long 0x00 "DMA4_CSEIi_17,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x708++0x3 line.long 0x00 "DMA4_CSFIi_17,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x6EC++0x3 line.long 0x00 "DMA4_CSRi_17,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x6FC++0x3 line.long 0x00 "DMA4_CSSAi_17,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_18" width 20. group.long 0x798++0x3 line.long 0x00 "DMA4_CCDNi_18," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x77C++0x3 line.long 0x00 "DMA4_CCENi_18,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x780++0x3 line.long 0x00 "DMA4_CCFNi_18,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x740++0x3 line.long 0x00 "DMA4_CCRi_18,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x778++0x3 line.long 0x00 "DMA4_CDACi_18,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x76C++0x3 line.long 0x00 "DMA4_CDEIi_18,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x770++0x3 line.long 0x00 "DMA4_CDFIi_18,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x790++0x3 line.long 0x00 "DMA4_CDPi_18,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x760++0x3 line.long 0x00 "DMA4_CDSAi_18,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x754++0x3 line.long 0x00 "DMA4_CENi_18,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x758++0x3 line.long 0x00 "DMA4_CFNi_18,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x748++0x3 line.long 0x00 "DMA4_CICRi_18,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x744++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_18,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x794++0x3 line.long 0x00 "DMA4_CNDPi_18,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x784++0x3 line.long 0x00 "DMA4_COLORi_18,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x774++0x3 line.long 0x00 "DMA4_CSACi_18,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x750++0x3 line.long 0x00 "DMA4_CSDPi_18,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x764++0x3 line.long 0x00 "DMA4_CSEIi_18,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x768++0x3 line.long 0x00 "DMA4_CSFIi_18,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x74C++0x3 line.long 0x00 "DMA4_CSRi_18,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x75C++0x3 line.long 0x00 "DMA4_CSSAi_18,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_19" width 20. group.long 0x7F8++0x3 line.long 0x00 "DMA4_CCDNi_19," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x7DC++0x3 line.long 0x00 "DMA4_CCENi_19,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x7E0++0x3 line.long 0x00 "DMA4_CCFNi_19,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x7A0++0x3 line.long 0x00 "DMA4_CCRi_19,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7D8++0x3 line.long 0x00 "DMA4_CDACi_19,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x7CC++0x3 line.long 0x00 "DMA4_CDEIi_19,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x7D0++0x3 line.long 0x00 "DMA4_CDFIi_19,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x7F0++0x3 line.long 0x00 "DMA4_CDPi_19,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x7C0++0x3 line.long 0x00 "DMA4_CDSAi_19,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x7B4++0x3 line.long 0x00 "DMA4_CENi_19,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x7B8++0x3 line.long 0x00 "DMA4_CFNi_19,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x7A8++0x3 line.long 0x00 "DMA4_CICRi_19,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x7A4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_19,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7F4++0x3 line.long 0x00 "DMA4_CNDPi_19,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x7E4++0x3 line.long 0x00 "DMA4_COLORi_19,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x7D4++0x3 line.long 0x00 "DMA4_CSACi_19,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x7B0++0x3 line.long 0x00 "DMA4_CSDPi_19,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x7C4++0x3 line.long 0x00 "DMA4_CSEIi_19,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x7C8++0x3 line.long 0x00 "DMA4_CSFIi_19,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x7AC++0x3 line.long 0x00 "DMA4_CSRi_19,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x7BC++0x3 line.long 0x00 "DMA4_CSSAi_19,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_20" width 20. group.long 0x858++0x3 line.long 0x00 "DMA4_CCDNi_20," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x83C++0x3 line.long 0x00 "DMA4_CCENi_20,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x840++0x3 line.long 0x00 "DMA4_CCFNi_20,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x800++0x3 line.long 0x00 "DMA4_CCRi_20,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x838++0x3 line.long 0x00 "DMA4_CDACi_20,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x82C++0x3 line.long 0x00 "DMA4_CDEIi_20,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x830++0x3 line.long 0x00 "DMA4_CDFIi_20,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x850++0x3 line.long 0x00 "DMA4_CDPi_20,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x820++0x3 line.long 0x00 "DMA4_CDSAi_20,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x814++0x3 line.long 0x00 "DMA4_CENi_20,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x818++0x3 line.long 0x00 "DMA4_CFNi_20,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x808++0x3 line.long 0x00 "DMA4_CICRi_20,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x804++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_20,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x854++0x3 line.long 0x00 "DMA4_CNDPi_20,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x844++0x3 line.long 0x00 "DMA4_COLORi_20,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x834++0x3 line.long 0x00 "DMA4_CSACi_20,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x810++0x3 line.long 0x00 "DMA4_CSDPi_20,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x824++0x3 line.long 0x00 "DMA4_CSEIi_20,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x828++0x3 line.long 0x00 "DMA4_CSFIi_20,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x80C++0x3 line.long 0x00 "DMA4_CSRi_20,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x81C++0x3 line.long 0x00 "DMA4_CSSAi_20,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_21" width 20. group.long 0x8B8++0x3 line.long 0x00 "DMA4_CCDNi_21," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x89C++0x3 line.long 0x00 "DMA4_CCENi_21,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x8A0++0x3 line.long 0x00 "DMA4_CCFNi_21,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x860++0x3 line.long 0x00 "DMA4_CCRi_21,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x898++0x3 line.long 0x00 "DMA4_CDACi_21,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x88C++0x3 line.long 0x00 "DMA4_CDEIi_21,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x890++0x3 line.long 0x00 "DMA4_CDFIi_21,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x8B0++0x3 line.long 0x00 "DMA4_CDPi_21,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x880++0x3 line.long 0x00 "DMA4_CDSAi_21,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x874++0x3 line.long 0x00 "DMA4_CENi_21,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x878++0x3 line.long 0x00 "DMA4_CFNi_21,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x868++0x3 line.long 0x00 "DMA4_CICRi_21,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x864++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_21,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8B4++0x3 line.long 0x00 "DMA4_CNDPi_21,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x8A4++0x3 line.long 0x00 "DMA4_COLORi_21,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x894++0x3 line.long 0x00 "DMA4_CSACi_21,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x870++0x3 line.long 0x00 "DMA4_CSDPi_21,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x884++0x3 line.long 0x00 "DMA4_CSEIi_21,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x888++0x3 line.long 0x00 "DMA4_CSFIi_21,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x86C++0x3 line.long 0x00 "DMA4_CSRi_21,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x87C++0x3 line.long 0x00 "DMA4_CSSAi_21,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_22" width 20. group.long 0x918++0x3 line.long 0x00 "DMA4_CCDNi_22," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x8FC++0x3 line.long 0x00 "DMA4_CCENi_22,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x900++0x3 line.long 0x00 "DMA4_CCFNi_22,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x8C0++0x3 line.long 0x00 "DMA4_CCRi_22,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8F8++0x3 line.long 0x00 "DMA4_CDACi_22,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x8EC++0x3 line.long 0x00 "DMA4_CDEIi_22,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x8F0++0x3 line.long 0x00 "DMA4_CDFIi_22,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x910++0x3 line.long 0x00 "DMA4_CDPi_22,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x8E0++0x3 line.long 0x00 "DMA4_CDSAi_22,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x8D4++0x3 line.long 0x00 "DMA4_CENi_22,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x8D8++0x3 line.long 0x00 "DMA4_CFNi_22,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x8C8++0x3 line.long 0x00 "DMA4_CICRi_22,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x8C4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_22,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x914++0x3 line.long 0x00 "DMA4_CNDPi_22,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x904++0x3 line.long 0x00 "DMA4_COLORi_22,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x8F4++0x3 line.long 0x00 "DMA4_CSACi_22,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x8D0++0x3 line.long 0x00 "DMA4_CSDPi_22,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x8E4++0x3 line.long 0x00 "DMA4_CSEIi_22,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x8E8++0x3 line.long 0x00 "DMA4_CSFIi_22,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x8CC++0x3 line.long 0x00 "DMA4_CSRi_22,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x8DC++0x3 line.long 0x00 "DMA4_CSSAi_22,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_23" width 20. group.long 0x978++0x3 line.long 0x00 "DMA4_CCDNi_23," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x95C++0x3 line.long 0x00 "DMA4_CCENi_23,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x960++0x3 line.long 0x00 "DMA4_CCFNi_23,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x920++0x3 line.long 0x00 "DMA4_CCRi_23,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x958++0x3 line.long 0x00 "DMA4_CDACi_23,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x94C++0x3 line.long 0x00 "DMA4_CDEIi_23,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x950++0x3 line.long 0x00 "DMA4_CDFIi_23,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x970++0x3 line.long 0x00 "DMA4_CDPi_23,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x940++0x3 line.long 0x00 "DMA4_CDSAi_23,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x934++0x3 line.long 0x00 "DMA4_CENi_23,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x938++0x3 line.long 0x00 "DMA4_CFNi_23,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x928++0x3 line.long 0x00 "DMA4_CICRi_23,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x924++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_23,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x974++0x3 line.long 0x00 "DMA4_CNDPi_23,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x964++0x3 line.long 0x00 "DMA4_COLORi_23,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x954++0x3 line.long 0x00 "DMA4_CSACi_23,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x930++0x3 line.long 0x00 "DMA4_CSDPi_23,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x944++0x3 line.long 0x00 "DMA4_CSEIi_23,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x948++0x3 line.long 0x00 "DMA4_CSFIi_23,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x92C++0x3 line.long 0x00 "DMA4_CSRi_23,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x93C++0x3 line.long 0x00 "DMA4_CSSAi_23,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_24" width 20. group.long 0x9D8++0x3 line.long 0x00 "DMA4_CCDNi_24," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0x9BC++0x3 line.long 0x00 "DMA4_CCENi_24,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0x9C0++0x3 line.long 0x00 "DMA4_CCFNi_24,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x980++0x3 line.long 0x00 "DMA4_CCRi_24,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x9B8++0x3 line.long 0x00 "DMA4_CDACi_24,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0x9AC++0x3 line.long 0x00 "DMA4_CDEIi_24,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0x9B0++0x3 line.long 0x00 "DMA4_CDFIi_24,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0x9D0++0x3 line.long 0x00 "DMA4_CDPi_24,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0x9A0++0x3 line.long 0x00 "DMA4_CDSAi_24,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x994++0x3 line.long 0x00 "DMA4_CENi_24,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x998++0x3 line.long 0x00 "DMA4_CFNi_24,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x988++0x3 line.long 0x00 "DMA4_CICRi_24,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x984++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_24,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x9D4++0x3 line.long 0x00 "DMA4_CNDPi_24,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x9C4++0x3 line.long 0x00 "DMA4_COLORi_24,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0x9B4++0x3 line.long 0x00 "DMA4_CSACi_24,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x990++0x3 line.long 0x00 "DMA4_CSDPi_24,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0x9A4++0x3 line.long 0x00 "DMA4_CSEIi_24,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0x9A8++0x3 line.long 0x00 "DMA4_CSFIi_24,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x98C++0x3 line.long 0x00 "DMA4_CSRi_24,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x99C++0x3 line.long 0x00 "DMA4_CSSAi_24,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_25" width 20. group.long 0xA38++0x3 line.long 0x00 "DMA4_CCDNi_25," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0xA1C++0x3 line.long 0x00 "DMA4_CCENi_25,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0xA20++0x3 line.long 0x00 "DMA4_CCFNi_25,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0x9E0++0x3 line.long 0x00 "DMA4_CCRi_25,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA18++0x3 line.long 0x00 "DMA4_CDACi_25,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0xA0C++0x3 line.long 0x00 "DMA4_CDEIi_25,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0xA10++0x3 line.long 0x00 "DMA4_CDFIi_25,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0xA30++0x3 line.long 0x00 "DMA4_CDPi_25,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0xA00++0x3 line.long 0x00 "DMA4_CDSAi_25,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0x9F4++0x3 line.long 0x00 "DMA4_CENi_25,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0x9F8++0x3 line.long 0x00 "DMA4_CFNi_25,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0x9E8++0x3 line.long 0x00 "DMA4_CICRi_25,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0x9E4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_25,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA34++0x3 line.long 0x00 "DMA4_CNDPi_25,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xA24++0x3 line.long 0x00 "DMA4_COLORi_25,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0xA14++0x3 line.long 0x00 "DMA4_CSACi_25,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0x9F0++0x3 line.long 0x00 "DMA4_CSDPi_25,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0xA04++0x3 line.long 0x00 "DMA4_CSEIi_25,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0xA08++0x3 line.long 0x00 "DMA4_CSFIi_25,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0x9EC++0x3 line.long 0x00 "DMA4_CSRi_25,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0x9FC++0x3 line.long 0x00 "DMA4_CSSAi_25,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_26" width 20. group.long 0xA98++0x3 line.long 0x00 "DMA4_CCDNi_26," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0xA7C++0x3 line.long 0x00 "DMA4_CCENi_26,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0xA80++0x3 line.long 0x00 "DMA4_CCFNi_26,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0xA40++0x3 line.long 0x00 "DMA4_CCRi_26,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA78++0x3 line.long 0x00 "DMA4_CDACi_26,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0xA6C++0x3 line.long 0x00 "DMA4_CDEIi_26,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0xA70++0x3 line.long 0x00 "DMA4_CDFIi_26,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0xA90++0x3 line.long 0x00 "DMA4_CDPi_26,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0xA60++0x3 line.long 0x00 "DMA4_CDSAi_26,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0xA54++0x3 line.long 0x00 "DMA4_CENi_26,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0xA58++0x3 line.long 0x00 "DMA4_CFNi_26,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0xA48++0x3 line.long 0x00 "DMA4_CICRi_26,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0xA44++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_26,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA94++0x3 line.long 0x00 "DMA4_CNDPi_26,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xA84++0x3 line.long 0x00 "DMA4_COLORi_26,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0xA74++0x3 line.long 0x00 "DMA4_CSACi_26,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0xA50++0x3 line.long 0x00 "DMA4_CSDPi_26,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0xA64++0x3 line.long 0x00 "DMA4_CSEIi_26,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0xA68++0x3 line.long 0x00 "DMA4_CSFIi_26,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0xA4C++0x3 line.long 0x00 "DMA4_CSRi_26,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0xA5C++0x3 line.long 0x00 "DMA4_CSSAi_26,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_27" width 20. group.long 0xAF8++0x3 line.long 0x00 "DMA4_CCDNi_27," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0xADC++0x3 line.long 0x00 "DMA4_CCENi_27,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0xAE0++0x3 line.long 0x00 "DMA4_CCFNi_27,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0xAA0++0x3 line.long 0x00 "DMA4_CCRi_27,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAD8++0x3 line.long 0x00 "DMA4_CDACi_27,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0xACC++0x3 line.long 0x00 "DMA4_CDEIi_27,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0xAD0++0x3 line.long 0x00 "DMA4_CDFIi_27,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0xAF0++0x3 line.long 0x00 "DMA4_CDPi_27,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0xAC0++0x3 line.long 0x00 "DMA4_CDSAi_27,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0xAB4++0x3 line.long 0x00 "DMA4_CENi_27,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0xAB8++0x3 line.long 0x00 "DMA4_CFNi_27,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0xAA8++0x3 line.long 0x00 "DMA4_CICRi_27,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0xAA4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_27,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAF4++0x3 line.long 0x00 "DMA4_CNDPi_27,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xAE4++0x3 line.long 0x00 "DMA4_COLORi_27,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0xAD4++0x3 line.long 0x00 "DMA4_CSACi_27,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0xAB0++0x3 line.long 0x00 "DMA4_CSDPi_27,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0xAC4++0x3 line.long 0x00 "DMA4_CSEIi_27,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0xAC8++0x3 line.long 0x00 "DMA4_CSFIi_27,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0xAAC++0x3 line.long 0x00 "DMA4_CSRi_27,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0xABC++0x3 line.long 0x00 "DMA4_CSSAi_27,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_28" width 20. group.long 0xB58++0x3 line.long 0x00 "DMA4_CCDNi_28," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0xB3C++0x3 line.long 0x00 "DMA4_CCENi_28,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0xB40++0x3 line.long 0x00 "DMA4_CCFNi_28,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0xB00++0x3 line.long 0x00 "DMA4_CCRi_28,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB38++0x3 line.long 0x00 "DMA4_CDACi_28,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0xB2C++0x3 line.long 0x00 "DMA4_CDEIi_28,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0xB30++0x3 line.long 0x00 "DMA4_CDFIi_28,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0xB50++0x3 line.long 0x00 "DMA4_CDPi_28,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0xB20++0x3 line.long 0x00 "DMA4_CDSAi_28,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0xB14++0x3 line.long 0x00 "DMA4_CENi_28,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0xB18++0x3 line.long 0x00 "DMA4_CFNi_28,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0xB08++0x3 line.long 0x00 "DMA4_CICRi_28,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0xB04++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_28,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB54++0x3 line.long 0x00 "DMA4_CNDPi_28,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xB44++0x3 line.long 0x00 "DMA4_COLORi_28,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0xB34++0x3 line.long 0x00 "DMA4_CSACi_28,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0xB10++0x3 line.long 0x00 "DMA4_CSDPi_28,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0xB24++0x3 line.long 0x00 "DMA4_CSEIi_28,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0xB28++0x3 line.long 0x00 "DMA4_CSFIi_28,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0xB0C++0x3 line.long 0x00 "DMA4_CSRi_28,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0xB1C++0x3 line.long 0x00 "DMA4_CSSAi_28,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_29" width 20. group.long 0xBB8++0x3 line.long 0x00 "DMA4_CCDNi_29," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0xB9C++0x3 line.long 0x00 "DMA4_CCENi_29,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0xBA0++0x3 line.long 0x00 "DMA4_CCFNi_29,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0xB60++0x3 line.long 0x00 "DMA4_CCRi_29,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB98++0x3 line.long 0x00 "DMA4_CDACi_29,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0xB8C++0x3 line.long 0x00 "DMA4_CDEIi_29,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0xB90++0x3 line.long 0x00 "DMA4_CDFIi_29,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0xBB0++0x3 line.long 0x00 "DMA4_CDPi_29,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0xB80++0x3 line.long 0x00 "DMA4_CDSAi_29,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0xB74++0x3 line.long 0x00 "DMA4_CENi_29,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0xB78++0x3 line.long 0x00 "DMA4_CFNi_29,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0xB68++0x3 line.long 0x00 "DMA4_CICRi_29,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0xB64++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_29,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xBB4++0x3 line.long 0x00 "DMA4_CNDPi_29,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xBA4++0x3 line.long 0x00 "DMA4_COLORi_29,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0xB94++0x3 line.long 0x00 "DMA4_CSACi_29,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0xB70++0x3 line.long 0x00 "DMA4_CSDPi_29,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0xB84++0x3 line.long 0x00 "DMA4_CSEIi_29,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0xB88++0x3 line.long 0x00 "DMA4_CSFIi_29,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0xB6C++0x3 line.long 0x00 "DMA4_CSRi_29,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0xB7C++0x3 line.long 0x00 "DMA4_CSSAi_29,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_30" width 20. group.long 0xC18++0x3 line.long 0x00 "DMA4_CCDNi_30," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0xBFC++0x3 line.long 0x00 "DMA4_CCENi_30,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0xC00++0x3 line.long 0x00 "DMA4_CCFNi_30,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0xBC0++0x3 line.long 0x00 "DMA4_CCRi_30,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xBF8++0x3 line.long 0x00 "DMA4_CDACi_30,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0xBEC++0x3 line.long 0x00 "DMA4_CDEIi_30,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0xBF0++0x3 line.long 0x00 "DMA4_CDFIi_30,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0xC10++0x3 line.long 0x00 "DMA4_CDPi_30,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0xBE0++0x3 line.long 0x00 "DMA4_CDSAi_30,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0xBD4++0x3 line.long 0x00 "DMA4_CENi_30,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0xBD8++0x3 line.long 0x00 "DMA4_CFNi_30,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0xBC8++0x3 line.long 0x00 "DMA4_CICRi_30,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0xBC4++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_30,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC14++0x3 line.long 0x00 "DMA4_CNDPi_30,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xC04++0x3 line.long 0x00 "DMA4_COLORi_30,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0xBF4++0x3 line.long 0x00 "DMA4_CSACi_30,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0xBD0++0x3 line.long 0x00 "DMA4_CSDPi_30,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0xBE4++0x3 line.long 0x00 "DMA4_CSEIi_30,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0xBE8++0x3 line.long 0x00 "DMA4_CSFIi_30,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0xBCC++0x3 line.long 0x00 "DMA4_CSRi_30,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0xBDC++0x3 line.long 0x00 "DMA4_CSSAi_30,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end tree "DMA_Channel_31" width 20. group.long 0xC78++0x3 line.long 0x00 "DMA4_CCDNi_31," hexmask.long.word 0x00 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." group.long 0xC5C++0x3 line.long 0x00 "DMA4_CCENi_31,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" group.long 0xC60++0x3 line.long 0x00 "DMA4_CCFNi_31,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" group.long 0xC20++0x3 line.long 0x00 "DMA4_CCRi_31,Channel Control Register" bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side - . - ." "0,1" bitfld.long 0x00 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized. - . - ." "0,1" bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Specifyes that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request - . - ." "0,1" textline " " bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode - . - ." "0,1" bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode - . - ." "0,1" bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as two msb, with the five bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x00 18. " BS ,Block synchronization This bit used in conjuntion with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable - . - ." "0,1" bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel. - . - . - . - ." "Constant_address_mode,1,2,3" bitfld.long 0x00 10. " WR_ACTIVE ,Indicates if the channel write context is active or not - . - ." "0,1" textline " " bitfld.long 0x00 9. " RD_ACTIVE ,Indicates if the channel read context is active or not - . - ." "0,1" bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit - . - ." "0,1" bitfld.long 0x00 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel. - . - ." "0,1" textline " " bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side - . - ." "0,1" bitfld.long 0x00 5. " FS ,Frame synchronization This bit used in conjuntion with the BS to see how the DMA request is serviced in a synchronized transfer FS=0 and BS=0: An element is transferred once a DMA request is made. FS=0 and.." "0,1" bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjuntion with the second_level_ synchro_control_upper (as two msb) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC58++0x3 line.long 0x00 "DMA4_CDACi_31,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.long 0xC4C++0x3 line.long 0x00 "DMA4_CDEIi_31,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" group.long 0xC50++0x3 line.long 0x00 "DMA4_CDFIi_31,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16].." group.long 0xC70++0x3 line.long 0x00 "DMA4_CDPi_31,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3 - . - ." "No_fast-start_mode,1" bitfld.long 0x00 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode - . - . - . - ." "0,1,Undefined,Undefined" bitfld.long 0x00 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer. - . - ." "0,1" textline " " bitfld.long 0x00 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type - . - . - . - . - . - . - . - ." "Undefined,1,2,3,Undefined,Undefined,Undefined,Undefined" bitfld.long 0x00 2.--3. " SRC_VALID ,Source address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" bitfld.long 0x00 0.--1. " DEST_VALID ,Destination address valid - . - . - . - ." "0,1,2,Undefined_addressing_mode" group.long 0xC40++0x3 line.long 0x00 "DMA4_CDSAi_31,Channel Destination Start Address" hexmask.long 0x00 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.long 0xC34++0x3 line.long 0x00 "DMA4_CENi_31,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" group.long 0xC38++0x3 line.long 0x00 "DMA4_CFNi_31,Channel Frame Number" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" group.long 0xC28++0x3 line.long 0x00 "DMA4_CICRi_31,Channel Interrupt Control Register" bitfld.long 0x00 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt - . - ." "0,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt - . - ." "0,1" bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt - . - ." "0,1" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt - . - ." "0,1" bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable (start of last frame) - . - ." "0,1" bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame) - . - ." "0,1" textline " " bitfld.long 0x00 2. " HALF_IE ,Enables or disables the half frame interrupt. - . - ." "0,1" bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision) - . - ." "0,1" group.long 0xC24++0x3 line.long 0x00 "DMA4_CLNK_CTRLi_31,Channel Link Control Register" bitfld.long 0x00 15. " ENABLE_LNK ,Enables or disable the channel linking. - . - ." "0,1" bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC74++0x3 line.long 0x00 "DMA4_CNDPi_31,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xC64++0x3 line.long 0x00 "DMA4_COLORi_31,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data .." rgroup.long 0xC54++0x3 line.long 0x00 "DMA4_CSACi_31,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be correupted." hexmask.long 0x00 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.long 0xC30++0x3 line.long 0x00 "DMA4_CSDPi_31,Channel Source Destination Parameters" bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control - . - ." "0,1" bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control - . - ." "0,1" textline " " bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock - . - ." "Endianness_adapt,Endianness_lock" bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting - . - . - . - ." "0,Write_(Posted),2,Undefined" bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" textline " " bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data. - . - ." "0,1" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed - . - . - . - ." "single_access,1,2,3" bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data. - . - ." "0,1" textline " " bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel. - . - . - . - ." "8_bits_scalar,16_bits_scalar,32_bits_scalar,?..." group.long 0xC44++0x3 line.long 0x00 "DMA4_CSEIi_31,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" group.long 0xC48++0x3 line.long 0x00 "DMA4_CSFIi_31,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x00 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused.." group.long 0xC2C++0x3 line.long 0x00 "DMA4_CSRi_31,Channel Status Register" bitfld.long 0x00 14. " SUPER_BLOCK ,End of Super block event" "0,1" bitfld.long 0x00 12. " DRAIN_END ,End of channel draining" "0,1" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event - . - . - . - ." "No_address_error,1" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 8. " TRANS_ERR ,Transaction error event - . - . - . - ." "No_transaction_error,1" bitfld.long 0x00 7. " PKT ,End of Packet transfer - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 6. " SYNC ,Synchronization status of a channel. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 5. " BLOCK ,End of block event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 4. " LAST ,Last frame (start of last frame) - . - . - . - ." "Status_bit_unchanged,1" textline " " bitfld.long 0x00 3. " FRAME ,End of frame event - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 2. " HALF ,Half of frame event. - . - . - . - ." "Status_bit_unchanged,1" bitfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer - . - . - . - ." "Status_bit_unchanged,1" group.long 0xC3C++0x3 line.long 0x00 "DMA4_CSSAi_31,Channel Source Start Address" hexmask.long 0x00 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" tree.end textline "" width 20. rgroup.long 0x0++0x3 line.long 0x00 "DMA4_REVISION,This register contains the DMA revision code" hexmask.long 0x00 0.--31. 1. " REVISION ,Reserved, Write 0's for future compatibility. Read returns 0" rgroup.long 0x28++0x3 line.long 0x00 "DMA4_SYSSTATUS,The register provides status information about the module excluding the interrupt status information (see interrupt status register)" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "OnGoing,Completed" group.long 0x2C++0x3 line.long 0x00 "DMA4_OCP_SYSCONFIG,DMA system configuration register" bitfld.long 0x00 12.--13. " MIDLEMODE ,Read write power management, standby/wait control - . - . - . - ." "Force,No,Smart,?..." bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activities during wake-up Bit 8: Interface clock 0x0: Interface clock can be switched-off Bit 9: Functional clock 0x0: Functional clock can be switched-off" "0,1,2,3" bitfld.long 0x00 5. " EMUFREE ,Enable sensitivity to MSuspend - . - ." "Frozen,Ignored" textline " " bitfld.long 0x00 3.--4. " SIDLEMODE ,Configuration port power management, Idle req/ack control - . - . - . - ." "Force,No,Smart,?..." bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy - . - ." "Free_Running,Clock_Gating" rgroup.long 0x64++0x3 line.long 0x00 "DMA4_CAPS_0,DMA Capabilities Register 0 LSW" bitfld.long 0x00 21. " LINK_LIST_CPBLTY_TYPE4 ,Link List capability for type4 descriptor capability" "Low,High" bitfld.long 0x00 20. " LINK_LIST_CPBLTY_TYPE123 ,Link List capability for type123 descriptor capability" "Low,High" bitfld.long 0x00 19. " CONST_FILL_CPBLTY ,Constant_Fill_Capability - . - ." "No_LCH,Any_LCH" textline " " bitfld.long 0x00 18. " TRANSPARENT_BLT_CPBLTY ,Transparent_BLT_Capability - . - ." "No_LCH,Any_LCH" rgroup.long 0x6C++0x3 line.long 0x00 "DMA4_CAPS_2,DMA Capabilities Register 2" bitfld.long 0x00 8. " SEPARATE_SRC_AND_DST_INDEX_CPBLTY ,Separate_source/destination_index_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 7. " DST_DOUBLE_INDEX_ADRS_CPBLTY ,Destination_double_index_address_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 6. " DST_SINGLE_INDEX_ADRS_CPBLTY ,Destination_single_index_address_capability - . - ." "Not_Supported,Supported" textline " " bitfld.long 0x00 5. " DST_POST_INCRMNT_ADRS_CPBLTY ,Destination_post_increment_address_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 4. " DST_CONST_ADRS_CPBLTY ,Destination_constant_address_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 3. " SRC_DOUBLE_INDEX_ADRS_CPBLTY ,Source_double_index_address_capability - . - ." "Not_Supported,Supported" textline " " bitfld.long 0x00 2. " SRC_SINGLE_INDEX_ADRS_CPBLTY ,Source_single_index_address_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 1. " SRC_POST_INCREMENT_ADRS_CPBLTY ,Source_post_increment_address_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 0. " SRC_CONST_ADRS_CPBLTY ,Source_constant_address_capability - . - ." "Not_Supported,Supported" rgroup.long 0x70++0x3 line.long 0x00 "DMA4_CAPS_3,DMA Capabilities Register 3" bitfld.long 0x00 7. " BLOCK_SYNCHR_CPBLTY ,Block_synchronization_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 6. " PKT_SYNCHR_CPBLTY ,Packet_synchronization_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 5. " CHANNEL_CHANINIG_CPBLTY ,Channel_Chaninig_capability - . - ." "Not_Supported,Supported" textline " " bitfld.long 0x00 4. " CHANNEL_INTERLEAVE_CPBLTY ,Channel_interleave_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 1. " FRAME_SYNCHR_CPBLTY ,Frame_synchronization_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 0. " ELMNT_SYNCHR_CPBLTY ,Element_synchronization_capability - . - ." "Not_Supported,Supported" rgroup.long 0x74++0x3 line.long 0x00 "DMA4_CAPS_4,DMA Capabilities Register 4" bitfld.long 0x00 14. " EOSB_INTERRUPT_CPBLTY ,End of Super Block detection capability." "Not_Supported,Supported" bitfld.long 0x00 12. " DRAIN_END_INTERRUPT_CPBLTY ,Drain End detection capability." "Not_Supported,Supported" bitfld.long 0x00 11. " MISALIGNED_ADRS_ERR_INTERRUPT_CPBLTY ,Misaligned error detection capability." "Not_Supported,Supported" textline " " bitfld.long 0x00 10. " SUPERVISOR_ERR_INTERRUPT_CPBLTY ,Supervisor error detection capability." "Not_Supported,Supported" bitfld.long 0x00 8. " TRANS_ERR_INTERRUPT_CPBLTY ,Transaction error detection capability." "Not_Supported,Supported" bitfld.long 0x00 7. " PKT_INTERRUPT_CPBLTY ,End of Packet detection capability. - . - ." "Not_Supported,Supported" textline " " bitfld.long 0x00 6. " SYNC_STATUS_CPBLTY ,Sync_status_capability - . - ." "Not_Supported,Supported" bitfld.long 0x00 5. " BLOCK_INTERRUPT_CPBLTY ,End of block detection capability. - . - ." "Not_Supported,Supported" bitfld.long 0x00 4. " LAST_FRAME_INTERRUPT_CPBLTY ,Start of last frame detection capability. - . - ." "Not_Supported,Supported" textline " " bitfld.long 0x00 3. " FRAME_INTERRUPT_CPBLTY ,End of frame detection capability. - . - ." "Not_Supported,Supported" bitfld.long 0x00 2. " HALF_FRAME_INTERRUPT_CPBLTY ,Detection capability of the half of frame end. - . - ." "Not_Supported,Supported" bitfld.long 0x00 1. " EVENT_DROP_INTERRUPT_CPBLTY ,Request collision detection capability. - . - ." "Not_Supported,Supported" group.long 0x78++0x3 line.long 0x00 "DMA4_GCR," bitfld.long 0x00 24. " CHANNEL_ID_GATE ,Gates the Channel ID bus monitoring on both Read and Write ports 0x0: Gates the Channel ID qualifiers on both Read and Write Ports 0x1: Does not gate the Channel ID qualifiers on both Read and Write Ports" "0,1" hexmask.long.byte 0x00 16.--23. 1. " ARBITRATION_RATE ,Arbitration switching rate between prioritized and regular channel queues" bitfld.long 0x00 14.--15. " HI_LO_FIFO_BUDGET ,Allow to have a separate Global FIFO budget for high and low priority channels. For Hi priority Channel: (Per_channel_Maximum FIFO depth + 1) x Number of active High priority Channel =&lt; High Bud.." "No_budget,75%/25%,25%/75%,50%/50%" textline " " bitfld.long 0x00 12.--13. " HI_THREAD_RESERVED ,Allow thread reservation for high priority channel on both read and write ports. - . - . - . - ." "No_ThreadID_Rsrv.,One_ThreadID_Rsrv.,Two_ThreadID_Rsrv.,Three_ThreadID_Rsrv." hexmask.long.byte 0x00 0.--7. 1. " MAX_CHANNEL_FIFO_DEPTH ,Maximum FIFO depth allocated to one logical channel. Maximum FIFO depth can not be 0x0. It should be at least 0x1 or greater. Note that If channel limit is less than destination burst size enough data will not be accum.." tree.end tree.end tree.open "Control_Module" tree "SYSCTRL_PADCONF_WKUP" base ad:0x4A31E000 width 56. rgroup.long 0x0++0x3 line.long 0x00 "CONTROL_PADCONF_WKUP_REVISION,Control module revision identifier Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "CONTROL_PADCONF_WKUP_HWINFO,Information about the IP module hardware configuration that is, typically the module HDL generics (if any). Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " IP_HWINFO ,IP-module dependent" group.long 0x10++0x3 line.long 0x00 "CONTROL_PADCONF_WKUP_SYSCONFIG,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 2.--3. " IP_SYSCONFIG_IDLEMODE ,Select the local clock-gating strategy - . - . 0x2,0x3: Clock is automatically gated when there is no access to the Control Module through L4-interconnect. - ." "0,1,2,3" group.long 0x40++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_GPIO_WK0_PAD1_GPIO_WK1,Register control for Pads gpio_wk0 and gpio_wk1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPIO_WK1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPIO_WK1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " GPIO_WK1_INPUTENABLE ,Input enable value for pad gpio_wk1 - . - ." "0,1" textline " " bitfld.long 0x00 20. " GPIO_WK1_PULLTYPESELECT ,pullup/down selection for pad gpio_wk1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " GPIO_WK1_PULLUDENABLE ,pullup/down enable for pad gpio_wk1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPIO_WK1_MUXMODE ,Functional multiplexing selection for pad gpio_wk1 - . - . - . - ." "Reserved,1,2,Select_gpio_wk1,4,5,Select_hw_dbg2,Select_safe_mode" textline " " bitfld.long 0x00 15. " GPIO_WK0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " GPIO_WK0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " GPIO_WK0_INPUTENABLE ,Input enable value for pad gpio_wk0 - . - ." "0,1" textline " " bitfld.long 0x00 4. " GPIO_WK0_PULLTYPESELECT ,pullup/down selection for pad gpio_wk0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPIO_WK0_PULLUDENABLE ,pullup/down enable for pad gpio_wk0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " GPIO_WK0_MUXMODE ,Functional multiplexing selection for pad gpio_wk0 - . - . - . - ." "Reserved,1,2,Select_gpio_wk0,4,5,Select_hw_dbg1,Select_safe_mode" group.long 0x44++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_GPIO_WK2_PAD1_GPIO_WK3,Register control for Pads gpio_wk2 and gpio_wk3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPIO_WK3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPIO_WK3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " GPIO_WK3_INPUTENABLE ,Input enable value for pad gpio_wk3 - . - ." "0,1" textline " " bitfld.long 0x00 20. " GPIO_WK3_PULLTYPESELECT ,pullup/down selection for pad gpio_wk3 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " GPIO_WK3_PULLUDENABLE ,pullup/down enable for pad gpio_wk3 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPIO_WK3_MUXMODE ,Functional multiplexing selection for pad gpio_wk3 - . - . - . - ." "Reserved,1,2,Select_gpio_wk3,4,5,Select_hw_dbg4,Select_safe_mode" textline " " bitfld.long 0x00 15. " GPIO_WK2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " GPIO_WK2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " GPIO_WK2_INPUTENABLE ,Input enable value for pad gpio_wk2 - . - ." "0,1" textline " " bitfld.long 0x00 4. " GPIO_WK2_PULLTYPESELECT ,pullup/down selection for pad gpio_wk2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPIO_WK2_PULLUDENABLE ,pullup/down enable for pad gpio_wk2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " GPIO_WK2_MUXMODE ,Functional multiplexing selection for pad gpio_wk2 - . - . - . - ." "Reserved,1,2,Select_gpio_wk2,4,5,Select_hw_dbg3,Select_safe_mode" group.long 0x48++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_GPIO_WK4_PAD1_SR_SCL,Register control for Pads gpio_wk4 and sr_scl Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SR_SCL_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SR_SCL_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " SR_SCL_INPUTENABLE ,Input enable value for pad sr_scl - . - ." "0,1" textline " " bitfld.long 0x00 20. " SR_SCL_PULLTYPESELECT ,pullup/down selection for pad sr_scl - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " SR_SCL_PULLUDENABLE ,pullup/down enable for pad sr_scl - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 15. " GPIO_WK4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPIO_WK4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " GPIO_WK4_INPUTENABLE ,Input enable value for pad gpio_wk4 - . - ." "0,1" bitfld.long 0x00 4. " GPIO_WK4_PULLTYPESELECT ,pullup/down selection for pad gpio_wk4 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 3. " GPIO_WK4_PULLUDENABLE ,pullup/down enable for pad gpio_wk4 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " GPIO_WK4_MUXMODE ,Functional multiplexing selection for pad gpio_wk4 - . - . - . - ." "Reserved,1,2,Select_gpio_wk4,4,5,Select_hw_dbg5,Select_safe_mode" group.long 0x4C++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_SR_SDA_PAD1_FREF_XTAL_IN,Register control for Pads sr_sda and fref_xtal_in Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 16.--18. " FREF_XTAL_IN_MUXMODE ,Functional multiplexing selection for pad fref_xtal_in - . - ." "Select_fref_xtal_in,1,2,3,Select_c2c_wakereqin,5,6,7" bitfld.long 0x00 15. " SR_SDA_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " SR_SDA_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" textline " " bitfld.long 0x00 8. " SR_SDA_INPUTENABLE ,Input enable value for pad sr_sda - . - ." "0,1" bitfld.long 0x00 4. " SR_SDA_PULLTYPESELECT ,pullup/down selection for pad sr_sda - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SR_SDA_PULLUDENABLE ,pullup/down enable for pad sr_sda - . - ." "pullup/down_disabled,pullup/down_enabled" group.long 0x50++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_FREF_SLICER_IN_PAD1_FREF_CLK_IOREQ,Register control for Pads fref_slicer_in and fref_clk_ioreq Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " FREF_CLK_IOREQ_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " FREF_CLK_IOREQ_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " FREF_CLK_IOREQ_INPUTENABLE ,Input enable value for pad fref_clk_ioreq - . - ." "0,1" textline " " bitfld.long 0x00 20. " FREF_CLK_IOREQ_PULLTYPESELECT ,pullup/down selection for pad fref_clk_ioreq - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " FREF_CLK_IOREQ_PULLUDENABLE ,pullup/down enable for pad fref_clk_ioreq - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " FREF_SLICER_IN_MUXMODE ,Functional multiplexing selection for pad fref_slicer_in - . - . - . - ." "Select_fref_slicer_in,1,2,Select_gpi_wk5,Select_c2c_wakereqin,5,6,Select_safe_mode" group.long 0x54++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_FREF_CLK0_OUT_PAD1_FREF_CLK3_REQ,Register control for Pads fref_clk0_out and fref_clk3_req Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " FREF_CLK3_REQ_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " FREF_CLK3_REQ_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " FREF_CLK3_REQ_INPUTENABLE ,Input enable value for pad fref_clk3_req - . - ." "0,1" textline " " bitfld.long 0x00 20. " FREF_CLK3_REQ_PULLTYPESELECT ,pullup/down selection for pad fref_clk3_req - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " FREF_CLK3_REQ_PULLUDENABLE ,pullup/down enable for pad fref_clk3_req - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " FREF_CLK3_REQ_MUXMODE ,Functional multiplexing selection for pad fref_clk3_req - . - . - . - . - . - . - . - ." "Select_fref_clk3_req,Select_fref_clk1_req,Reserved,Select_gpio_wk30,Select_c2c_wakereqin,Select_sdmmc2_dat4,Select_hw_dbg7,Select_safe_mode" textline " " bitfld.long 0x00 15. " FREF_CLK0_OUT_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " FREF_CLK0_OUT_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " FREF_CLK0_OUT_INPUTENABLE ,Input enable value for pad fref_clk0_out - . - ." "0,1" textline " " bitfld.long 0x00 4. " FREF_CLK0_OUT_PULLTYPESELECT ,pullup/down selection for pad fref_clk0_out - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " FREF_CLK0_OUT_PULLUDENABLE ,pullup/down enable for pad fref_clk0_out - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " FREF_CLK0_OUT_MUXMODE ,Functional multiplexing selection for pad fref_clk0_out - . - . - . - . - . - . - ." "Select_fref_clk0_out,Select_fref_clk1_req,Reserved,Select_gpio_wk6,4,Select_sdmmc2_dat7,Select_hw_dbg6,Select_safe_mode" group.long 0x58++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_FREF_CLK3_OUT_PAD1_FREF_CLK4_REQ,Register control for Pads fref_clk3_out and fref_clk4_req Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " FREF_CLK4_REQ_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " FREF_CLK4_REQ_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " FREF_CLK4_REQ_INPUTENABLE ,Input enable value for pad fref_clk4_req - . - ." "0,1" textline " " bitfld.long 0x00 20. " FREF_CLK4_REQ_PULLTYPESELECT ,pullup/down selection for pad fref_clk4_req - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " FREF_CLK4_REQ_PULLUDENABLE ,pullup/down enable for pad fref_clk4_req - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " FREF_CLK4_REQ_MUXMODE ,Functional multiplexing selection for pad fref_clk4_req - . - . - . - . - ." "Select_fref_clk4_req,Select_fref_clk5_out,2,Select_gpio_wk7,4,Select_sdmmc2_dat6,Select_hw_dbg9,7" textline " " bitfld.long 0x00 15. " FREF_CLK3_OUT_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " FREF_CLK3_OUT_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " FREF_CLK3_OUT_INPUTENABLE ,Input enable value for pad fref_clk3_out - . - ." "0,1" textline " " bitfld.long 0x00 4. " FREF_CLK3_OUT_PULLTYPESELECT ,pullup/down selection for pad fref_clk3_out - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " FREF_CLK3_OUT_PULLUDENABLE ,pullup/down enable for pad fref_clk3_out - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " FREF_CLK3_OUT_MUXMODE ,Functional multiplexing selection for pad fref_clk3_out - . - . - . - . - . - . - . - ." "Select_fref_clk3_out,Select_fref_clk2_req,Reserved,Select_gpio_wk31,Select_c2c_wakereqout,Select_sdmmc2_dat5,Select_hw_dbg8,Select_safe_mode" group.long 0x5C++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_FREF_CLK4_OUT_PAD1_SYS_32K,Register control for Pads fref_clk4_out and sys_32k Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SYS_32K_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SYS_32K_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " SYS_32K_INPUTENABLE ,Input enable value for pad sys_32k - . - ." "0,1" textline " " bitfld.long 0x00 20. " SYS_32K_PULLTYPESELECT ,pullup/down selection for pad sys_32k - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " SYS_32K_PULLUDENABLE ,pullup/down enable for pad sys_32k - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 15. " FREF_CLK4_OUT_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " FREF_CLK4_OUT_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " FREF_CLK4_OUT_INPUTENABLE ,Input enable value for pad fref_clk4_out - . - ." "0,1" bitfld.long 0x00 4. " FREF_CLK4_OUT_PULLTYPESELECT ,pullup/down selection for pad fref_clk4_out - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 3. " FREF_CLK4_OUT_PULLUDENABLE ,pullup/down enable for pad fref_clk4_out - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " FREF_CLK4_OUT_MUXMODE ,Functional multiplexing selection for pad fref_clk4_out - . - . - ." "Select_fref_clk4_out,1,2,Select_gpio_wk8,4,5,Select_hw_dbg10,7" group.long 0x60++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_SYS_NRESPWRON_PAD1_SYS_NRESWARM,Register control for Pads sys_nrespwron and sys_nreswarm Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SYS_NRESWARM_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SYS_NRESWARM_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 4. " SYS_NRESPWRON_PULLTYPESELECT ,pullup/down selection for pad sys_nrespwron - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 3. " SYS_NRESPWRON_PULLUDENABLE ,pullup/down enable for pad sys_nrespwron - . - ." "pullup/down_disabled,pullup/down_enabled" group.long 0x64++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_SYS_PWR_REQ_PAD1_SYS_PWRON_RESET_OUT,Register control for Pads sys_pwr_req and sys_pwron_reset_out Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SYS_PWRON__RESET_OUT_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SYS_PWRON__RESET_OUT_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " SYS_PWRON__RESET_OUT_INPUTENABLE ,Input enable value for pad sys_pwron_reset_out - . - ." "0,1" textline " " bitfld.long 0x00 20. " SYS_PWRON__RESET_OUT_PULLTYPESELECT ,pullup/down selection for pad sys_pwron_reset_out - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " SYS_PWRON__RESET_OUT_PULLUDENABLE ,pullup/down enable for pad sys_pwron_reset_out - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SYS_PWRON__RESET_OUT_MUXMODE ,Functional multiplexing selection for pad sys_pwron_reset_out - . - . - ." "0,1,2,Select_gpio_wk29,4,5,Select_hw_dbg11,7" textline " " bitfld.long 0x00 15. " SYS_PWR__REQ_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " SYS_PWR__REQ_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " SYS_PWR__REQ_INPUTENABLE ,Input enable value for pad sys_pwr_req - . - ." "0,1" textline " " bitfld.long 0x00 4. " SYS_PWR__REQ_PULLTYPESELECT ,pullup/down selection for pad sys_pwr_req - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SYS_PWR__REQ_PULLUDENABLE ,pullup/down enable for pad sys_pwr_req - . - ." "pullup/down_disabled,pullup/down_enabled" group.long 0x68++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_SYS_BOOT6_PAD1_SYS_BOOT7,Register control for Pads sys_boot6 and sys_boot7 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SYS_BOOT7_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SYS_BOOT7_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " SYS_BOOT7_INPUTENABLE ,Input enable value for pad sys_boot7 - . - ." "0,1" textline " " bitfld.long 0x00 20. " SYS_BOOT7_PULLTYPESELECT ,pullup/down selection for pad sys_boot7 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " SYS_BOOT7_PULLUDENABLE ,pullup/down enable for pad sys_boot7 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SYS_BOOT7_MUXMODE ,Functional multiplexing selection for pad sys_boot7 - . - . - . - . - ." "Select_sys_boot7,Select_dpm_emu19,2,Select_gpio_wk10,4,5,Select_hw_dbg13,Select_safe_mode" textline " " bitfld.long 0x00 15. " SYS_BOOT6_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " SYS_BOOT6_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " SYS_BOOT6_INPUTENABLE ,Input enable value for pad sys_boot6 - . - ." "0,1" textline " " bitfld.long 0x00 4. " SYS_BOOT6_PULLTYPESELECT ,pullup/down selection for pad sys_boot6 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SYS_BOOT6_PULLUDENABLE ,pullup/down enable for pad sys_boot6 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " SYS_BOOT6_MUXMODE ,Functional multiplexing selection for pad sys_boot6 - . - . - . - . - . - ." "Select_sys_boot6,Select_dpm_emu18,2,Select_gpio_wk9,Select_c2c_wakereqout,5,Select_hw_dbg12,Select_safe_mode" group.long 0x6C++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_JTAG_NTRST_PAD1_JTAG_TCK,Register control for Pads jtag_ntrst and jtag_tck Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " JTAG_TCK_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " JTAG_TCK_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " JTAG_TCK_INPUTENABLE ,Input enable value for pad jtag_tck - . - ." "0,1" textline " " bitfld.long 0x00 20. " JTAG_TCK_PULLTYPESELECT ,pullup/down selection for pad jtag_tck - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " JTAG_TCK_PULLUDENABLE ,pullup/down enable for pad jtag_tck - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " JTAG_TCK_MUXMODE ,Functional multiplexing selection for pad jtag_tck - . - ." "Select_jtag_tck,1,2,3,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " JTAG_NTRST_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " JTAG_NTRST_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " JTAG_NTRST_INPUTENABLE ,Input enable value for pad jtag_ntrst - . - ." "0,1" textline " " bitfld.long 0x00 4. " JTAG_NTRST_PULLTYPESELECT ,pullup/down selection for pad jtag_ntrst - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " JTAG_NTRST_PULLUDENABLE ,pullup/down enable for pad jtag_ntrst - . - ." "pullup/down_disabled,pullup/down_enabled" group.long 0x70++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_JTAG_RTCK_PAD1_JTAG_TMS_TMSC,Register control for Pads jtag_rtck and jtag_tms_tmsc Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " JTAG_TMS_TMSC_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " JTAG_TMS_TMSC_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " JTAG_TMS_TMSC_INPUTENABLE ,Input enable value for pad jtag_tms_tmsc - . - ." "0,1" textline " " bitfld.long 0x00 16.--18. " JTAG_TMS_TMSC_MUXMODE ,Functional multiplexing selection for pad jtag_tms_tmsc - . - ." "Select_jtag_tms_tmsc,1,2,3,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " JTAG_RTCK_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " JTAG_RTCK_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" textline " " bitfld.long 0x00 4. " JTAG_RTCK_PULLTYPESELECT ,pullup/down selection for pad jtag_rtck - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " JTAG_RTCK_PULLUDENABLE ,pullup/down enable for pad jtag_rtck - . - ." "pullup/down_disabled,pullup/down_enabled" group.long 0x74++0x3 line.long 0x00 "CONTROL_WKUP_PAD0_JTAG_TDI_PAD1_JTAG_TDO,Register control for Pads jtag_tdi and jtag_tdo Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " JTAG_TDO_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " JTAG_TDO_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " JTAG_TDO_INPUTENABLE ,Input enable value for pad jtag_tdo - . - ." "0,1" textline " " bitfld.long 0x00 20. " JTAG_TDO_PULLTYPESELECT ,pullup/down selection for pad jtag_tdo - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " JTAG_TDO_PULLUDENABLE ,pullup/down enable for pad jtag_tdo - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 15. " JTAG_TDI_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " JTAG_TDI_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " JTAG_TDI_INPUTENABLE ,Input enable value for pad jtag_tdi - . - ." "0,1" bitfld.long 0x00 4. " JTAG_TDI_PULLTYPESELECT ,pullup/down selection for pad jtag_tdi - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 3. " JTAG_TDI_PULLUDENABLE ,pullup/down enable for pad jtag_tdi - . - ." "pullup/down_disabled,pullup/down_enabled" rgroup.long 0x7C++0x3 line.long 0x00 "CONTROL_WKUP_PADCONF_WAKEUPEVENT_0,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 24. " JTAG_TDO_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad jtag_tdo - . - ." "0,1" bitfld.long 0x00 23. " JTAG_TDI_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad jtag_tdi - . - ." "0,1" bitfld.long 0x00 22. " JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad jtag_tms_tmsc - . - ." "0,1" textline " " bitfld.long 0x00 21. " JTAG_RTCK_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad jtag_rtck - . - ." "0,1" bitfld.long 0x00 20. " JTAG_TCK_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad jtag_tck - . - ." "0,1" bitfld.long 0x00 19. " JTAG_NTRST_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad jtag_ntrst - . - ." "0,1" textline " " bitfld.long 0x00 18. " SYS_BOOT7_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_boot7 - . - ." "0,1" bitfld.long 0x00 17. " SYS_BOOT6_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_boot6 - . - ." "0,1" bitfld.long 0x00 16. " SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_pwron_reset_out - . - ." "0,1" textline " " bitfld.long 0x00 15. " SYS_PWR_REQ_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_pwr_req - . - ." "0,1" bitfld.long 0x00 14. " SYS_NRESWARM_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_nreswarm - . - ." "0,1" bitfld.long 0x00 13. " SYS_32K_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_32k - . - ." "0,1" textline " " bitfld.long 0x00 12. " FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad fref_clk4_out - . - ." "0,1" bitfld.long 0x00 11. " FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad fref_clk4_req - . - ." "0,1" bitfld.long 0x00 10. " FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad fref_clk3_out - . - ." "0,1" textline " " bitfld.long 0x00 9. " FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad fref_clk3_req - . - ." "0,1" bitfld.long 0x00 8. " FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad fref_clk0_out - . - ." "0,1" bitfld.long 0x00 7. " FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad fref_clk_ioreq - . - ." "0,1" textline " " bitfld.long 0x00 6. " SR_SDA_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sr_sda - . - ." "0,1" bitfld.long 0x00 5. " SR_SCL_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sr_scl - . - ." "0,1" bitfld.long 0x00 4. " GPIO_WK4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpio_wk4 - . - ." "0,1" textline " " bitfld.long 0x00 3. " GPIO_WK3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpio_wk3 - . - ." "0,1" bitfld.long 0x00 2. " GPIO_WK2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpio_wk2 - . - ." "0,1" bitfld.long 0x00 1. " GPIO_WK1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpio_wk1 - . - ." "0,1" textline " " bitfld.long 0x00 0. " GPIO_WK0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpio_wk0 - . - ." "0,1" group.long 0x5A0++0x3 line.long 0x00 "CONTROL_SMART1NOPMIO_PADCONF_0,SMART1 NOPM I/O control 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " FREF_DR0_SC ,Slew rate control for group fref_dr0 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 18.--19. " GPIO_DR7_SC ,Slew rate control for group gpio_dr7 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 14.--15. " DPM_DR0_SC ,Slew rate control for group dpm_dr0 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " GPIOWK4_DR0_SC ,Slew rate control for group gpiowk4_dr0 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" group.long 0x5A4++0x3 line.long 0x00 "CONTROL_SMART1NOPMIO_PADCONF_1,SMART1 NOPM I/O control 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " FREF_DR0_LB ,Load control for group fref_dr0 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 18.--19. " GPIO_DR7_LB ,Load control for group gpio_dr7 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 14.--15. " DPM_DR0_LB ,Load control for group dpm_dr0 - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " GPIOWK4_DR0_LB ,Load control for group gpiowk4_dr0 - . - . - . - ." "0,1,2,3" group.long 0x5A8++0x3 line.long 0x00 "CONTROL_WKUP_PADCONF_MODE,PAD Voltage Mode control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " VDDS_DV_FREF ,PAD Voltage level control for vdds_dv_fref - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" bitfld.long 0x00 30. " VDDS_DV_BANK2_SHARED1 ,PAD Voltage level control for vdds_dv_bank2_shared1 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" group.long 0x5AC++0x3 line.long 0x00 "CONTROL_XTAL_OSCILLATOR,XTAL OSCILLATOR control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " OSCILLATOR_BOOST ,Fast startup control - . - ." "0,1" bitfld.long 0x00 30. " OSCILLATOR_OS_OUT ,Oscillator output - . - ." "0,BOOST_is_disabled" group.long 0x5B0++0x3 line.long 0x00 "CONTROL_SMART3NOPMIO_PADCONF_0,SMART3 NOPM IO control 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " FREF_DR1_MB ,50-? output buffer mode control for group fref_dr1 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 28.--29. " FREF_DR5_MB ,50-? output buffer mode control for group fref_dr5 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 26.--27. " FREF_DR6_MB ,50-? output buffer mode control for group fref_dr6 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " FREF_DR7_MB ,50-? output buffer mode control for group Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 22.--23. " FREF_DR4_MB ,50-? output buffer mode control for group fref_dr4 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" group.long 0x5B4++0x3 line.long 0x00 "CONTROL_SMART3NOPMIO_PADCONF_1,SMART3 NOPM IO control 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " FREF_DR1_LB0 ,50-? output buffer load control for group fref_dr1 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 30. " FREF_DR5_LB0 ,50-? output buffer load control for group fref_dr5 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 29. " FREF_DR6_LB0 ,50-? output buffer load control for group fref_dr6 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" textline " " bitfld.long 0x00 28. " FREF_DR7_LB0 ,50-? output buffer load control for group fref_dr7 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 27. " FREF_DR4_LB0 ,50-? output buffer load control for group fref_dr4 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" group.long 0x600++0x3 line.long 0x00 "CONTROL_GPIOWK,GPIOWK pads I/O control Access conditions. Read: unrestricted; Write: unrestricted" bitfld.long 0x00 31. " PAD_GPIO_WK1_LOW ,LOW enable for gpio_wk1 PAD - . - ." "0,1" bitfld.long 0x00 30. " Reserved ," "0,1" bitfld.long 0x00 29. " PAD_GPIO_WK2_LOW ,LOW enable for gpio_wk2 PAD - . - ." "0,1" textline " " bitfld.long 0x00 28. " GPIOWK_IO_PWRDNZ ,PWRDNZ control to gpiowk0-gpiowk2 IOs - This bit is used to protect the gpio_wk0-gpio_wk2 pads associated I/O cell when SIM_VDDS is not stable. . - . - . - ." "0,1" hexmask.long 0x00 0.--27. 1. " Reserved ," group.long 0x604++0x3 line.long 0x00 "CONTROL_I2C_2,I2C pads control 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SR_SDA_GLFENB ,Active_high glitch free operation enable pin for sr i2c receiver - . - ." "Disable,Enable" bitfld.long 0x00 29.--30. " SR_SDA_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for sr i2c - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 28. " SR_SDA_PULLUPRESX ,Active_low internal pull_up resistor enabled for sr i2c - . - ." "Enable,Disable" textline " " bitfld.long 0x00 27. " SR_SCL_GLFENB ,Active_high glitch free operation enable pin for sr i2c receiver - . - ." "Disable,Enable" bitfld.long 0x00 25.--26. " SR_SCL_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for sr i2c - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 24. " SR_SCL_PULLUPRESX ,Active_low internal pull_up resistor enabled for sr i2c - . - ." "Enable,Disable" group.long 0x608++0x3 line.long 0x00 "CONTROL_JTAG,JTAG pads control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " JTAG_NTRST_EN ,bus holder enable for jtag_ntrst PAD - . - ." "0,1" bitfld.long 0x00 30. " JTAG_TCK_EN ,bus holder enable for jtag_tck PAD - . - ." "0,1" bitfld.long 0x00 29. " JTAG_RTCK_EN ,bus holder enable for jtag_rtck PAD - . - ." "0,1" textline " " bitfld.long 0x00 28. " JTAG_TDI_EN ,bus holder enable for jtag_tdi PAD - . - ." "0,1" bitfld.long 0x00 27. " JTAG_TDO_EN ,bus holder enable for jtag_tdo PAD - . - ." "0,1" group.long 0x60C++0x3 line.long 0x00 "CONTROL_SYS,SYS controls Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SYS_NRESWARM_PIPU ,Pull up enable for sys_nreswarm PAD - . - ." "Enable_pull_up,Disable_pull_up" group.long 0x614++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW,Wake-up control spare RW Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW ,Wake-up control spare register bits RW" rgroup.long 0x618++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_R,Wake-up control spare R Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_R ,Wake-up control spare register bits R" group.long 0x61C++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_R_C0,Wake-up control spare RC Access conditions. Read: unrestricted, Write: unrestricted" eventfld.long 0x00 31. " WKUP_CONTROL_SPARE_R_C0 ,Wake-up control spare register bits RC" "0,1" eventfld.long 0x00 30. " WKUP_CONTROL_SPARE_R_C1 ,Wake-up control spare register bits RC" "0,1" eventfld.long 0x00 29. " WKUP_CONTROL_SPARE_R_C2 ,Wake-up control spare register bits RC" "0,1" textline " " eventfld.long 0x00 28. " WKUP_CONTROL_SPARE_R_C3 ,Wake-up control spare register bits RC" "0,1" eventfld.long 0x00 27. " WKUP_CONTROL_SPARE_R_C4 ,Wake-up control spare register bits RC" "0,1" eventfld.long 0x00 26. " WKUP_CONTROL_SPARE_R_C5 ,Wake-up control spare register bits RC" "0,1" textline " " eventfld.long 0x00 25. " WKUP_CONTROL_SPARE_R_C6 ,Wake-up control spare register bits RC" "0,1" eventfld.long 0x00 24. " WKUP_CONTROL_SPARE_R_C7 ,Wake-up control spare register bits RC" "0,1" group.long 0x620++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW1,WKUP control spare RW1 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW1 ,wkup control spare register bits RW1" group.long 0x624++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW2,WKUP control spare RW2 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW2 ,wkup control spare register bits RW2" group.long 0x628++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW3,WKUP control spare RW3 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW3 ,wkup control spare register bits RW3" group.long 0x62C++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW4,WKUP control spare RW4 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW4 ,wkup control spare register bits RW4" group.long 0x630++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW5,WKUP control spare RW5 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW5 ,wkup control spare register bits RW5" group.long 0x634++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW6,WKUP control spare RW6 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW6 ,wkup control spare register bits RW6" group.long 0x638++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW7,WKUP control spare RW7 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW7 ,wkup control spare register bits RW7" group.long 0x63C++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW8,WKUP control spare RW8 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW8 ,wkup control spare register bits RW8" group.long 0x640++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_RW9,WKUP control spare RW9 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_RW9 ,wkup control spare register bits RW9" rgroup.long 0x64C++0x3 line.long 0x00 "CONTROL_WKUP_CONTROL_SPARE_R1,WKUP control spare R1 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " WKUP_CONTROL_SPARE_R1 ,wkup control spare register bits R1" tree.end tree "SYSCTRL_GENERAL_CORE" base ad:0x4A002000 width 36. rgroup.long 0x0++0x3 line.long 0x00 "CONTROL_GEN_CORE_REVISION,Control module instance revision identifier" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "CONTROL_GEN_CORE_HWINFO,Information about the IP module hardware configuration" hexmask.long 0x00 0.--31. 1. " IP_HWINFO ,IP-module dependent" group.long 0x10++0x3 line.long 0x00 "CONTROL_GEN_CORE_SYSCONFIG,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 2.--3. " IP_SYSCONFIG_IDLEMODE ,Select the local clock-gating strategy - . - . 0x2,0x3: Clock is automatically gated when there is no access to the Control Module through L4-interconnect. - ." "0,1,2,3" group.long 0x200++0x3 line.long 0x00 "CONTROL_STD_FUSE_DIE_ID_0,Die ID Register - Part 0. Access conditions. Read: unrestricted" rgroup.long 0x204++0x3 line.long 0x00 "CONTROL_ID_CODE,ID_CODE Key Register Access conditions. Read: unrestricted" bitfld.long 0x00 28.--31. " VERSION ,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 12.--27. 1. " HAWKEYE ,Hawkeye number" hexmask.long.word 0x00 1.--11. 1. " TI_IDM ,Manufacturer identity(TI)" textline " " bitfld.long 0x00 0. " - ,Always set to 1" "0,1" group.long 0x208++0x3 line.long 0x00 "CONTROL_STD_FUSE_DIE_ID_1,Die ID Register - Part 1. Access conditions. Read: unrestricted" group.long 0x20C++0x3 line.long 0x00 "CONTROL_STD_FUSE_DIE_ID_2,Die ID Register - Part 2. Access conditions. Read: unrestricted" group.long 0x210++0x3 line.long 0x00 "CONTROL_STD_FUSE_DIE_ID_3,Die ID Register - Part 3. Access conditions. Read: unrestricted" rgroup.long 0x214++0x3 line.long 0x00 "CONTROL_STD_FUSE_PROD_ID_0,Prod ID Register - Part 0. This register shows the device type. Access conditions. Read: unrestricted" hexmask.long.byte 0x00 0.--7. 1. " DEVICE_TYPE ,Define the device type 0xF0 = GP device Other values = Reserved" rgroup.long 0x218++0x3 line.long 0x00 "CONTROL_STD_FUSE_PROD_ID_1,Prod ID Register - Part 1.This register shows the device type. Access conditions. Read: unrestricted" bitfld.long 0x00 16.--17. " SILICON_TYPE ,Define the silicon performance type" "0,1,2,3" rgroup.long 0x21C++0x3 line.long 0x00 "CONTROL_STD_FUSE_USB_CONF,Standard Fuse conf [31:0]. Register shows part of the chip standard eFuse configuration. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditions. Read: unrestri.." hexmask.long.word 0x00 16.--31. 1. " USB_PROD_ID ,USB Product Identification" hexmask.long.word 0x00 0.--15. 1. " USB_VENDOR_ID ,USB Vendor Identification" rgroup.long 0x220++0x3 line.long 0x00 "CONTROL_STD_FUSE_CONF,Standard fuse configuration register. The register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access cond.." bitfld.long 0x00 16. " STD_FUSE_FACE_DETECT_DISABLE ,Disables face detect - . - ." "Enables_face_detect,Disables_face_detect" bitfld.long 0x00 15. " STD_FUSE_CRYPTO_DISABLE ,Disables cryptographic modules - . - ." "0,1" bitfld.long 0x00 14. " STD_FUSE_MODEM3G_DISABLE ,Disables the 3G modem - . - ." "Enables_3G_modem,Disables_3G_modem" textline " " bitfld.long 0x00 13. " STD_FUSE_CH_SPEEDUP_DISABLE ,ROM code settings for configuration header block and speedup block. Only software access (no hardware access). - . - ." "0,1" bitfld.long 0x00 12. " STD_FUSE_ROM_HIDE ,MPU BOOT ROM space (4-KB ROM code protection) - . - ." "0,1" bitfld.long 0x00 11. " STD_FUSE_DPLL_CLK_TRIMMING_DISABLE ,Controls DPLLs - . - ." "Enables_DPLL_trimming,Disables_DPLL_trimming" textline " " bitfld.long 0x00 9. " STD_FUSE_DSS_VENC_MVENAB ,Enables implementation-specific features. Controls DSS_VENC_MVENAB. - . - ." "Disables_DSS_VENC_MVENAB,Enables_DSS_VENC_MVENAB" bitfld.long 0x00 8. " STD_FUSE_ISS_EFUSE4_EN ,Enables implementation-specific features. Controls ISS.EFUSE4_EN. Sets to 0. - . - ." "Disables_ISS_EFUSE4,Enables_ISS_EFUSE4" bitfld.long 0x00 7. " STD_FUSE_ISS_EFUSE3_EN ,Enables implementation specific features. Controls ISS.EFUSE3_EN. Sets to 0. - . - ." "Disables_ISS_EFUSE3,Enables_ISS_EFUSE3" textline " " bitfld.long 0x00 6. " STD_FUSE_ISS_EFUSE2_EN ,Enables implementation-specific features. Controls ISS.EFUSE2_EN. Sets to 0. - . - ." "Disables_ISS_EFUSE2,Enables_ISS_EFUSE2" bitfld.long 0x00 5. " STD_FUSE_ISS_EFUSE1_EN ,Enables implementation-specific features. Controls ISS.EFUSE1_EN. Sets to 1. - . - ." "Disables_ISS_EFUSE1,Enables_ISS_EFUSE1" bitfld.long 0x00 4. " STD_FUSE_SGX540_3D_CLOCK_SOURCE ,Force 3D graphic engine clock source" "0,1" textline " " bitfld.long 0x00 3. " STD_FUSE_SGX540_3D_DISABLE ,Disable the 3D Gx engine (SGX540) - . - ." "Enables_SGX,Disables_SGX" bitfld.long 0x00 2. " STD_FUSE_CORTEXA9_MPU_DISABLE ,Configures Cortex-A9 MPU boot mode. It disables one Cortex-A9 core. - . - ." "Boot_SMP_mode,Boot_IP_mode" bitfld.long 0x00 1. " BSC_ACCESS_PROTECT ,Reserved for bsc_access protect" "0,1" textline " " bitfld.long 0x00 0. " CUST_IEEE1500_DISABLE ,Customer eFuse control/IEEE1500 access path disable" "0,1" rgroup.long 0x228++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_WKUP,Standard Fuse OPP VDD_WKUP [31:0]. Register shows part of the chip standard eFuse configuration. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditions. Re.." hexmask.long 0x00 0.--31. 1. " STD_FUSE_OPP_VDD_WKUP ," rgroup.long 0x22C++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_IVA_0,Standard Fuse OPP VDD_IVA_0. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditio.." hexmask.long.byte 0x00 24.--31. 1. " VDD_IVA_OPP100_SENN_REC ,Voltage domain VDD_IVA OPP100 [7:0] from Standard Fuse" bitfld.long 0x00 20.--23. " VDD_IVA_OPP50_SENP_GAIN ,Voltage domain VDD_IVA OPP50 [23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " VDD_IVA_OPP50_SENN_GAIN ,Voltage domain VDD_IVA OPP50 [19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " VDD_IVA_OPP50_SENP_REC ,Voltage domain VDD_IVA OPP50 [15:8] from Standard Fuse" hexmask.long.byte 0x00 0.--7. 1. " VDD_IVA_OPP50_SENN_REC ,Voltage domain VDD_IVA OPP50 [7:0] from Standard Fuse" rgroup.long 0x230++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_IVA_1,Standard Fuse OPP VDD_IVA_1. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditio.." hexmask.long.byte 0x00 24.--31. 1. " VDD_IVA_OPP_TURBO_SENP_REC ,Voltage domain VDD_IVA OPP_TURBO [15:8] from Standard Fuse" hexmask.long.byte 0x00 16.--23. 1. " VDD_IVA_OPP_TURBO_SENN_REC ,Voltage domain VDD_IVA OPP_TURBO [7:0] from Standard Fuse" bitfld.long 0x00 12.--15. " VDD_IVA_OPP100_SENP_GAIN ,Voltage domain VDD_IVA OPP100 [23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " VDD_IVA_OPP100_SENN_GAIN ,Voltage domain VDD_IVA OPP100 [19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VDD_IVA_OPP100_SENP_REC ,Voltage domain VDD_IVA OPP100 [15:8] from Standard Fuse" rgroup.long 0x234++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_IVA_2,Standard Fuse OPP VDD_IVA_2. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditio.." bitfld.long 0x00 4.--7. " VDD_IVA_OPP_TURBO_SENP_GAIN ,Voltage domain VDD_IVA OPP_TURBO [23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " VDD_IVA_OPP_TURBO_SENN_GAIN ,Voltage domain VDD_IVA OPP_TURBO [19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x238++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_IVA_3,Standard Fuse OPP VDD_IVA_3. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditio.." bitfld.long 0x00 26.--27. " VDD_IVA_SR_SENN ,VDD_IVA Smart Reflex from Standard FUSE" "0,1,2,3" bitfld.long 0x00 24.--25. " VDD_IVA_SR_SENP ,VDD_IVA Smart Reflex from Standard FUSE" "0,1,2,3" rgroup.long 0x240++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_MPU_0,Standard Fuse OPP VDD_MPU_0. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditio.." hexmask.long.byte 0x00 24.--31. 1. " VDD_MPU_OPP100_SENN_REC ,Voltage domain VDD_MPU OPP100 [7:0] from Standard Fuse" bitfld.long 0x00 20.--23. " VDD_MPU_OPP50_SENP_GAIN ,Voltage domain VDD_MPU OPP50 [23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " VDD_MPU_OPP50_SENN_GAIN ,Voltage domain VDD_MPU OPP50 [19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " VDD_MPU_OPP50_SENP_REC ,Voltage domain VDD_MPU OPP50 [15:8] from Standard Fuse" hexmask.long.byte 0x00 0.--7. 1. " VDD_MPU_OPP50_SENN_REC ,Voltage domain VDD_MPU OPP50 [7:0] from Standard Fuse" rgroup.long 0x244++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_MPU_1,Standard Fuse OPP VDD_MPU_1. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditio.." hexmask.long.byte 0x00 24.--31. 1. " VDD_MPU_OPP_TURBO_SENP_REC ,Voltage domain VDD_MPU OPP_TURBO [15:8] from Standard Fuse" hexmask.long.byte 0x00 16.--23. 1. " VDD_MPU_OPP_TURBO_SENN_REC ,Voltage domain VDD_MPU OPP_TURBO [7:0] from Standard Fuse" bitfld.long 0x00 12.--15. " VDD_MPU_OPP100_SENP_GAIN ,Voltage domain VDD_MPU OPP100 [23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " VDD_MPU_OPP100_SENN_GAIN ,Voltage domain VDD_MPU OPP100 [19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VDD_MPU_OPP100_SENP_REC ,Voltage domain VDD_MPU OPP100 [15:8] from Standard Fuse" rgroup.long 0x248++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_MPU_2,Standard Fuse OPP VDD_MPU_2. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditio.." bitfld.long 0x00 28.--31. " VDD_MPU_OPP_NITRO_SENP_GAIN ,Voltage domain VDD_MPU OPP_NITRO [23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " VDD_MPU_OPP_NITRO_SENN_GAIN ,Voltage domain VDD_MPU OPP_NITRO [19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " VDD_MPU_OPP_NITRO_SENP_REC ,Voltage domain VDD_MPU OPP_NITRO [15:8] from Standard Fuse" textline " " hexmask.long.byte 0x00 8.--15. 1. " VDD_MPU_OPP_NITRO_SENN_REC ,Voltage domain VDD_MPU OPP_NITRO [7:0] from Standard Fuse" bitfld.long 0x00 4.--7. " VDD_MPU_OPP_TURBO_SENP_GAIN ,Voltage domain VDD_MPU OPP_TURBO [23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " VDD_MPU_OPP_TURBO_SENN_GAIN ,Voltage domain VDD_MPU OPP_TURBO [19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x24C++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_MPU_3,Standard Fuse OPP VDD_MPU_3. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditio.." bitfld.long 0x00 26.--27. " VDD_MPU_SR_SENN ,VDD_MPU SmartReflex from Standard Fuse" "0,1,2,3" bitfld.long 0x00 24.--25. " VDD_MPU_SR_SENP ,VDD_MPU SmartReflex from Standard Fuse" "0,1,2,3" bitfld.long 0x00 20.--23. " VDD_MPU_OPP_NITRO1.2G_SENP_GAIN ,Voltage domain VDD_MPU OPP_NITRO1.2G[23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " VDD_MPU_OPP_NITRO1.2G_SENN_GAIN ,Voltage domain VDD_MPU OPP_NITRO1.2G[19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " VDD_MPU_OPP_NITRO1.2G_SENP_REC ,Voltage domain VDD_MPU OPP_NITRO1.2G[15:8] from Standard Fuse" hexmask.long.byte 0x00 0.--7. 1. " VDD_MPU_OPP_NITRO1.2G_SENN_REC ,Voltage domain VDD_MPU OPP_NITRO1.2G[7:0] from Standard Fuse" rgroup.long 0x254++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_CORE_0,Standard Fuse OPP VDD_CORE_0. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access condit.." hexmask.long.byte 0x00 24.--31. 1. " VDD_CORE_OPP100_SENN_REC ,Voltage domain VDD_CORE OPP100 [7:0] from Standard Fuse" bitfld.long 0x00 20.--23. " VDD_CORE_OPP50_SENP_GAIN ,Voltage domain VDD_CORE OPP50 [23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " VDD_CORE_OPP50_SENN_GAIN ,Voltage domain VDD_CORE OPP50 [19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " VDD_CORE_OPP50_SENP_REC ,Voltage domain VDD_CORE OPP50 [15:8] from Standard Fuse" hexmask.long.byte 0x00 0.--7. 1. " VDD_CORE_OPP50_SENN_REC ,Voltage domain VDD_CORE OPP50 [7:0] from Standard Fuse" rgroup.long 0x258++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_CORE_1,Standard Fuse OPP VDD_CORE_1. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access condit.." hexmask.long.byte 0x00 24.--31. 1. " VDD_CORE_OPP100_SENP_REC ,Voltage domain VDD_CORE OPP100 [15:8] (1.1V) from Standard Fuse." hexmask.long.byte 0x00 16.--23. 1. " VDD_CORE_OPP100_SENN_REC ,Voltage domain VDD_CORE OPP100 [7:0] (1.1V) from Standard Fuse." bitfld.long 0x00 12.--15. " VDD_CORE_OPP100_SENP_GAIN ,VVoltage domain VDD_CORE OPP100 [23:20] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " VDD_CORE_OPP100_SENN_GAIN ,Voltage domain VDD_CORE OPP100 [19:16] from Standard Fuse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VDD_CORE_OPP100_SENP_REC ,Voltage domain VDD_CORE OPP100 [15:8] from Standard Fuse" rgroup.long 0x25C++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_VDD_CORE_2,Standard Fuse OPP VDD_CORE_2. Register shows part of the chip eFuse configuration on the L4 interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access condit.." bitfld.long 0x00 10.--11. " VDD_CORE_SR_SENN ,VDD_CORE SmartReflex from Standard FUSE" "0,1,2,3" bitfld.long 0x00 8.--9. " VDD_CORE_SR_SENP ,VDD_CORE SmartReflex from Standard FUSE" "0,1,2,3" rgroup.long 0x260++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_BGAP,Standard Fuse OPP BGAP. Register shows part of the chip standard eFuse configuration. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditions. Read: unrestricte.." hexmask.long 0x00 0.--31. 1. " STD_FUSE_OPP_BGAP ," rgroup.long 0x264++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_DPLL_0,Standard Fuse OPP DPLL. Register shows part of the chip standard eFuse configuration. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditions. Read: unrestric.." hexmask.long 0x00 0.--31. 1. " STD_FUSE_OPP_DPLL_0 ," rgroup.long 0x268++0x3 line.long 0x00 "CONTROL_STD_FUSE_OPP_DPLL_1,Standard Fuse OPP DPLL. Register shows part of the chip standard eFuse configuration. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain. Access conditions. Read: unrestric.." hexmask.long 0x00 0.--31. 1. " STD_FUSE_OPP_DPLL_1 ," rgroup.long 0x2C4++0x3 line.long 0x00 "CONTROL_STATUS,Control Module Status Register Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 11.--12. " SYSCTRL_GENERAL_CONF ,Sysctrl_General_ IP configuration - ." "0,SMP_configuration,2,3" bitfld.long 0x00 8.--10. " DEVICE_TYPE ,Device type captured at reset time Device type value sampled at power-on reset. - ." "0,1,2,General_Purpose_(GP),4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " SYS_BOOT ,Sys.Boot pins state captured at reset time Sys.Boot pin values sampled at power-on reset" rgroup.long 0x2D0++0x3 line.long 0x00 "CONTROL_SEC_ERR_STATUS_FUNC,Firewall Error Status functional Register Access conditions. Read Only" bitfld.long 0x00 20. " C2C_INIT_FW_ERROR ,C2C init firewall. MID config: unused (reserved) - . - ." "0,Error_from_firewall" bitfld.long 0x00 19. " L4_AUDIOBE_FW_ERROR ,L4 AudioBE firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 18. " DEBUGSS_FW_ERROR ,DebugSS firewall - . - ." "0,Error_from_firewall" textline " " bitfld.long 0x00 17. " L4_CONFIG_FW_ERROR ,L4 Config firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 16. " L4_PERIPH_FW_ERROR ,L4 PER firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 15. " ISS_FW_ERROR ,ISS firewall - . - ." "0,Error_from_firewall" textline " " bitfld.long 0x00 14. " DSS_FW_ERROR ,DSS firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 13. " SGX_FW_ERROR ,SGX firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 12. " C2C_FW_ERROR ,C2C firewall. MID config: unused (reserved). - . - ." "0,Error_from_firewall" textline " " bitfld.long 0x00 6. " SL2_FW_ERROR ,SL2 firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 5. " DUAL_CORTEX_M3_FW_ERROR ,Dual Cortex M3 firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 4. " IVAHD_FW_ERROR ,IVAHD firewall - . - ." "0,Error_from_firewall" textline " " bitfld.long 0x00 3. " EMIF_FW_ERROR ,EMIF firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 2. " GPMC_FW_ERROR ,GPMC firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 1. " L3RAM_FW_ERROR ,L3RAM firewall - . - ." "0,Error_from_firewall" rgroup.long 0x2D4++0x3 line.long 0x00 "CONTROL_SEC_ERR_STATUS_DEBUG,Error Status debug Register. Read All / Write All. Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 20. " C2C_INIT_DBGFW_ERROR ,C2C init debug firewall. MID config: unused (reserved) - . - ." "0,Error_from_firewall" bitfld.long 0x00 19. " L4_AUDIOBE_DBGFW_ERROR ,L4 AudioBE debug firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 18. " DEBUGSS_DBGFW_ERROR ,DebugSS debug firewall - . - ." "0,Error_from_firewall" textline " " bitfld.long 0x00 17. " L4_CONFIG_DBGFW_ERROR ,L4 Config debug firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 16. " L4_PERIPH_DBGFW_ERROR ,L4 PER debug firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 15. " ISS_DBGFW_ERROR ,ISS debug firewall - . - ." "0,Error_from_firewall" textline " " bitfld.long 0x00 14. " DSS_DBGFW_ERROR ,DSS debug firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 13. " SGX_DBGFW_ERROR ,SGX debug firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 12. " C2C_DBGFW_ERROR ,C2C debug firewall. MID config: unused (reserved). - . - ." "0,Error_from_firewall" textline " " bitfld.long 0x00 6. " SL2_DBGFW_ERROR ,SL2 debug firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 5. " DUAL_CORTEX_M3__DBGFW_ERROR ,Dual Cortex M3 debug firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 4. " IVAHD_DBGFW_ERROR ,IVAHD debug firewall - . - ." "0,Error_from_firewall" textline " " bitfld.long 0x00 3. " EMIF_DBGFW_ERROR ,EMIF debug firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 2. " GPMC_DBGFW_ERROR ,GPMC debug firewall - . - ." "0,Error_from_firewall" bitfld.long 0x00 1. " L3RAM_DBGFW_ERROR ,L3RAM debug firewall - . - ." "0,Error_from_firewall" group.long 0x300++0x3 line.long 0x00 "CONTROL_DEV_CONF,Device configuration register. Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 1.--31. 1. " DEV_CONF ,Spare bits for device configuration." bitfld.long 0x00 0. " USBPHY_PD ,Power down entire USB phy (data, common module and UTMI). controls USB2PHYCORE.PD pin. - . - ." "Normal_operation,1" group.long 0x314++0x3 line.long 0x00 "CONTROL_LDOVBB_IVA_VOLTAGE_CTRL,IVA Voltage Body Bias LDO control register Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 10. " LDOVBBIVA_FBB_MUX_CTRL ,Override control of eFuse Adaptive Body Bias set1 voltage value - . - ." "0,1" bitfld.long 0x00 5.--9. " LDOVBBIVA_FBB_VSET_IN ,eFuse Adaptive Body Bias set1 voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LDOVBBIVA_FBB_VSET_OUT ,Override value for Adaptive Body Bias set1 voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x318++0x3 line.long 0x00 "CONTROL_LDOVBB_MPU_VOLTAGE_CTRL,MPU Voltage Body Bias LDO control register Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 10. " LDOVBBMPU_FBB_MUX_CTRL ,Override control of eFuse Adaptive Body Bias set1 voltage value - . - ." "0,1" bitfld.long 0x00 5.--9. " LDOVBBMPU_FBB_VSET_IN ,eFuse Adaptive Body Bias set1 voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LDOVBBMPU_FBB_VSET_OUT ,Override value for Adaptive Body Bias set1 voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x320++0x3 line.long 0x00 "CONTROL_LDOSRAM_IVA_VOLTAGE_CTRL,IVA SRAM LDO control register Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 26. " LDOSRAMIVA_RETMODE_MUX_CTRL ,Override control of eFuse Retention Mode Voltage value - . - ." "0,1" bitfld.long 0x00 21.--25. " LDOSRAMIVA_RETMODE_VSET_IN ,eFuse Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " LDOSRAMIVA_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10. " LDOSRAMIVA_ACTMODE_MUX_CTRL ,Override control of eFuse Active Mode Voltage value - . - ." "0,1" bitfld.long 0x00 5.--9. " LDOSRAMIVA_ACTMODE_VSET_IN ,eFuse Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LDOSRAMIVA_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x324++0x3 line.long 0x00 "CONTROL_LDOSRAM_MPU_VOLTAGE_CTRL,MPU SRAM LDO control register Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 26. " LDOSRAMMPU_RETMODE_MUX_CTRL ,Override control of eFuse Retention Mode Voltage value - . - ." "0,1" bitfld.long 0x00 21.--25. " LDOSRAMMPU_RETMODE_VSET_IN ,eFuse Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " LDOSRAMMPU_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10. " LDOSRAMMPU_ACTMODE_MUX_CTRL ,Override control of eFuse Active Mode Voltage value - . - ." "0,1" bitfld.long 0x00 5.--9. " LDOSRAMMPU_ACTMODE_VSET_IN ,eFuse Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LDOSRAMMPU_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x328++0x3 line.long 0x00 "CONTROL_LDOSRAM_CORE_VOLTAGE_CTRL,Core SRAM LDO control register Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 26. " LDOSRAMCORE_RETMODE_MUX_CTRL ,Override control of eFuse Retention Mode Voltage value - . - ." "0,1" bitfld.long 0x00 21.--25. " LDOSRAMCORE_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " LDOSRAMCORE_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10. " LDOSRAMCORE_ACTMODE_MUX_CTRL ,Override control of eFuse Active Mode Voltage value - . - ." "0,1" bitfld.long 0x00 5.--9. " LDOSRAMCORE_ACTMODE_VSET_IN ,eFuse Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LDOSRAMCORE_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x32C++0x3 line.long 0x00 "CONTROL_TEMP_SENSOR,Control VBGAPTS temperature sensor and thermal comparator shutdown register Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 12. " BGAP_TEMPSOFF ,Temperature sensor and thermal shutdown mode. - . - ." "0,1" bitfld.long 0x00 11. " BGAP_TSHUT ,Thermal shutdown comparator output. It is low during normal operation and goes high during a thermal shutdown event." "0,1" bitfld.long 0x00 10. " BGAP_TEMP_SENSOR_CONTCONV ,VDD level digital inputs. When high the ADC is in continuous conversion mode. - . - ." "0,1" textline " " bitfld.long 0x00 9. " BGAP_TEMP_SENSOR_SOC ,ADC Start of Conversion. A transition to high starts a new ADC conversion cycle" "0,1" bitfld.long 0x00 8. " BGAP_TEMP_SENSOR_EOCZ ,ADC End of Conversion. Active low, when CTRL_ TEMP(7:0) is valid." "0,1" hexmask.long.byte 0x00 0.--7. 1. " BGAP_TEMP_SENSOR_DTEMP ,Temperature data from the ADC. Valid if EOCZ is low." group.long 0x330++0x3 line.long 0x00 "CONTROL_DPLL_NWELL_TRIM_0,Dpll trim (Software override) - Part 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 29. " DPLL_ABE_NWELL_TRIM_MUX_CTRL ,Software override selection over eFuse values. - . - ." "0,1" bitfld.long 0x00 24.--28. " DPLL_ABE_NWELL_TRIM ,Software override value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DPLL_PER_NWELL_TRIM_MUX_CTRL ,Software override selection over eFuse values. - . - ." "0,1" textline " " bitfld.long 0x00 18.--22. " DPLL_PER_NWELL_TRIM ,Software override value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 17. " DPLL_CORE_NWELL_TRIM_MUX_CTRL ,Software override selection over eFuse values. - . - ." "0,1" bitfld.long 0x00 12.--16. " DPLL_CORE_NWELL_TRIM ,Software override value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 11. " DPLL_IVA_NWELL_TRIM_MUX_CTRL ,Software override selection over eFuse values. - . - ." "0,1" bitfld.long 0x00 6.--10. " DPLL_IVA_NWELL_TRIM ,Software override value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DPLL_MPU_NWELL_TRIM_MUX_CTRL ,Software override selection over eFuse values. - . - ." "0,1" textline " " bitfld.long 0x00 0.--4. " DPLL_MPU_NWELL_TRIM ,Software override value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x334++0x3 line.long 0x00 "CONTROL_DPLL_NWELL_TRIM_1,Dpll trim (Software override) - Part 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 23. " DPLL_USB_NWELL_TRIM_MUX_CTRL ,Software override selection over eFuse values. - . - ." "0,1" bitfld.long 0x00 18.--22. " DPLL_USB_NWELL_TRIM ,Software override value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " DPLL_DSI2_NWELL_TRIM_MUX_CTRL ,Software override selection over eFuse values. - . - ." "0,1" textline " " bitfld.long 0x00 6.--10. " DPLL_DSI2_NWELL_TRIM ,Software override value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DPLL_DSI1_NWELL_TRIM_MUX_CTRL ,Software override selection over eFuse values. - . - ." "0,1" bitfld.long 0x00 0.--4. " DPLL_DSI1_NWELL_TRIM ,Software override value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x33C++0x3 line.long 0x00 "CONTROL_USBOTGHS_CONTROL,USBOTGHS software control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 8. " DISCHRGVBUS ,USBOTGHS value for signal dischrgvbus (OTG_PD_VBUS ). controls discharging of VBUS for completing SRP. - . - ." "0,1" bitfld.long 0x00 7. " CHRGVBUS ,USBOTGHS value for signal chrgvbus (OTG_PU_VBUS). controls charging of VBUS for initiating SRP. - . - ." "0,1" bitfld.long 0x00 6. " DRVVBUS ,USBOTGHS value for signal drvvbus (OTG_DRV_VBUS). controls the driving of 5V power on VBUS. - . - ." "0,1" textline " " bitfld.long 0x00 5. " IDPULLUP ,USBOTGHS value for signal Idpullup (OTG_PU_ID). Enables sampling of the ID pin of the USB connector. - . - ." "0,1" bitfld.long 0x00 4. " IDDIG ,Sets the USBOTGHS signal iddig (ID). Indicates the value of the ID pin of the USB connector. - . - ." "0,1" bitfld.long 0x00 3. " SESSEND ,Sets the USBOTGHS signal sessend (BSESSEND). Indicates if VBUS is below the B-Device session end threshold. The threshold Vth is between 0.2V and 0.8V. - . - ." "0,1" textline " " bitfld.long 0x00 2. " VBUSVALID ,Sets the USBOTGHS signal vbusvalid (VBUSVLD). Indicates if VBUS is above the threshold for normal operation. The threshold Vth is between 4.4V and 4.75V." "0,1" bitfld.long 0x00 1. " BVALID ,Sets the USBOTGHS signal bvalid (BSESSVLD). Signal is currently unconnected (reserved for future use). - . - ." "0,1" bitfld.long 0x00 0. " AVALID ,Sets the USBOTGHS signal avalid (ASESSVLD). Indicates if VBUS is above the A-Device session valid threshold. The threshold Vth is between 0.8V and 2.0V. - . - ." "0,1" group.long 0x340++0x3 line.long 0x00 "CONTROL_DSS_CONTROL,DSS software control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " DSS_MUX6_SELECT ,Mux6 select value for DSS. - . - ." "0,1" group.long 0x348++0x3 line.long 0x00 "CONTROL_CORTEX_M3_MMUADDRTRANSLTR,CORTEX_M3 reg Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long.tbyte 0x00 0.--19. 1. " CORTEX_M3_MMUADDRTRANSLTR ,Used to save the mmu address boot" group.long 0x34C++0x3 line.long 0x00 "CONTROL_CORTEX_M3_MMUADDRLOGICTR,Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long.tbyte 0x00 0.--19. 1. " CORTEX_M3_MMUADDRLOGICTR ," group.long 0x350++0x3 line.long 0x00 "CONTROL_HWOBS_CONTROL,Hardware observability control. This register enables or disables hardware observability outputs (to save power primarily) Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 3.--7. " HWOBS_CLKDIV_SEL ,Clock divider selection on po_hwobs(0). - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " HWOBS_ALL_ZERO_MODE ,Used to gate observable signals. When set all outputs are set to zero (can be used to check the path from hardware observability to external pads). - . - ." "0,1" bitfld.long 0x00 1. " HWOBS_ALL_ONE_MODE ,Used to gate observable signals. When set all outputs are set to one (can be used to check the path from hardware observability to external pads). - . - ." "0,1" textline " " bitfld.long 0x00 0. " HWOBS_MACRO_ENABLE ,Used to gate observable signals coming from macros using the 32-bit HWOBS bus definition. When deasserted all outputs of the HWOBS busdef are set to zero. - . - ." "0,1" group.long 0x3FC++0x3 line.long 0x00 "CONTROL_GEN_CORE_OCPREG_SPARE,The lower 4 bits of this register are assigned to control PWRDN mode globally, and the LVCMOS buffers enable control of the EMIF1 and EMIF2 PHYs. Read: Unrestricted; Write: Unrestricted" hexmask.long 0x00 4.--31. 1. " OCPREG_SPARE ,?..." bitfld.long 0x00 3. " OCPREG_SPARE3 ,emif2phydata0?emif2phydata3 power-down mode control - . - ." "Normal_mode_selected,Power-down_mode_selected" bitfld.long 0x00 2. " OCPREG_SPARE2 ,emif2phycmd0, emif2phydata0?emif2phydata3 I/O LVCMOS buffers enable - . - ." "0,1" textline " " bitfld.long 0x00 1. " OCPREG_SPARE1 ,emif1phydata0?emif1phydata3 power-down mode control - . - ." "0,1" bitfld.long 0x00 0. " OCPREG_SPARE0 ,emif1phycmd0, emif1phydata0?emif1phydata3 I/O LVCMOS buffers enable - . - ." "0,1" group.long 0x400++0x3 line.long 0x00 "CONTROL_DEBOBS_FINAL_MUX_SEL,Final mux select signal. It selects between core and wkup signal (controls external observability logic). Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " SELECT ,The i-th (i=0..31) bit from this bit field controls the multiplexing between the core and the wake-up signals to be observed at i-th hw_dbg line." group.long 0x408++0x3 line.long 0x00 "CONTROL_DEBOBS_MMR_MPU,Dual Cortex-A9 register to control hardware observability muxing inside dual Cortex-A9 (controls external observability logic)." bitfld.long 0x00 0.--3. " SELECT ,Control external observability logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x42C++0x3 line.long 0x00 "CONTROL_CONF_SDMA_REQ_SEL0,System DMA requests view channel 0 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long.byte 0x00 0.--6. 1. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x430++0x3 line.long 0x00 "CONTROL_CONF_SDMA_REQ_SEL1,System DMA requests view channel 1 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long.byte 0x00 0.--6. 1. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x434++0x3 line.long 0x00 "CONTROL_CONF_SDMA_REQ_SEL2,System DMA requests view channel 2 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long.byte 0x00 0.--6. 1. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x438++0x3 line.long 0x00 "CONTROL_CONF_SDMA_REQ_SEL3,System DMA requests view channel 3 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long.byte 0x00 0.--6. 1. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . -.." group.long 0x440++0x3 line.long 0x00 "CONTROL_CONF_CLK_SEL0,clk view channel 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - ." "hwobs_coredpll_clkout,hwobs_abedpll_clkout,hwobs_perdpll_clkout,hwobs_dsi1dpll_clkout,hwobs_dsi2dpll_clkout,reserved,hwobs_usbdpll_clkout,?..." group.long 0x444++0x3 line.long 0x00 "CONTROL_CONF_CLK_SEL1,clk view channel 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - ." "hwobs_coredpll_clkout,hwobs_abedpll_clkout,hwobs_perdpll_clkout,hwobs_dsi1dpll_clkout,hwobs_dsi2dpll_clkout,reserved,hwobs_usbdpll_clkout,?..." group.long 0x448++0x3 line.long 0x00 "CONTROL_CONF_CLK_SEL2,clk view channel 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - ." "hwobs_coredpll_clkout,hwobs_abedpll_clkout,hwobs_perdpll_clkout,hwobs_dsi1dpll_clkout,hwobs_dsi2dpll_clkout,reserved,hwobs_usbdpll_clkout,?..." group.long 0x44C++0x3 line.long 0x00 "CONTROL_CONF_DPLL_FREQLOCK_SEL,dpll_freqlock view Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - ." "hwobs_coredpll_freqlock,hwobs_abedpll_freqlock,hwobs_perdpll_freqlock,hwobs_dsi1dpll_freqlock,hwobs_dsi2dpll_freqlock,reserved,hwobs_usbdpll_freqlock,?..." group.long 0x450++0x3 line.long 0x00 "CONTROL_CONF_DPLL_TINITZ_SEL,dpll_tinitz view Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - ." "hwobs_coredpll_tinitz,1,2,3,4,5,6,7" group.long 0x454++0x3 line.long 0x00 "CONTROL_CONF_DPLL_PHASELOCK_SEL,dpll_phaselock view Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - ." "hwobs_coredpll_phaselock,hwobs_abedpll_phaselock,hwobs_perdpll_phaselock,hwobs_dsi1dpll_phaselock,hwobs_dsi2dpll_phaselock,reserved,hwobs_usbdpll_phaselock,?..." group.long 0x45C++0x3 line.long 0x00 "CONTROL_CONF_DPLL_TENABLE_SEL,dpll_tenable view Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - ." "hwobs_coredpll_tenable,hwobs_abedpll_tenable,hwobs_perdpll_tenable,hwobs_dsi1dpll_tenable,hwobs_dsi2dpll_tenable,reserved,hwobs_usbdpll_tenable,?..." group.long 0x460++0x3 line.long 0x00 "CONTROL_CONF_DPLL_TENABLEDIV_SEL,dpll_tenablediv view Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - ." "hwobs_coredpll_tenablediv,hwobs_abedpll_tenablediv,hwobs_perdpll_tenablediv,hwobs_dsi1dpll_tenablediv,hwobs_dsi2dpll_tenablediv,reserved,hwobs_usbdpll_tenablediv,?..." group.long 0x464++0x3 line.long 0x00 "CONTROL_CONF_DPLL_BYPASSACK_SEL,dpll_bypassack view Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - ." "hwobs_coredpll_bypassack,hwobs_abedpll_bypassack,hwobs_perdpll_bypassack,hwobs_dsi1dpll_bypassack,hwobs_dsi2dpll_bypassack,reserved,hwobs_usbdpll_bypassack,?..." group.long 0x468++0x3 line.long 0x00 "CONTROL_CONF_DPLL_IDLE_SEL,dpll_idle view Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--2. " MULT ,Select one of the following signals: - . - . - . - . - . - . - . - ." "hwobs_coredpll_idle,hwobs_abedpll_idle,hwobs_perdpll_idle,hwobs_dsi1dpll_idle,hwobs_dsi2dpll_idle,reserved,hwobs_usbdpll_idle,?..." group.long 0x480++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_0,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_0,clk_view_0,reserved,reserved,4,hwobs_int_cm2_0,hwobs_int_ivahd_0,reserved,hwobs_int_abe_0,9,reserved,reserved,12,13,14,15" group.long 0x484++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_1,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_1,clk_view_1,reserved,reserved,reserved,hwobs_int_cm2_1,hwobs_int_ivahd_1,reserved,hwobs_int_abe_1,9,reserved,reserved,12,13,14,15" group.long 0x488++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_2,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_2,clk_view_2,reserved,reserved,reserved,hwobs_int_cm2_2,hwobs_int_ivahd_2,reserved,hwobs_int_abe_2,9,reserved,reserved,12,13,14,15" group.long 0x48C++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_3,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_3,dpll_freqlock,reserved,reserved,reserved,hwobs_int_cm2_3,hwobs_int_ivahd_3,reserved,hwobs_int_abe_3,9,reserved,reserved,12,13,14,15" group.long 0x490++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_4,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_4,dpll_tinitz,reserved,reserved,reserved,hwobs_int_cm2_4,hwobs_int_ivahd_4,reserved,hwobs_int_abe_4,9,reserved,reserved,12,13,14,15" group.long 0x494++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_5,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_5,dpll_phaselock,reserved,reserved,reserved,hwobs_int_cm2_5,hwobs_int_ivahd_5,reserved,hwobs_int_abe_5,9,reserved,reserved,12,13,14,15" group.long 0x498++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_6,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_6,reserved,reserved,reserved,reserved,hwobs_int_cm2_6,hwobs_int_ivahd_6,reserved,hwobs_int_abe_6,9,reserved,reserved,12,13,14,15" group.long 0x49C++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_7,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_7,dpll_tenable,sdma_req_view_0,reserved,reserved,hwobs_int_cm2_7,hwobs_int_ivahd_7,reserved,hwobs_int_abe_7,9,reserved,reserved,12,13,14,15" group.long 0x4A0++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_8,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_8,dpll_tenablediv,sdma_req_view_1,reserved,reserved,hwobs_int_cm2_8,hwobs_int_ivahd_8,reserved,hwobs_int_abe_8,9,reserved,reserved,12,13,14,15" group.long 0x4A4++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_9,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_9,dpll_bypassack,sdma_req_view_2,reserved,reserved,hwobs_int_cm2_9,hwobs_int_ivahd_9,reserved,hwobs_int_abe_9,9,reserved,hwobs_dssvenctvdetgp,12,13,14,15" group.long 0x4A8++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_10,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_10,dpll_idle,sdma_req_view_3,reserved,reserved,hwobs_int_cm2_10,hwobs_int_ivahd_10,reserved,hwobs_int_abe_10,9,reserved,11,12,13,14,15" group.long 0x4AC++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_11,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_11,hwobs_hsusbotg_sofpulse,sdma_req_view_all,reserved,reserved,hwobs_int_cm2_11,hwobs_int_ivahd_11,reserved,hwobs_int_abe_11,9,reserved,11,12,13,14,15" group.long 0x4B0++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_12,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_12,reserved,hwobs_coredivider_clkout3,reserved,reserved,hwobs_int_cm2_12,hwobs_int_ivahd_12,reserved,hwobs_int_abe_12,9,reserved,hwobs_dssdacpwrdndaccvbs,12,13,14,15" group.long 0x4B4++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_13,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_13,reserved,hwobs_perdivider_clkout4,reserved,reserved,hwobs_int_cm2_13,hwobs_int_ivahd_13,reserved,hwobs_int_abe_13,9,reserved,hwobs_dssdacpwrdnbgz,12,13,14,15" group.long 0x4B8++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_14,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_14,reserved,2,reserved,reserved,hwobs_int_cm2_14,hwobs_int_ivahd_14,reserved,hwobs_int_abe_14,9,reserved,reserved,12,13,14,15" group.long 0x4BC++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_15,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_15,reserved,0,reserved,reserved,hwobs_int_cm2_15,hwobs_int_ivahd_15,reserved,hwobs_int_abe_15,9,reserved,reserved,12,13,14,15" group.long 0x4C0++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_16,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_16,reserved,0,reserved,reserved,hwobs_int_cm2_16,hwobs_int_ivahd_16,reserved,hwobs_int_abe_16,9,reserved,reserved,12,13,14,15" group.long 0x4C4++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_17,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_17,reserved,0,reserved,reserved,hwobs_int_cm2_17,hwobs_int_ivahd_17,reserved,hwobs_int_abe_17,9,reserved,reserved,12,13,14,15" group.long 0x4C8++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_18,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_18,reserved,0,reserved,reserved,hwobs_int_cm2_18,hwobs_int_ivahd_18,reserved,hwobs_int_abe_18,9,reserved,reserved,12,13,14,15" group.long 0x4CC++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_19,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_19,reserved,0,reserved,reserved,hwobs_int_cm2_19,hwobs_int_ivahd_19,reserved,hwobs_int_abe_19,9,reserved,reserved,12,13,14,15" group.long 0x4D0++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_20,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_20,reserved,0,reserved,reserved,hwobs_int_cm2_20,hwobs_int_ivahd_20,reserved,hwobs_int_abe_20,9,reserved,reserved,12,13,14,15" group.long 0x4D4++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_21,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_21,reserved,0,reserved,reserved,hwobs_int_cm2_21,hwobs_int_ivahd_21,reserved,hwobs_int_abe_21,9,reserved,11,12,13,14,15" group.long 0x4D8++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_22,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_22,reserved,0,reserved,reserved,hwobs_int_cm2_22,hwobs_int_ivahd_22,reserved,hwobs_int_abe_22,9,reserved,11,12,13,14,15" group.long 0x4DC++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_23,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_23,reserved,0,reserved,reserved,hwobs_int_cm2_23,hwobs_int_ivahd_23,reserved,hwobs_int_abe_23,9,reserved,11,12,13,14,15" group.long 0x4E0++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_24,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_24,reserved,0,reserved,reserved,hwobs_int_cm2_24,hwobs_int_ivahd_24,reserved,hwobs_int_abe_24,9,reserved,11,12,13,14,15" group.long 0x4E4++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_25,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_25,reserved,0,reserved,reserved,hwobs_int_cm2_25,hwobs_int_ivahd_25,reserved,hwobs_int_abe_25,9,reserved,11,12,13,14,15" group.long 0x4E8++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_26,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_26,reserved,0,reserved,0,hwobs_int_cm2_26,hwobs_int_ivahd_26,reserved,hwobs_int_abe_26,9,reserved,11,12,13,14,15" group.long 0x4EC++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_27,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_27,reserved,0,reserved,0,hwobs_int_cm2_27,hwobs_int_ivahd_27,reserved,hwobs_int_abe_27,9,reserved,0,sdma_req_view_0,13,14,15" group.long 0x4F0++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_28,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_28,reserved,0,reserved,0,hwobs_int_cm2_28,hwobs_int_ivahd_28,reserved,hwobs_int_abe_28,9,reserved,0,sdma_req_view_1,13,14,15" group.long 0x4F4++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_29,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_29,reserved,0,reserved,0,hwobs_int_cm2_29,hwobs_int_ivahd_29,reserved,hwobs_int_abe_29,9,reserved,0,sdma_req_view_2,13,14,15" group.long 0x4F8++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_30,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_30,reserved,0,reserved,0,hwobs_int_cm2_30,hwobs_int_ivahd_30,reserved,hwobs_int_abe_30,9,reserved,0,sdma_req_view_3,13,14,15" group.long 0x4FC++0x3 line.long 0x00 "CONTROL_CORE_CONF_DEBUG_SEL_TST_31,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0.--3. " MODE ,Select one of the following signals: - . - . - . - . - . - . - . - . - . - . - . - . - ." "hwobs_int_mpu_31,reserved,0,reserved,0,hwobs_int_cm2_31,hwobs_int_ivahd_31,reserved,hwobs_int_abe_31,9,reserved,0,sdma_req_view_all,13,14,15" tree.end tree "SYSCTRL_PADCONF_CORE" base ad:0x4A100000 width 62. rgroup.long 0x0++0x3 line.long 0x00 "CONTROL_PADCONF_CORE_REVISION,Control module revision identifier Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "CONTROL_PADCONF_CORE_HWINFO,Information about the IP module hardware configuration that is, typically the module HDL generics (if any). Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " IP_HWINFO ,IP-module dependent" group.long 0x10++0x3 line.long 0x00 "CONTROL_PADCONF_CORE_SYSCONFIG,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 2.--3. " IP_SYSCONFIG_IDLEMODE ,Select the local clock-gating strategy - . - . 0x2,0x3: Clock is automatically gated when there is no access to the Control Module through L4-interconnect. - ." "0,1,2,3" group.long 0x40++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_AD0_PAD1_GPMC_AD1,Register control for Pads gpmc_ad0 and gpmc_ad1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_AD1_WAKEUPEVENT ,Pad_x wake-up event status latched in the I/O - . - ." "0,1" bitfld.long 0x00 30. " GPMC_AD1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_AD1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_AD1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad1 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_AD1_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad1 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_AD1_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad1. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_AD1_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad1 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_AD1_INPUTENABLE ,Input enable value for pad gpmc_ad1 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_AD1_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad1 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_AD1_PULLUDENABLE ,pullup/down enable for pad gpmc_ad1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_AD1_MUXMODE ,Functional multiplexing selection for pad gpmc_ad1 - . - ." "Select_gpmc_ad1,Select_sdmmc2_dat1,2,3,4,5,6,7" bitfld.long 0x00 15. " GPMC_AD0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_AD0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_AD0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_AD0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad0 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_AD0_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad0 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_AD0_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad0. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_AD0_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad0 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_AD0_INPUTENABLE ,Input enable value for pad gpmc_ad0 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_AD0_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_AD0_PULLUDENABLE ,pullup/down enable for pad gpmc_ad0 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_AD0_MUXMODE ,Functional multiplexing selection for pad gpmc_ad0 - . - ." "Select_gpmc_ad0,Select_sdmmc2_dat0,2,3,4,5,6,7" group.long 0x44++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_AD2_PAD1_GPMC_AD3,Register control for Pads gpmc_ad2 and gpmc_ad3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_AD3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_AD3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_AD3__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_AD3__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad3 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_AD3_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad3 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_AD3_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad3. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_AD3_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad3 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_AD3_INPUTENABLE ,Input enable value for pad gpmc_ad3 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_AD3_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad3 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_AD3_PULLUDENABLE ,pullup/down enable for pad gpmc_ad3 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_AD3_MUXMODE ,Functional multiplexing selection for pad gpmc_ad3 - . - ." "Select_gpmc_ad3,Select_sdmmc2_dat3,2,3,4,5,6,7" bitfld.long 0x00 15. " GPMC_AD2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_AD2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_AD2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_AD2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad2 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_AD2_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad2 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_AD2_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad2. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_AD2_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad2 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_AD2_INPUTENABLE ,Input enable value for pad gpmc_ad2 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_AD2_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_AD2_PULLUDENABLE ,pullup/down enable for pad gpmc_ad2 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_AD2_MUXMODE ,Functional multiplexing selection for pad gpmc_ad2 - . - ." "Select_gpmc_ad2,Select_sdmmc2_dat2,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_AD4_PAD1_GPMC_AD5,Register control for Pads gpmc_ad4 and gpmc_ad5 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_AD5_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_AD5_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_AD5__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad5 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_AD5__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad5 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_AD5_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad5 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_AD5_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad5. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_AD5_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad5 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_AD5_INPUTENABLE ,Input enable value for pad gpmc_ad5 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_AD5_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad5 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_AD5_PULLUDENABLE ,pullup/down enable for pad gpmc_ad5 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_AD5_MUXMODE ,Functional multiplexing selection for pad gpmc_ad5 - . - . - ." "Select_gpmc_ad5,Select_sdmmc2_dat5,Select_sdmmc2_dir_dat1,3,4,5,6,7" bitfld.long 0x00 15. " GPMC_AD4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_AD4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_AD4__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad4 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_AD4__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad4 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_AD4_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad4 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_AD4_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad4. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_AD4_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad4 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_AD4_INPUTENABLE ,Input enable value for pad gpmc_ad4 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_AD4_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad4 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_AD4_PULLUDENABLE ,pullup/down enable for pad gpmc_ad4 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_AD4_MUXMODE ,Functional multiplexing selection for pad gpmc_ad4 - . - . - ." "Select_gpmc_ad4,Select_sdmmc2_dat4,Select_sdmmc2_dir_dat0,3,4,5,6,7" group.long 0x4C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_AD6_PAD1_GPMC_AD7,Register control for Pads gpmc_ad6 and gpmc_ad7 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_AD7_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_AD7_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_AD7__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad7 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_AD7__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad7 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_AD7_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad7 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_AD7_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad7. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_AD7_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad7 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_AD7_INPUTENABLE ,Input enable value for pad gpmc_ad7 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_AD7_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad7 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_AD7_PULLUDENABLE ,pullup/down enable for pad gpmc_ad7 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_AD7_MUXMODE ,Functional multiplexing selection for pad gpmc_ad7 - . - . - ." "Select_gpmc_ad7,Select_sdmmc2_dat7,Select_sdmmc2_clk_fdbk,3,4,5,6,7" bitfld.long 0x00 15. " GPMC_AD6_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_AD6_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_AD6__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad6 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_AD6__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad6 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_AD6_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad6 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_AD6_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad6. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_AD6_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad6 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_AD6_INPUTENABLE ,Input enable value for pad gpmc_ad6 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_AD6_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad6 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_AD6_PULLUDENABLE ,pullup/down enable for pad gpmc_ad6 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_AD6_MUXMODE ,Functional multiplexing selection for pad gpmc_ad6 - . - . - ." "Select_gpmc_ad6,Select_sdmmc2_dat6,Select_sdmmc2_dir_cmd,3,4,5,6,7" group.long 0x50++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_AD8_PAD1_GPMC_AD9,Register control for Pads gpmc_ad8 and gpmc_ad9 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_AD9_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_AD9_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_AD9__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad9 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_AD9__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad9 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_AD9_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad9 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_AD9_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad9. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_AD9_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad9 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_AD9_INPUTENABLE ,Input enable value for pad gpmc_ad9 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_AD9_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad9 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_AD9_PULLUDENABLE ,pullup/down enable for pad gpmc_ad9 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_AD9_MUXMODE ,Functional multiplexing selection for pad gpmc_ad9 - . - . - . - . - ." "Select_gpmc_ad9,Select_kpd_row1,Select_c2c_data14,Select_gpio_33,4,Select_sdmmc1_dat1,6,7" bitfld.long 0x00 15. " GPMC_AD8_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_AD8_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_AD8__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad8 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_AD8__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad8 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_AD8_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad8 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_AD8_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad8. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_AD8_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad8 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_AD8_INPUTENABLE ,Input enable value for pad gpmc_ad8 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_AD8_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad8 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_AD8_PULLUDENABLE ,pullup/down enable for pad gpmc_ad8 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_AD8_MUXMODE ,Functional multiplexing selection for pad gpmc_ad8 - . - . - . - . - ." "Select_gpmc_ad8,Select_kpd_row0,Select_c2c_data15,Select_gpio_32,4,Select_sdmmc1_dat0,6,7" group.long 0x54++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_AD10_PAD1_GPMC_AD11,Register control for Pads gpmc_ad10 and gpmc_ad11 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_AD11_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_AD11_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_AD11__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad11 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_AD11__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad11 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_AD11_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad11 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_AD11_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad11. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_AD11_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad11 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_AD11_INPUTENABLE ,Input enable value for pad gpmc_ad11 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_AD11_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad11 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_AD11_PULLUDENABLE ,pullup/down enable for pad gpmc_ad11 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_AD11_MUXMODE ,Functional multiplexing selection for pad gpmc_ad11 - . - . - . - . - ." "Select_gpmc_ad11,Select_kpd_row3,Select_c2c_data12,Select_gpio_35,4,Select_sdmmc1_dat3,6,7" bitfld.long 0x00 15. " GPMC_AD10_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_AD10_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_AD10__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad10 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_AD10__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad10 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_AD10_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad10 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_AD10_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad10. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_AD10_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad10 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_AD10_INPUTENABLE ,Input enable value for pad gpmc_ad10 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_AD10_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad10 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_AD10_PULLUDENABLE ,pullup/down enable for pad gpmc_ad10 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_AD10_MUXMODE ,Functional multiplexing selection for pad gpmc_ad10 - . - . - . - . - ." "Select_gpmc_ad10,Select_kpd_row2,Select_c2c_data13,Select_gpio_34,4,Select_sdmmc1_dat2,6,7" group.long 0x58++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_AD12_PAD1_GPMC_AD13,Register control for Pads gpmc_ad12 and gpmc_ad13 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_AD13_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_AD13_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_AD13__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad13 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_AD13__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad13 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_AD13_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad13 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_AD13_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad13. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_AD13_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad13 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_AD13_INPUTENABLE ,Input enable value for pad gpmc_ad13 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_AD13_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad13 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_AD13_PULLUDENABLE ,pullup/down enable for pad gpmc_ad13 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_AD13_MUXMODE ,Functional multiplexing selection for pad gpmc_ad13 - . - . - . - . - ." "Select_gpmc_ad13,Select_kpd_col1,Select_c2c_data10,Select_gpio_37,4,Select_sdmmc1_dat5,6,7" bitfld.long 0x00 15. " GPMC_AD12_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_AD12_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_AD12__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad12 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_AD12__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad12 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_AD12_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad12 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_AD12_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad12. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_AD12_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad12 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_AD12_INPUTENABLE ,Input enable value for pad gpmc_ad12 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_AD12_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad12 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_AD12_PULLUDENABLE ,pullup/down enable for pad gpmc_ad12 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_AD12_MUXMODE ,Functional multiplexing selection for pad gpmc_ad12 - . - . - . - . - ." "Select_gpmc_ad12,Select_kpd_col0,Select_c2c_data11,Select_gpio_36,4,Select_sdmmc1_dat4,6,7" group.long 0x5C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_AD14_PAD1_GPMC_AD15,Register control for Pads gpmc_ad14 and gpmc_ad15 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_AD15_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_AD15_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_AD15__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad15 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_AD15__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad15 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_AD15_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad15 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_AD15_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad15. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_AD15_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad15 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_AD15_INPUTENABLE ,Input enable value for pad gpmc_ad15 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_AD15_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad15 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_AD15_PULLUDENABLE ,pullup/down enable for pad gpmc_ad15 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_AD15_MUXMODE ,Functional multiplexing selection for pad gpmc_ad15 - . - . - . - . - ." "Select_gpmc_ad15,Select_kpd_col3,Select_c2c_data8,Select_gpio_39,4,Select_sdmmc1_dat7,6,7" bitfld.long 0x00 15. " GPMC_AD14_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_AD14_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_AD14__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ad14 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_AD14__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ad14 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_AD14_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ad14 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_AD14_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ad14. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_AD14_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ad14 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_AD14_INPUTENABLE ,Input enable value for pad gpmc_ad14 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_AD14_PULLTYPESELECT ,pullup/down selection for pad gpmc_ad14 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_AD14_PULLUDENABLE ,pullup/down enable for pad gpmc_ad14 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_AD14_MUXMODE ,Functional multiplexing selection for pad gpmc_ad14 - . - . - . - . - ." "Select_gpmc_ad14,Select_kpd_col2,Select_c2c_data9,Select_gpio_38,4,Select_sdmmc1_dat6,6,7" group.long 0x60++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_A16_PAD1_GPMC_A17,Register control for Pads gpmc_a16 and gpmc_a17 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_A17_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_A17_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_A17__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a17 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_A17__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a17 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_A17_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a17 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_A17_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a17. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_A17_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a17 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_A17_INPUTENABLE ,Input enable value for pad gpmc_a17 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_A17_PULLTYPESELECT ,pullup/down selection for pad gpmc_a17 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_A17_PULLUDENABLE ,pullup/down enable for pad gpmc_a17 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_A17_MUXMODE ,Functional multiplexing selection for pad gpmc_a17 - . - . - . - . - . - ." "Select_gpmc_a17,Select_kpd_row5,Select_c2c_datain1,Select_gpio_41,Select_venc_656_data1,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_A16_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_A16_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_A16__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a16 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_A16__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a16 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_A16_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a16 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_A16_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a16. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_A16_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a16 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_A16_INPUTENABLE ,Input enable value for pad gpmc_a16 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_A16_PULLTYPESELECT ,pullup/down selection for pad gpmc_a16 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_A16_PULLUDENABLE ,pullup/down enable for pad gpmc_a16 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_A16_MUXMODE ,Functional multiplexing selection for pad gpmc_a16 - . - . - . - . - . - ." "Select_gpmc_a16,Select_kpd_row4,Select_c2c_datain0,Select_gpio_40,Select_venc_656_data0,5,6,Select_safe_mode" group.long 0x64++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_A18_PAD1_GPMC_A19,Register control for Pads gpmc_a18 and gpmc_a19 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_A19_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_A19_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_A19__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a19 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_A19__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a19 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_A19_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a19 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_A19_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a19. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_A19_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a19 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_A19_INPUTENABLE ,Input enable value for pad gpmc_a19 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_A19_PULLTYPESELECT ,pullup/down selection for pad gpmc_a19 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_A19_PULLUDENABLE ,pullup/down enable for pad gpmc_a19 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_A19_MUXMODE ,Functional multiplexing selection for pad gpmc_a19 - . - . - . - . - . - ." "Select_gpmc_a19,Select_kpd_row7,Select_c2c_datain3,Select_gpio_43,Select_venc_656_data3,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_A18_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_A18_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_A18__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a18 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_A18__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a18 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_A18_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a18 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_A18_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a18. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_A18_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a18 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_A18_INPUTENABLE ,Input enable value for pad gpmc_a18 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_A18_PULLTYPESELECT ,pullup/down selection for pad gpmc_a18 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_A18_PULLUDENABLE ,pullup/down enable for pad gpmc_a18 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_A18_MUXMODE ,Functional multiplexing selection for pad gpmc_a18 - . - . - . - . - . - ." "Select_gpmc_a18,Select_kpd_row6,Select_c2c_datain2,Select_gpio_42,Select_venc_656_data2,5,6,Select_safe_mode" group.long 0x68++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_A20_PAD1_GPMC_A21,Register control for Pads gpmc_a20 and gpmc_a21 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_A21_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_A21_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_A21__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a21 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_A21__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a21 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_A21_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a21 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_A21_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a21. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_A21_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a21 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_A21_INPUTENABLE ,Input enable value for pad gpmc_a21 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_A21_PULLTYPESELECT ,pullup/down selection for pad gpmc_a21 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_A21_PULLUDENABLE ,pullup/down enable for pad gpmc_a21 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_A21_MUXMODE ,Functional multiplexing selection for pad gpmc_a21 - . - . - . - . - . - ." "Select_gpmc_a21,Select_kpd_col5,Select_c2c_datain5,Select_gpio_45,Select_venc_656_data5,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_A20_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_A20_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_A20__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a20 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_A20__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a20 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_A20_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a20 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_A20_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a20. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_A20_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a20 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_A20_INPUTENABLE ,Input enable value for pad gpmc_a20 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_A20_PULLTYPESELECT ,pullup/down selection for pad gpmc_a20 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_A20_PULLUDENABLE ,pullup/down enable for pad gpmc_a20 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_A20_MUXMODE ,Functional multiplexing selection for pad gpmc_a20 - . - . - . - . - . - ." "Select_gpmc_a20,Select_kpd_col4,Select_c2c_datain4,Select_gpio_44,Select_venc_656_data4,5,6,Select_safe_mode" group.long 0x6C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_A22_PAD1_GPMC_A23,Register control for Pads gpmc_a22 and gpmc_a23 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_A23_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_A23_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_A23__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a23 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_A23__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a23 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_A23_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a23 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_A23_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a23. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_A23_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a23 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_A23_INPUTENABLE ,Input enable value for pad gpmc_a23 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_A23_PULLTYPESELECT ,pullup/down selection for pad gpmc_a23 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_A23_PULLUDENABLE ,pullup/down enable for pad gpmc_a23 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_A23_MUXMODE ,Functional multiplexing selection for pad gpmc_a23 - . - . - . - . - . - ." "Select_gpmc_a23,Select_kpd_col7,Select_c2c_datain7,Select_gpio_47,Select_venc_656_data7,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_A22_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_A22_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_A22__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a22 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_A22__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a22 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_A22_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a22 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_A22_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a22. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_A22_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a22 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_A22_INPUTENABLE ,Input enable value for pad gpmc_a22 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_A22_PULLTYPESELECT ,pullup/down selection for pad gpmc_a22 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_A22_PULLUDENABLE ,pullup/down enable for pad gpmc_a22 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_A22_MUXMODE ,Functional multiplexing selection for pad gpmc_a22 - . - . - . - . - . - ." "Select_gpmc_a22,Select_kpd_col6,Select_c2c_datain6,Select_gpio_46,Select_venc_656_data6,5,6,Select_safe_mode" group.long 0x70++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_A24_PAD1_GPMC_A25,Register control for Pads gpmc_a24 and gpmc_a25 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_A25_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_A25_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_A25__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a25 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_A25__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a25 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_A25_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a25 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_A25_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a25. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_A25_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a25 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_A25_INPUTENABLE ,Input enable value for pad gpmc_a25 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_A25_PULLTYPESELECT ,pullup/down selection for pad gpmc_a25 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_A25_PULLUDENABLE ,pullup/down enable for pad gpmc_a25 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_A25_MUXMODE ,Functional multiplexing selection for pad gpmc_a25 - . - . - . - ." "Select_gpmc_a25,1,Select_c2c_clkout1,Select_gpio_49,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_A24_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_A24_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_A24__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_a24 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_A24__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_a24 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_A24_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_a24 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_A24_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_a24. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_A24_OFFMODEENABLE ,OffMode mode override control for pad gpmc_a24 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_A24_INPUTENABLE ,Input enable value for pad gpmc_a24 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_A24_PULLTYPESELECT ,pullup/down selection for pad gpmc_a24 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_A24_PULLUDENABLE ,pullup/down enable for pad gpmc_a24 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_A24_MUXMODE ,Functional multiplexing selection for pad gpmc_a24 - . - . - . - . - ." "Select_gpmc_a24,Select_kpd_col8,Select_c2c_clkout0,Select_gpio_48,4,5,6,Select_safe_mode" group.long 0x74++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_NCS0_PAD1_GPMC_NCS1,Register control for Pads gpmc_ncs0 and gpmc_ncs1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_NCS1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_NCS1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_NCS1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ncs1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_NCS1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ncs1 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_NCS1_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ncs1 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_NCS1_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ncs1. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_NCS1_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ncs1 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_NCS1_INPUTENABLE ,Input enable value for pad gpmc_ncs1 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_NCS1_PULLTYPESELECT ,pullup/down selection for pad gpmc_ncs1 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_NCS1_PULLUDENABLE ,pullup/down enable for pad gpmc_ncs1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_NCS1_MUXMODE ,Functional multiplexing selection for pad gpmc_ncs1 - . - . - . - ." "Select_gpmc_ncs1,1,Select_c2c_dataout6,Select_gpio_51,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_NCS0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_NCS0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_NCS0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ncs0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_NCS0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ncs0 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_NCS0_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ncs0 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_NCS0_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ncs0. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_NCS0_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ncs0 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_NCS0_INPUTENABLE ,Input enable value for pad gpmc_ncs0 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_NCS0_PULLTYPESELECT ,pullup/down selection for pad gpmc_ncs0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_NCS0_PULLUDENABLE ,pullup/down enable for pad gpmc_ncs0 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_NCS0_MUXMODE ,Functional multiplexing selection for pad gpmc_ncs0 - . - . - ." "Select_gpmc_ncs0,1,2,Select_gpio_50,Select_sys_ndmareq0,5,6,7" group.long 0x78++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_NCS2_PAD1_GPMC_NCS3,Register control for Pads gpmc_ncs2 and gpmc_ncs3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_NCS3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_NCS3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_NCS3__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ncs3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_NCS3__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ncs3 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_NCS3_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ncs3 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_NCS3_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ncs3. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_NCS3_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ncs3 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_NCS3_INPUTENABLE ,Input enable value for pad gpmc_ncs3 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_NCS3_PULLTYPESELECT ,pullup/down selection for pad gpmc_ncs3 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_NCS3_PULLUDENABLE ,pullup/down enable for pad gpmc_ncs3 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_NCS3_MUXMODE ,Functional multiplexing selection for pad gpmc_ncs3 - . - . - . - . - ." "Select_gpmc_ncs3,Select_gpmc_dir,Select_c2c_dataout4,Select_gpio_53,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_NCS2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_NCS2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_NCS2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ncs2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_NCS2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ncs2 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_NCS2_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ncs2 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_NCS2_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ncs2. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_NCS2_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ncs2 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_NCS2_INPUTENABLE ,Input enable value for pad gpmc_ncs2 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_NCS2_PULLTYPESELECT ,pullup/down selection for pad gpmc_ncs2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_NCS2_PULLUDENABLE ,pullup/down enable for pad gpmc_ncs2 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_NCS2_MUXMODE ,Functional multiplexing selection for pad gpmc_ncs2 - . - . - . - . - ." "Select_gpmc_ncs2,Select_kpd_row8,Select_c2c_dataout7,Select_gpio_52,4,5,6,Select_safe_mode" group.long 0x7C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_NWP_PAD1_GPMC_CLK,Register control for Pads gpmc_nwp and gpmc_clk Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_CLK_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_CLK_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_CLK__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_clk - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_CLK__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_clk - . - ." "0,1" bitfld.long 0x00 27. " GPMC_CLK_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_clk - . - ." "0,1" bitfld.long 0x00 26. " GPMC_CLK_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_clk. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_CLK_OFFMODEENABLE ,OffMode mode override control for pad gpmc_clk - . - ." "0,1" bitfld.long 0x00 24. " GPMC_CLK_INPUTENABLE ,Input enable value for pad gpmc_clk - . - ." "0,1" bitfld.long 0x00 20. " GPMC_CLK_PULLTYPESELECT ,pullup/down selection for pad gpmc_clk - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_CLK_PULLUDENABLE ,pullup/down enable for pad gpmc_clk - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_CLK_MUXMODE ,Functional multiplexing selection for pad gpmc_clk - . - . - . - ." "Select_gpmc_clk,1,2,Select_gpio_55,Select_sys_ndmareq2,Select_sdmmc1_cmd,6,7" bitfld.long 0x00 15. " GPMC_NWP_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_NWP_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_NWP__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_nwp - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_NWP__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_nwp - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_NWP_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_nwp - . - ." "0,1" bitfld.long 0x00 10. " GPMC_NWP_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_nwp. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_NWP_OFFMODEENABLE ,OffMode mode override control for pad gpmc_nwp - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_NWP_INPUTENABLE ,Input enable value for pad gpmc_nwp - . - ." "0,1" bitfld.long 0x00 4. " GPMC_NWP_PULLTYPESELECT ,pullup/down selection for pad gpmc_nwp - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_NWP_PULLUDENABLE ,pullup/down enable for pad gpmc_nwp - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_NWP_MUXMODE ,Functional multiplexing selection for pad gpmc_nwp - . - . - . - ." "Select_gpmc_nwp,Select_dsi1_te0,2,Select_gpio_54,Select_sys_ndmareq1,5,6,7" group.long 0x80++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_NADV_ALE_PAD1_GPMC_NOE,Register control for Pads gpmc_nadv_ale and gpmc_noe Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_NOE_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_NOE_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_NOE__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_noe - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_NOE__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_noe - . - ." "0,1" bitfld.long 0x00 27. " GPMC_NOE_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_noe - . - ." "0,1" bitfld.long 0x00 26. " GPMC_NOE_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_noe. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_NOE_OFFMODEENABLE ,OffMode mode override control for pad gpmc_noe - . - ." "0,1" bitfld.long 0x00 24. " GPMC_NOE_INPUTENABLE ,Input enable value for pad gpmc_noe - . - ." "0,1" bitfld.long 0x00 20. " GPMC_NOE_PULLTYPESELECT ,pullup/down selection for pad gpmc_noe - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_NOE_PULLUDENABLE ,pullup/down enable for pad gpmc_noe - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_NOE_MUXMODE ,Functional multiplexing selection for pad gpmc_noe - . - ." "Select_gpmc_noe,Select_sdmmc2_clk,2,3,4,5,6,7" bitfld.long 0x00 15. " GPMC_NADV_ALE_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_NADV_ALE_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_NADV_ALE__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_nadv_ale - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_NADV_ALE__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_nadv_ale - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_NADV_ALE_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_nadv_ale - . - ." "0,1" bitfld.long 0x00 10. " GPMC_NADV_ALE_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_nadv_ale. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_NADV_ALE_OFFMODEENABLE ,OffMode mode override control for pad gpmc_nadv_ale - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_NADV_ALE_INPUTENABLE ,Input enable value for pad gpmc_nadv_ale - . - ." "0,1" bitfld.long 0x00 4. " GPMC_NADV_ALE_PULLTYPESELECT ,pullup/down selection for pad gpmc_nadv_ale - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_NADV_ALE_PULLUDENABLE ,pullup/down enable for pad gpmc_nadv_ale - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_NADV_ALE_MUXMODE ,Functional multiplexing selection for pad gpmc_nadv_ale - . - . - . - . - ." "Select_gpmc_nadv_ale,Select_dsi1_te1,2,Select_gpio_56,Select_sys_ndmareq3,Select_sdmmc1_clk,6,7" group.long 0x84++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_NWE_PAD1_GPMC_NBE0_CLE,Register control for Pads gpmc_nwe and gpmc_nbe0_cle Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_NBE0_CLE_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_NBE0_CLE_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_NBE0_CLE__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_nbe0_cle - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_NBE0_CLE__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_nbe0_cle - . - ." "0,1" bitfld.long 0x00 27. " GPMC_NBE0_CLE_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_nbe0_cle - . - ." "0,1" bitfld.long 0x00 26. " GPMC_NBE0_CLE_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_nbe0_cle. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_NBE0_CLE_OFFMODEENABLE ,OffMode mode override control for pad gpmc_nbe0_cle - . - ." "0,1" bitfld.long 0x00 24. " GPMC_NBE0_CLE_INPUTENABLE ,Input enable value for pad gpmc_nbe0_cle - . - ." "0,1" bitfld.long 0x00 20. " GPMC_NBE0_CLE_PULLTYPESELECT ,pullup/down selection for pad gpmc_nbe0_cle - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_NBE0_CLE_PULLUDENABLE ,pullup/down enable for pad gpmc_nbe0_cle - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_NBE0_CLE_MUXMODE ,Functional multiplexing selection for pad gpmc_nbe0_cle - . - . - ." "Select_gpmc_nbe0_cle,Select_dsi2_te0,2,Select_gpio_59,4,5,6,7" bitfld.long 0x00 15. " GPMC_NWE_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_NWE_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_NWE__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_nwe - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_NWE__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_nwe - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_NWE_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_nwe - . - ." "0,1" bitfld.long 0x00 10. " GPMC_NWE_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_nwe. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_NWE_OFFMODEENABLE ,OffMode mode override control for pad gpmc_nwe - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_NWE_INPUTENABLE ,Input enable value for pad gpmc_nwe - . - ." "0,1" bitfld.long 0x00 4. " GPMC_NWE_PULLTYPESELECT ,pullup/down selection for pad gpmc_nwe - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_NWE_PULLUDENABLE ,pullup/down enable for pad gpmc_nwe - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_NWE_MUXMODE ,Functional multiplexing selection for pad gpmc_nwe - . - ." "Select_gpmc_nwe,Select_sdmmc2_cmd,2,3,4,5,6,7" group.long 0x88++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_NBE1_PAD1_GPMC_WAIT0,Register control for Pads gpmc_nbe1 and gpmc_wait0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_WAIT0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_WAIT0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_WAIT0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_wait0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_WAIT0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_wait0 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_WAIT0__OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_wait0 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_WAIT0__OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_wait0. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_WAIT0_OFFMODEENABLE ,OffMode mode override control for pad gpmc_wait0 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_WAIT0_INPUTENABLE ,Input enable value for pad gpmc_wait0 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_WAIT0_PULLTYPESELECT ,pullup/down selection for pad gpmc_wait0 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_WAIT0_PULLUDENABLE ,pullup/down enable for pad gpmc_wait0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_WAIT0_MUXMODE ,Functional multiplexing selection for pad gpmc_wait0 - . - . - ." "Select_gpmc_wait0,Select_dsi2_te1,2,Select_gpio_61,4,5,6,7" bitfld.long 0x00 15. " GPMC_NBE1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_NBE1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_NBE1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_nbe1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_NBE1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_nbe1 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_NBE1_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_nbe1 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_NBE1_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_nbe1. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_NBE1_OFFMODEENABLE ,OffMode mode override control for pad gpmc_nbe1 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_NBE1_INPUTENABLE ,Input enable value for pad gpmc_nbe1 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_NBE1_PULLTYPESELECT ,pullup/down selection for pad gpmc_nbe1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_NBE1_PULLUDENABLE ,pullup/down enable for pad gpmc_nbe1 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_NBE1_MUXMODE ,Functional multiplexing selection for pad gpmc_nbe1 - . - . - . - ." "Select_gpmc_nbe1,1,Select_c2c_dataout5,Select_gpio_60,4,5,6,Select_safe_mode" group.long 0x8C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_WAIT1_PAD1_GPMC_WAIT2,Register control for Pads gpmc_wait1 and gpmc_wait2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_WAIT2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_WAIT2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_WAIT2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_wait2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_WAIT2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_wait2 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_WAIT2_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_wait2 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_WAIT2_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_wait2. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_WAIT2_OFFMODEENABLE ,OffMode mode override control for pad gpmc_wait2 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_WAIT2_INPUTENABLE ,Input enable value for pad gpmc_wait2 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_WAIT2_PULLTYPESELECT ,pullup/down selection for pad gpmc_wait2 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_WAIT2_PULLUDENABLE ,pullup/down enable for pad gpmc_wait2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_WAIT2_MUXMODE ,Functional multiplexing selection for pad gpmc_wait2 - . - . - . - . - . - ." "Select_gpmc_wait2,Select_usbc1_icusb_txen,Select_c2c_dataout3,Select_gpio_100,Select_sys_ndmareq0,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_WAIT1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_WAIT1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_WAIT1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_wait1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_WAIT1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_wait1 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_WAIT1_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_wait1 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_WAIT1_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_wait1. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_WAIT1_OFFMODEENABLE ,OffMode mode override control for pad gpmc_wait1 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_WAIT1_INPUTENABLE ,Input enable value for pad gpmc_wait1 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_WAIT1_PULLTYPESELECT ,pullup/down selection for pad gpmc_wait1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_WAIT1_PULLUDENABLE ,pullup/down enable for pad gpmc_wait1 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_WAIT1_MUXMODE ,Functional multiplexing selection for pad gpmc_wait1 - . - . - . - ." "Select_gpmc_wait1,1,Select_c2c_dataout2,Select_gpio_62,4,5,6,Select_safe_mode" group.long 0x90++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_NCS4_PAD1_GPMC_NCS5,Register control for Pads gpmc_ncs4 and gpmc_ncs5 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_NCS5_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_NCS5_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_NCS5__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ncs5 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_NCS5__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ncs5 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_NCS5_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ncs5 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_NCS5_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ncs5 . This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_NCS5_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ncs5 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_NCS5_INPUTENABLE ,Input enable value for pad gpmc_ncs5 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_NCS5_PULLTYPESELECT ,pullup/down selection for pad gpmc_ncs5 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_NCS5_PULLUDENABLE ,pullup/down enable for pad gpmc_ncs5 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_NCS5_MUXMODE ,Functional multiplexing selection for pad gpmc_ncs5 - . - . - . - . - . - ." "Select_gpmc_ncs5,Select_dsi1_te1,Select_c2c_clkin1,Select_gpio_102,Select_sys_ndmareq2,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_NCS4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_NCS4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_NCS4__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ncs4 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_NCS4__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ncs4 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_NCS4_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ncs4 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_NCS4_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ncs4. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_NCS4_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ncs4 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_NCS4_INPUTENABLE ,Input enable value for pad gpmc_ncs4 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_NCS4_PULLTYPESELECT ,pullup/down selection for pad gpmc_ncs4 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_NCS4_PULLUDENABLE ,pullup/down enable for pad gpmc_cs4 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_NCS4_MUXMODE ,Functional multiplexing selection for pad gpmc_ncs4 - . - . - . - . - . - ." "Select_gpmc_ncs4,Select_dsi1_te0,Select_c2c_clkin0,Select_gpio_101,Select_sys_ndmareq1,5,6,Select_safe_mode" group.long 0x94++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPMC_NCS6_PAD1_GPMC_NCS7,Register control for Pads gpmc_ncs6 and gpmc_ncs7 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_NCS7_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPMC_NCS7_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPMC_NCS7__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ncs7 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPMC_NCS7__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ncs7 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_NCS7_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ncs7 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_NCS7_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ncs7. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPMC_NCS7_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ncs7 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_NCS7_INPUTENABLE ,Input enable value for pad gpmc_ncs7 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_NCS7_PULLTYPESELECT ,pullup/down selection for pad gpmc_ncs7 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPMC_NCS7_PULLUDENABLE ,pullup/down enable for pad gpmc_ncs7 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPMC_NCS7_MUXMODE ,Functional multiplexing selection for pad gpmc_ncs7 - . - . - . - . - ." "Select_gpmc_ncs7,Select_dsi2_te1,Select_c2c_dataout1,Select_gpio_104,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPMC_NCS6_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPMC_NCS6_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPMC_NCS6__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpmc_ncs6 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPMC_NCS6__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpmc_ncs6 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPMC_NCS6_OFFMODEOUTVALUE ,OffMode mode output value for pad gpmc_ncs6 - . - ." "0,1" bitfld.long 0x00 10. " GPMC_NCS6_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpmc_ncs6. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPMC_NCS6_OFFMODEENABLE ,OffMode mode override control for pad gpmc_ncs6 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPMC_NCS6_INPUTENABLE ,Input enable value for pad gpmc_ncs6 - . - ." "0,1" bitfld.long 0x00 4. " GPMC_NCS6_PULLTYPESELECT ,pullup/down selection for pad gpmc_ncs6 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPMC_NCS6_PULLUDENABLE ,pullup/down enable for pad gpmc_ncs6 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPMC_NCS6_MUXMODE ,Functional multiplexing selection for pad gpmc_ncs6 - . - . - . - . - . - ." "Select_gpmc_ncs6,Select_dsi2_te0,Select_c2c_dataout0,Select_gpio_103,Select_sys_ndmareq3,5,6,Select_safe_mode" group.long 0x98++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPIO63_PAD1_GPIO64,Register control for Pads gpio63 and gpio64 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPIO64_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPIO64_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPIO64_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpio64 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPIO64_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpio64 - . - ." "0,1" bitfld.long 0x00 27. " GPIO64_OFFMODEOUTVALUE ,OffMode mode output value for pad gpio64 - . - ." "0,1" bitfld.long 0x00 26. " GPIO64_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpio64. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPIO64_OFFMODEENABLE ,OffMode mode override control for pad gpio64 - . - ." "0,1" bitfld.long 0x00 24. " GPIO64_INPUTENABLE ,Input enable value for pad gpio64 - . - ." "0,1" bitfld.long 0x00 20. " GPIO64_PULLTYPESELECT ,pullup/down selection for pad gpio64 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPIO64_PULLUDENABLE ,pullup/down enable for pad gpio64 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPIO64_MUXMODE ,Functional multiplexing selection for pad gpio64 - . - . - ." "Reserved,1,2,Select_gpio_64,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPIO63_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPIO63_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPIO63_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpio63 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPIO63_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpio63 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPIO63_OFFMODEOUTVALUE ,OffMode mode output value for pad gpio63 - . - ." "0,1" bitfld.long 0x00 10. " GPIO63_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpio63. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPIO63_OFFMODEENABLE ,OffMode mode override control for pad gpio63 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPIO63_INPUTENABLE ,Input enable value for pad gpio63 - . - ." "0,1" bitfld.long 0x00 4. " GPIO63_PULLTYPESELECT ,pullup/down selection for pad gpio63 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPIO63_PULLUDENABLE ,pullup/down enable for pad gpio63 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPIO63_MUXMODE ,Functional multiplexing selection for pad gpio63 - . - . - ." "Reserved,1,2,Select_gpio_63,4,5,6,Select_safe_mode" group.long 0x9C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_GPIO65_PAD1_GPIO66,Register control for Pads gpio65 and gpio66 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPIO66_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " GPIO66_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " GPIO66_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpio66 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " GPIO66_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpio66 - . - ." "0,1" bitfld.long 0x00 27. " GPIO66_OFFMODEOUTVALUE ,OffMode mode output value for pad gpio66 - . - ." "0,1" bitfld.long 0x00 26. " GPIO66_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpio66. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " GPIO66_OFFMODEENABLE ,OffMode mode override control for pad gpio66 - . - ." "0,1" bitfld.long 0x00 24. " GPIO66_INPUTENABLE ,Input enable value for pad gpio66 - . - ." "0,1" bitfld.long 0x00 20. " GPIO66_PULLTYPESELECT ,pullup/down selection for pad gpio66 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " GPIO66_PULLUDENABLE ,pullup/down enable for pad gpio66 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " GPIO66_MUXMODE ,Functional multiplexing selection for pad gpio66 - . - . - ." "Reserved,1,2,Select_gpio_66,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " GPIO65_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " GPIO65_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " GPIO65_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad gpio65 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " GPIO65_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad gpio65 - . - ." "0,1" textline " " bitfld.long 0x00 11. " GPIO65_OFFMODEOUTVALUE ,OffMode mode output value for pad GPIO65 - . - ." "0,1" bitfld.long 0x00 10. " GPIO65_OFFMODEOUTENABLE ,OffMode mode output enable value for pad gpio65. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " GPIO65_OFFMODEENABLE ,OffMode mode override control for pad gpio65 - . - ." "0,1" textline " " bitfld.long 0x00 8. " GPIO65_INPUTENABLE ,Input enable value for pad gpio65 - . - ." "0,1" bitfld.long 0x00 4. " GPIO65_PULLTYPESELECT ,pullup/down selection for pad gpio65 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " GPIO65_PULLUDENABLE ,pullup/down enable for pad gpio65 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " GPIO65_MUXMODE ,Functional multiplexing selection for pad gpio65 - . - . - ." "Reserved,1,2,Select_gpio_65,4,5,6,Select_safe_mode" group.long 0xA0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_CSI21_DX0_PAD1_CSI21_DY0,Register control for Pads csi21_dx0 and csi21_dy0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CSI21_DY0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " CSI21_DY0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " CSI21_DY0_INPUTENABLE ,Input enable value for pad csi21_dy0 - . - ." "0,1" textline " " bitfld.long 0x00 20. " CSI21_DY0_PULLTYPESELECT ,pullup/down selection for pad csi21_dy0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " CSI21_DY0_PULLUDENABLE ,pullup/down enable for pad csi21_dy0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " CSI21_DY0_MUXMODE ,Functional multiplexing selection for pad csi21_dy0 - . - . - ." "Select_csi21_dy0,1,2,Select_gpi_68,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " CSI21_DX0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " CSI21_DX0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " CSI21_DX0_INPUTENABLE ,Input enable value for pad csi21_dx0 - . - ." "0,1" textline " " bitfld.long 0x00 4. " CSI21_DX0_PULLTYPESELECT ,pullup/down selection for pad csi21_dx0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " CSI21_DX0_PULLUDENABLE ,pullup/down enable for pad csi21_dx0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " CSI21_DX0_MUXMODE ,Functional multiplexing selection for pad csi21_dx0 - . - . - ." "Select_csi21_dx0,1,2,Select_gpi_67,4,5,6,Select_safe_mode" group.long 0xA4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_CSI21_DX1_PAD1_CSI21_DY1,Register control for Pads csi21_dx1 and csi21_dy1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CSI21_DY1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " CSI21_DY1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " CSI21_DY1_INPUTENABLE ,Input enable value for pad csi21_dy1 - . - ." "0,1" textline " " bitfld.long 0x00 20. " CSI21_DY1_PULLTYPESELECT ,pullup/down selection for pad csi21_dy1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " CSI21_DY1_PULLUDENABLE ,pullup/down enable for pad csi21_dy1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " CSI21_DY1_MUXMODE ,Functional multiplexing selection for pad csi21_dy1 - . - . - ." "Select_csi21_dy1,1,2,Select_gpi_70,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " CSI21_DX1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " CSI21_DX1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " CSI21_DX1_INPUTENABLE ,Input enable value for pad csi21_dx1 - . - ." "0,1" textline " " bitfld.long 0x00 4. " CSI21_DX1_PULLTYPESELECT ,pullup/down selection for pad csi21_dx1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " CSI21_DX1_PULLUDENABLE ,pullup/down enable for pad csi21_dx1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " CSI21_DX1_MUXMODE ,Functional multiplexing selection for pad csi21_dx1 - . - . - ." "Select_csi21_dx1,1,2,Select_gpi_69,4,5,6,Select_safe_mode" group.long 0xA8++0x3 line.long 0x00 "CONTROL_CORE_PAD0_CSI21_DX2_PAD1_CSI21_DY2,Register control for Pads csi21_dx2 and csi21_dy2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CSI21_DY2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " CSI21_DY2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " CSI21_DY2_INPUTENABLE ,Input enable value for pad csi21_dy2 - . - ." "0,1" textline " " bitfld.long 0x00 20. " CSI21_DY2_PULLTYPESELECT ,pullup/down selection for pad csi21_dy2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " CSI21_DY2_PULLUDENABLE ,pullup/down enable for pad csi21_dy2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " CSI21_DY2_MUXMODE ,Functional multiplexing selection for pad csi21_dy2 - . - . - ." "Select_csi21_dy2,1,2,Select_gpi_72,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " CSI21_DX2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " CSI21_DX2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " CSI21_DX2_INPUTENABLE ,Input enable value for pad csi21_dx2 - . - ." "0,1" textline " " bitfld.long 0x00 4. " CSI21_DX2_PULLTYPESELECT ,pullup/down selection for pad csi21_dx2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " CSI21_DX2_PULLUDENABLE ,pullup/down enable for pad csi21_dx2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " CSI21_DX2_MUXMODE ,Functional multiplexing selection for pad csi21_dx2 - . - . - ." "Select_csi21_dx2,1,2,Select_gpi_71,4,5,6,Select_safe_mode" group.long 0xAC++0x3 line.long 0x00 "CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3,Register control for Pads csi21_dx3 and csi21_dy3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CSI21_DY3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " CSI21_DY3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " CSI21_DY3_INPUTENABLE ,Input enable value for pad csi21_dy3 - . - ." "0,1" textline " " bitfld.long 0x00 20. " CSI21_DY3_PULLTYPESELECT ,pullup/down selection for pad csi21_dy3 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " CSI21_DY3_PULLUDENABLE ,pullup/down enable for pad csi21_dy3 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " CSI21_DY3_MUXMODE ,Functional multiplexing selection for pad csi21_dy3 - . - . - ." "Select_csi21_dy3,1,2,Select_gpi_74,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " CSI21_DX3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " CSI21_DX3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " CSI21_DX3_INPUTENABLE ,Input enable value for pad csi21_dx3 - . - ." "0,1" textline " " bitfld.long 0x00 4. " CSI21_DX3_PULLTYPESELECT ,pullup/down selection for pad csi21_dx3 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " CSI21_DX3_PULLUDENABLE ,pullup/down enable for pad csi21_dx3 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " CSI21_DX3_MUXMODE ,Functional multiplexing selection for pad csi21_dx3 - . - . - ." "Select_csi21_dx3,1,2,Select_gpi_73,4,5,6,Select_safe_mode" group.long 0xB0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4,Register control for Pads csi21_dx4 and csi21_dy4 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CSI21_DY4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " CSI21_DY4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " CSI21_DY4_INPUTENABLE ,Input enable value for pad csi21_dy4 - . - ." "0,1" textline " " bitfld.long 0x00 20. " CSI21_DY4_PULLTYPESELECT ,pullup/down selection for pad csi21_dy4 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " CSI21_DY4_PULLUDENABLE ,pullup/down enable for pad csi21_dy4 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " CSI21_DY4_MUXMODE ,Functional multiplexing selection for pad csi21_dy4 - . - . - ." "Select_csi21_dy4,1,2,Select_gpi_76,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " CSI21_DX4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " CSI21_DX4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " CSI21_DX4_INPUTENABLE ,Input enable value for pad csi21_dx4 - . - ." "0,1" textline " " bitfld.long 0x00 4. " CSI21_DX4_PULLTYPESELECT ,pullup/down selection for pad csi21_dx4 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " CSI21_DX4_PULLUDENABLE ,pullup/down enable for pad csi21_dx4 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " CSI21_DX4_MUXMODE ,Functional multiplexing selection for pad csi21_dx4 - . - . - ." "Select_csi21_dx4,1,2,Select_gpi_75,4,5,6,Select_safe_mode" group.long 0xB4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_CSI22_DX0_PAD1_CSI22_DY0,Register control for Pads csi22_dx0 and csi22_dy0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CSI22_DY0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " CSI22_DY0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " CSI22_DY0_INPUTENABLE ,Input enable value for pad csi22_dy0 - . - ." "0,1" textline " " bitfld.long 0x00 20. " CSI22_DY0_PULLTYPESELECT ,pullup/down selection for pad csi22_dy0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " CSI22_DY0_PULLUDENABLE ,pullup/down enable for pad csi22_dy0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " CSI22_DY0_MUXMODE ,Functional multiplexing selection for pad csi22_dy0 - . - . - ." "Select_csi22_dy0,1,2,Select_gpi_78,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " CSI22_DX0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " CSI22_DX0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " CSI22_DX0_INPUTENABLE ,Input enable value for pad csi22_dx0 - . - ." "0,1" textline " " bitfld.long 0x00 4. " CSI22_DX0_PULLTYPESELECT ,pullup/down selection for pad csi22_dx0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " CSI22_DX0_PULLUDENABLE ,pullup/down enable for pad csi22_dx0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " CSI22_DX0_MUXMODE ,Functional multiplexing selection for pad csi22_dx0 - . - . - ." "Select_csi22_dx0,1,2,Select_gpi_77,4,5,6,Select_safe_mode" group.long 0xB8++0x3 line.long 0x00 "CONTROL_CORE_PAD0_CSI22_DX1_PAD1_CSI22_DY1,Register control for Pads csi22_dx1 and csi22_dy1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CSI22_DY1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " CSI22_DY1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " CSI22_DY1_INPUTENABLE ,Input enable value for pad csi22_dy1 - . - ." "0,1" textline " " bitfld.long 0x00 20. " CSI22_DY1_PULLTYPESELECT ,pullup/down selection for pad csi22_dy1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " CSI22_DY1_PULLUDENABLE ,pullup/down enable for pad csi22_dy1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " CSI22_DY1_MUXMODE ,Functional multiplexing selection for pad csi22_dy1 - . - . - ." "Select_csi22_dy1,1,2,Select_gpi_80,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " CSI22_DX1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " CSI22_DX1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " CSI22_DX1_INPUTENABLE ,Input enable value for pad csi22_dx1 - . - ." "0,1" textline " " bitfld.long 0x00 4. " CSI22_DX1_PULLTYPESELECT ,pullup/down selection for pad csi22_dx1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " CSI22_DX1_PULLUDENABLE ,pullup/down enable for pad csi22_dx1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " CSI22_DX1_MUXMODE ,Functional multiplexing selection for pad csi22_dx1 - . - . - ." "Select_csi22_dx1,1,2,Select_gpi_79,4,5,6,Select_safe_mode" group.long 0xBC++0x3 line.long 0x00 "CONTROL_CORE_PAD0_CAM_SHUTTER_PAD1_CAM_STROBE,Register control for Pads cam_shutter and cam_strobe Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CAM_STROBE_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " CAM_STROBE_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " CAM_STROBE__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad cam_strobe - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " CAM_STROBE__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad cam_strobe - . - ." "0,1" bitfld.long 0x00 27. " CAM_STROBE_OFFMODEOUTVALUE ,OffMode mode output value for pad cam_strobe - . - ." "0,1" bitfld.long 0x00 26. " CAM_STROBE_OFFMODEOUTENABLE ,OffMode mode output enable value for pad cam_strobe. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " CAM_STROBE_OFFMODEENABLE ,OffMode mode override control for pad cam_strobe - . - ." "0,1" bitfld.long 0x00 24. " CAM_STROBE_INPUTENABLE ,Input enable value for pad cam_strobe - . - ." "0,1" bitfld.long 0x00 20. " CAM_STROBE_PULLTYPESELECT ,pullup/down selection for pad cam_strobe - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " CAM_STROBE_PULLUDENABLE ,pullup/down enable for pad cam_strobe - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " CAM_STROBE_MUXMODE ,Functional multiplexing selection for pad cam_strobe - . - . - ." "Select_cam_strobe,1,2,Select_gpio_82,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " CAM_SHUTTER_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " CAM_SHUTTER_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " CAM_SHUTTER__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad cam_shutter - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " CAM_SHUTTER__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad cam_shutter - . - ." "0,1" textline " " bitfld.long 0x00 11. " CAM_SHUTTER__OFFMODEOUTVALUE ,OffMode mode output value for pad cam_shutter - . - ." "0,1" bitfld.long 0x00 10. " CAM_SHUTTER__OFFMODEOUTENABLE ,OffMode mode output enable value for pad cam_shutter. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " CAM_SHUTTER__OFFMODEENABLE ,OffMode mode override control for pad cam_shutter - . - ." "0,1" textline " " bitfld.long 0x00 8. " CAM_SHUTTER_INPUTENABLE ,Input enable value for pad cam_shutter - . - ." "0,1" bitfld.long 0x00 4. " CAM_SHUTTER__PULLTYPESELECT ,pullup/down selection for pad cam_shutter - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " CAM_SHUTTER__PULLUDENABLE ,pullup/down enable for pad cam_shutter - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " CAM_SHUTTER__MUXMODE ,Functional multiplexing selection for pad cam_shutter - . - . - ." "Select_cam_shutter,1,2,Select_gpio_81,4,5,6,Select_safe_mode" group.long 0xC0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_CAM_GLOBALRESET_PAD1_USBB1_ULPITLL_CLK,Register control for Pads cam_globalreset and usbb1_ulpitll_clk Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB1_ULPITLL_CLK_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB1_ULPITLL_CLK_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB1_ULPITLL_CLK__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_clk - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB1_ULPITLL_CLK__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_clk - . - ." "0,1" bitfld.long 0x00 27. " USBB1_ULPITLL_CLK__OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_clk - . - ." "0,1" bitfld.long 0x00 26. " USBB1_ULPITLL_CLK__OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_clk. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB1_ULPITLL_CLK__OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_clk - . - ." "0,1" bitfld.long 0x00 24. " USBB1_ULPITLL_CLK__INPUTENABLE ,Input enable value for pad usbb1_ulpitll_clk - . - ." "0,1" bitfld.long 0x00 20. " USBB1_ULPITLL_CLK__PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_clk - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB1_ULPITLL_CLK__PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_clk - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB1_ULPITLL_CLK__MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_clk - . - . - . - . - . - ." "Select_usbb1_ulpitll_clk,Select_hsi1_cawake,2,Select_gpio_84,Select_usbb1_ulpiphy_clk,5,Select_hw_dbg20,Select_safe_mode" bitfld.long 0x00 15. " CAM_GLOBALRESET__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " CAM_GLOBALRESET__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " CAM_GLOBALRESET__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad cam_globalreset - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " CAM_GLOBALRESET__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad cam_globalreset - . - ." "0,1" textline " " bitfld.long 0x00 11. " CAM_GLOBALRESET__OFFMODEOUTVALUE ,OffMode mode output value for pad cam_globalreset - . - ." "0,1" bitfld.long 0x00 10. " CAM_GLOBALRESET__OFFMODEOUTENABLE ,OffMode mode output enable value for pad cam_globalreset. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " CAM_GLOBALRESET__OFFMODEENABLE ,OffMode mode override control for pad cam_globalreset - . - ." "0,1" textline " " bitfld.long 0x00 8. " CAM_GLOBALRESET__INPUTENABLE ,Input enable value for pad cam_globalreset - . - ." "0,1" bitfld.long 0x00 4. " CAM_GLOBALRESET__PULLTYPESELECT ,pullup/down selection for pad cam_globalreset - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " CAM_GLOBALRESET__PULLUDENABLE ,pullup/down enable for pad cam_globalreset - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " CAM_GLOBALRESET__MUXMODE ,Functional multiplexing selection for pad cam_globalreset - . - . - ." "Select_cam_globalreset,1,2,Select_gpio_83,4,5,6,Select_safe_mode" group.long 0xC4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB1_ULPITLL_STP_PAD1_USBB1_ULPITLL_DIR,Register control for Pads usbb1_ulpitll_stp and usbb1_ulpitll_dir Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB1_ULPITLL__DIR_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB1_ULPITLL__DIR_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB1_ULPITLL_DIR_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_dir - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB1_ULPITLL_DIR_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_dir - . - ." "0,1" bitfld.long 0x00 27. " USBB1_ULPITLL_DIR_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_dir - . - ." "0,1" bitfld.long 0x00 26. " USBB1_ULPITLL_DIR_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_dir. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB1_ULPITLL_DIR_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_dir - . - ." "0,1" bitfld.long 0x00 24. " USBB1_ULPITLL__DIR_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_dir - . - ." "0,1" bitfld.long 0x00 20. " USBB1_ULPITLL__DIR_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_dir - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB1_ULPITLL__DIR_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_dir - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB1_ULPITLL__DIR_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_dir - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_dir,Select_hsi1_caflag,Select_mcbsp4_fsr,Select_gpio_86,Select_usbb1_ulpiphy_dir,5,Select_hw_dbg22,Select_safe_mode" bitfld.long 0x00 15. " USBB1_ULPITLL__STP_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB1_ULPITLL__STP_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB1_ULPITLL__STP_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_stp - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB1_ULPITLL__STP_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_stp - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB1_ULPITLL__STP_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_stp - . - ." "0,1" bitfld.long 0x00 10. " USBB1_ULPITLL__STP_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_stp. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB1_ULPITLL__STP_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_stp - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB1_ULPITLL__STP_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_stp - . - ." "0,1" bitfld.long 0x00 4. " USBB1_ULPITLL__STP_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_stp - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB1_ULPITLL__STP_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_stp - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB1_ULPITLL__STP_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_stp - . - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_stp,Select_hsi1_cadata,Select_mcbsp4_clkr,Select_gpio_85,Select_usbb1_ulpiphy_stp,Select_usbb1_mm_rxdp,Select_hw_dbg21,Select_safe_mode" group.long 0xC8++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB1_ULPITLL_NXT_PAD1_USBB1_ULPITLL_DAT0,Register control for Pads usbb1_ulpitll_nxt and usbb1_ulpitll_dat0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB1_ULPITLL__DAT0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB1_ULPITLL__DAT0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB1_ULPITLL_DAT0_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_dat0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB1_ULPITLL_DAT0_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_dat0 - . - ." "0,1" bitfld.long 0x00 27. " USBB1_ULPITLL__DAT0_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_dat0 - . - ." "0,1" bitfld.long 0x00 26. " USBB1_ULPITLL__DAT0_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_dat0. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB1_ULPITLL__DAT0_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_dat0 - . - ." "0,1" bitfld.long 0x00 24. " USBB1_ULPITLL__DAT0_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_dat0 - . - ." "0,1" bitfld.long 0x00 20. " USBB1_ULPITLL__DAT0_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_dat0 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB1_ULPITLL__DAT0_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_dat0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB1_ULPITLL__DAT0_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_dat0 - . - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_dat0,Select_hsi1_acwake,Select_mcbsp4_clkx,Select_gpio_88,Select_usbb1_ulpiphy_dat0,Select_usbb1_mm_txen,Select_hw_dbg24,Select_safe_mode" bitfld.long 0x00 15. " USBB1_ULPITLL__NXT_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB1_ULPITLL__NXT_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB1_ULPITLL__NXT_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_nxt - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB1_ULPITLL__NXT_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_nxt - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB1_ULPITLL__NXT_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_nxt - . - ." "0,1" bitfld.long 0x00 10. " USBB1_ULPITLL__NXT_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_nxt. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB1_ULPITLL__NXT_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_nxt - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB1_ULPITLL__NXT_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_nxt - . - ." "0,1" bitfld.long 0x00 4. " USBB1_ULPITLL__NXT_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_nxt - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB1_ULPITLL__NXT_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_nxt - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB1_ULPITLL__NXT_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_nxt - . - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_nxt,Select_hsi1_acready,Select_mcbsp4_fsx,Select_gpio_87,Select_usbb1_ulpiphy_nxt,Select_usbb1_mm_rxdm,Select_hw_dbg23,Select_safe_mode" group.long 0xCC++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB1_ULPITLL_DAT1_PAD1_USBB1_ULPITLL_DAT2,Register control for Pads usbb1_ulpitll_dat1 and usbb1_ulpitll_dat2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB1_ULPITLL__DAT2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB1_ULPITLL__DAT2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB1_ULPITLL__DAT2_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_dat2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB1_ULPITLL__DAT2_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_dat2 - . - ." "0,1" bitfld.long 0x00 27. " USBB1_ULPITLL__DAT2_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_dat2 - . - ." "0,1" bitfld.long 0x00 26. " USBB1_ULPITLL__DAT2_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_dat2. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB1_ULPITLL__DAT2_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_dat2 - . - ." "0,1" bitfld.long 0x00 24. " USBB1_ULPITLL__DAT2_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_dat2 - . - ." "0,1" bitfld.long 0x00 20. " USBB1_ULPITLL__DAT2_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_dat2 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB1_ULPITLL__DAT2_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_dat2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB1_ULPITLL__DAT2_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_dat2 - . - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_dat2,Select_hsi1_acflag,Select_mcbsp4_dr,Select_gpio_90,Select_usbb1_ulpiphy_dat2,Select_usbb1_mm_txse0,Select_hw_dbg26,Select_safe_mode" bitfld.long 0x00 15. " USBB1_ULPITLL__DAT1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB1_ULPITLL__DAT1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB1_ULPITLL__DAT1_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_dat1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB1_ULPITLL__DAT1_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_dat1 - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB1_ULPITLL__DAT1_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_dat1 - . - ." "0,1" bitfld.long 0x00 10. " USBB1_ULPITLL__DAT1_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_dat1. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB1_ULPITLL__DAT1_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_dat1 - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB1_ULPITLL__DAT1_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_dat1 - . - ." "0,1" bitfld.long 0x00 4. " USBB1_ULPITLL__DAT1_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_dat1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB1_ULPITLL__DAT1_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_dat1 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB1_ULPITLL__DAT1_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_dat1 - . - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_dat1,Select_hsi1_acdata,Select_mcbsp4_dx,Select_gpio_89,Select_usbb1_ulpiphy_dat1,Select_usbb1_mm_txdat,Select_hw_dbg25,Select_safe_mode" group.long 0xD0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB1_ULPITLL_DAT3_PAD1_USBB1_ULPITLL_DAT4,Register control for Pads usbb1_ulpitll_dat3 and usbb1_ulpitll_dat4 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB1_ULPITLL__DAT4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB1_ULPITLL__DAT4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB1_ULPITLL__DAT4_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_dat4 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB1_ULPITLL__DAT4_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_dat4 - . - ." "0,1" bitfld.long 0x00 27. " USBB1_ULPITLL__DAT4_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_dat4 - . - ." "0,1" bitfld.long 0x00 26. " USBB1_ULPITLL__DAT4_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_dat4. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB1_ULPITLL__DAT4_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_dat4 - . - ." "0,1" bitfld.long 0x00 24. " USBB1_ULPITLL__DAT4_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_dat4 - . - ." "0,1" bitfld.long 0x00 20. " USBB1_ULPITLL__DAT4_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_dat4 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB1_ULPITLL__DAT4_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_dat4 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB1_ULPITLL_DAT4_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_dat4 - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_dat4,Select_dmtimer8_pwm_evt,Select_abe_mcbsp3_dr,Select_gpio_92,Select_usbb1_ulpiphy_dat4,5,Select_hw_dbg28,Select_safe_mode" bitfld.long 0x00 15. " USBB1_ULPITLL__DAT3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB1_ULPITLL__DAT3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB1_ULPITLL__DAT3_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_dat3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB1_ULPITLL__DAT3_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_dat3 - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB1_ULPITLL__DAT3_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_dat3 - . - ." "0,1" bitfld.long 0x00 10. " USBB1_ULPITLL__DAT3_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_dat3. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB1_ULPITLL__DAT3_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_dat3 - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB1_ULPITLL__DAT3_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_dat3 - . - ." "0,1" bitfld.long 0x00 4. " USBB1_ULPITLL__DAT3_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_dat3 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB1_ULPITLL__DAT3_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_dat3 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB1_ULPITLL__DAT3_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_dat3 - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_dat3,Select_hsi1_caready,2,Select_gpio_91,Select_usbb1_ulpiphy_dat3,Select_usbb1_mm_rxrcv,Select_hw_dbg27,Select_safe_mode" group.long 0xD4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB1_ULPITLL_DAT5_PAD1_USBB1_ULPITLL_DAT6,Register control for Pads usbb1_ulpitll_dat5 and usbb1_ulpitll_dat6 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB1_ULPITLL__DAT6_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB1_ULPITLL__DAT6_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB1_ULPITLL_DAT6_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_dat6 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB1_ULPITLL_DAT6_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_dat6 - . - ." "0,1" bitfld.long 0x00 27. " USBB1_ULPITLL_DAT6_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_dat6 - . - ." "0,1" bitfld.long 0x00 26. " USBB1_ULPITLL_DAT6_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_dat6. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB1_ULPITLL_DAT6_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_dat6 - . - ." "0,1" bitfld.long 0x00 24. " USBB1_ULPITLL__DAT6_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_dat6 - . - ." "0,1" bitfld.long 0x00 20. " USBB1_ULPITLL__DAT6_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_dat6 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB1_ULPITLL__DAT6_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_dat6 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB1_ULPITLL_DAT6_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_dat6 - . - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_dat6,Select_dmtimer10_pwm_evt,Select_abe_mcbsp3_clkx,Select_gpio_94,Select_usbb1_ulpiphy_dat6,Select_abe_dmic_din3,Select_hw_dbg30,Select_safe_mode" bitfld.long 0x00 15. " USBB1_ULPITLL__DAT5_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB1_ULPITLL__DAT5_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB1_ULPITLL__DAT5_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_dat5 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB1_ULPITLL__DAT5_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_dat5 - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB1_ULPITLL__DAT5_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_dat5 - . - ." "0,1" bitfld.long 0x00 10. " USBB1_ULPITLL__DAT5_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_dat5. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB1_ULPITLL__DAT5_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_dat5 - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB1_ULPITLL__DAT5_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_dat5 - . - ." "0,1" bitfld.long 0x00 4. " USBB1_ULPITLL__DAT5_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_dat5 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB1_ULPITLL__DAT5_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_dat5 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB1_ULPITLL__DAT5_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_dat5 - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_dat5,Select_dmtimer9_pwm_evt,Select_abe_mcbsp3_dx,Select_gpio_93,Select_usbb1_ulpiphy_dat5,5,Select_hw_dbg29,Select_safe_mode" group.long 0xD8++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB1_ULPITLL_DAT7_PAD1_USBB1_HSIC_DATA,Register control for Pads usbb1_ulpitll_dat7 and usbb1_hsic_data Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB1_HSIC_DATA_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB1_HSIC_DATA_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 27. " USBB1_HSIC__DATA_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_hsic_data - . - ." "0,1" textline " " bitfld.long 0x00 26. " USBB1_HSIC__DATA_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_hsic_data. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 25. " USBB1_HSIC__DATA_OFFMODEENABLE ,OffMode mode override control for pad usbb1_hsic_data - . - ." "0,1" bitfld.long 0x00 16.--18. " USBB1_HSIC_DATA_MUXMODE ,Functional multiplexing selection for pad usbb1_hsic_data - . - . - ." "Select_usbb1_hsic_data,1,2,Select_gpio_96,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " USBB1_ULPITLL__DAT7_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " USBB1_ULPITLL__DAT7_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB1_ULPITLL__DAT7_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb1_ulpitll_dat7 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 12. " USBB1_ULPITLL__DAT7_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb1_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 11. " USBB1_ULPITLL__DAT7_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 10. " USBB1_ULPITLL__DAT7_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_ulpitll_dat7. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 9. " USBB1_ULPITLL__DAT7_OFFMODEENABLE ,OffMode mode override control for pad usbb1_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 8. " USBB1_ULPITLL__DAT7_INPUTENABLE ,Input enable value for pad usbb1_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 4. " USBB1_ULPITLL__DAT7_PULLTYPESELECT ,pullup/down selection for pad usbb1_ulpitll_dat7 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 3. " USBB1_ULPITLL__DAT7_PULLUDENABLE ,pullup/down enable for pad usbb1_ulpitll_dat7 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " USBB1_ULPITLL__DAT7_MUXMODE ,Functional multiplexing selection for pad usbb1_ulpitll_dat7 - . - . - . - . - . - . - . - ." "Select_usbb1_ulpitll_dat7,Select_dmtimer11_pwm_evt,Select_abe_mcbsp3_fsx,Select_gpio_95,Select_usbb1_ulpiphy_dat7,Select_abe_dmic_clk3,Select_hw_dbg31,Select_safe_mode" group.long 0xDC++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB1_HSIC_STROBE_PAD1_USBC1_ICUSB_DP,Register control for Pads usbb1_hsic_strobe and usbc1_icusb_dp Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBC1_ICUSB__DP_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBC1_ICUSB_DP_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBC1_ICUSB_DP_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbc1_icusb_dp - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBC1_ICUSB_DP_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbc1_icusb_dp - . - ." "0,1" bitfld.long 0x00 27. " USBC1_ICUSB_DP_OFFMODEOUTVALUE ,OffMode mode output value for pad usbc1_icusb_dp - . - ." "0,1" bitfld.long 0x00 26. " USBC1_ICUSB_DP_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbc1_icusb_dp. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBC1_ICUSB_DP_OFFMODEENABLE ,OffMode mode override control for pad usbc1_icusb_dp - . - ." "0,1" bitfld.long 0x00 24. " USBC1_ICUSB__DP_INPUTENABLE ,Input enable value for pad usbc1_icusb_dp - . - ." "0,1" bitfld.long 0x00 20. " USBC1_ICUSB__DP_PULLTYPESELECT ,pullup/down selection for pad usbc1_icusb_dp - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBC1_ICUSB_DP_PULLUDENABLE ,pullup/down enable for pad usbc1_icusb_dp - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBC1_ICUSB_DP_MUXMODE ,Functional multiplexing selection for pad usbc1_icusb_dp - . - . - ." "Select_usbc1_icusb_dp,1,2,Select_gpio_98,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " USBB1_HSIC_STROBE_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB1_HSIC_STROBE_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 11. " USBB1_HSIC__STROBE_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb1_hsic_strobe - . - ." "0,1" bitfld.long 0x00 10. " USBB1_HSIC__STROBE_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb1_hsic_strobe. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 9. " USBB1_HSIC__STROBE_OFFMODEENABLE ,OffMode mode override control for pad usbb1_hsic_strobe - . - ." "0,1" bitfld.long 0x00 0.--2. " USBB1_HSIC__STROBE_MUXMODE ,Functional multiplexing selection for pad usbb1_hsic_strobe - . - . - ." "Select_usbb1_hsic_strobe,1,2,Select_gpio_97,4,5,6,Select_safe_mode" group.long 0xE0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBC1_ICUSB_DM_PAD1_SDMMC1_CLK,Register control for Pads usbc1_icusb_dm and sdmmc1_clk Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SDMMC1__CLK_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SDMMC1_CLK_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SDMMC1_CLK__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_clk - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SDMMC1_CLK__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_clk - . - ." "0,1" bitfld.long 0x00 27. " SDMMC1_CLK_OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_clk - . - ." "0,1" bitfld.long 0x00 26. " SDMMC1_CLK_OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_clk. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SDMMC1_CLK_OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_clk - . - ." "0,1" bitfld.long 0x00 24. " SDMMC1_CLK_INPUTENABLE ,Input enable value for pad sdmmc1_clk - . - ." "0,1" bitfld.long 0x00 20. " SDMMC1__CLK_PULLTYPESELECT ,pullup/down selection for pad sdmmc1_clk - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SDMMC1_CLK_PULLUDENABLE ,pullup/down enable for pad sdmmc1_clk - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SDMMC1_CLK_MUXMODE ,Functional multiplexing selection for pad sdmmc1_clk - . - . - . - ." "Select_sdmmc1_clk,1,Select_dpm_emu19,Select_gpio_100,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " USBC1_ICUSB__DM_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBC1_ICUSB_DM_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBC1_ICUSB__DM_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbc1_icusb_dm - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBC1_ICUSB__DM_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbc1_icusb_dm - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBC1_ICUSB__DM_OFFMODEOUTVALUE ,OffMode mode output value for pad usbc1_icusb_dm - . - ." "0,1" bitfld.long 0x00 10. " USBC1_ICUSB__DM_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbc1_icusb_dm. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBC1_ICUSB__DM_OFFMODEENABLE ,OffMode mode override control for pad usbc1_icusb_dm - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBC1_ICUSB__DM_INPUTENABLE ,Input enable value for pad usbc1_icusb_dm - . - ." "0,1" bitfld.long 0x00 4. " USBC1_ICUSB__DM_PULLTYPESELECT ,pullup/down selection for pad usbc1_icusb_dm - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBC1_ICUSB__DM_PULLUDENABLE ,pullup/down enable for pad usbc1_icusb_dm - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBC1_ICUSB__DM_MUXMODE ,Functional multiplexing selection for pad usbc1_icusb_dm - . - . - ." "Select_usbc1_icusb_dm,1,2,Select_gpio_99,4,5,6,Select_safe_mode" group.long 0xE4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SDMMC1_CMD_PAD1_SDMMC1_DAT0,Register control for Pads sdmmc1_cmd and sdmmc1_dat0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SDMMC1_DAT0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SDMMC1_DAT0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SDMMC1_DAT0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_dat0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SDMMC1_DAT0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_dat0 - . - ." "0,1" bitfld.long 0x00 27. " SDMMC1_DAT0__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_dat0 - . - ." "0,1" bitfld.long 0x00 26. " SDMMC1_DAT0__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_dat0. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SDMMC1_DAT0__OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_dat0 - . - ." "0,1" bitfld.long 0x00 24. " SDMMC1_DAT0__INPUTENABLE ,Input enable value for pad sdmmc1_dat0 - . - ." "0,1" bitfld.long 0x00 20. " SDMMC1_DAT0__PULLTYPESELECT ,pullup/down selection for pad sdmmc1_dat0 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SDMMC1_DAT0__PULLUDENABLE ,pullup/down enable for pad sdmmc1_dat0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SDMMC1_DAT0__MUXMODE ,Functional multiplexing selection for pad sdmmc1_dat0 - . - . - . - ." "Select_sdmmc1_dat0,1,Select_dpm_emu18,Select_gpio_102,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " SDMMC1_CMD__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SDMMC1_CMD__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SDMMC1_CMD__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_cmd - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SDMMC1_CMD__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_cmd - . - ." "0,1" textline " " bitfld.long 0x00 11. " SDMMC1_CMD__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_cmd - . - ." "0,1" bitfld.long 0x00 10. " SDMMC1_CMD__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_cmd. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SDMMC1_CMD__OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_cmd - . - ." "0,1" textline " " bitfld.long 0x00 8. " SDMMC1_CMD__INPUTENABLE ,Input enable value for pad sdmmc1_cmd - . - ." "0,1" bitfld.long 0x00 4. " SDMMC1_CMD__PULLTYPESELECT ,pullup/down selection for pad sdmmc1_cmd - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SDMMC1_CMD__PULLUDENABLE ,pullup/down enable for pad sdmmc1_cmd - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SDMMC1_CMD__MUXMODE ,Functional multiplexing selection for pad sdmmc1_cmd - . - . - . - ." "Select_sdmmc1_cmd,1,Select_uart1_rx,Select_gpio_101,4,5,6,Select_safe_mode" group.long 0xE8++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SDMMC1_DAT1_PAD1_SDMMC1_DAT2,Register control for Pads sdmmc1_dat1 and sdmmc1_dat2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SDMMC1_DAT2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SDMMC1_DAT2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SDMMC1_DAT2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_dat2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SDMMC1_DAT2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_dat2 - . - ." "0,1" bitfld.long 0x00 27. " SDMMC1_DAT2__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_dat2 - . - ." "0,1" bitfld.long 0x00 26. " SDMMC1_DAT2__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_dat2. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SDMMC1_DAT2__OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_dat2 - . - ." "0,1" bitfld.long 0x00 24. " SDMMC1_DAT2__INPUTENABLE ,Input enable value for pad sdmmc1_dat2 - . - ." "0,1" bitfld.long 0x00 20. " SDMMC1_DAT2__PULLTYPESELECT ,pullup/down selection for pad sdmmc1_dat2 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SDMMC1_DAT2__PULLUDENABLE ,pullup/down enable for pad sdmmc1_dat2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SDMMC1_DAT2__MUXMODE ,Functional multiplexing selection for pad sdmmc1_dat2 - . - . - . - . - ." "Select_sdmmc1_dat2,1,Select_dpm_emu16,Select_gpio_104,Select_jtag_tms_tmsc,5,6,Select_safe_mode" bitfld.long 0x00 15. " SDMMC1_DAT1__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SDMMC1_DAT1__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SDMMC1_DAT1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_dat1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SDMMC1_DAT1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_dat1 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SDMMC1_DAT1__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_dat1 - . - ." "0,1" bitfld.long 0x00 10. " SDMMC1_DAT1__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_dat1. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SDMMC1_DAT1__OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_dat1 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SDMMC1_DAT1__INPUTENABLE ,Input enable value for pad sdmmc1_dat1 - . - ." "0,1" bitfld.long 0x00 4. " SDMMC1_DAT1__PULLTYPESELECT ,pullup/down selection for pad sdmmc1_dat1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SDMMC1_DAT1__PULLUDENABLE ,pullup/down enable for pad sdmmc1_dat1 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SDMMC1_DAT1__MUXMODE ,Functional multiplexing selection for pad sdmmc1_dat1 - . - . - . - ." "Select_sdmmc1_dat1,1,Select_dpm_emu17,Select_gpio_103,4,5,6,Select_safe_mode" group.long 0xEC++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SDMMC1_DAT3_PAD1_SDMMC1_DAT4,Register control for Pads sdmmc1_dat3 and sdmmc1_dat4 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SDMMC1_DAT4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SDMMC1_DAT4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SDMMC1_DAT4__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_dat4 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SDMMC1_DAT4__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_dat4 - . - ." "0,1" bitfld.long 0x00 27. " SDMMC1_DAT4__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_dat4 - . - ." "0,1" bitfld.long 0x00 26. " SDMMC1_DAT4__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_dat4. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SDMMC1_DAT4__OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_dat4 - . - ." "0,1" bitfld.long 0x00 24. " SDMMC1_DAT4__INPUTENABLE ,Input enable value for pad sdmmc1_dat4 - . - ." "0,1" bitfld.long 0x00 20. " SDMMC1_DAT4__PULLTYPESELECT ,pullup/down selection for pad sdmmc1_dat4 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SDMMC1_DAT4__PULLUDENABLE ,pullup/down enable for pad sdmmc1_dat4 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SDMMC1_DAT4__MUXMODE ,Functional multiplexing selection for pad sdmmc1_dat4 - . - . - ." "Select_sdmmc1_dat4,1,2,Select_gpio_106,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " SDMMC1_DAT3__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SDMMC1_DAT3__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SDMMC1_DAT3__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_dat3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SDMMC1_DAT3__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_dat3 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SDMMC1_DAT3__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_dat3 - . - ." "0,1" bitfld.long 0x00 10. " SDMMC1_DAT3__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_dat3. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SDMMC1_DAT3__OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_dat3 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SDMMC1_DAT3__INPUTENABLE ,Input enable value for pad sdmmc1_dat3 - . - ." "0,1" bitfld.long 0x00 4. " SDMMC1_DAT3__PULLTYPESELECT ,pullup/down selection for pad sdmmc1_dat3 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SDMMC1_DAT3__PULLUDENABLE ,pullup/down enable for pad sdmmc1_dat3 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SDMMC1_DAT3__MUXMODE ,Functional multiplexing selection for pad sdmmc1_dat3 - . - . - . - . - ." "Select_sdmmc1_dat3,1,Select_dpm_emu15,Select_gpio_105,Select_jtag_tck,5,6,Select_safe_mode" group.long 0xF0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SDMMC1_DAT5_PAD1_SDMMC1_DAT6,Register control for Pads sdmmc1_dat5 and sdmmc1_dat6 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SDMMC1_DAT6_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SDMMC1_DAT6_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SDMMC1_DAT6__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_dat6 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SDMMC1_DAT6__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_dat6 - . - ." "0,1" bitfld.long 0x00 27. " SDMMC1_DAT6__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_dat6 - . - ." "0,1" bitfld.long 0x00 26. " SDMMC1_DAT6__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_dat6. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SDMMC1_DAT6__OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_dat6 - . - ." "0,1" bitfld.long 0x00 24. " SDMMC1_DAT6__INPUTENABLE ,Input enable value for pad sdmmc1_dat6 - . - ." "0,1" bitfld.long 0x00 20. " SDMMC1_DAT6__PULLTYPESELECT ,pullup/down selection for pad sdmmc1_dat6 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SDMMC1_DAT6__PULLUDENABLE ,pullup/down enable for pad sdmmc1_dat6 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SDMMC1_DAT6__MUXMODE ,Functional multiplexing selection for pad sdmmc1_dat6 - . - . - ." "Select_sdmmc1_dat6,1,2,Select_gpio_108,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " SDMMC1_DAT5__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SDMMC1_DAT5__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SDMMC1_DAT5__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_dat5 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SDMMC1_DAT5__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_dat5 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SDMMC1_DAT5__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_dat5 - . - ." "0,1" bitfld.long 0x00 10. " SDMMC1_DAT5__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_dat5. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SDMMC1_DAT5__OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_dat5 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SDMMC1_DAT5__INPUTENABLE ,Input enable value for pad sdmmc1_dat5 - . - ." "0,1" bitfld.long 0x00 4. " SDMMC1_DAT5__PULLTYPESELECT ,pullup/down selection for pad sdmmc1_dat5 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SDMMC1_DAT5__PULLUDENABLE ,pullup/down enable for pad sdmmc1_dat5 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SDMMC1_DAT5__MUXMODE ,Functional multiplexing selection for pad sdmmc1_dat5 - . - . - ." "Select_sdmmc1_dat5,1,2,Select_gpio_107,4,5,6,Select_safe_mode" group.long 0xF4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SDMMC1_DAT7_PAD1_ABE_MCBSP2_CLKX,Register control for Pads sdmmc1_dat7 and abe_mcbsp2_clkx Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_MCBSP2__CLKX_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " ABE_MCBSP2__CLKX_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " ABE_MCBSP2__CLKX_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_mcbsp2_clkx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " ABE_MCBSP2__CLKX_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_mcbsp2_clkx - . - ." "0,1" bitfld.long 0x00 27. " ABE_MCBSP2__CLKX_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_mcbsp2_clkx - . - ." "0,1" bitfld.long 0x00 26. " ABE_MCBSP2__CLKX_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_mcbsp2_clkx. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " ABE_MCBSP2__CLKX_OFFMODEENABLE ,OffMode mode override control for pad abe_mcbsp2_clkx - . - ." "0,1" bitfld.long 0x00 24. " ABE_MCBSP2__CLKX_INPUTENABLE ,Input enable value for pad abe_mcbsp2_clkx - . - ." "0,1" bitfld.long 0x00 20. " ABE_MCBSP2__CLKX_PULLTYPESELECT ,pullup/down selection for pad abe_mcbsp2_clkx - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " ABE_MCBSP2__CLKX_PULLUDENABLE ,pullup/down enable for pad abe_mcbsp2_clkx - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " ABE_MCBSP2__CLKX_MUXMODE ,Functional multiplexing selection for pad abe_mcbsp2_clkx - . - . - . - . - . - ." "Select_abe_mcbsp2_clkx,Select_mcspi2_clk,Select_abe_mcasp_ahclkx,Select_gpio_110,Select_usbb2_mm_rxdm,5,6,Select_safe_mode" bitfld.long 0x00 15. " SDMMC1_DAT7__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SDMMC1_DAT7__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SDMMC1_DAT7__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc1_dat7 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SDMMC1_DAT7__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc1_dat7 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SDMMC1_DAT7__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc1_dat7 - . - ." "0,1" bitfld.long 0x00 10. " SDMMC1_DAT7__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc1_dat7. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SDMMC1_DAT7__OFFMODEENABLE ,OffMode mode override control for pad sdmmc1_dat7 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SDMMC1_DAT7__INPUTENABLE ,Input enable value for pad sdmmc1_dat7 - . - ." "0,1" bitfld.long 0x00 4. " SDMMC1_DAT7__PULLTYPESELECT ,pullup/down selection for pad sdmmc1_dat7 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SDMMC1_DAT7__PULLUDENABLE ,pullup/down enable for pad sdmmc1_dat7 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SDMMC1_DAT7__MUXMODE ,Functional multiplexing selection for pad sdmmc1_dat7 - . - . - ." "Select_sdmmc1_dat7,1,2,Select_gpio_109,4,5,6,Select_safe_mode" group.long 0xF8++0x3 line.long 0x00 "CONTROL_CORE_PAD0_ABE_MCBSP2_DR_PAD1_ABE_MCBSP2_DX,Register control for Pads abe_mcbsp2_dr and abe_mcbsp2_dx Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_MCBSP2_DX__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " ABE_MCBSP2_DX__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " ABE_MCBSP2_DX__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_mcbsp2_dx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " ABE_MCBSP2_DX__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_mcbsp2_dx - . - ." "0,1" bitfld.long 0x00 27. " ABE_MCBSP2_DX__OFFMODEOUTVALUE ,OffMode mode output value for pad abe_mcbsp2_dx - . - ." "0,1" bitfld.long 0x00 26. " ABE_MCBSP2_DX__OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_mcbsp2_dx. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " ABE_MCBSP2_DX__OFFMODEENABLE ,OffMode mode override control for pad abe_mcbsp2_dx - . - ." "0,1" bitfld.long 0x00 24. " ABE_MCBSP2_DX__INPUTENABLE ,Input enable value for pad abe_mcbsp2_dx - . - ." "0,1" bitfld.long 0x00 20. " ABE_MCBSP2_DX__PULLTYPESELECT ,pullup/down selection for pad abe_mcbsp2_dx - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " ABE_MCBSP2_DX__PULLUDENABLE ,pullup/down enable for pad abe_mcbsp2_dx - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " ABE_MCBSP2_DX__MUXMODE ,Functional multiplexing selection for pad abe_mcbsp2_dx - . - . - . - . - . - ." "Select_abe_mcbsp2_dx,Select_mcspi2_simo,Select_abe_mcasp_amute,Select_gpio_112,Select_usbb2_mm_rxrcv,5,6,Select_safe_mode" bitfld.long 0x00 15. " ABE_MCBSP2_DR__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " ABE_MCBSP2_DR__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " ABE_MCBSP2_DR__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_mcbsp2_dr - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " ABE_MCBSP2_DR__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_mcbsp2_dr - . - ." "0,1" textline " " bitfld.long 0x00 11. " ABE_MCBSP2_DR__OFFMODEOUTVALUE ,OffMode mode output value for pad abe_mcbsp2_dr - . - ." "0,1" bitfld.long 0x00 10. " ABE_MCBSP2_DR__OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_mcbsp2_dr. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " ABE_MCBSP2_DR__OFFMODEENABLE ,OffMode mode override control for pad abe_mcbsp2_dr - . - ." "0,1" textline " " bitfld.long 0x00 8. " ABE_MCBSP2_DR__INPUTENABLE ,Input enable value for pad abe_mcbsp2_dr - . - ." "0,1" bitfld.long 0x00 4. " ABE_MCBSP2_DR__PULLTYPESELECT ,pullup/down selection for pad abe_mcbsp2_dr - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " ABE_MCBSP2_DR__PULLUDENABLE ,pullup/down enable for pad abe_mcbsp2_dr - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " ABE_MCBSP2_DR__MUXMODE ,Functional multiplexing selection for pad abe_mcbsp2_dr - . - . - . - . - . - ." "Select_abe_mcbsp2_dr,Select_mcspi2_somi,Select_abe_mcasp_axr,Select_gpio_111,Select_usbb2_mm_rxdp,5,6,Select_safe_mode" group.long 0xFC++0x3 line.long 0x00 "CONTROL_CORE_PAD0_ABE_MCBSP2_FSX_PAD1_ABE_MCBSP1_CLKX,Register control for Pads abe_mcbsp2_fsx and abe_mcbsp1_clkx Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_MCBSP1_CLKX_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " ABE_MCBSP1_CLKX_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " ABE_MCBSP1_CLKX__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_mcbsp1_clkx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " ABE_MCBSP1_CLKX__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_mcbsp1_clkx - . - ." "0,1" bitfld.long 0x00 27. " ABE_MCBSP1_CLKX__OFFMODEOUTVALUE ,OffMode mode output value for pad abe_mcbsp1_clkx - . - ." "0,1" bitfld.long 0x00 26. " ABE_MCBSP1_CLKX__OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_mcbsp1_clkx. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " ABE_MCBSP1_CLKX__OFFMODEENABLE ,OffMode mode override control for pad abe_mcbsp1_clkx - . - ." "0,1" bitfld.long 0x00 24. " ABE_MCBSP1_CLKX__INPUTENABLE ,Input enable value for pad abe_mcbsp1_clkx - . - ." "0,1" bitfld.long 0x00 20. " ABE_MCBSP1_CLKX__PULLTYPESELECT ,pullup/down selection for pad abe_mcbsp1_clkx - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " ABE_MCBSP1_CLKX__PULLUDENABLE ,pullup/down enable for pad abe_mcbsp1_clkx - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " ABE_MCBSP1_CLKX__MUXMODE ,Functional multiplexing selection for pad abe_mcbsp1_clkx - . - . - . - ." "Select_abe_mcbsp1_clkx,Select_abe_slimbus1_clock,2,Select_gpio_114,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " ABE_MCBSP2_FSX__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " ABE_MCBSP2_FSX__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " ABE_MCBSP2_FSX__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_mcbsp2_fsx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " ABE_MCBSP2_FSX__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_mcbsp2_fsx - . - ." "0,1" textline " " bitfld.long 0x00 11. " ABE_MCBSP2_FSX__OFFMODEOUTVALUE ,OffMode mode output value for pad abe_mcbsp2_fsx - . - ." "0,1" bitfld.long 0x00 10. " ABE_MCBSP2_FSX__OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_mcbsp2_fsx. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " ABE_MCBSP2_FSX__OFFMODEENABLE ,OffMode mode override control for pad abe_mcbsp2_fsx - . - ." "0,1" textline " " bitfld.long 0x00 8. " ABE_MCBSP2_FSX__INPUTENABLE ,Input enable value for pad abe_mcbsp2_fsx - . - ." "0,1" bitfld.long 0x00 4. " ABE_MCBSP2_FSX__PULLTYPESELECT ,pullup/down selection for pad abe_mcbsp2_fsx - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " ABE_MCBSP2_FSX__PULLUDENABLE ,pullup/down enable for pad abe_mcbsp2_fsx - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " ABE_MCBSP2_FSX__MUXMODE ,Functional multiplexing selection for pad abe_mcbsp2_fsx - . - . - . - . - . - ." "Select_abe_mcbsp2_fsx,Select_mcspi2_cs0,Select_abe_mcasp_afsx,Select_gpio_113,Select_usbb2_mm_txen,5,6,Select_safe_mode" group.long 0x100++0x3 line.long 0x00 "CONTROL_CORE_PAD0_ABE_MCBSP1_DR_PAD1_ABE_MCBSP1_DX,Register control for Pads abe_mcbsp1_dr and abe_mcbsp1_dx Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_MCBSP1_DX__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " ABE_MCBSP1_DX__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " ABE_MCBSP1__DX_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_mcbsp1_dx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " ABE_MCBSP1__DX_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_mcbsp1_dx - . - ." "0,1" bitfld.long 0x00 27. " ABE_MCBSP1__DX_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_mcbsp1_dx - . - ." "0,1" bitfld.long 0x00 26. " ABE_MCBSP1__DX_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_mcbsp1_dx. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " ABE_MCBSP1__DX_OFFMODEENABLE ,OffMode mode override control for pad abe_mcbsp1_dx - . - ." "0,1" bitfld.long 0x00 24. " ABE_MCBSP1__DX_INPUTENABLE ,Input enable value for pad abe_mcbsp1_dx - . - ." "0,1" bitfld.long 0x00 20. " ABE_MCBSP1__DX_PULLTYPESELECT ,pullup/down selection for pad abe_mcbsp1_dx - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " ABE_MCBSP1__DX_PULLUDENABLE ,pullup/down enable for pad abe_mcbsp1_dx - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " ABE_MCBSP1__DX_MUXMODE ,Functional multiplexing selection for pad abe_mcbsp1_dx - . - . - . - . - ." "Select_abe_mcbsp1_dx,Select_sdmmc3_dat2,Select_abe_mcasp_aclkx,Select_gpio_116,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " ABE_MCBSP1__DR_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " ABE_MCBSP1__DR_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " ABE_MCBSP1__DR_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_mcbsp1_dr - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " ABE_MCBSP1__DR_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_mcbsp1_dr - . - ." "0,1" textline " " bitfld.long 0x00 11. " ABE_MCBSP1__DR_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_mcbsp1_dr - . - ." "0,1" bitfld.long 0x00 10. " ABE_MCBSP1__DR_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_mcbsp1_dr. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " ABE_MCBSP1__DR_OFFMODEENABLE ,OffMode mode override control for pad abe_mcbsp1_dr - . - ." "0,1" textline " " bitfld.long 0x00 8. " ABE_MCBSP1__DR_INPUTENABLE ,Input enable value for pad abe_mcbsp1_dr - . - ." "0,1" bitfld.long 0x00 4. " ABE_MCBSP1__DR_PULLTYPESELECT ,pullup/down selection for pad abe_mcbsp1_dr - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " ABE_MCBSP1__DR_PULLUDENABLE ,pullup/down enable for pad abe_mcbsp1_dr - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " ABE_MCBSP1__DR_MUXMODE ,Functional multiplexing selection for pad abe_mcbsp1_dr - . - . - . - ." "Select_abe_mcbsp1_dr,Select_abe_slimbus1_data,2,Select_gpio_115,4,5,6,Select_safe_mode" group.long 0x104++0x3 line.long 0x00 "CONTROL_CORE_PAD0_ABE_MCBSP1_FSX_PAD1_ABE_PDM_UL_DATA,Register control for Pads abe_mcbsp1_fsx and abe_pdm_ul_data Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_PDM_UL__DATA_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " ABE_PDM_UL__DATA_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " ABE_PDM_UL__DATA_INPUTENABLE ,Input enable value for pad abe_pdm_ul_data - . - ." "0,1" textline " " bitfld.long 0x00 20. " ABE_PDM_UL__DATA_PULLTYPESELECT ,pullup/down selection for pad abe_pdm_ul_data - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " ABE_PDM_UL_DATA_PULLUDENABLE ,pullup/down enable for pad abe_pdm_ul_data - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " ABE_PDM_UL_DATA_MUXMODE ,Functional multiplexing selection for pad abe_pdm_ul_data - . - . - ." "Select_abe_pdm_ul_data,Select_abe_mcbsp3_dr,2,3,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " ABE_MCBSP1_FSX_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " ABE_MCBSP1__FSX_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " ABE_MCBSP1__FSX_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_mcbsp1_fsx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 12. " ABE_MCBSP1__FSX_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_mcbsp1_fsx - . - ." "0,1" bitfld.long 0x00 11. " ABE_MCBSP1__FSX_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_mcbsp1_fsx - . - ." "0,1" bitfld.long 0x00 10. " ABE_MCBSP1__FSX_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_mcbsp1_fsx. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 9. " ABE_MCBSP1_FSX_OFFMODEENABLE ,OffMode mode override control for pad abe_mcbsp1_fsx - . - ." "0,1" bitfld.long 0x00 8. " ABE_MCBSP1_FSX_INPUTENABLE ,Input enable value for pad abe_mcbsp1_fsx - . - ." "0,1" bitfld.long 0x00 4. " ABE_MCBSP1_FSX_PULLTYPESELECT ,pullup/down selection for pad abe_mcbsp1_fsx - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 3. " ABE_MCBSP1_FSX_PULLUDENABLE ,pullup/down enable for pad abe_mcbsp1_fsx - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " ABE_MCBSP1_FSX_MUXMODE ,Functional multiplexing selection for pad abe_mcbsp1_fsx - . - . - . - . - ." "Select_abe_mcbsp1_fsx,Select_sdmmc3_dat3,Select_abe_mcasp_amutein,Select_gpio_117,4,5,6,Select_safe_mode" group.long 0x108++0x3 line.long 0x00 "CONTROL_CORE_PAD0_ABE_PDM_DL_DATA_PAD1_ABE_PDM_FRAME,Register control for Pads abe_pdm_dl_data and abe_pdm_frame Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_PDM__FRAME_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " ABE_PDM__FRAME_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " ABE_PDM_FRAME__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_pdm_frame - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " ABE_PDM_FRAME__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_pdm_frame - . - ." "0,1" bitfld.long 0x00 27. " ABE_PDM__FRAME_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_pdm_frame - . - ." "0,1" bitfld.long 0x00 26. " ABE_PDM__FRAME_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_pdm_frame. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " ABE_PDM__FRAME_OFFMODEENABLE ,OffMode mode override control for pad abe_pdm_frame - . - ." "0,1" bitfld.long 0x00 24. " ABE_PDM_FRAME_INPUTENABLE ,Input enable value for pad abe_pdm_frame - . - ." "0,1" bitfld.long 0x00 20. " ABE_PDM_FRAME_PULLTYPESELECT ,pullup/down selection for pad abe_pdm_frame - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " ABE_PDM_FRAME_PULLUDENABLE ,pullup/down enable for pad abe_pdm_frame - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " ABE_PDM_FRAME_MUXMODE ,Functional multiplexing selection for pad abe_pdm_frame - . - . - ." "Select_abe_pdm_frame,Select_abe_mcbsp3_clkx,2,3,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " ABE_PDM_DL__DATA_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " ABE_PDM__DL_DATA_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " ABE_PDM__DL_DATA_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_pdm_dl_data - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " ABE_PDM_DL__DATA_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_pdm_dl_data - . - ." "0,1" textline " " bitfld.long 0x00 11. " ABE_PDM_DL__DATA_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_pdm_dl_data - . - ." "0,1" bitfld.long 0x00 10. " ABE_PDM_DL__DATA_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_pdm_dl_data. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " ABE_PDM_DL__DATA_OFFMODEENABLE ,OffMode mode override control for pad abe_pdm_dl_data - . - ." "0,1" textline " " bitfld.long 0x00 8. " ABE_PDM_DL__DATA_INPUTENABLE ,Input enable value for pad abe_pdm_dl_data - . - ." "0,1" bitfld.long 0x00 4. " ABE_PDM_DL__DATA_PULLTYPESELECT ,pullup/down selection for pad abe_pdm_dl_data - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " ABE_PDM_DL__DATA_PULLUDENABLE ,pullup/down enable for pad abe_pdm_dl_data - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " ABE_PDM_DL__DATA_MUXMODE ,Functional multiplexing selection for pad abe_pdm_dl_data - . - . - ." "Select_abe_pdm_dl_data,Select_abe_mcbsp3_dx,2,3,4,5,6,Select_safe_mode" group.long 0x10C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_ABE_PDM_LB_CLK_PAD1_ABE_CLKS,Register control for Pads abe_pdm_lb_clk and abe_clks Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_CLKS_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " ABE_CLKS_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " ABE_CLKS__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_clks - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " ABE_CLKS_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_clks - . - ." "0,1" bitfld.long 0x00 27. " ABE_CLKS_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_clks - . - ." "0,1" bitfld.long 0x00 26. " ABE_CLKS_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_clks. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " ABE_CLKS_OFFMODEENABLE ,OffMode mode override control for pad abe_clks - . - ." "0,1" bitfld.long 0x00 24. " ABE_CLKS_INPUTENABLE ,Input enable value for pad abe_clks - . - ." "0,1" bitfld.long 0x00 20. " ABE_CLKS_PULLTYPESELECT ,pullup/down selection for pad abe_clks - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " ABE_CLKS_PULLUDENABLE ,pullup/down enable for pad abe_clks - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " ABE_CLKS_MUXMODE ,Functional multiplexing selection for pad abe_clks - . - . - ." "Select_abe_clks,1,2,Select_gpio_118,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " ABE_PDM_LB__CLK_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " ABE_PDM_LB__CLK_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " ABE_PDM_LB__CLK_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_pdm_lb_clk - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " ABE_PDM_LB_CLK_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_pdm_lb_clk - . - ." "0,1" textline " " bitfld.long 0x00 11. " ABE_PDM_LB_CLK_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_pdm_lb_clk - . - ." "0,1" bitfld.long 0x00 10. " ABE_PDM_LB_CLK_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_pdm_lb_clk. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " ABE_PDM_LB_CLK_OFFMODEENABLE ,OffMode mode override control for pad abe_pdm_lb_clk - . - ." "0,1" textline " " bitfld.long 0x00 8. " ABE_PDM_LB_CLK_INPUTENABLE ,Input enable value for pad abe_pdm_lb_clk - . - ." "0,1" bitfld.long 0x00 4. " ABE_PDM_LB_CLK_PULLTYPESELECT ,pullup/down selection for pad abe_pdm_lb_clk - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " ABE_PDM_LB_CLK_PULLUDENABLE ,pullup/down enable for pad abe_pdm_lb_clk - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " ABE_PDM_LB_CLK_MUXMODE ,Functional multiplexing selection for pad abe_pdm_lb_clk - . - . - ." "Select_abe_pdm_lb_clk,Select_abe_mcbsp3_fsx,2,3,4,5,6,Select_safe_mode" group.long 0x110++0x3 line.long 0x00 "CONTROL_CORE_PAD0_ABE_DMIC_CLK1_PAD1_ABE_DMIC_DIN1,Register control for Pads abe_dmic_clk1 and abe_dmic_din1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_DMIC_DIN1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " ABE_DMIC_DIN1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " ABE_DMIC__DIN1_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_dmic_din1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " ABE_DMIC_DIN1_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_dmic_din1 - . - ." "0,1" bitfld.long 0x00 27. " ABE_DMIC_DIN1_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_dmic_din1 - . - ." "0,1" bitfld.long 0x00 26. " ABE_DMIC_DIN1_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_dmic_din1. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " ABE_DMIC_DIN1_OFFMODEENABLE ,OffMode mode override control for pad abe_dmic_din1 - . - ." "0,1" bitfld.long 0x00 24. " ABE_DMIC_DIN1_INPUTENABLE ,Input enable value for pad abe_dmic_din1 - . - ." "0,1" bitfld.long 0x00 20. " ABE_DMIC_DIN1_PULLTYPESELECT ,pullup/down selection for pad abe_dmic_din1 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " ABE_DMIC_DIN1_PULLUDENABLE ,pullup/down enable for pad abe_dmic_din1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " ABE_DMIC_DIN1_MUXMODE ,Functional multiplexing selection for pad abe_dmic_din1 - . - . - . - . - ." "Select_abe_dmic_din1,1,2,Select_gpio_120,Select_usbb2_mm_txdat,Select_uart4_rts,6,Select_safe_mode" bitfld.long 0x00 15. " ABE_DMIC_CLK1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " ABE_DMIC_CLK1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " ABE_DMIC__CLK1_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_dmic_clk1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " ABE_DMIC__CLK1_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_dmic_clk1 - . - ." "0,1" textline " " bitfld.long 0x00 11. " ABE_DMIC_CLK1_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_dmic_clk1 - . - ." "0,1" bitfld.long 0x00 10. " ABE_DMIC_CLK1_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_dmic_clk1. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " ABE_DMIC_CLK1_OFFMODEENABLE ,OffMode mode override control for pad abe_dmic_clk1 - . - ." "0,1" textline " " bitfld.long 0x00 8. " ABE_DMIC_CLK1_INPUTENABLE ,Input enable value for pad abe_dmic_clk1 - . - ." "0,1" bitfld.long 0x00 4. " ABE_DMIC_CLK1_PULLTYPESELECT ,pullup/down selection for pad abe_dmic_clk1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " ABE_DMIC_CLK1_PULLUDENABLE ,pullup/down enable for pad abe_dmic_clk1 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " ABE_DMIC_CLK1_MUXMODE ,Functional multiplexing selection for pad abe_dmic_clk1 - . - . - . - . - ." "Select_abe_dmic_clk1,1,2,Select_gpio_119,Select_usbb2_mm_txse0,Select_uart4_cts,6,Select_safe_mode" group.long 0x114++0x3 line.long 0x00 "CONTROL_CORE_PAD0_ABE_DMIC_DIN2_PAD1_ABE_DMIC_DIN3,Register control for Pads abe_dmic_din2 and abe_dmic_din3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_DMIC_DIN3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " ABE_DMIC_DIN3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " ABE_DMIC__DIN3_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_dmic_din3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " ABE_DMIC_DIN3_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_dmic_din3 - . - ." "0,1" bitfld.long 0x00 27. " ABE_DMIC_DIN3_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_dmic_din3 - . - ." "0,1" bitfld.long 0x00 26. " ABE_DMIC_DIN3_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_dmic_din3. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " ABE_DMIC_DIN3_OFFMODEENABLE ,OffMode mode override control for pad abe_dmic_din3 - . - ." "0,1" bitfld.long 0x00 24. " ABE_DMIC_DIN3_INPUTENABLE ,Input enable value for pad abe_dmic_din3 - . - ." "0,1" bitfld.long 0x00 20. " ABE_DMIC_DIN3_PULLTYPESELECT ,pullup/down selection for pad abe_dmic_din3 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " ABE_DMIC_DIN3_PULLUDENABLE ,pullup/down enable for pad abe_dmic_din3 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " ABE_DMIC_DIN3_MUXMODE ,Functional multiplexing selection for pad abe_dmic_din3 - . - . - . - . - . - ." "Select_abe_dmic_din3,Select_slimbus2_data,Select_abe_dmic_clk2,Select_gpio_122,4,Select_dmtimer9_pwm_evt,6,Select_safe_mode" bitfld.long 0x00 15. " ABE_DMIC_DIN2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " ABE_DMIC_DIN2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " ABE_DMIC__DIN2_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad abe_dmic_din2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " ABE_DMIC__DIN2_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad abe_dmic_din2 - . - ." "0,1" textline " " bitfld.long 0x00 11. " ABE_DMIC_DIN2_OFFMODEOUTVALUE ,OffMode mode output value for pad abe_dmic_din2 - . - ." "0,1" bitfld.long 0x00 10. " ABE_DMIC_DIN2_OFFMODEOUTENABLE ,OffMode mode output enable value for pad abe_dmic_din2. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " ABE_DMIC_DIN2_OFFMODEENABLE ,OffMode mode override control for pad abe_dmic_din2 - . - ." "0,1" textline " " bitfld.long 0x00 8. " ABE_DMIC_DIN2_INPUTENABLE ,Input enable value for pad abe_dmic_din2 - . - ." "0,1" bitfld.long 0x00 4. " ABE_DMIC_DIN2_PULLTYPESELECT ,pullup/down selection for pad abe_dmic_din2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " ABE_DMIC_DIN2_PULLUDENABLE ,pullup/down enable for pad abe_dmic_din2 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " ABE_DMIC_DIN2_MUXMODE ,Functional multiplexing selection for pad abe_dmic_din2 - . - . - . - . - . - ." "Select_abe_dmic_din2,Select_slimbus2_clock,Select_abe_mcasp_axr,Select_gpio_121,4,Select_dmtimer11_pwm_evt,6,Select_safe_mode" group.long 0x118++0x3 line.long 0x00 "CONTROL_CORE_PAD0_UART2_CTS_PAD1_UART2_RTS,Register control for Pads uart2_cts and uart2_rts Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " UART2_RTS_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " UART2_RTS_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " UART2_RTS__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart2_rts - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " UART2_RTS_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart2_rts - . - ." "0,1" bitfld.long 0x00 27. " UART2_RTS_OFFMODEOUTVALUE ,OffMode mode output value for pad uart2_rts - . - ." "0,1" bitfld.long 0x00 26. " UART2_RTS_OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart2_rts. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " UART2_RTS_OFFMODEENABLE ,OffMode mode override control for pad uart2_rts - . - ." "0,1" bitfld.long 0x00 24. " UART2_RTS_INPUTENABLE ,Input enable value for pad uart2_rts - . - ." "0,1" bitfld.long 0x00 20. " UART2_RTS_PULLTYPESELECT ,pullup/down selection for pad uart2_rts - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " UART2_RTS_PULLUDENABLE ,pullup/down enable for pad uart2_rts - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " UART2_RTS_MUXMODE ,Functional multiplexing selection for pad uart2_rts - . - . - . - ." "Select_uart2_rts,Select_sdmmc3_cmd,2,Select_gpio_124,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " UART2_CTS_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " UART2_CTS_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " UART2_CTS__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart2_cts - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " UART2_CTS__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart2_cts - . - ." "0,1" textline " " bitfld.long 0x00 11. " UART2_CTS_OFFMODEOUTVALUE ,OffMode mode output value for pad uart2_cts - . - ." "0,1" bitfld.long 0x00 10. " UART2_CTS_OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart2_cts. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " UART2_CTS_OFFMODEENABLE ,OffMode mode override control for pad uart2_cts - . - ." "0,1" textline " " bitfld.long 0x00 8. " UART2_CTS_INPUTENABLE ,Input enable value for pad uart2_cts - . - ." "0,1" bitfld.long 0x00 4. " UART2_CTS_PULLTYPESELECT ,pullup/down selection for pad uart2_cts - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " UART2_CTS_PULLUDENABLE ,pullup/down enable for pad uart2_cts - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " UART2_CTS_MUXMODE ,Functional multiplexing selection for pad uart2_cts - . - . - . - ." "Select_uart2_cts,Select_sdmmc3_clk,2,Select_gpio_123,4,5,6,Select_safe_mode" group.long 0x11C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_UART2_RX_PAD1_UART2_TX,Register control for Pads uart2_rx and uart2_tx Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " UART2_TX_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " UART2_TX_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " UART2_TX__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart2_tx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " UART2_TX_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart2_tx - . - ." "0,1" bitfld.long 0x00 27. " UART2_TX_OFFMODEOUTVALUE ,OffMode mode output value for pad uart2_tx - . - ." "0,1" bitfld.long 0x00 26. " UART2_TX_OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart2_tx. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " UART2_TX_OFFMODEENABLE ,OffMode mode override control for pad uart2_tx - . - ." "0,1" bitfld.long 0x00 24. " UART2_TX_INPUTENABLE ,Input enable value for pad uart2_tx - . - ." "0,1" bitfld.long 0x00 20. " UART2_TX_PULLTYPESELECT ,pullup/down selection for pad uart2_tx - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " UART2_TX_PULLUDENABLE ,pullup/down enable for pad uart2_tx - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " UART2_TX_MUXMODE ,Functional multiplexing selection for pad uart2_tx - . - . - . - ." "Select_uart2_tx,Select_sdmmc3_dat1,2,Select_gpio_126,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " UART2_RX_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " UART2_RX_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " UART2_RX__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart2_rx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " UART2_RX__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart2_rx - . - ." "0,1" textline " " bitfld.long 0x00 11. " UART2_RX_OFFMODEOUTVALUE ,OffMode mode output value for pad uart2_rx - . - ." "0,1" bitfld.long 0x00 10. " UART2_RX_OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart2_rx. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " UART2_RX_OFFMODEENABLE ,OffMode mode override control for pad uart2_rx - . - ." "0,1" textline " " bitfld.long 0x00 8. " UART2_RX_INPUTENABLE ,Input enable value for pad uart2_rx - . - ." "0,1" bitfld.long 0x00 4. " UART2_RX_PULLTYPESELECT ,pullup/down selection for pad uart2_rx - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " UART2_RX_PULLUDENABLE ,pullup/down enable for pad uart2_rx - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " UART2_RX_MUXMODE ,Functional multiplexing selection for pad uart2_rx - . - . - . - ." "Select_uart2_rx,Select_sdmmc3_dat0,2,Select_gpio_125,4,5,6,Select_safe_mode" group.long 0x120++0x3 line.long 0x00 "CONTROL_CORE_PAD0_HDQ_SIO_PAD1_I2C1_SCL,Register control for Pads hdq_sio and i2c1_scl Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " I2C1_SCL_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " I2C1_SCL_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " I2C1_SCL_INPUTENABLE ,Input enable value for pad i2c1_scl - . - ." "0,1" textline " " bitfld.long 0x00 20. " I2C1_SCL_PULLTYPESELECT ,pullup/down selection for pad i2c1_scl - . - ." "Pulldown_selected,Pullup_selected" bitfld.long 0x00 19. " I2C1_SCL_PULLUDENABLE ,pullup/down enable for pad i2c1_scl - . - ." "Pullup/down_disabled,Pullup/down_enabled" bitfld.long 0x00 15. " HDQ_SIO_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " HDQ_SIO_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " HDQ_SIO_OFFMODEPULLTYPESELECT ,OffMode mode pullup/pulldown selection for pad hdq_sio - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " HDQ_SIO_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad hdq_sio - . - ." "0,1" textline " " bitfld.long 0x00 11. " HDQ_SIO_OFFMODEOUTVALUE ,OffMode mode output value for pad hdq_sio - . - ." "0,1" bitfld.long 0x00 10. " HDQ_SIO_OFFMODEOUTENABLE ,OffMode mode output enable value for pad hdq_sio. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " HDQ_SIO_OFFMODEENABLE ,OffMode mode override control for pad hdq_sio - . - ." "0,1" textline " " bitfld.long 0x00 8. " HDQ_SIO_INPUTENABLE ,Input enable value for pad hdq_sio - . - ." "0,1" bitfld.long 0x00 4. " HDQ_SIO_PULLTYPESELECT ,Pullup/down selection for pad hdq_sio - . - ." "Pulldown_selected,Pullip_selected" bitfld.long 0x00 3. " HDQ_SIO_PULLUDENABLE ,Pullup/down enable for pad hdq_sio - . - ." "Pullup/down_disabled,Pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " HDQ_SIO_MUXMODE ,Functional multiplexing selection for pad hdq_sio - . - . - . - . - ." "Select_hdq_sio,Select_i2c3_sccb,Select_i2c2_sccb,Select_gpio_127,4,5,6,Select_safe_mode" group.long 0x124++0x3 line.long 0x00 "CONTROL_CORE_PAD0_I2C1_SDA_PAD1_I2C2_SCL,Register control for Pads i2c1_sda and i2c2_scl Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " I2C2_SCL_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " I2C2_SCL_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " I2C2_SCL__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad i2c2_scl - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " I2C2_SCL__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad i2c2_scl - . - ." "0,1" bitfld.long 0x00 27. " I2C2_SCL_OFFMODEOUTVALUE ,OffMode mode output value for pad i2c2_scl - . - ." "0,1" bitfld.long 0x00 26. " I2C2_SCL_OFFMODEOUTENABLE ,OffMode mode output enable value for pad i2c2_scl. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " I2C2_SCL_OFFMODEENABLE ,OffMode mode override control for pad i2c2_scl - . - ." "0,1" bitfld.long 0x00 24. " I2C2_SCL_INPUTENABLE ,Input enable value for pad i2c2_scl - . - ." "0,1" bitfld.long 0x00 20. " I2C2_SCL_PULLTYPESELECT ,pullup/down selection for pad i2c2_scl - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " I2C2_SCL_PULLUDENABLE ,pullup/down enable for pad i2c2_scl - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " I2C2_SCL_MUXMODE ,Functional multiplexing selection for pad i2c2_scl - . - . - . - ." "Select_i2c2_scl,Select_uart1_rx,2,Select_gpio_128,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " I2C1_SDA_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " I2C1_SDA_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 8. " I2C1_SDA_INPUTENABLE ,Input enable value for pad i2c1_sda - . - ." "0,1" bitfld.long 0x00 4. " I2C1_SDA_PULLTYPESELECT ,pullup/down selection for pad i2c1_sda - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 3. " I2C1_SDA_PULLUDENABLE ,pullup/down enable for pad i2c1_sda - . - ." "pullup/down_disabled,pullup/down_enabled" group.long 0x128++0x3 line.long 0x00 "CONTROL_CORE_PAD0_I2C2_SDA_PAD1_I2C3_SCL,Register control for Pads i2c2_sda and i2c3_scl Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " I2C3_SCL_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " I2C3_SCL_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " I2C3_SCL__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad i2c3_scl - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " I2C3_SCL__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad i2c3_scl - . - ." "0,1" bitfld.long 0x00 27. " I2C3_SCL_OFFMODEOUTVALUE ,OffMode mode output value for pad i2c3_scl - . - ." "0,1" bitfld.long 0x00 26. " I2C3_SCL_OFFMODEOUTENABLE ,OffMode mode output enable value for pad i2c3_scl. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " I2C3_SCL_OFFMODEENABLE ,OffMode mode override control for pad i2c3_scl - . - ." "0,1" bitfld.long 0x00 24. " I2C3_SCL_INPUTENABLE ,Input enable value for pad i2c3_scl - . - ." "0,1" bitfld.long 0x00 20. " I2C3_SCL_PULLTYPESELECT ,pullup/down selection for pad i2c3_scl - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " I2C3_SCL_PULLUDENABLE ,pullup/down enable for pad i2c3_scl - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " I2C3_SCL_MUXMODE ,Functional multiplexing selection for pad i2c3_scl - . - . - ." "Select_i2c3_scl,1,2,Select_gpio_130,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " I2C2_SDA_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " I2C2_SDA_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " I2C2_SDA__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad i2c2_sda - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " I2C2_SDA__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad i2c2_sda - . - ." "0,1" textline " " bitfld.long 0x00 11. " I2C2_SDA_OFFMODEOUTVALUE ,OffMode mode output value for pad i2c2_sda - . - ." "0,1" bitfld.long 0x00 10. " I2C2_SDA_OFFMODEOUTENABLE ,OffMode mode output enable value for pad i2c2_sda. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " I2C2_SDA_OFFMODEENABLE ,OffMode mode override control for pad i2c2_sda - . - ." "0,1" textline " " bitfld.long 0x00 8. " I2C2_SDA_INPUTENABLE ,Input enable value for pad i2c2_sda - . - ." "0,1" bitfld.long 0x00 4. " I2C2_SDA_PULLTYPESELECT ,pullup/down selection for pad i2c2_sda - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " I2C2_SDA_PULLUDENABLE ,pullup/down enable for pad i2c2_sda - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " I2C2_SDA_MUXMODE ,Functional multiplexing selection for pad i2c2_sda - . - . - . - ." "Select_i2c2_sda,Select_uart1_tx,2,Select_gpio_129,4,5,6,Select_safe_mode" group.long 0x12C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_I2C3_SDA_PAD1_I2C4_SCL,Register control for Pads i2c3_sda and i2c4_scl Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " I2C4_SCL_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " I2C4_SCL_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " I2C4_SCL__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad i2c4_scl - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " I2C4_SCL__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad i2c4_scl - . - ." "0,1" bitfld.long 0x00 27. " I2C4_SCL_OFFMODEOUTVALUE ,OffMode mode output value for pad i2c4_scl - . - ." "0,1" bitfld.long 0x00 26. " I2C4_SCL_OFFMODEOUTENABLE ,OffMode mode output enable value for pad i2c4_scl. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " I2C4_SCL_OFFMODEENABLE ,OffMode mode override control for pad i2c4_scl - . - ." "0,1" bitfld.long 0x00 24. " I2C4_SCL_INPUTENABLE ,Input enable value for pad i2c4_scl - . - ." "0,1" bitfld.long 0x00 20. " I2C4_SCL_PULLTYPESELECT ,pullup/down selection for pad i2c4_scl - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " I2C4_SCL_PULLUDENABLE ,pullup/down enable for pad i2c4_scl - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " I2C4_SCL_MUXMODE ,Functional multiplexing selection for pad i2c4_scl - . - . - ." "Select_i2c4_scl,1,2,Select_gpio_132,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " I2C3_SDA_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " I2C3_SDA_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " I2C3_SDA__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad i2c3_sda - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " I2C3_SDA__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad i2c3_sda - . - ." "0,1" textline " " bitfld.long 0x00 11. " I2C3_SDA_OFFMODEOUTVALUE ,OffMode mode output value for pad i2c3_sda - . - ." "0,1" bitfld.long 0x00 10. " I2C3_SDA_OFFMODEOUTENABLE ,OffMode mode output enable value for pad i2c3_sda. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " I2C3_SDA_OFFMODEENABLE ,OffMode mode override control for pad i2c3_sda - . - ." "0,1" textline " " bitfld.long 0x00 8. " I2C3_SDA_INPUTENABLE ,Input enable value for pad i2c3_sda - . - ." "0,1" bitfld.long 0x00 4. " I2C3_SDA_PULLTYPESELECT ,pullup/down selection for pad i2c3_sda - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " I2C3_SDA_PULLUDENABLE ,pullup/down enable for pad i2c3_sda - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " I2C3_SDA_MUXMODE ,Functional multiplexing selection for pad i2c3_sda - . - . - ." "Select_i2c3_sda,1,2,Select_gpio_131,4,5,6,Select_safe_mode" group.long 0x130++0x3 line.long 0x00 "CONTROL_CORE_PAD0_I2C4_SDA_PAD1_MCSPI1_CLK,Register control for Pads i2c4_sda and mcspi1_clk Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " MCSPI1_CLK_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " MCSPI1_CLK_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " MCSPI1_CLK_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi1_clk - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " MCSPI1_CLK_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi1_clk - . - ." "0,1" bitfld.long 0x00 27. " MCSPI1_CLK_OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi1_clk - . - ." "0,1" bitfld.long 0x00 26. " MCSPI1_CLK_OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi1_clk. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " MCSPI1_CLK_OFFMODEENABLE ,OffMode mode override control for pad mcspi1_clk - . - ." "0,1" bitfld.long 0x00 24. " MCSPI1_CLK_INPUTENABLE ,Input enable value for pad mcspi1_clk - . - ." "0,1" bitfld.long 0x00 20. " MCSPI1__CLK_PULLTYPESELECT ,pullup/down selection for pad mcspi1_clk - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " MCSPI1__CLK_PULLUDENABLE ,pullup/down enable for pad mcspi1_clk - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " MCSPI1__CLK_MUXMODE ,Functional multiplexing selection for pad mcspi1_clk - . - . - ." "Select_mcspi1_clk,1,2,Select_gpio_134,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " I2C4__SDA_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " I2C4_SDA__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " I2C4_SDA__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad i2c4_sda - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " I2C4_SDA__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad i2c4_sda - . - ." "0,1" textline " " bitfld.long 0x00 11. " I2C4_SDA__OFFMODEOUTVALUE ,OffMode mode output value for pad i2c4_sda - . - ." "0,1" bitfld.long 0x00 10. " I2C4_SDA__OFFMODEOUTENABLE ,OffMode mode output enable value for pad i2c4_sda. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " I2C4_SDA__OFFMODEENABLE ,OffMode mode override control for pad i2c4_sda - . - ." "0,1" textline " " bitfld.long 0x00 8. " I2C4_SDA__INPUTENABLE ,Input enable value for pad i2c4_sda - . - ." "0,1" bitfld.long 0x00 4. " I2C4_SDA__PULLTYPESELECT ,pullup/down selection for pad i2c4_sda - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " I2C4_SDA__PULLUDENABLE ,pullup/down enable for pad i2c4_sda - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " I2C4_SDA__MUXMODE ,Functional multiplexing selection for pad i2c4_sda - . - . - ." "Select_i2c4_sda,1,2,Select_gpio_133,4,5,6,Select_safe_mode" group.long 0x134++0x3 line.long 0x00 "CONTROL_CORE_PAD0_MCSPI1_SOMI_PAD1_MCSPI1_SIMO,Register control for Pads mcspi1_somi and mcspi1_simo Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " MCSPI1_SIMO_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " MCSPI1_SIMO_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " MCSPI1_SIMO__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi1_simo - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " MCSPI1_SIMO__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi1_simo - . - ." "0,1" bitfld.long 0x00 27. " MCSPI1_SIMO__OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi1_simo - . - ." "0,1" bitfld.long 0x00 26. " MCSPI1_SIMO__OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi1_simo. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " MCSPI1_SIMO__OFFMODEENABLE ,OffMode mode override control for pad mcspi1_simo - . - ." "0,1" bitfld.long 0x00 24. " MCSPI1_SIMO__INPUTENABLE ,Input enable value for pad mcspi1_simo - . - ." "0,1" bitfld.long 0x00 20. " MCSPI1_SIMO__PULLTYPESELECT ,pullup/down selection for pad mcspi1_simo - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " MCSPI1_SIMO__PULLUDENABLE ,pullup/down enable for pad mcspi1_simo - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " MCSPI1__SIMO_MUXMODE ,Functional multiplexing selection for pad mcspi1_simo - . - . - ." "Select_mcspi1_simo,1,2,Select_gpio_136,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " MCSPI1__SOMI_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " MCSPI1__SOMI_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " MCSPI1__SOMI_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi1_somi - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " MCSPI1__SOMI_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi1_somi - . - ." "0,1" textline " " bitfld.long 0x00 11. " MCSPI1__SOMI_OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi1_somi - . - ." "0,1" bitfld.long 0x00 10. " MCSPI1__SOMI_OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi1_somi. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " MCSPI1__SOMI_OFFMODEENABLE ,OffMode mode override control for pad mcspi1_somi - . - ." "0,1" textline " " bitfld.long 0x00 8. " MCSPI1_SOMI__INPUTENABLE ,Input enable value for pad mcspi1_somi - . - ." "0,1" bitfld.long 0x00 4. " MCSPI1_SOMI__PULLTYPESELECT ,pullup/down selection for pad mcspi1_somi - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " MCSPI1_SOMI__PULLUDENABLE ,pullup/down enable for pad mcspi1_somi - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " MCSPI1__SOMI_MUXMODE ,Functional multiplexing selection for pad mcspi1_somi - . - . - ." "Select_mcspi1_somi,1,2,Select_gpio_135,4,5,6,Select_safe_mode" group.long 0x138++0x3 line.long 0x00 "CONTROL_CORE_PAD0_MCSPI1_CS0_PAD1_MCSPI1_CS1,Register control for Pads mcspi1_cs0 and mcspi1_cs1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " MCSPI1_CS1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " MCSPI1_CS1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " MCSPI1_CS1_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi1_cs1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " MCSPI1_CS1_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi1_cs1 - . - ." "0,1" bitfld.long 0x00 27. " MCSPI1_CS1_OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi1_cs1 - . - ." "0,1" bitfld.long 0x00 26. " MCSPI1_CS1_OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi1_cs1. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " MCSPI1_CS1_OFFMODEENABLE ,OffMode mode override control for pad mcspi1_cs1 - . - ." "0,1" bitfld.long 0x00 24. " MCSPI1_CS1_INPUTENABLE ,Input enable value for pad mcspi1_cs1 - . - ." "0,1" bitfld.long 0x00 20. " MCSPI1_CS1__PULLTYPESELECT ,pullup/down selection for pad mcspi1_cs1 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " MCSPI1_CS1__PULLUDENABLE ,pullup/down enable for pad mcspi1_cs1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " MCSPI1_CS1_MUXMODE ,Functional multiplexing selection for pad mcspi1_cs1 - . - . - . - ." "Select_mcspi1_cs1,Select_uart1_rx,2,Select_gpio_138,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " MCSPI1_CS0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " MCSPI1_CS0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " MCSPI1_CS0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi1_cs0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " MCSPI1_CS0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi1_cs0 - . - ." "0,1" textline " " bitfld.long 0x00 11. " MCSPI1_CS0__OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi1_cs0 - . - ." "0,1" bitfld.long 0x00 10. " MCSPI1_CS0__OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi1_cs0. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " MCSPI1_CS0_OFFMODEENABLE ,OffMode mode override control for pad mcspi1_cs0 - . - ." "0,1" textline " " bitfld.long 0x00 8. " MCSPI1_CS0_INPUTENABLE ,Input enable value for pad mcspi1_cs0 - . - ." "0,1" bitfld.long 0x00 4. " MCSPI1_CS0__PULLTYPESELECT ,pullup/down selection for pad mcspi1_cs0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " MCSPI1_CS0__PULLUDENABLE ,pullup/down enable for pad mcspi1_cs0 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " MCSPI1_CS0_MUXMODE ,Functional multiplexing selection for pad mcspi1_cs0 - . - . - ." "Select_mcspi1_cs0,1,2,Select_gpio_137,4,5,6,Select_safe_mode" group.long 0x13C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_MCSPI1_CS2_PAD1_MCSPI1_CS3,Register control for Pads mcspi1_cs2 and mcspi1_cs3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " MCSPI1_CS3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " MCSPI1_CS3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " MCSPI1_CS3_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi1_cs3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " MCSPI1_CS3_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi1_cs3 - . - ." "0,1" bitfld.long 0x00 27. " MCSPI1_CS3_OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi1_cs3 - . - ." "0,1" bitfld.long 0x00 26. " MCSPI1_CS3_OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi1_cs3. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " MCSPI1_CS3_OFFMODEENABLE ,OffMode mode override control for pad mcspi1_cs3 - . - ." "0,1" bitfld.long 0x00 24. " MCSPI1_CS3_INPUTENABLE ,Input enable value for pad mcspi1_cs3 - . - ." "0,1" bitfld.long 0x00 20. " MCSPI1__CS3_PULLTYPESELECT ,pullup/down selection for pad mcspi1_cs3 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " MCSPI1_CS3_PULLUDENABLE ,pullup/down enable for pad mcspi1_cs3 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " MCSPI1_CS3_MUXMODE ,Functional multiplexing selection for pad mcspi1_cs3 - . - . - . - . - ." "Select_mcspi1_cs3,Select_uart1_rts,Select_slimbus2_data,Select_gpio_140,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " MCSPI1_CS2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " MCSPI1_CS2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " MCSPI1_CS2_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi1_cs2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " MCSPI1_CS2_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi1_cs2 - . - ." "0,1" textline " " bitfld.long 0x00 11. " MCSPI1_CS2_OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi1_cs2 - . - ." "0,1" bitfld.long 0x00 10. " MCSPI1_CS2_OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi1_cs2. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " MCSPI1_CS2_OFFMODEENABLE ,OffMode mode override control for pad mcspi1_cs2 - . - ." "0,1" textline " " bitfld.long 0x00 8. " MCSPI1_CS2_INPUTENABLE ,Input enable value for pad mcspi1_cs2 - . - ." "0,1" bitfld.long 0x00 4. " MCSPI1__CS2_PULLTYPESELECT ,pullup/down selection for pad mcspi1_cs2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " MCSPI1_CS2_PULLUDENABLE ,pullup/down enable for pad mcspi1_cs2 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " MCSPI1_CS2_MUXMODE ,Functional multiplexing selection for pad mcspi1_cs2 - . - . - . - . - ." "Select_mcspi1_cs2,Select_uart1_cts,Select_slimbus2_clock,Select_gpio_139,4,5,6,Select_safe_mode" group.long 0x140++0x3 line.long 0x00 "CONTROL_CORE_PAD0_UART3_CTS_RCTX_PAD1_UART3_RTS_SD,Register control for Pads uart3_cts_rctx and uart3_rts_sd Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " UART3_RTS_SD_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " UART3_RTS_SD_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " UART3_RTS__SD_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart3_rts_sd - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " UART3_RTS_SD__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart3_rts_sd - . - ." "0,1" bitfld.long 0x00 27. " UART3_RTS_SD__OFFMODEOUTVALUE ,OffMode mode output value for pad uart3_rts_sd - . - ." "0,1" bitfld.long 0x00 26. " UART3_RTS_SD__OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart3_rts_sd. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " UART3_RTS_SD__OFFMODEENABLE ,OffMode mode override control for pad uart3_rts_sd - . - ." "0,1" bitfld.long 0x00 24. " UART3_RTS_SD_INPUTENABLE ,Input enable value for pad uart3_rts_sd - . - ." "0,1" bitfld.long 0x00 20. " UART3_RTS_SD_PULLTYPESELECT ,pullup/down selection for pad uart3_rts_sd - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " UART3_RTS_SD_PULLUDENABLE ,pullup/down enable for pad uart3_rts_sd - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " UART3_RTS_SD_MUXMODE ,Functional multiplexing selection for pad uart3_rts_sd - . - . - ." "Select_uart3_rts_sd,1,2,Select_gpio_142,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " UART3_CTS_RCTX_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " UART3_CTS__RCTX_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " UART3_CTS_RCTX__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart3_cts_rctx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " UART3_CTS_RCTX__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart3_cts_rctx - . - ." "0,1" textline " " bitfld.long 0x00 11. " UART3_CTS_RCTX_OFFMODEOUTVALUE ,OffMode mode output value for pad uart3_cts_rctx - . - ." "0,1" bitfld.long 0x00 10. " UART3_CTS_RCTX_OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart3_cts_rctx. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " UART3_CTS_RCTX_OFFMODEENABLE ,OffMode mode override control for pad uart3_cts_rctx - . - ." "0,1" textline " " bitfld.long 0x00 8. " UART3_CTS_RCTX_INPUTENABLE ,Input enable value for pad uart3_cts_rctx - . - ." "0,1" bitfld.long 0x00 4. " UART3_CTS_RCTX_PULLTYPESELECT ,pullup/down selection for pad uart3_cts_rctx - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " UART3_CTS_RCTX_PULLUDENABLE ,pullup/down enable for pad uart3_cts_rctx - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " UART3_CTS_RCTX_MUXMODE ,Functional multiplexing selection for pad uart3_cts_rctx - . - . - . - ." "Select_uart3_cts_rctx,Select_uart1_tx,2,Select_gpio_141,4,5,6,Select_safe_mode" group.long 0x144++0x3 line.long 0x00 "CONTROL_CORE_PAD0_UART3_RX_IRRX_PAD1_UART3_TX_IRTX,Register control for Pads uart3_rx_irrx and uart3_tx_irtx Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " UART3_TX_IRTX_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " UART3_TX_IRTX_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " UART3_TX__IRTX_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart3_tx_irtx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " UART3_TX_IRTX_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart3_tx_irtx - . - ." "0,1" bitfld.long 0x00 27. " UART3_TX_IRTX_OFFMODEOUTVALUE ,OffMode mode output value for pad uart3_tx_irtx - . - ." "0,1" bitfld.long 0x00 26. " UART3_TX_IRTX_OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart3_tx_irtx. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " UART3_TX_IRTX_OFFMODEENABLE ,OffMode mode override control for pad uart3_tx_irtx - . - ." "0,1" bitfld.long 0x00 24. " UART3_TX_IRTX_INPUTENABLE ,Input enable value for pad uart3_tx_irtx - . - ." "0,1" bitfld.long 0x00 20. " UART3_TX_IRTX_PULLTYPESELECT ,pullup/down selection for pad uart3_tx_irtx - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " UART3_TX_IRTX_PULLUDENABLE ,pullup/down enable for pad uart3_tx_irtx - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " UART3_TX_IRTX_MUXMODE ,Functional multiplexing selection for pad uart3_tx_irtx - . - . - . - ." "Select_uart3_tx_irtx,Select_dmtimer9_pwm_evt,2,Select_gpio_144,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " UART3_RX__IRRX_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " UART3_RX__IRRX_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " UART3_RX__IRRX_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart3_rx_irrx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " UART3_RX__IRRX_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart3_rx_irrx - . - ." "0,1" textline " " bitfld.long 0x00 11. " UART3_RX__IRRX_OFFMODEOUTVALUE ,OffMode mode output value for pad uart3_rx_irrx - . - ." "0,1" bitfld.long 0x00 10. " UART3_RX__IRRX_OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart3_rx_irrx. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " UART3_RX_IRRX_OFFMODEENABLE ,OffMode mode override control for pad uart3_rx_irrx - . - ." "0,1" textline " " bitfld.long 0x00 8. " UART3_RX_IRRX_INPUTENABLE ,Input enable value for pad uart3_rx_irrx - . - ." "0,1" bitfld.long 0x00 4. " UART3_RX_IRRX_PULLTYPESELECT ,pullup/down selection for pad uart3_rx_irrx - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " UART3_RX_IRRX_PULLUDENABLE ,pullup/down enable for pad uart3_rx_irrx - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " UART3_RX_IRRX_MUXMODE ,Functional multiplexing selection for pad uart3_rx_irrx - . - . - . - ." "Select_uart3_rx_irrx,Select_dmtimer8_pwm_evt,2,Select_gpio_143,4,5,6,Select_safe_mode" group.long 0x148++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SDMMC5_CLK_PAD1_SDMMC5_CMD,Register control for Pads sdmmc5_clk and sdmmc5_cmd Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SDMMC5_CMD__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SDMMC5_CMD__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SDMMC5_CMD_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc5_cmd - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SDMMC5_CMD_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc5_cmd - . - ." "0,1" bitfld.long 0x00 27. " SDMMC5_CMD_OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc5_cmd - . - ." "0,1" bitfld.long 0x00 26. " SDMMC5_CMD_OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc5_cmd. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SDMMC5_CMD_OFFMODEENABLE ,OffMode mode override control for pad sdmmc5_cmd - . - ." "0,1" bitfld.long 0x00 24. " SDMMC5_CMD_INPUTENABLE ,Input enable value for pad sdmmc5_cmd - . - ." "0,1" bitfld.long 0x00 20. " SDMMC5_CMD__PULLTYPESELECT ,pullup/down selection for pad sdmmc5_cmd - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SDMMC5_CMD__PULLUDENABLE ,pullup/down enable for pad sdmmc5_cmd - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SDMMC5_CMD_MUXMODE ,Functional multiplexing selection for pad sdmmc5_cmd - . - . - . - . - . - ." "Select_sdmmc5_cmd,Select_mcspi2_simo,Select_usbc1_icusb_dm,Select_gpio_146,4,Select_sdmmc2_cmd,6,Select_safe_mode" bitfld.long 0x00 15. " SDMMC5__CLK_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SDMMC5__CLK_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SDMMC5__CLK_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc5_clk - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SDMMC5__CLK_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc5_clk - . - ." "0,1" textline " " bitfld.long 0x00 11. " SDMMC5__CLK_OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc5_clk - . - ." "0,1" bitfld.long 0x00 10. " SDMMC5__CLK_OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc5_clk. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SDMMC5_CLK_OFFMODEENABLE ,OffMode mode override control for pad sdmmc5_clk - . - ." "0,1" textline " " bitfld.long 0x00 8. " SDMMC5_CLK_INPUTENABLE ,Input enable value for pad sdmmc5_clk - . - ." "0,1" bitfld.long 0x00 4. " SDMMC5__CLK_PULLTYPESELECT ,pullup/down selection for pad sdmmc5_clk - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SDMMC5__CLK_PULLUDENABLE ,pullup/down enable for pad sdmmc5_clk - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SDMMC5_CLK_MUXMODE ,Functional multiplexing selection for pad sdmmc5_clk - . - . - . - . - . - ." "Select_sdmmc5_clk,Select_mcspi2_clk,Select_usbc1_icusb_dp,Select_gpio_145,4,Select_sdmmc2_clk,6,Select_safe_mode" group.long 0x14C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SDMMC5_DAT0_PAD1_SDMMC5_DAT1,Register control for Pads sdmmc5_dat0 and sdmmc5_dat1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SDMMC5_DAT1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SDMMC5_DAT1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SDMMC5_DAT1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc5_dat1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SDMMC5_DAT1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc5_dat1 - . - ." "0,1" bitfld.long 0x00 27. " SDMMC5_DAT1__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc5_dat1 - . - ." "0,1" bitfld.long 0x00 26. " SDMMC5_DAT1__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc5_dat1. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SDMMC5_DAT1__OFFMODEENABLE ,OffMode mode override control for pad sdmmc5_dat1 - . - ." "0,1" bitfld.long 0x00 24. " SDMMC5_DAT1__INPUTENABLE ,Input enable value for pad sdmmc5_dat1 - . - ." "0,1" bitfld.long 0x00 20. " SDMMC5_DAT1__PULLTYPESELECT ,pullup/down selection for pad sdmmc5_dat1 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SDMMC5_DAT1__PULLUDENABLE ,pullup/down enable for pad sdmmc5_dat1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SDMMC5_DAT1__MUXMODE ,Functional multiplexing selection for pad sdmmc5_dat1 - . - . - . - . - ." "Select_sdmmc5_dat1,1,Select_usbc1_icusb_txen,Select_gpio_148,4,Select_sdmmc2_dat1,6,Select_safe_mode" bitfld.long 0x00 15. " SDMMC5_DAT0__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SDMMC5_DAT0__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SDMMC5_DAT0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc5_dat0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SDMMC5_DAT0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc5_dat0 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SDMMC5_DAT0__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc5_dat0 - . - ." "0,1" bitfld.long 0x00 10. " SDMMC5_DAT0__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc5_dat0. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SDMMC5_DAT0__OFFMODEENABLE ,OffMode mode override control for pad sdmmc5_dat0 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SDMMC5_DAT0__INPUTENABLE ,Input enable value for pad sdmmc5_dat0 - . - ." "0,1" bitfld.long 0x00 4. " SDMMC5_DAT0__PULLTYPESELECT ,pullup/down selection for pad sdmmc5_dat0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SDMMC5_DAT0__PULLUDENABLE ,pullup/down enable for pad sdmmc5_dat0 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SDMMC5_DAT0__MUXMODE ,Functional multiplexing selection for pad sdmmc5_dat0 - . - . - . - . - . - ." "Select_sdmmc5_dat0,Select_mcspi2_somi,Select_usbc1_icusb_rcv,Select_gpio_147,4,sdmmc2_dat0,6,Select_safe_mode" group.long 0x150++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SDMMC5_DAT2_PAD1_SDMMC5_DAT3,Register control for Pads sdmmc5_dat2 and sdmmc5_dat3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SDMMC5_DAT3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SDMMC5_DAT3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SDMMC5_DAT3__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc5_dat3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SDMMC5_DAT3__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc5_dat3 - . - ." "0,1" bitfld.long 0x00 27. " SDMMC5_DAT3__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc5_dat3 - . - ." "0,1" bitfld.long 0x00 26. " SDMMC5_DAT3__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc5_dat3. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SDMMC5_DAT3__OFFMODEENABLE ,OffMode mode override control for pad sdmmc5_dat3 - . - ." "0,1" bitfld.long 0x00 24. " SDMMC5_DAT3__INPUTENABLE ,Input enable value for pad sdmmc5_dat3 - . - ." "0,1" bitfld.long 0x00 20. " SDMMC5_DAT3__PULLTYPESELECT ,pullup/down selection for pad sdmmc5_dat3 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SDMMC5_DAT3__PULLUDENABLE ,pullup/down enable for pad sdmmc5_dat3 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SDMMC5_DAT3__MUXMODE ,Functional multiplexing selection for pad sdmmc5_dat3 - . - . - . - . - ." "Select_sdmmc5_dat3,Select_mcspi2_cs0,2,Select_gpio_150,4,Select_sdmmc2_dat3,6,Select_safe_mode" bitfld.long 0x00 15. " SDMMC5_DAT2__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SDMMC5_DAT2__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SDMMC5_DAT2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sdmmc5_dat2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SDMMC5_DAT2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sdmmc5_dat2 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SDMMC5_DAT2__OFFMODEOUTVALUE ,OffMode mode output value for pad sdmmc5_dat2 - . - ." "0,1" bitfld.long 0x00 10. " SDMMC5_DAT2__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sdmmc5_dat2. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SDMMC5_DAT2__OFFMODEENABLE ,OffMode mode override control for pad sdmmc5_dat2 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SDMMC5_DAT2__INPUTENABLE ,Input enable value for pad sdmmc5_dat2 - . - ." "0,1" bitfld.long 0x00 4. " SDMMC5_DAT2__PULLTYPESELECT ,pullup/down selection for pad sdmmc5_dat2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SDMMC5_DAT2__PULLUDENABLE ,pullup/down enable for pad sdmmc5_dat2 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SDMMC5_DAT2__MUXMODE ,Functional multiplexing selection for pad sdmmc5_dat2 - . - . - . - . - ." "Select_sdmmc5_dat2,Select_mcspi2_cs1,2,Select_gpio_149,4,Select_sdmmc2_dat2,6,Select_safe_mode" group.long 0x154++0x3 line.long 0x00 "CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO,Register control for Pads mcspi4_clk and mcspi4_simo Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " MCSPI4_SIMO_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " MCSPI4_SIMO_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " MCSPI4_SIMO__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi4_simo - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " MCSPI4_SIMO__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi4_simo - . - ." "0,1" bitfld.long 0x00 27. " MCSPI4_SIMO__OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi4_simo - . - ." "0,1" bitfld.long 0x00 26. " MCSPI4_SIMO__OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi4_simo. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " MCSPI4_SIMO__OFFMODEENABLE ,OffMode mode override control for pad mcspi4_simo - . - ." "0,1" bitfld.long 0x00 24. " MCSPI4_SIMO__INPUTENABLE ,Input enable value for pad mcspi4_simo - . - ." "0,1" bitfld.long 0x00 20. " MCSPI4_SIMO__PULLTYPESELECT ,pullup/down selection for pad mcspi4_simo - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " MCSPI4_SIMO__PULLUDENABLE ,pullup/down enable for pad mcspi4_simo - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " MCSPI4_SIMO__MUXMODE ,Functional multiplexing selection for pad mcspi4_simo - . - . - . - . - ." "Select_mcspi4_simo,Select_sdmmc4_cmd,Select_kpd_col7,Select_gpio_152,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " MCSPI4_CLK__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " MCSPI4_CLK__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " MCSPI4_CLK__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi4_clk - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " MCSPI4_CLK__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi4_clk - . - ." "0,1" textline " " bitfld.long 0x00 11. " MCSPI4_CLK__OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi4_clk - . - ." "0,1" bitfld.long 0x00 10. " MCSPI4_CLK__OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi4_clk. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " MCSPI4_CLK__OFFMODEENABLE ,OffMode mode override control for pad mcspi4_clk - . - ." "0,1" textline " " bitfld.long 0x00 8. " MCSPI4_CLK__INPUTENABLE ,Input enable value for pad mcspi4_clk - . - ." "0,1" bitfld.long 0x00 4. " MCSPI4_CLK__PULLTYPESELECT ,pullup/down selection for pad mcspi4_clk - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " MCSPI4_CLK__PULLUDENABLE ,pullup/down enable for pad mcspi4_clk - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " MCSPI4_CLK__MUXMODE ,Functional multiplexing selection for pad mcspi4_clk - . - . - . - . - ." "Select_mcspi4_clk,Select_sdmmc4_clk,Select_kpd_col6,Select_gpio_151,4,5,6,Select_safe_mode" group.long 0x158++0x3 line.long 0x00 "CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0,Register control for Pads mcspi4_somi and mcspi4_cs0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " MCSPI4_CS0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " MCSPI4_CS0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " MCSPI4_CS0_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi4_cs0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " MCSPI4_CS0_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi4_cs0 - . - ." "0,1" bitfld.long 0x00 27. " MCSPI4_CS0_OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi4_cs0 - . - ." "0,1" bitfld.long 0x00 26. " MCSPI4_CS0_OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi4_cs0. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " MCSPI4_CS0_OFFMODEENABLE ,OffMode mode override control for pad mcspi4_cs0 - . - ." "0,1" bitfld.long 0x00 24. " MCSPI4_CS0_INPUTENABLE ,Input enable value for pad mcspi4_cs0 - . - ." "0,1" bitfld.long 0x00 20. " MCSPI4__CS0_PULLTYPESELECT ,pullup/down selection for pad mcspi4_cs0 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " MCSPI4__CS0_PULLUDENABLE ,pullup/down enable for pad mcspi4_cs0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " MCSPI4__CS0_MUXMODE ,Functional multiplexing selection for pad mcspi4_cs0 - . - . - . - . - ." "Select_mcspi4_cs0,Select_sdmmc4_dat3,Select_kpd_row7,Select_gpio_154,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " MCSPI4__SOMI_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " MCSPI4__SOMI_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " MCSPI4_SOMI__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad mcspi4_somi - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " MCSPI4_SOMI__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad mcspi4_somi - . - ." "0,1" textline " " bitfld.long 0x00 11. " MCSPI4_SOMI__OFFMODEOUTVALUE ,OffMode mode output value for pad mcspi4_somi - . - ." "0,1" bitfld.long 0x00 10. " MCSPI4_SOMI__OFFMODEOUTENABLE ,OffMode mode output enable value for pad mcspi4_somi. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " MCSPI4_SOMI__OFFMODEENABLE ,OffMode mode override control for pad mcspi4_somi - . - ." "0,1" textline " " bitfld.long 0x00 8. " MCSPI4_SOMI__INPUTENABLE ,Input enable value for pad mcspi4_somi - . - ." "0,1" bitfld.long 0x00 4. " MCSPI4_SOMI__PULLTYPESELECT ,pullup/down selection for pad mcspi4_somi - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " MCSPI4_SOMI__PULLUDENABLE ,pullup/down enable for pad mcspi4_somi - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " MCSPI4_SOMI__MUXMODE ,Functional multiplexing selection for pad mcspi4_somi - . - . - . - . - ." "Select_mcspi4_somi,Select_sdmmc4_dat0,Select_kpd_row6,Select_gpio_153,4,5,6,Select_safe_mode" group.long 0x15C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_UART4_RX_PAD1_UART4_TX,Register control for Pads uart4_rx and uart4_tx Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " UART4_TX_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " UART4_TX_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " UART4_TX__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart4_tx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " UART4_TX__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart4_tx - . - ." "0,1" bitfld.long 0x00 27. " UART4_TX__OFFMODEOUTVALUE ,OffMode mode output value for pad uart4_tx - . - ." "0,1" bitfld.long 0x00 26. " UART4_TX__OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart4_tx. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " UART4_TX__OFFMODEENABLE ,OffMode mode override control for pad uart4_tx - . - ." "0,1" bitfld.long 0x00 24. " UART4_TX__INPUTENABLE ,Input enable value for pad uart4_tx - . - ." "0,1" bitfld.long 0x00 20. " UART4_TX__PULLTYPESELECT ,pullup/down selection for pad uart4_tx - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " UART4_TX__PULLUDENABLE ,pullup/down enable for pad uart4_tx - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " UART4_TX__MUXMODE ,Functional multiplexing selection for pad uart4_tx - . - . - . - . - ." "Select_uart4_tx,Select_sdmmc4_dat1,Select_kpd_col8,Select_gpio_156,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " UART4_RX__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " UART4_RX__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " UART4_RX__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad uart4_rx - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " UART4_RX__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad uart4_rx - . - ." "0,1" textline " " bitfld.long 0x00 11. " UART4_RX__OFFMODEOUTVALUE ,OffMode mode output value for pad uart4_rx - . - ." "0,1" bitfld.long 0x00 10. " UART4_RX__OFFMODEOUTENABLE ,OffMode mode output enable value for pad uart4_rx. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " UART4_RX__OFFMODEENABLE ,OffMode mode override control for pad uart4_rx - . - ." "0,1" textline " " bitfld.long 0x00 8. " UART4_RX_INPUTENABLE ,Input enable value for pad uart4_rx - . - ." "0,1" bitfld.long 0x00 4. " UART4_RX__PULLTYPESELECT ,pullup/down selection for pad uart4_rx - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " UART4_RX__PULLUDENABLE ,pullup/down enable for pad uart4_rx - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " UART4_RX__MUXMODE ,Functional multiplexing selection for pad uart4_rx - . - . - . - . - ." "Select_uart4_rx,Select_sdmmc4_dat2,Select_kpd_row8,Select_gpio_155,4,5,6,Select_safe_mode" group.long 0x160++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB2_ULPITLL_CLK_PAD1_USBB2_ULPITLL_STP,Register control for Pads usbb2_ulpitll_clk and usbb2_ulpitll_stp Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB2_ULPITLL_STP_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB2_ULPITLL_STP_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB2_ULPITLL__STP_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_stp - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB2_ULPITLL__STP_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_stp - . - ." "0,1" bitfld.long 0x00 27. " USBB2_ULPITLL__STP_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_stp - . - ." "0,1" bitfld.long 0x00 26. " USBB2_ULPITLL__STP_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_stp. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB2_ULPITLL__STP_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_stp - . - ." "0,1" bitfld.long 0x00 24. " USBB2_ULPITLL__STP_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_stp - . - ." "0,1" bitfld.long 0x00 20. " USBB2_ULPITLL__STP_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_stp - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB2_ULPITLL__STP_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_stp - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB2_ULPITLL__STP_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_stp - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_stp,Select_usbb2_ulpiphy_stp,Select_sdmmc4_clk,Select_gpio_158,Select_hsi2_cadata,Select_dispc2_data23,6,Select_safe_mode" bitfld.long 0x00 15. " USBB2_ULPITLL__CLK_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB2_ULPITLL__CLK_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB2_ULPITLL__CLK_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_clk - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB2_ULPITLL__CLK_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_clk - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB2_ULPITLL__CLK_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_clk - . - ." "0,1" bitfld.long 0x00 10. " USBB2_ULPITLL__CLK_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_clk. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB2_ULPITLL__CLK_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_clk - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB2_ULPITLL__CLK_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_clk - . - ." "0,1" bitfld.long 0x00 4. " USBB2_ULPITLL__CLK_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_clk - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB2_ULPITLL__CLK_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_clk - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB2_ULPITLL__CLK_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_clk - . - . - . - . - . - ." "Select_usbb2_ulpitll_clk,Select_usbb2_ulpiphy_clk,Select_sdmmc4_cmd,Select_gpio_157,Select_hsi2_cawake,5,6,Select_safe_mode" group.long 0x164++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB2_ULPITLL_DIR_PAD1_USBB2_ULPITLL_NXT,Register control for Pads usbb2_ulpitll_dir and usbb2_ulpitll_nxt Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB2_ULPITLL_NXT_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB2_ULPITLL_NXT_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB2_ULPITLL__NXT_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_nxt - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB2_ULPITLL__NXT_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_nxt - . - ." "0,1" bitfld.long 0x00 27. " USBB2_ULPITLL__NXT_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_nxt - . - ." "0,1" bitfld.long 0x00 26. " USBB2_ULPITLL__NXT_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_nxt. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB2_ULPITLL__NXT_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_nxt - . - ." "0,1" bitfld.long 0x00 24. " USBB2_ULPITLL__NXT_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_nxt - . - ." "0,1" bitfld.long 0x00 20. " USBB2_ULPITLL__NXT_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_nxt - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB2_ULPITLL__NXT_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_nxt - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB2_ULPITLL__NXT_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_nxt - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_nxt,Select_usbb2_ulpiphy_nxt,Select_sdmmc4_dat1,Select_gpio_160,Select_hsi2_acready,Select_dispc2_data21,6,Select_safe_mode" bitfld.long 0x00 15. " USBB2_ULPITLL__DIR_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB2_ULPITLL__DIR_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB2_ULPITLL__DIR_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_dir - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB2_ULPITLL__DIR_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_dir - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB2_ULPITLL__DIR_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_dir - . - ." "0,1" bitfld.long 0x00 10. " USBB2_ULPITLL__DIR_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_dir. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB2_ULPITLL__DIR_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_dir - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB2_ULPITLL__DIR_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_dir - . - ." "0,1" bitfld.long 0x00 4. " USBB2_ULPITLL__DIR_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_dir - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB2_ULPITLL__DIR_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_dir - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB2_ULPITLL__DIR_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_dir - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_dir,Select_usbb2_ulpiphy_dir,Select_sdmmc4_dat0,Select_gpio_159,Select_hsi2_caflag,Select_dispc2_data22,6,Select_safe_mode" group.long 0x168++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB2_ULPITLL_DAT0_PAD1_USBB2_ULPITLL_DAT1,Register control for Pads usbb2_ulpitll_dat0 and usbb2_ulpitll_dat1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB2_ULPITLL__DAT1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB2_ULPITLL__DAT1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB2_ULPITLL_DAT1_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_dat1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB2_ULPITLL_DAT1_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_dat1 - . - ." "0,1" bitfld.long 0x00 27. " USBB2_ULPITLL_DAT1_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_dat1 - . - ." "0,1" bitfld.long 0x00 26. " USBB2_ULPITLL_DAT1_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_dat1. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB2_ULPITLL_DAT1_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_dat1 - . - ." "0,1" bitfld.long 0x00 24. " USBB2_ULPITLL__DAT1_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_dat1 - . - ." "0,1" bitfld.long 0x00 20. " USBB2_ULPITLL__DAT1_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_dat1 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB2_ULPITLL__DAT1_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_dat1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB2_ULPITLL__DAT1_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_dat1 - . - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_dat1,Select_usbb2_ulpiphy_dat1,Select_sdmmc4_dat3,Select_gpio_162,Select_hsi2_acdata,Select_dispc2_data19,Select_usbb2_mm_txdat,Select_safe_mode" bitfld.long 0x00 15. " USBB2_ULPITLL__DAT0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB2_ULPITLL__DAT0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB2_ULPITLL__DAT0_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_dat0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB2_ULPITLL__DAT0_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_dat0 - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB2_ULPITLL__DAT0_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_dat0 - . - ." "0,1" bitfld.long 0x00 10. " USBB2_ULPITLL__DAT0_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_dat0. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB2_ULPITLL__DAT0_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_dat0 - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB2_ULPITLL__DAT0_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_dat0 - . - ." "0,1" bitfld.long 0x00 4. " USBB2_ULPITLL__DAT0_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_dat0 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB2_ULPITLL__DAT0_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_dat0 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB2_ULPITLL__DAT0_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_dat0 - . - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_dat0,Select_usbb2_ulpiphy_dat0,Select_sdmmc4_dat2,Select_gpio_161,Select_hsi2_acwake,Select_dispc2_data20,Select_usbb2_mm_txen,Select_safe_mode" group.long 0x16C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB2_ULPITLL_DAT2_PAD1_USBB2_ULPITLL_DAT3,Register control for Pads usbb2_ulpitll_dat2 and usbb2_ulpitll_dat3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB2_ULPITLL__DAT3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB2_ULPITLL__DAT3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB2_ULPITLL_DAT3_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_dat3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB2_ULPITLL_DAT3_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_dat3 - . - ." "0,1" bitfld.long 0x00 27. " USBB2_ULPITLL_DAT3_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_dat3 - . - ." "0,1" bitfld.long 0x00 26. " USBB2_ULPITLL_DAT3_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_dat3. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB2_ULPITLL_DAT3_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_dat3 - . - ." "0,1" bitfld.long 0x00 24. " USBB2_ULPITLL__DAT3_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_dat3 - . - ." "0,1" bitfld.long 0x00 20. " USBB2_ULPITLL__DAT3_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_dat3 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB2_ULPITLL__DAT3_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_dat3 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB2_ULPITLL__DAT3_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_dat3 - . - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_dat3,Select_usbb2_ulpiphy_dat3,Select_sdmmc3_dat1,Select_gpio_164,Select_hsi2_caready,Select_dispc2_data15,Select_rfbi_data15,Select_safe_mode" bitfld.long 0x00 15. " USBB2_ULPITLL__DAT2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB2_ULPITLL__DAT2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB2_ULPITLL__DAT2_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_dat2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB2_ULPITLL__DAT2_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_dat2 - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB2_ULPITLL__DAT2_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_dat2 - . - ." "0,1" bitfld.long 0x00 10. " USBB2_ULPITLL__DAT2_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_dat2. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB2_ULPITLL__DAT2_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_dat2 - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB2_ULPITLL__DAT2_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_dat2 - . - ." "0,1" bitfld.long 0x00 4. " USBB2_ULPITLL__DAT2_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_dat2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB2_ULPITLL__DAT2_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_dat2 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB2_ULPITLL__DAT2_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_dat2 - . - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_dat2,Select_usbb2_ulpiphy_dat2,Select_sdmmc3_dat2,Select_gpio_163,Select_hsi2_acflag,Select_dispc2_data18,Select_usbb2_mm_txse0,Select_safe_mode" group.long 0x170++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB2_ULPITLL_DAT4_PAD1_USBB2_ULPITLL_DAT5,Register control for Pads usbb2_ulpitll_dat4 and usbb2_ulpitll_dat5 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB2_ULPITLL__DAT5_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB2_ULPITLL__DAT5_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB2_ULPITLL_DAT5_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_dat5 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB2_ULPITLL_DAT5_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_dat5 - . - ." "0,1" bitfld.long 0x00 27. " USBB2_ULPITLL_DAT5_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_dat5 - . - ." "0,1" bitfld.long 0x00 26. " USBB2_ULPITLL_DAT5_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_dat5. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB2_ULPITLL_DAT5_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_dat5 - . - ." "0,1" bitfld.long 0x00 24. " USBB2_ULPITLL__DAT5_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_dat5 - . - ." "0,1" bitfld.long 0x00 20. " USBB2_ULPITLL__DAT5_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_dat5 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB2_ULPITLL__DAT5_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_dat5 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB2_ULPITLL__DAT5_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_dat5 - . - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_dat5,Select_usbb2_ulpiphy_dat5,Select_sdmmc3_dat3,Select_gpio_166,Select_mcspi3_cs0,Select_dispc2_data13,Select_rfbi_data13,Select_safe_mode" bitfld.long 0x00 15. " USBB2_ULPITLL__DAT4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB2_ULPITLL__DAT4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB2_ULPITLL__DAT4_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_dat4 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB2_ULPITLL__DAT4_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_dat4 - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB2_ULPITLL__DAT4_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_dat4 - . - ." "0,1" bitfld.long 0x00 10. " USBB2_ULPITLL__DAT4_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_dat4. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB2_ULPITLL__DAT4_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_dat4 - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB2_ULPITLL__DAT4_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_dat4 - . - ." "0,1" bitfld.long 0x00 4. " USBB2_ULPITLL__DAT4_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_dat4 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB2_ULPITLL__DAT4_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_dat4 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB2_ULPITLL__DAT4_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_dat4 - . - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_dat4,Select_usbb2_ulpiphy_dat4,Select_sdmmc3_dat0,Select_gpio_165,Select_mcspi3_somi,Select_dispc2_data14,Select_rfbi_data14,Select_safe_mode" group.long 0x174++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB2_ULPITLL_DAT6_PAD1_USBB2_ULPITLL_DAT7,Register control for Pads usbb2_ulpitll_dat6 and usbb2_ulpitll_dat7 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB2_ULPITLL__DAT7_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB2_ULPITLL__DAT7_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " USBB2_ULPITLL_DAT7_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_dat7 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " USBB2_ULPITLL_DAT7_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 27. " USBB2_ULPITLL_DAT7_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 26. " USBB2_ULPITLL_DAT7_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_dat7. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " USBB2_ULPITLL_DAT7_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 24. " USBB2_ULPITLL__DAT7_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 20. " USBB2_ULPITLL__DAT7_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_dat7 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " USBB2_ULPITLL__DAT7_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_dat7 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " USBB2_ULPITLL__DAT7_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_dat7 - . - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_dat7,Select_usbb2_ulpiphy_dat7,Select_sdmmc3_clk,Select_gpio_168,Select_mcspi3_clk,Select_dispc2_data11,Select_rfbi_data11,Select_safe_mode" bitfld.long 0x00 15. " USBB2_ULPITLL__DAT6_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " USBB2_ULPITLL__DAT6_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " USBB2_ULPITLL__DAT6_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad usbb2_ulpitll_dat6 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " USBB2_ULPITLL__DAT6_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad usbb2_ulpitll_dat6 - . - ." "0,1" textline " " bitfld.long 0x00 11. " USBB2_ULPITLL__DAT6_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_ulpitll_dat6 - . - ." "0,1" bitfld.long 0x00 10. " USBB2_ULPITLL__DAT6_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_ulpitll_dat6. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB2_ULPITLL__DAT6_OFFMODEENABLE ,OffMode mode override control for pad usbb2_ulpitll_dat6 - . - ." "0,1" textline " " bitfld.long 0x00 8. " USBB2_ULPITLL__DAT6_INPUTENABLE ,Input enable value for pad usbb2_ulpitll_dat6 - . - ." "0,1" bitfld.long 0x00 4. " USBB2_ULPITLL__DAT6_PULLTYPESELECT ,pullup/down selection for pad usbb2_ulpitll_dat6 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " USBB2_ULPITLL__DAT6_PULLUDENABLE ,pullup/down enable for pad usbb2_ulpitll_dat6 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " USBB2_ULPITLL__DAT6_MUXMODE ,Functional multiplexing selection for pad usbb2_ulpitll_dat6 - . - . - . - . - . - . - . - ." "Select_usbb2_ulpitll_dat6,Select_usbb2_ulpiphy_dat6,Select_sdmmc3_cmd,Select_gpio_167,Select_mcspi3_simo,Select_dispc2_data12,Select_rfbi_data12,Select_safe_mode" group.long 0x178++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBB2_HSIC_DATA_PAD1_USBB2_HSIC_STROBE,Register control for Pads usbb2_hsic_data and usbb2_hsic_strobe Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBB2_HSIC_STROBE_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBB2_HSIC_STROBE_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 27. " USBB2_HSIC__STROBE_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_hsic_strobe - . - ." "0,1" textline " " bitfld.long 0x00 26. " USBB2_HSIC__STROBE_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_hsic_strobe. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 25. " USBB2_HSIC__STROBE_OFFMODEENABLE ,OffMode mode override control for pad usbb2_hsic_strobe - . - ." "0,1" bitfld.long 0x00 16.--18. " USBB2_HSIC__STROBE_MUXMODE ,Functional multiplexing selection for pad usbb2_hsic_strobe - . - . - ." "Select_usbb2_hsic_strobe,1,2,Select_gpio_170,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " USBB2_HSIC__DATA_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " USBB2_HSIC__DATA_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 11. " USBB2_HSIC__DATA_OFFMODEOUTVALUE ,OffMode mode output value for pad usbb2_hsic_data - . - ." "0,1" textline " " bitfld.long 0x00 10. " USBB2_HSIC__DATA_OFFMODEOUTENABLE ,OffMode mode output enable value for pad usbb2_hsic_data. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " USBB2_HSIC__DATA_OFFMODEENABLE ,OffMode mode override control for pad usbb2_hsic_data - . - ." "0,1" bitfld.long 0x00 0.--2. " USBB2_HSIC__DATA_MUXMODE ,Functional multiplexing selection for pad usbb2_hsic_data - . - . - ." "Select_usbb2_hsic_data,1,2,Select_gpio_169,4,5,6,Select_safe_mode" group.long 0x17C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_KPD_COL3_PAD1_KPD_COL4,Register control for Pads kpd_col3 and kpd_col4 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " KPD_COL4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " KPD_COL4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " KPD_COL4__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_col4 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " KPD_COL4__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_col4 - . - ." "0,1" bitfld.long 0x00 27. " KPD_COL4_OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_col4 - . - ." "0,1" bitfld.long 0x00 26. " KPD_COL4_OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_col4. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " KPD_COL4_OFFMODEENABLE ,OffMode mode override control for pad kpd_col4 - . - ." "0,1" bitfld.long 0x00 24. " KPD_COL4_INPUTENABLE ,Input enable value for pad kpd_col4 - . - ." "0,1" bitfld.long 0x00 20. " KPD_COL4_PULLTYPESELECT ,pullup/down selection for pad kpd_col4 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " KPD_COL4_PULLUDENABLE ,pullup/down enable for pad kpd_col4 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " KPD_COL4_MUXMODE ,Functional multiplexing selection for pad kpd_col4 - . - . - . - ." "Select_kpd_col4,Select_kpd_col1,2,Select_gpio_172,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " KPD_COL3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " KPD_COL3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " KPD_COL3__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_col3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " KPD_COL3__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_col3 - . - ." "0,1" textline " " bitfld.long 0x00 11. " KPD_COL3__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_col3 - . - ." "0,1" bitfld.long 0x00 10. " KPD_COL3__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_col3. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " KPD_COL3__OFFMODEENABLE ,OffMode mode override control for pad kpd_col3 - . - ." "0,1" textline " " bitfld.long 0x00 8. " KPD_COL3__INPUTENABLE ,Input enable value for pad kpd_col3 - . - ." "0,1" bitfld.long 0x00 4. " KPD_COL3__PULLTYPESELECT ,pullup/down selection for pad kpd_col3 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " KPD_COL3__PULLUDENABLE ,pullup/down enable for pad kpd_col3 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " KPD_COL3__MUXMODE ,Functional multiplexing selection for pad kpd_col3 - . - . - . - ." "Select_kpd_col3,Select_kpd_col0,2,Select_gpio_171,4,5,6,Select_safe_mode" group.long 0x180++0x3 line.long 0x00 "CONTROL_CORE_PAD0_KPD_COL5_PAD1_KPD_COL0,Register control for Pads kpd_col5 and kpd_col0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " KPD_COL0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " KPD_COL0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " KPD_COL0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_col0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " KPD_COL0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_col0 - . - ." "0,1" bitfld.long 0x00 27. " KPD_COL0__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_col0 - . - ." "0,1" bitfld.long 0x00 26. " KPD_COL0__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_col0. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " KPD_COL0__OFFMODEENABLE ,OffMode mode override control for pad kpd_col0 - . - ." "0,1" bitfld.long 0x00 24. " KPD_COL0_INPUTENABLE ,Input enable value for pad kpd_col0 - . - ." "0,1" bitfld.long 0x00 20. " KPD_COL0_PULLTYPESELECT ,pullup/down selection for pad kpd_col0 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " KPD_COL0_PULLUDENABLE ,pullup/down enable for pad kpd_col0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " KPD_COL0_MUXMODE ,Functional multiplexing selection for pad kpd_col0 - . - . - . - ." "Select_kpd_col0,Select_kpd_col3,2,Select_gpio_174,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " KPD_COL5_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " KPD_COL5_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " KPD_COL5__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_col5 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " KPD_COL5__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_col5 - . - ." "0,1" textline " " bitfld.long 0x00 11. " KPD_COL5__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_col5 - . - ." "0,1" bitfld.long 0x00 10. " KPD_COL5__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_col5. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " KPD_COL5__OFFMODEENABLE ,OffMode mode override control for pad kpd_col5 - . - ." "0,1" textline " " bitfld.long 0x00 8. " KPD_COL5__INPUTENABLE ,Input enable value for pad kpd_col5 - . - ." "0,1" bitfld.long 0x00 4. " KPD_COL5__PULLTYPESELECT ,pullup/down selection for pad kpd_col5 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " KPD_COL5__PULLUDENABLE ,pullup/down enable for pad kpd_col5 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " KPD_COL5__MUXMODE ,Functional multiplexing selection for pad kpd_col5 - . - . - . - ." "Select_kpd_col5,Select_kpd_col2,2,Select_gpio_173,4,5,6,Select_safe_mode" group.long 0x184++0x3 line.long 0x00 "CONTROL_CORE_PAD0_KPD_COL1_PAD1_KPD_COL2,Register control for Pads kpd_col1 and kpd_col2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " KPD_COL2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " KPD_COL2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " KPD_COL2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_col2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " KPD_COL2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_col2 - . - ." "0,1" bitfld.long 0x00 27. " KPD_COL2__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_col2 - . - ." "0,1" bitfld.long 0x00 26. " KPD_COL2__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_col2. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " KPD_COL2__OFFMODEENABLE ,OffMode mode override control for pad kpd_col2 - . - ." "0,1" bitfld.long 0x00 24. " KPD_COL2__INPUTENABLE ,Input enable value for pad kpd_col2 - . - ." "0,1" bitfld.long 0x00 20. " KPD_COL2__PULLTYPESELECT ,pullup/down selection for pad kpd_col2 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " KPD_COL2__PULLUDENABLE ,pullup/down enable for pad kpd_col2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " KPD_COL2__MUXMODE ,Functional multiplexing selection for pad kpd_col2 - . - . - . - ." "Select_kpd_col2,Select_kpd_col5,2,Select_gpio_1,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " KPD_COL1__WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " KPD_COL1__WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " KPD_COL1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_col1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " KPD_COL1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_col1 - . - ." "0,1" textline " " bitfld.long 0x00 11. " KPD_COL1__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_col1 - . - ." "0,1" bitfld.long 0x00 10. " KPD_COL1__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_col1. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " KPD_COL1__OFFMODEENABLE ,OffMode mode override control for pad kpd_col1 - . - ." "0,1" textline " " bitfld.long 0x00 8. " KPD_COL1__INPUTENABLE ,Input enable value for pad kpd_col1 - . - ." "0,1" bitfld.long 0x00 4. " KPD_COL1__PULLTYPESELECT ,pullup/down selection for pad kpd_col1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " KPD_COL1__PULLUDENABLE ,pullup/down enable for pad kpd_col1 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " KPD_COL1__MUXMODE ,Functional multiplexing selection for pad kpd_col1 - . - . - . - ." "Select_kpd_col1,Select_kpd_col4,2,Select_gpio_0,4,5,6,Select_safe_mode" group.long 0x188++0x3 line.long 0x00 "CONTROL_CORE_PAD0_KPD_ROW3_PAD1_KPD_ROW4,Register control for Pads kpd_row3 and kpd_row4 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " KPD_ROW4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " KPD_ROW4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " KPD_ROW4__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_row4 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " KPD_ROW4__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_row4 - . - ." "0,1" bitfld.long 0x00 27. " KPD_ROW4__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_row4 - . - ." "0,1" bitfld.long 0x00 26. " KPD_ROW4__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_row4. This is an active low signal. - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " KPD_ROW4__OFFMODEENABLE ,OffMode mode override control for pad kpd_row4 - . - ." "0,1" bitfld.long 0x00 24. " KPD_ROW4_INPUTENABLE ,Input enable value for pad kpd_row4 - . - ." "0,1" bitfld.long 0x00 20. " KPD_ROW4_PULLTYPESELECT ,pullup/down selection for pad kpd_row4 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " KPD_ROW4_PULLUDENABLE ,pullup/down enable for pad kpd_row4 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " KPD_ROW4_MUXMODE ,Functional multiplexing selection for pad kpd_row4 - . - . - . - ." "Select_kpd_row4,Select_kpd_row1,2,Select_gpio_176,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " KPD_ROW3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " KPD_ROW3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " KPD_ROW3__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_row3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " KPD__ROW3__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_row3 - . - ." "0,1" textline " " bitfld.long 0x00 11. " KPD__ROW3__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_row3 - . - ." "0,1" bitfld.long 0x00 10. " KPD__ROW3__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_row3. This is an active low signal. - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " KPD__ROW3__OFFMODEENABLE ,OffMode mode override control for pad kpd_row3 - . - ." "0,1" textline " " bitfld.long 0x00 8. " KPD_ROW3_INPUTENABLE ,Input enable value for pad kpd_row3 - . - ." "0,1" bitfld.long 0x00 4. " KPD_ROW3_PULLTYPESELECT ,pullup/down selection for pad kpd_row3 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " KPD_ROW3_PULLUDENABLE ,pullup/down enable for pad kpd_row3 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " KPD_ROW3_MUXMODE ,Functional multiplexing selection for pad kpd_row3 - . - . - . - ." "Select_kpd_row3,Select_kpd_row0,2,Select_gpio_175,4,5,6,Select_safe_mode" group.long 0x18C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_KPD_ROW5_PAD1_KPD_ROW0,Register control for Pads kpd_row5 and kpd_row0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " KPD_ROW0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " KPD_ROW0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " KPD_ROW0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_row0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " KPD_ROW0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_row0 - . - ." "0,1" bitfld.long 0x00 27. " KPD_ROW0__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_row0 - . - ." "0,1" bitfld.long 0x00 26. " KPD_ROW0__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_row0. This is an active low signal. - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " KPD_ROW0__OFFMODEENABLE ,OffMode mode override control for pad kpd_row0 - . - ." "0,1" bitfld.long 0x00 24. " KPD_ROW0_INPUTENABLE ,Input enable value for pad kpd_row0 - . - ." "0,1" bitfld.long 0x00 20. " KPD_ROW0_PULLTYPESELECT ,pullup/down selection for pad kpd_row0 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " KPD_ROW0_PULLUDENABLE ,pullup/down enable for pad kpd_row0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " KPD_ROW0_MUXMODE ,Functional multiplexing selection for pad kpd_row0 - . - . - . - ." "Select_kpd_row0,Select_kpd_row3,2,Select_gpio_178,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " KPD_ROW5_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " KPD_ROW5_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " KPD_ROW5__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_row5 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " KPD__ROW5__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_row5 - . - ." "0,1" textline " " bitfld.long 0x00 11. " KPD__ROW5__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_row5 - . - ." "0,1" bitfld.long 0x00 10. " KPD__ROW5__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_row5. This is an active low signal. - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " KPD__ROW5__OFFMODEENABLE ,OffMode mode override control for pad kpd_row5 - . - ." "0,1" textline " " bitfld.long 0x00 8. " KPD_ROW5_INPUTENABLE ,Input enable value for pad kpd_row5 - . - ." "0,1" bitfld.long 0x00 4. " KPD_ROW5_PULLTYPESELECT ,pullup/down selection for pad kpd_row5 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " KPD_ROW5_PULLUDENABLE ,pullup/down enable for pad kpd_row5 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " KPD_ROW5_MUXMODE ,Functional multiplexing selection for pad kpd_row5 - . - . - . - ." "Select_kpd_row5,Select_kpd_row2,2,Select_gpio_177,4,5,6,Select_safe_mode" group.long 0x190++0x3 line.long 0x00 "CONTROL_CORE_PAD0_KPD_ROW1_PAD1_KPD_ROW2,Register control for Pads kpd_row1 and kpd_row2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " KPD_ROW2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " KPD_ROW2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " KPD_ROW2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_row2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " KPD_ROW2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_row2 - . - ." "0,1" bitfld.long 0x00 27. " KPD_ROW2__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_row2 - . - ." "0,1" bitfld.long 0x00 26. " KPD_ROW2__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_row2. This is an active low signal. - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " KPD_ROW2__OFFMODEENABLE ,OffMode mode override control for pad kpd_row2 - . - ." "0,1" bitfld.long 0x00 24. " KPD_ROW2_INPUTENABLE ,Input enable value for pad kpd_row2 - . - ." "0,1" bitfld.long 0x00 20. " KPD_ROW2_PULLTYPESELECT ,pullup/down selection for pad kpd_row2 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " KPD_ROW2_PULLUDENABLE ,pullup/down enable for pad kpd_row2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " KPD_ROW2_MUXMODE ,Functional multiplexing selection for pad kpd_row2 - . - . - . - ." "Select_kpd_row2,Select_kpd_row5,2,Select_gpio_3,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " KPD_ROW1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " KPD_ROW1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " KPD_ROW1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad kpd_row1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " KPD__ROW1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad kpd_row1 - . - ." "0,1" textline " " bitfld.long 0x00 11. " KPD__ROW1__OFFMODEOUTVALUE ,OffMode mode output value for pad kpd_row1 - . - ." "0,1" bitfld.long 0x00 10. " KPD__ROW1__OFFMODEOUTENABLE ,OffMode mode output enable value for pad kpd_row1. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " KPD__ROW1__OFFMODEENABLE ,OffMode mode override control for pad kpd_row1 - . - ." "0,1" textline " " bitfld.long 0x00 8. " KPD_ROW1_INPUTENABLE ,Input enable value for pad kpd_row1 - . - ." "0,1" bitfld.long 0x00 4. " KPD_ROW1_PULLTYPESELECT ,pullup/down selection for pad kpd_row1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " KPD_ROW1_PULLUDENABLE ,pullup/down enable for pad kpd_row1 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " KPD_ROW1_MUXMODE ,Functional multiplexing selection for pad kpd_row1 - . - . - . - ." "Select_kpd_row1,Select_kpd_row4,2,Select_gpio_2,4,5,6,Select_safe_mode" group.long 0x194++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBA0_OTG_CE_PAD1_USBA0_OTG_DP,Register control for Pads usba0_otg_ce and usba0_otg_dp Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USBA0_OTG_ ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " USBA0_OTG_ ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 20. " USBA0_OTG_DP__PULLTYPESELECT ,Pullup/down selection for pad usba0_otg_dp - . - ." "Pulldown_selected,Pullup_selected" textline " " bitfld.long 0x00 19. " USBA0_OTG__DP_PULLUDENABLE ,Pullup/down enable for pad usba0_otg_dp - . - ." "Pullup/down_disabled,Pullup/down_enabled" bitfld.long 0x00 16.--18. " USBA0_OTG_DP_MUXMODE ,Functional multiplexing selection for pad usba0_otg_dp - . - . - . - ." "Select_usba0_otg_dp,Select_uart3_rx_irrx,Select_uart2_rx,3,4,5,6,Select_safe_mode" bitfld.long 0x00 4. " USBA0_OTG__CE_PULLTYPESELECT ,Pullup/down selection for pad usba0_otg_ce - . - ." "Pulldown_selected,Pullup_selected" textline " " bitfld.long 0x00 3. " USBA0_OTG__CE_PULLUDENABLE ,Pullup/down enable for pad usba0_otg_ce - . - ." "Pullup/down_disabled,Pullup/down_enabled" group.long 0x198++0x3 line.long 0x00 "CONTROL_CORE_PAD0_USBA0_OTG_DM_PAD1_FREF_CLK1_OUT,Register control for Pads usba0_otg_dm and fref_clk1_out Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " FREF_CLK1_OUT_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " FREF_CLK1_OUT_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " FREF_CLK1__OUT_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad fref_clk1_out - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " FREF_CLK1__OUT_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad fref_clk1_out - . - ." "0,1" bitfld.long 0x00 27. " FREF_CLK1__OUT_OFFMODEOUTVALUE ,OffMode mode output value for pad fref_clk1_out - . - ." "0,1" bitfld.long 0x00 26. " FREF_CLK1__OUT_OFFMODEOUTENABLE ,OffMode mode output enable value for pad fref_clk1_out. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " FREF_CLK1_OUT_OFFMODEENABLE ,OffMode mode override control for pad fref_clk1_out - . - ." "0,1" bitfld.long 0x00 24. " FREF_CLK1_OUT_INPUTENABLE ,Input enable value for pad fref_clk1_out - . - ." "0,1" bitfld.long 0x00 20. " FREF_CLK1_OUT_PULLTYPESELECT ,Pullup/down selection for pad fref_clk1_out - . - ." "Pulldown_selected,Pullup_selected" textline " " bitfld.long 0x00 19. " FREF_CLK1_OUT_PULLUDENABLE ,Pullup/down enable for pad fref_clk1_out - . - ." "Pullup/down_disabled,Pullup/down_enabled" bitfld.long 0x00 16.--18. " FREF_CLK1_OUT_MUXMODE ,Functional multiplexing selection for pad fref_clk1_out - . - . - ." "Select_fref_clk1_out,1,2,Select_gpio_181,4,5,6,Select_safe_mode" bitfld.long 0x00 4. " USBA0_OTG__DM_PULLTYPESELECT ,Pullup/down selection for pad usba0_otg_dm - . - ." "Pulldown_selected,Pullup_selected" textline " " bitfld.long 0x00 3. " USBA0_OTG__DM_PULLUDENABLE ,Pullup/down enable for pad usba0_otg_dm - . - ." "Pullup/down_disabled,Pullup/down_enabled" bitfld.long 0x00 0.--2. " USBA0_OTG__DM_MUXMODE ,Functional multiplexing selection for pad usba0_otg_dm - . - . - . - ." "Select_usba0_otg_dm,Select_uart3_tx_irtx,Select_uart2_tx,3,4,5,6,Select_safe_mode" group.long 0x19C++0x3 line.long 0x00 "CONTROL_CORE_PAD0_FREF_CLK2_OUT_PAD1_SYS_NIRQ1,Register control for Pads fref_clk2_out and sys_nirq1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SYS_NIRQ1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SYS_NIRQ1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 24. " SYS_NIRQ1_INPUTENABLE ,Input enable value for pad sys_nirq1 - . - ." "0,1" textline " " bitfld.long 0x00 20. " SYS_NIRQ1_PULLTYPESELECT ,pullup/down selection for pad sys_nirq1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 19. " SYS_NIRQ1_PULLUDENABLE ,pullup/down enable for pad sys_nirq1 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SYS_NIRQ1_MUXMODE ,Functional multiplexing selection for pad sys_nirq1 - . - ." "Select_sys_nirq1,1,2,3,4,5,6,Select_safe_mode" textline " " bitfld.long 0x00 15. " FREF_CLK2_OUT_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " FREF_CLK2_OUT_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " FREF_CLK2__OUT_OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad fref_clk2_out - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 12. " FREF_CLK2__OUT_OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad fref_clk2_out - . - ." "0,1" bitfld.long 0x00 11. " FREF_CLK2__OUT_OFFMODEOUTVALUE ,OffMode mode output value for pad fref_clk2_out - . - ." "0,1" bitfld.long 0x00 10. " FREF_CLK2__OUT_OFFMODEOUTENABLE ,OffMode mode output enable value for pad fref_clk2_out. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 9. " FREF_CLK2__OUT_OFFMODEENABLE ,OffMode mode override control for pad fref_clk2_out - . - ." "0,1" bitfld.long 0x00 8. " FREF_CLK2__OUT_INPUTENABLE ,Input enable value for pad fref_clk2_out - . - ." "0,1" bitfld.long 0x00 4. " FREF_CLK2__OUT_PULLTYPESELECT ,pullup/down selection for pad fref_clk2_out - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 3. " FREF_CLK2_OUT_PULLUDENABLE ,pullup/down enable for pad fref_clk2_out - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " FREF_CLK2_OUT_MUXMODE ,Functional multiplexing selection for pad fref_clk2_out - . - . - ." "Select_fref_clk2_out,1,2,Select_gpio_182,4,5,6,Select_safe_mode" group.long 0x1A0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SYS_NIRQ2_PAD1_SYS_BOOT0,Register control for Pads sys_nirq2 and sys_boot0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SYS_BOOT0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SYS_BOOT0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SYS_BOOT0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sys_boot0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SYS_BOOT0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sys_boot0 - . - ." "0,1" bitfld.long 0x00 27. " SYS_BOOT0__OFFMODEOUTVALUE ,OffMode mode output value for pad sys_boot0 - . - ." "0,1" bitfld.long 0x00 26. " SYS_BOOT0__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sys_boot0. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SYS_BOOT0_OFFMODEENABLE ,OffMode mode override control for pad sys_boot0 - . - ." "0,1" bitfld.long 0x00 24. " SYS_BOOT0_INPUTENABLE ,Input enable value for pad sys_boot0 - . - ." "0,1" bitfld.long 0x00 20. " SYS_BOOT0_PULLTYPESELECT ,pullup/down selection for pad sys_boot0 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SYS_BOOT0_PULLUDENABLE ,pullup/down enable for pad sys_boot0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SYS_BOOT0_MUXMODE ,Functional multiplexing selection for pad sys_boot0 - . - . - ." "Select_sys_boot0,1,2,Select_gpio_184,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " SYS_NIRQ2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SYS_NIRQ2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SYS_NIRQ2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sys_nirq2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SYS_NIRQ2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sys_nirq2 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SYS_NIRQ2__OFFMODEOUTVALUE ,OffMode mode output value for pad sys_nirq2 - . - ." "0,1" bitfld.long 0x00 10. " SYS_NIRQ2__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sys_nirq2. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SYS_NIRQ2_OFFMODEENABLE ,OffMode mode override control for pad sys_nirq2 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SYS_NIRQ2_INPUTENABLE ,Input enable value for pad sys_nirq2 - . - ." "0,1" bitfld.long 0x00 4. " SYS_NIRQ2_PULLTYPESELECT ,pullup/down selection for pad sys_nirq2 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SYS_NIRQ2_PULLUDENABLE ,pullup/down enable for pad sys_nirq2 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SYS_NIRQ2_MUXMODE ,Functional multiplexing selection for pad sys_nirq2 - . - . - ." "Select_sys_nirq2,1,2,Select_gpio_183,4,5,6,Select_safe_mode" group.long 0x1A4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SYS_BOOT1_PAD1_SYS_BOOT2,Register control for Pads sys_boot1 and sys_boot2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SYS_BOOT2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SYS_BOOT2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SYS_BOOT2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sys_boot2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SYS_BOOT2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sys_boot2 - . - ." "0,1" bitfld.long 0x00 27. " SYS_BOOT2__OFFMODEOUTVALUE ,OffMode mode output value for pad sys_boot2 - . - ." "0,1" bitfld.long 0x00 26. " SYS_BOOT2__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sys_boot2. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SYS_BOOT2_OFFMODEENABLE ,OffMode mode override control for pad sys_boot2 - . - ." "0,1" bitfld.long 0x00 24. " SYS_BOOT2_INPUTENABLE ,Input enable value for pad sys_boot2 - . - ." "0,1" bitfld.long 0x00 20. " SYS_BOOT2_PULLTYPESELECT ,pullup/down selection for pad sys_boot2 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SYS_BOOT2_PULLUDENABLE ,pullup/down enable for pad sys_boot2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SYS_BOOT2_MUXMODE ,Functional multiplexing selection for pad sys_boot2 - . - . - ." "Select_sys_boot2,1,2,Select_gpio_186,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " SYS_BOOT1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SYS_BOOT1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SYS_BOOT1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sys_boot1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SYS_BOOT1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sys_boot1 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SYS_BOOT1__OFFMODEOUTVALUE ,OffMode mode output value for pad sys_boot1 - . - ." "0,1" bitfld.long 0x00 10. " SYS_BOOT1__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sys_boot1. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SYS_BOOT1_OFFMODEENABLE ,OffMode mode override control for pad sys_boot1 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SYS_BOOT1_INPUTENABLE ,Input enable value for pad sys_boot1 - . - ." "0,1" bitfld.long 0x00 4. " SYS_BOOT1_PULLTYPESELECT ,pullup/down selection for pad sys_boot1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SYS_BOOT1_PULLUDENABLE ,pullup/down enable for pad sys_boot1 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SYS_BOOT1_MUXMODE ,Functional multiplexing selection for pad sys_boot1 - . - . - ." "Select_sys_boot1,1,2,Select_gpio_185,4,5,6,Select_safe_mode" group.long 0x1A8++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SYS_BOOT3_PAD1_SYS_BOOT4,Register control for Pads sys_boot3 and sys_boot4 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SYS_BOOT4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " SYS_BOOT4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " SYS_BOOT4__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sys_boot4 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " SYS_BOOT4__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sys_boot4 - . - ." "0,1" bitfld.long 0x00 27. " SYS_BOOT4_OFFMODEOUTVALUE ,OffMode mode output value for pad sys_boot4 - . - ." "0,1" bitfld.long 0x00 26. " SYS_BOOT4_OFFMODEOUTENABLE ,OffMode mode output enable value for pad sys_boot4. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " SYS_BOOT4_OFFMODEENABLE ,OffMode mode override control for pad sys_boot4 - . - ." "0,1" bitfld.long 0x00 24. " SYS_BOOT4_INPUTENABLE ,Input enable value for pad sys_boot4 - . - ." "0,1" bitfld.long 0x00 20. " SYS_BOOT4_PULLTYPESELECT ,pullup/down selection for pad sys_boot4 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " SYS_BOOT4_PULLUDENABLE ,pullup/down enable for pad sys_boot4 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " SYS_BOOT4_MUXMODE ,Functional multiplexing selection for pad sys_boot4 - . - . - ." "Select_sys_boot4,1,2,Select_gpio_188,4,5,6,Select_safe_mode" bitfld.long 0x00 15. " SYS_BOOT3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SYS_BOOT3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SYS_BOOT3__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sys_boot3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SYS_BOOT3__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sys_boot3 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SYS_BOOT3__OFFMODEOUTVALUE ,OffMode mode output value for pad sys_boot3 - . - ." "0,1" bitfld.long 0x00 10. " SYS_BOOT3__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sys_boot3. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SYS_BOOT3_OFFMODEENABLE ,OffMode mode override control for pad sys_boot3 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SYS_BOOT3_INPUTENABLE ,Input enable value for pad sys_boot3 - . - ." "0,1" bitfld.long 0x00 4. " SYS_BOOT3_PULLTYPESELECT ,pullup/down selection for pad sys_boot3 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SYS_BOOT3_PULLUDENABLE ,pullup/down enable for pad sys_boot3 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SYS_BOOT3_MUXMODE ,Functional multiplexing selection for pad sys_boot3 - . - . - ." "Select_sys_boot3,1,2,Select_gpio_187,4,5,6,Select_safe_mode" group.long 0x1AC++0x3 line.long 0x00 "CONTROL_CORE_PAD0_SYS_BOOT5_PAD1_DPM_EMU0,Register control for Pads sys_boot5 and dpm_emu0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU0_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU0_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU0__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu0 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU0__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu0 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU0__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu0 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU0__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu0. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU0__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu0 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU0_INPUTENABLE ,Input enable value for pad dpm_emu0 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU0_PULLTYPESELECT ,pullup/down selection for pad dpm_emu0 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU0_PULLUDENABLE ,pullup/down enable for pad dpm_emu0 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU0_MUXMODE ,Functional multiplexing selection for pad dpm_emu0 - . - . - . - ." "Select_dpm_emu0,1,2,Select_gpio_11,4,5,Select_hw_dbg0,Select_safe_mode" bitfld.long 0x00 15. " SYS_BOOT5_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " SYS_BOOT5_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " SYS_BOOT5__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad sys_boot5 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " SYS_BOOT5__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad sys_boot5 - . - ." "0,1" textline " " bitfld.long 0x00 11. " SYS_BOOT5__OFFMODEOUTVALUE ,OffMode mode output value for pad sys_boot5 - . - ." "0,1" bitfld.long 0x00 10. " SYS_BOOT5__OFFMODEOUTENABLE ,OffMode mode output enable value for pad sys_boot5. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " SYS_BOOT5_OFFMODEENABLE ,OffMode mode override control for pad sys_boot5 - . - ." "0,1" textline " " bitfld.long 0x00 8. " SYS_BOOT5_INPUTENABLE ,Input enable value for pad sys_boot5 - . - ." "0,1" bitfld.long 0x00 4. " SYS_BOOT5_PULLTYPESELECT ,pullup/down selection for pad sys_boot5 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " SYS_BOOT5_PULLUDENABLE ,pullup/down enable for pad sys_boot5 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " SYS_BOOT5_MUXMODE ,Functional multiplexing selection for pad sys_boot5 - . - . - ." "Select_sys_boot5,1,2,Select_gpio_189,4,5,6,Select_safe_mode" group.long 0x1B0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU1_PAD1_DPM_EMU2,Register control for Pads dpm_emu1 and dpm_emu2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU2_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU2_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU2__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu2 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU2__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu2 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU2__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu2 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU2__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu2. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU2__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu2 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU2_INPUTENABLE ,Input enable value for pad dpm_emu2 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU2_PULLTYPESELECT ,pullup/down selection for pad dpm_emu2 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU2_PULLUDENABLE ,pullup/down enable for pad dpm_emu2 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU2_MUXMODE ,Functional multiplexing selection for pad dpm_emu2 - . - . - . - . - . - ." "Select_dpm_emu2,Select_usba0_ulpiphy_clk,2,Select_gpio_13,4,Select_dispc2_fid,Select_hw_dbg2,Select_safe_mode" bitfld.long 0x00 15. " DPM_EMU1_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " DPM_EMU1_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU1__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu1 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " DPM_EMU1__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu1 - . - ." "0,1" textline " " bitfld.long 0x00 11. " DPM_EMU1__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu1 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU1__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu1. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " DPM_EMU1__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu1 - . - ." "0,1" textline " " bitfld.long 0x00 8. " DPM_EMU1_INPUTENABLE ,Input enable value for pad dpm_emu1 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU1__PULLTYPESELECT ,pullup/down selection for pad dpm_emu1 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " DPM_EMU1_PULLUDENABLE ,pullup/down enable for pad dpm_emu1 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " DPM_EMU1_MUXMODE ,Functional multiplexing selection for pad dpm_emu1 - . - . - . - ." "Select_dpm_emu1,1,2,Select_gpio_12,4,5,Select_hw_dbg1,Select_safe_mode" group.long 0x1B4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU3_PAD1_DPM_EMU4,Register control for Pads dpm_emu3 and dpm_emu4 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU4_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU4_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU4__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu4 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU4__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu4 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU4__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu4 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU4__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu4. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU4_OFFMODEENABLE ,OffMode mode override control for pad dpm_emu4 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU4_INPUTENABLE ,Input enable value for pad dpm_emu4 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU4_PULLTYPESELECT ,pullup/down selection for pad dpm_emu4 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU4_PULLUDENABLE ,pullup/down enable for pad dpm_emu4 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU4_MUXMODE ,Functional multiplexing selection for pad dpm_emu4 - . - . - . - . - . - . - ." "Select_dpm_emu4,Select_usba0_ulpiphy_dir,2,Select_gpio_15,Select_rfbi_data9,Select_dispc2_data9,Select_hw_dbg4,Select_safe_mode" bitfld.long 0x00 15. " DPM_EMU3_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " DPM_EMU3_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU3__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu3 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " DPM_EMU3__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu3 - . - ." "0,1" textline " " bitfld.long 0x00 11. " DPM_EMU3__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu3 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU3__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu3. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " DPM_EMU3__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu3 - . - ." "0,1" textline " " bitfld.long 0x00 8. " DPM_EMU3_INPUTENABLE ,Input enable value for pad dpm_emu3 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU3_PULLTYPESELECT ,pullup/down selection for pad dpm_emu3 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " DPM_EMU3_PULLUDENABLE ,pullup/down enable for pad dpm_emu3 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " DPM_EMU3_MUXMODE ,Functional multiplexing selection for pad dpm_emu3 - . - . - . - . - . - . - ." "Select_dpm_emu3,Select_usba0_ulpiphy_stp,2,Select_gpio_14,Select_rfbi_data10,Select_dispc2_data10,Select_hw_dbg3,Select_safe_mode" group.long 0x1B8++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU5_PAD1_DPM_EMU6,Register control for Pads dpm_emu5 and dpm_emu6 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU6_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU6_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU6__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu6 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU6__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu6 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU6__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu6 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU6__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu6. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU6__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu6 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU6_INPUTENABLE ,Input enable value for pad dpm_emu6 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU6_PULLTYPESELECT ,pullup/down selection for pad dpm_emu6 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU6_PULLUDENABLE ,pullup/down enable for pad dpm_emu6 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU6_MUXMODE ,Functional multiplexing selection for pad dpm_emu6 - . - . - . - . - . - . - . - ." "Select_dpm_emu6,Select_usba0_ulpiphy_dat0,Select_uart3_tx_irtx,Select_gpio_17,Select_rfbi_hsync0,Select_dispc2_data17,Select_hw_dbg6,Select_safe_mode" bitfld.long 0x00 15. " DPM_EMU5_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " DPM_EMU5_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU5__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu5 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " DPM_EMU5__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu5 - . - ." "0,1" textline " " bitfld.long 0x00 11. " DPM_EMU5__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu5 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU5__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu5. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " DPM_EMU5__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu5 - . - ." "0,1" textline " " bitfld.long 0x00 8. " DPM_EMU5_INPUTENABLE ,Input enable value for pad dpm_emu5 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU5_PULLTYPESELECT ,pullup/down selection for pad dpm_emu5 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " DPM_EMU5_PULLUDENABLE ,pullup/down enable for pad dpm_emu5 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " DPM_EMU5_MUXMODE ,Functional multiplexing selection for pad dpm_emu5 - . - . - . - . - . - . - ." "Select_dpm_emu5,Select_usba0_ulpiphy_nxt,2,Select_gpio_16,Select_rfbi_te_vsync0,Select_dispc2_data16,Select_hw_dbg5,Select_safe_mode" group.long 0x1BC++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU7_PAD1_DPM_EMU8,Register control for Pads dpm_emu7 and dpm_emu8 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU8_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU8_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU8__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu8 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU8__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu8 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU8__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu8 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU8__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu8. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU8_OFFMODEENABLE ,OffMode mode override control for pad dpm_emu8 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU8_INPUTENABLE ,Input enable value for pad dpm_emu8 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU8_PULLTYPESELECT ,pullup/down selection for pad dpm_emu8 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU8_PULLUDENABLE ,pullup/down enable for pad dpm_emu8 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU8_MUXMODE ,Functional multiplexing selection for pad dpm_emu8 - . - . - . - . - . - . - . - ." "Select_dpm_emu8,Select_usba0_ulpiphy_dat2,Select_uart3_rts_sd,Select_gpio_19,Select_rfbi_re,Select_dispc2_pclk,Select_hw_dbg8,Select_safe_mode" bitfld.long 0x00 15. " DPM_EMU7_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " DPM_EMU7_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU7__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu7 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " DPM_EMU7__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu7 - . - ." "0,1" textline " " bitfld.long 0x00 11. " DPM_EMU7__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu7 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU7__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu7. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " DPM_EMU7_OFFMODEENABLE ,OffMode mode override control for pad dpm_emu7 - . - ." "0,1" textline " " bitfld.long 0x00 8. " DPM_EMU7_INPUTENABLE ,Input enable value for pad dpm_emu7 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU7_PULLTYPESELECT ,pullup/down selection for pad dpm_emu7 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " DPM_EMU7_PULLUDENABLE ,pullup/down enable for pad dpm_emu7 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " DPM_EMU7_MUXMODE ,Functional multiplexing selection for pad dpm_emu7 - . - . - . - . - . - . - . - ." "Select_dpm_emu7,Select_usba0_ulpiphy_dat1,Select_uart3_rx_irrx,Select_gpio_18,Select_rfbi_cs0,Select_dispc2_hsync,Select_hw_dbg7,Select_safe_mode" group.long 0x1C0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU9_PAD1_DPM_EMU10,Register control for Pads dpm_emu9 and dpm_emu10 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU10_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU10_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU10__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu10 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU10__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu10 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU10__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu10 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU10__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu10. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU10__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu10 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU10_INPUTENABLE ,Input enable value for pad dpm_emu10 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU10_PULLTYPESELECT ,pullup/down selection for pad dpm_emu10 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU10_PULLUDENABLE ,pullup/down enable for pad dpm_emu10 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU10_MUXMODE ,Functional multiplexing selection for pad dpm_emu10 - . - . - . - . - . - . - ." "Select_dpm_emu10,Select_usba0_ulpiphy_dat4,2,Select_gpio_21,Select_rfbi_a0,Select_dispc2_de,Select_hw_dbg10,Select_safe_mode" bitfld.long 0x00 15. " DPM_EMU9_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " DPM_EMU9_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU9__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu9 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " DPM_EMU9__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu9 - . - ." "0,1" textline " " bitfld.long 0x00 11. " DPM_EMU9__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu9 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU9__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu9. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " DPM_EMU9__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu9 - . - ." "0,1" textline " " bitfld.long 0x00 8. " DPM_EMU9_INPUTENABLE ,Input enable value for pad dpm_emu9 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU9_PULLTYPESELECT ,pullup/down selection for pad dpm_emu9 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " DPM_EMU9_PULLUDENABLE ,pullup/down enable for pad dpm_emu9 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " DPM_EMU9_MUXMODE ,Functional multiplexing selection for pad dpm_emu9 - . - . - . - . - . - . - . - ." "Select_dpm_emu9,Select_usba0_ulpiphy_dat3,Select_uart3_cts_rctx,Select_gpio_20,Select_rfbi_we,Select_dispc2_vsync,Select_hw_dbg9,Select_safe_mode" group.long 0x1C4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU11_PAD1_DPM_EMU12,Register control for Pads dpm_emu11 and dpm_emu12 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU12_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU12_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU12__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu12 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU12__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu12 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU12__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu12 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU12__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu12. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU12__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu12 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU12_INPUTENABLE ,Input enable value for pad dpm_emu12 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU12_PULLTYPESELECT ,pullup/down selection for pad dpm_emu12 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU12_PULLUDENABLE ,pullup/down enable for pad dpm_emu12 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU12_MUXMODE ,Functional multiplexing selection for pad dpm_emu12 - . - . - . - . - . - . - ." "Select_dpm_emu12,Select_usba0_ulpiphy_dat6,2,Select_gpio_23,Select_rfbi_data7,Select_dispc2_data7,Select_hw_dbg12,Select_safe_mode" bitfld.long 0x00 15. " DPM_EMU11_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " DPM_EMU11_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU11__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu11 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " DPM_EMU11__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu11 - . - ." "0,1" textline " " bitfld.long 0x00 11. " DPM_EMU11__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu11 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU11__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu11. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " DPM_EMU11__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu11 - . - ." "0,1" textline " " bitfld.long 0x00 8. " DPM_EMU11_INPUTENABLE ,Input enable value for pad dpm_emu11 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU11_PULLTYPESELECT ,pullup/down selection for pad dpm_emu11 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " DPM_EMU11_PULLUDENABLE ,pullup/down enable for pad dpm_emu11 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " DPM_EMU11_MUXMODE ,Functional multiplexing selection for pad dpm_emu11 - . - . - . - . - . - . - ." "Select_dpm_emu11,Select_usba0_ulpiphy_dat5,2,Select_gpio_22,Select_rfbi_data8,Select_dispc2_data8,Select_hw_dbg11,Select_safe_mode" group.long 0x1C8++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU13_PAD1_DPM_EMU14,Register control for Pads dpm_emu13 and dpm_emu14 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU14_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU14_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU14__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu14 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU14__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu14 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU14__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu14 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU14__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu14. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU14__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu14 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU14_INPUTENABLE ,Input enable value for pad dpm_emu14 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU14_PULLTYPESELECT ,pullup/down selection for pad dpm_emu14 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU14_PULLUDENABLE ,pullup/down enable for pad dpm_emu14 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU14_MUXMODE ,Functional multiplexing selection for pad dpm_emu14 - . - . - . - . - . - . - . - ." "Select_dpm_emu14,Reserved,Select_uart1_rx,Select_gpio_25,Select_rfbi_data5,Select_dispc2_data5,Select_hw_dbg14,Select_safe_mode" bitfld.long 0x00 15. " DPM_EMU13_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " DPM_EMU13_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU13__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu13 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " DPM_EMU13__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu13 - . - ." "0,1" textline " " bitfld.long 0x00 11. " DPM_EMU13__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu13 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU13__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu13. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " DPM_EMU13__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu13 - . - ." "0,1" textline " " bitfld.long 0x00 8. " DPM_EMU13_INPUTENABLE ,Input enable value for pad dpm_emu13 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU13_PULLTYPESELECT ,pullup/down selection for pad dpm_emu13 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " DPM_EMU13_PULLUDENABLE ,pullup/down enable for pad dpm_emu13 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " DPM_EMU13_MUXMODE ,Functional multiplexing selection for pad dpm_emu13 - . - . - . - . - . - . - ." "Select_dpm_emu13,Select_usba0_ulpiphy_dat7,2,Select_gpio_24,Select_rfbi_data6,Select_dispc2_data6,Select_hw_dbg13,Select_safe_mode" group.long 0x1CC++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU15_PAD1_DPM_EMU16,Register control for Pads dpm_emu15 and dpm_emu16 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU16_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU16_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU16__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu16 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU16__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu16 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU16__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu16 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU16__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu16. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU16__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu16 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU16_INPUTENABLE ,Input enable value for pad dpm_emu16 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU16_PULLTYPESELECT ,pullup/down selection for pad dpm_emu16 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU16_PULLUDENABLE ,pullup/down enable for pad dpm_emu16 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU16_MUXMODE ,Functional multiplexing selection for pad dpm_emu16 - . - . - . - . - . - . - . - ." "Select_dpm_emu16,Select_dmtimer8_pwm_evt,Select_dsi1_te0,Select_gpio_27,Select_rfbi_data3,Select_dispc2_data3,Select_hw_dbg16,Select_safe_mode" bitfld.long 0x00 15. " DPM_EMU15_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " DPM_EMU15_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU15__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu15 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " DPM_EMU15__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu15 - . - ." "0,1" textline " " bitfld.long 0x00 11. " DPM_EMU15__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu15 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU15__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu15. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " DPM_EMU15__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu15 - . - ." "0,1" textline " " bitfld.long 0x00 8. " DPM_EMU15_INPUTENABLE ,Input enable value for pad dpm_emu15 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU15_PULLTYPESELECT ,pullup/down selection for pad dpm_emu15 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " DPM_EMU15_PULLUDENABLE ,pullup/down enable for pad dpm_emu15 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " DPM_EMU15_MUXMODE ,Functional multiplexing selection for pad dpm_emu15 - . - . - . - . - . - . - ." "Select_dpm_emu15,Reserved,2,Select_gpio_26,Select_rfbi_data4,Select_dispc2_data4,Select_hw_dbg15,Select_safe_mode" group.long 0x1D0++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU17_PAD1_DPM_EMU18,Register control for Pads dpm_emu17 and dpm_emu18 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU18_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU18_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU18__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu18 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 28. " DPM_EMU18__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu18 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU18__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu18 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU18__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu18. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 25. " DPM_EMU18__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu18 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU18_INPUTENABLE ,Input enable value for pad dpm_emu18 - . - ." "0,1" bitfld.long 0x00 20. " DPM_EMU18_PULLTYPESELECT ,pullup/down selection for pad dpm_emu18 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 19. " DPM_EMU18_PULLUDENABLE ,pullup/down enable for pad dpm_emu18 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 16.--18. " DPM_EMU18_MUXMODE ,Functional multiplexing selection for pad dpm_emu18 - . - . - . - . - . - . - . - ." "Select_dpm_emu18,Select_dmtimer10_pwm_evt,Select_dsi2_te0,Select_gpio_190,Select_rfbi_data1,Select_dispc2_data1,Select_hw_dbg18,Select_safe_mode" bitfld.long 0x00 15. " DPM_EMU17_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" textline " " bitfld.long 0x00 14. " DPM_EMU17_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU17__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu17 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" bitfld.long 0x00 12. " DPM_EMU17__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu17 - . - ." "0,1" textline " " bitfld.long 0x00 11. " DPM_EMU17__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu17 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU17__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu17. This is an active low signal - . - ." "Output_enable,Output_disable" bitfld.long 0x00 9. " DPM_EMU17__OFFMODEENABLE ,OffMode mode override control for pad dpm_emu17 - . - ." "0,1" textline " " bitfld.long 0x00 8. " DPM_EMU17_INPUTENABLE ,Input enable value for pad dpm_emu17 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU17_PULLTYPESELECT ,pullup/down selection for pad dpm_emu17 - . - ." "pulldown_selected,pullup_selected" bitfld.long 0x00 3. " DPM_EMU17_PULLUDENABLE ,pullup/down enable for pad dpm_emu17 - . - ." "pullup/down_disabled,pullup/down_enabled" textline " " bitfld.long 0x00 0.--2. " DPM_EMU17_MUXMODE ,Functional multiplexing selection for pad dpm_emu17 - . - . - . - . - . - . - . - ." "Select_dpm_emu17,Select_dmtimer9_pwm_evt,Select_dsi1_te1,Select_gpio_28,Select_rfbi_data2,Select_dispc2_data2,Select_hw_dbg17,Select_safe_mode" group.long 0x1D4++0x3 line.long 0x00 "CONTROL_CORE_PAD0_DPM_EMU19,Register control for Pad dpm_emu19 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 15. " DPM_EMU19_WAKEUPEVENT ,Pad_x wake-up event status latched in the IO - . - ." "0,1" bitfld.long 0x00 14. " DPM_EMU19_WAKEUPENABLE ,Input pad wake-up enable (and OFF mode input enable value) - . - ." "0,1" bitfld.long 0x00 13. " DPM_EMU19__OFFMODEPULLTYPESELECT ,OffMode mode pullup/down selection for pad dpm_emu19 - . - ." "Offmode_pulldown_selected,Offmode_pullup_selected" textline " " bitfld.long 0x00 12. " DPM_EMU19__OFFMODEPULLUDENABLE ,OffMode mode pullup/down enable for pad dpm_emu19 - . - ." "0,1" bitfld.long 0x00 11. " DPM_EMU19__OFFMODEOUTVALUE ,OffMode mode output value for pad dpm_emu19 - . - ." "0,1" bitfld.long 0x00 10. " DPM_EMU19__OFFMODEOUTENABLE ,OffMode mode output enable value for pad dpm_emu19. This is an active low signal - . - ." "Output_enable,Output_disable" textline " " bitfld.long 0x00 9. " DPM_EMU19_OFFMODEENABLE ,OffMode mode override control for pad dpm_emu19 - . - ." "0,1" bitfld.long 0x00 8. " DPM_EMU19_INPUTENABLE ,Input enable value for pad dpm_emu19 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU19_PULLTYPESELECT ,pullup/down selection for pad dpm_emu19 - . - ." "pulldown_selected,pullup_selected" textline " " bitfld.long 0x00 3. " DPM_EMU19_PULLUDENABLE ,pullup/down enable for pad dpm_emu19 - . - ." "pullup/down_disabled,pullup/down_enabled" bitfld.long 0x00 0.--2. " DPM_EMU19_MUXMODE ,Functional multiplexing selection for pad dpm_emu19 - . - . - . - . - . - . - . - ." "Select_dpm_emu19,Select_dmtimer11_pwm_evt,Select_dsi2_te1,Select_gpio_191,Select_rfbi_data0,Select_dispc2_data0,Select_hw_dbg19,Select_safe_mode" rgroup.long 0x1D8++0x3 line.long 0x00 "CONTROL_PADCONF_WAKEUPEVENT_0,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " GPMC_CLK_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_clk - . - ." "0,1" bitfld.long 0x00 30. " GPMC_NWP_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_nwp - . - ." "0,1" bitfld.long 0x00 29. " GPMC_NCS3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ncs3 - . - ." "0,1" textline " " bitfld.long 0x00 28. " GPMC_NCS2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ncs2 - . - ." "0,1" bitfld.long 0x00 27. " GPMC_NCS1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ncs1 - . - ." "0,1" bitfld.long 0x00 26. " GPMC_NCS0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ncs0 - . - ." "0,1" textline " " bitfld.long 0x00 25. " GPMC_A25_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a25 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_A24_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a24 - . - ." "0,1" bitfld.long 0x00 23. " GPMC_A23_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a23 - . - ." "0,1" textline " " bitfld.long 0x00 22. " GPMC_A22_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a22 - . - ." "0,1" bitfld.long 0x00 21. " GPMC_A21_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a21 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_A20_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a20 - . - ." "0,1" textline " " bitfld.long 0x00 19. " GPMC_A19_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a19 - . - ." "0,1" bitfld.long 0x00 18. " GPMC_A18_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a18 - . - ." "0,1" bitfld.long 0x00 17. " GPMC_A17_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a17 - . - ." "0,1" textline " " bitfld.long 0x00 16. " GPMC_A16_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_a16 - . - ." "0,1" bitfld.long 0x00 15. " GPMC_AD15_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad15 - . - ." "0,1" bitfld.long 0x00 14. " GPMC_AD14_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad14 - . - ." "0,1" textline " " bitfld.long 0x00 13. " GPMC_AD13_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad13 - . - ." "0,1" bitfld.long 0x00 12. " GPMC_AD12_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad12 - . - ." "0,1" bitfld.long 0x00 11. " GPMC_AD11_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad11 - . - ." "0,1" textline " " bitfld.long 0x00 10. " GPMC_AD10_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad10 - . - ." "0,1" bitfld.long 0x00 9. " GPMC_AD9_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad9 - . - ." "0,1" bitfld.long 0x00 8. " GPMC_AD8_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad8 - . - ." "0,1" textline " " bitfld.long 0x00 7. " GPMC_AD7_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad7 - . - ." "0,1" bitfld.long 0x00 6. " GPMC_AD6_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad6 - . - ." "0,1" bitfld.long 0x00 5. " GPMC_AD5_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad5 - . - ." "0,1" textline " " bitfld.long 0x00 4. " GPMC_AD4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad4 - . - ." "0,1" bitfld.long 0x00 3. " GPMC_AD3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad3 - . - ." "0,1" bitfld.long 0x00 2. " GPMC_AD2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad2 - . - ." "0,1" textline " " bitfld.long 0x00 1. " GPMC_AD1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad1 - . - ." "0,1" bitfld.long 0x00 0. " GPMC_AD0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ad0 - . - ." "0,1" rgroup.long 0x1DC++0x3 line.long 0x00 "CONTROL_PADCONF_WAKEUPEVENT_1,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CAM_STROBE_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad cam_strobe - . - ." "0,1" bitfld.long 0x00 30. " CAM_SHUTTER_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad cam_shutter - . - ." "0,1" bitfld.long 0x00 29. " CSI22_DY1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi22_dy1 - . - ." "0,1" textline " " bitfld.long 0x00 28. " CSI22_DX1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi22_dx1 - . - ." "0,1" bitfld.long 0x00 27. " CSI22_DY0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi22_dy0 - . - ." "0,1" bitfld.long 0x00 26. " CSI22_DX0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi22_dx0 - . - ." "0,1" textline " " bitfld.long 0x00 25. " CSI21_DY4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dy4 - . - ." "0,1" bitfld.long 0x00 24. " CSI21_DX4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dx4 - . - ." "0,1" bitfld.long 0x00 23. " CSI21_DY3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dy3 - . - ." "0,1" textline " " bitfld.long 0x00 22. " CSI21_DX3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dx3 - . - ." "0,1" bitfld.long 0x00 21. " CSI21_DY2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dy2 - . - ." "0,1" bitfld.long 0x00 20. " CSI21_DX2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dx2 - . - ." "0,1" textline " " bitfld.long 0x00 19. " CSI21_DY1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dy1 - . - ." "0,1" bitfld.long 0x00 18. " CSI21_DX1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dx1 - . - ." "0,1" bitfld.long 0x00 17. " CSI21_DY0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dy0 - . - ." "0,1" textline " " bitfld.long 0x00 16. " CSI21_DX0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad csi21_dx0 - . - ." "0,1" bitfld.long 0x00 15. " GPIO66_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpio66 - . - ." "0,1" bitfld.long 0x00 14. " GPIO65_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpio65 - . - ." "0,1" textline " " bitfld.long 0x00 13. " GPIO64_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpio64 - . - ." "0,1" bitfld.long 0x00 12. " GPIO63_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpio63 - . - ." "0,1" bitfld.long 0x00 11. " GPMC_NCS7_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ncs7 - . - ." "0,1" textline " " bitfld.long 0x00 10. " GPMC_NCS6_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ncs6 - . - ." "0,1" bitfld.long 0x00 9. " GPMC_NCS5_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ncs5 - . - ." "0,1" bitfld.long 0x00 8. " GPMC_NCS4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_ncs4 - . - ." "0,1" textline " " bitfld.long 0x00 7. " GPMC_WAIT2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_wait2 - . - ." "0,1" bitfld.long 0x00 6. " GPMC_WAIT1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_wait1 - . - ." "0,1" bitfld.long 0x00 5. " GPMC_WAIT0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_wait0 - . - ." "0,1" textline " " bitfld.long 0x00 4. " GPMC_NBE1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_nbe1 - . - ." "0,1" bitfld.long 0x00 3. " GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_nbe0_cle - . - ." "0,1" bitfld.long 0x00 2. " GPMC_NWE_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_nwe - . - ." "0,1" textline " " bitfld.long 0x00 1. " GPMC_NOE_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_noe - . - ." "0,1" bitfld.long 0x00 0. " GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad gpmc_nadv_ale - . - ." "0,1" rgroup.long 0x1E0++0x3 line.long 0x00 "CONTROL_PADCONF_WAKEUPEVENT_2,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_mcbsp1_clkx - . - ." "0,1" bitfld.long 0x00 30. " ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_mcbsp2_fsx - . - ." "0,1" bitfld.long 0x00 29. " ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_mcbsp2_dx - . - ." "0,1" textline " " bitfld.long 0x00 28. " ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_mcbsp2_dr - . - ." "0,1" bitfld.long 0x00 27. " ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_mcbsp2_clkx - . - ." "0,1" bitfld.long 0x00 26. " SDMMC1_DAT7_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_dat7 - . - ." "0,1" textline " " bitfld.long 0x00 25. " SDMMC1_DAT6_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_dat6 - . - ." "0,1" bitfld.long 0x00 24. " SDMMC1_DAT5_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_dat5 - . - ." "0,1" bitfld.long 0x00 23. " SDMMC1_DAT4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_dat4 - . - ." "0,1" textline " " bitfld.long 0x00 22. " SDMMC1_DAT3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_dat3 - . - ." "0,1" bitfld.long 0x00 21. " SDMMC1_DAT2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_dat2 - . - ." "0,1" bitfld.long 0x00 20. " SDMMC1_DAT1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_dat1 - . - ." "0,1" textline " " bitfld.long 0x00 19. " SDMMC1_DAT0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_dat0 - . - ." "0,1" bitfld.long 0x00 18. " SDMMC1_CMD_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_cmd - . - ." "0,1" bitfld.long 0x00 17. " SDMMC1_CLK_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc1_clk - . - ." "0,1" textline " " bitfld.long 0x00 16. " USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbc1_icusb_dm - . - ." "0,1" bitfld.long 0x00 15. " USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbc1_icusb_dp - . - ." "0,1" bitfld.long 0x00 14. " USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_hsic_strobe - . - ." "0,1" textline " " bitfld.long 0x00 13. " USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_hsic_data - . - ." "0,1" bitfld.long 0x00 12. " USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 11. " USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_dat6 - . - ." "0,1" textline " " bitfld.long 0x00 10. " USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_dat5 - . - ." "0,1" bitfld.long 0x00 9. " USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_dat4 - . - ." "0,1" bitfld.long 0x00 8. " USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_dat3 - . - ." "0,1" textline " " bitfld.long 0x00 7. " USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_dat2 - . - ." "0,1" bitfld.long 0x00 6. " USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_dat1 - . - ." "0,1" bitfld.long 0x00 5. " USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_dat0 - . - ." "0,1" textline " " bitfld.long 0x00 4. " USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_nxt - . - ." "0,1" bitfld.long 0x00 3. " USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_dir - . - ." "0,1" bitfld.long 0x00 2. " USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_stp - . - ." "0,1" textline " " bitfld.long 0x00 1. " USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb1_ulpitll_clk - . - ." "0,1" bitfld.long 0x00 0. " CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad cam_globalreset - . - ." "0,1" rgroup.long 0x1E4++0x3 line.long 0x00 "CONTROL_PADCONF_WAKEUPEVENT_3,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " MCSPI1_CS3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi1_cs3 - . - ." "0,1" bitfld.long 0x00 30. " MCSPI1_CS2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi1_cs2 - . - ." "0,1" bitfld.long 0x00 29. " MCSPI1_CS1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi1_cs1 - . - ." "0,1" textline " " bitfld.long 0x00 28. " MCSPI1_CS0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi1_cs0 - . - ." "0,1" bitfld.long 0x00 27. " MCSPI1_SIMO_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi1_simo - . - ." "0,1" bitfld.long 0x00 26. " MCSPI1_SOMI_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi1_somi - . - ." "0,1" textline " " bitfld.long 0x00 25. " MCSPI1_CLK_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi1_clk - . - ." "0,1" bitfld.long 0x00 24. " I2C4_SDA_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad i2c4_sda - . - ." "0,1" bitfld.long 0x00 23. " I2C4_SCL_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad i2c4_scl - . - ." "0,1" textline " " bitfld.long 0x00 22. " I2C3_SDA_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad i2c3_sda - . - ." "0,1" bitfld.long 0x00 21. " I2C3_SCL_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad i2c3_scl - . - ." "0,1" bitfld.long 0x00 20. " I2C2_SDA_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad i2c2_sda - . - ." "0,1" textline " " bitfld.long 0x00 19. " I2C2_SCL_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad i2c2_scl - . - ." "0,1" bitfld.long 0x00 18. " I2C1_SDA_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad i2c1_sda - . - ." "0,1" bitfld.long 0x00 17. " I2C1_SCL_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad i2c1_scl - . - ." "0,1" textline " " bitfld.long 0x00 16. " HDQ_SIO_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad hdq_sio - . - ." "0,1" bitfld.long 0x00 15. " UART2_TX_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart2_tx - . - ." "0,1" bitfld.long 0x00 14. " UART2_RX_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart2_rx - . - ." "0,1" textline " " bitfld.long 0x00 13. " UART2_RTS_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart2_rts - . - ." "0,1" bitfld.long 0x00 12. " UART2_CTS_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart2_cts - . - ." "0,1" bitfld.long 0x00 11. " ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_dmic_din3 - . - ." "0,1" textline " " bitfld.long 0x00 10. " ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_dmic_din2 - . - ." "0,1" bitfld.long 0x00 9. " ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_dmic_din1 - . - ." "0,1" bitfld.long 0x00 8. " ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_dmic_clk1 - . - ." "0,1" textline " " bitfld.long 0x00 7. " ABE_CLKS_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_clks - . - ." "0,1" bitfld.long 0x00 6. " ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_pdm_lb_clk - . - ." "0,1" bitfld.long 0x00 5. " ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_pdm_frame - . - ." "0,1" textline " " bitfld.long 0x00 4. " ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_pdm_dl_data - . - ." "0,1" bitfld.long 0x00 3. " ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_pdm_ul_data - . - ." "0,1" bitfld.long 0x00 2. " ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_mcbsp1_fsx - . - ." "0,1" textline " " bitfld.long 0x00 1. " ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_mcbsp1_dx - . - ." "0,1" bitfld.long 0x00 0. " ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad abe_mcbsp1_dr - . - ." "0,1" rgroup.long 0x1E8++0x3 line.long 0x00 "CONTROL_PADCONF_WAKEUPEVENT_4,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " KPD_COL4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_col4 - . - ." "0,1" bitfld.long 0x00 30. " KPD_COL3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_col3 - . - ." "0,1" bitfld.long 0x00 29. " USBB2_HSIC__STROBE_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_hsic_strobe - . - ." "0,1" textline " " bitfld.long 0x00 28. " USBB2_HSIC__DATA_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_hsic_data - . - ." "0,1" bitfld.long 0x00 27. " USBB2_ULPITLL__DAT7_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_dat7 - . - ." "0,1" bitfld.long 0x00 26. " USBB2_ULPITLL__DAT6_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_dat6 - . - ." "0,1" textline " " bitfld.long 0x00 25. " USBB2_ULPITLL__DAT5_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_dat5 - . - ." "0,1" bitfld.long 0x00 24. " USBB2_ULPITLL__DAT4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_dat4 - . - ." "0,1" bitfld.long 0x00 23. " USBB2_ULPITLL__DAT3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_dat3 - . - ." "0,1" textline " " bitfld.long 0x00 22. " USBB2_ULPITLL__DAT2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_dat2 - . - ." "0,1" bitfld.long 0x00 21. " USBB2_ULPITLL__DAT1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_dat1 - . - ." "0,1" bitfld.long 0x00 20. " USBB2_ULPITLL__DAT0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_dat0 - . - ." "0,1" textline " " bitfld.long 0x00 19. " USBB2_ULPITLL__NXT_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_nxt - . - ." "0,1" bitfld.long 0x00 18. " USBB2_ULPITLL__DIR_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_dir - . - ." "0,1" bitfld.long 0x00 17. " USBB2_ULPITLL__STP_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_stp - . - ." "0,1" textline " " bitfld.long 0x00 16. " USBB2_ULPITLL__CLK_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usbb2_ulpitll_clk - . - ." "0,1" bitfld.long 0x00 15. " UART4_TX__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart4_tx - . - ." "0,1" bitfld.long 0x00 14. " UART4_RX__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart4_rx - . - ." "0,1" textline " " bitfld.long 0x00 13. " MCSPI4_CS0__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi4_cs0 - . - ." "0,1" bitfld.long 0x00 12. " MCSPI4_SOMI__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi4_somi - . - ." "0,1" bitfld.long 0x00 11. " MCSPI4_SIMO__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi4_simo - . - ." "0,1" textline " " bitfld.long 0x00 10. " MCSPI4_CLK__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad mcspi4_clk - . - ." "0,1" bitfld.long 0x00 9. " SDMMC5_DAT3__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc5_dat3 - . - ." "0,1" bitfld.long 0x00 8. " SDMMC5_DAT2__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc5_dat2 - . - ." "0,1" textline " " bitfld.long 0x00 7. " SDMMC5_DAT1__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc5_dat1 - . - ." "0,1" bitfld.long 0x00 6. " SDMMC5_DAT0__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc5_dat0 - . - ." "0,1" bitfld.long 0x00 5. " SDMMC5_CMD__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc5_cmd - . - ." "0,1" textline " " bitfld.long 0x00 4. " SDMMC5_CLK__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sdmmc5_clk - . - ." "0,1" bitfld.long 0x00 3. " UART3_TX_IRTX__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart3_tx_irtx - . - ." "0,1" bitfld.long 0x00 2. " UART3_RX_IRRX__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart3_rx_irrx - . - ." "0,1" textline " " bitfld.long 0x00 1. " UART3_RTS_SD__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart3_rts_sd - . - ." "0,1" bitfld.long 0x00 0. " UART3_CTS_RCTX__DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad uart3_cts_rctx - . - ." "0,1" rgroup.long 0x1EC++0x3 line.long 0x00 "CONTROL_PADCONF_WAKEUPEVENT_5,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_EMU10_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu10 - . - ." "0,1" bitfld.long 0x00 30. " DPM_EMU9_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu9 - . - ." "0,1" bitfld.long 0x00 29. " DPM_EMU8_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu8 - . - ." "0,1" textline " " bitfld.long 0x00 28. " DPM_EMU7_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu7 - . - ." "0,1" bitfld.long 0x00 27. " DPM_EMU6_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu6 - . - ." "0,1" bitfld.long 0x00 26. " DPM_EMU5_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu5 - . - ." "0,1" textline " " bitfld.long 0x00 25. " DPM_EMU4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu4 - . - ." "0,1" bitfld.long 0x00 24. " DPM_EMU3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu3 - . - ." "0,1" bitfld.long 0x00 23. " DPM_EMU2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu2 - . - ." "0,1" textline " " bitfld.long 0x00 22. " DPM_EMU1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu1 - . - ." "0,1" bitfld.long 0x00 21. " DPM_EMU0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu0 - . - ." "0,1" bitfld.long 0x00 20. " SYS_BOOT5_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_boot5 - . - ." "0,1" textline " " bitfld.long 0x00 19. " SYS_BOOT4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_boot4 - . - ." "0,1" bitfld.long 0x00 18. " SYS_BOOT3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_boot3 - . - ." "0,1" bitfld.long 0x00 17. " SYS_BOOT2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_boot2 - . - ." "0,1" textline " " bitfld.long 0x00 16. " SYS_BOOT1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_boot1 - . - ." "0,1" bitfld.long 0x00 15. " SYS_BOOT0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_boot0 - . - ." "0,1" bitfld.long 0x00 14. " SYS_NIRQ2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_nirq2 - . - ." "0,1" textline " " bitfld.long 0x00 13. " SYS_NIRQ1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad sys_nirq1 - . - ." "0,1" bitfld.long 0x00 12. " FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad fref_clk2_out - . - ." "0,1" bitfld.long 0x00 11. " FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad fref_clk1_out - . - ." "0,1" textline " " bitfld.long 0x00 10. " USBA0_OTG_DP_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad usba0_otg_dp - . - ." "0,1" bitfld.long 0x00 9. " KPD_ROW2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_row2 - . - ." "0,1" bitfld.long 0x00 8. " KPD_ROW1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_row1 - . - ." "0,1" textline " " bitfld.long 0x00 7. " KPD_ROW0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_row0 - . - ." "0,1" bitfld.long 0x00 6. " KPD_ROW5_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_row5 - . - ." "0,1" bitfld.long 0x00 5. " KPD_ROW4_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_row4 - . - ." "0,1" textline " " bitfld.long 0x00 4. " KPD_ROW3_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_row3 - . - ." "0,1" bitfld.long 0x00 3. " KPD_COL2_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_col2 - . - ." "0,1" bitfld.long 0x00 2. " KPD_COL1_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_col1 - . - ." "0,1" textline " " bitfld.long 0x00 1. " KPD_COL0_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_col0 - . - ." "0,1" bitfld.long 0x00 0. " KPD_COL5_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad kpd_col5 - . - ." "0,1" rgroup.long 0x1F0++0x3 line.long 0x00 "CONTROL_PADCONF_WAKEUPEVENT_6,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 8. " DPM_EMU19_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the IO for pad dpm_emu19 - . - ." "0,1" bitfld.long 0x00 7. " DPM_EMU18_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu18 - . - ." "0,1" bitfld.long 0x00 6. " DPM_EMU17_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu17 - . - ." "0,1" textline " " bitfld.long 0x00 5. " DPM_EMU16_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu16 - . - ." "0,1" bitfld.long 0x00 4. " DPM_EMU15_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu15 - . - ." "0,1" bitfld.long 0x00 3. " DPM_EMU14_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu14 - . - ." "0,1" textline " " bitfld.long 0x00 2. " DPM_EMU13_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu13 - . - ." "0,1" bitfld.long 0x00 1. " DPM_EMU12_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu12 - . - ." "0,1" bitfld.long 0x00 0. " DPM_EMU11_DUPLICATEWAKEUPEVENT ,Wake-up event status latched in the I/O for pad dpm_emu11 - . - ." "0,1" group.long 0x5A0++0x3 line.long 0x00 "CONTROL_PADCONF_GLOBAL,Global PAD control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " FORCE_OFFMODE_EN ,Force offmode enable for PADs - . - ." "Disable,Enable" group.long 0x5A4++0x3 line.long 0x00 "CONTROL_CORE_PADCONF_MODE,PAD Voltage Mode control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " VDDS_DV_BANK0 ,PAD Voltage level control for vdds_dv_bank0 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" bitfld.long 0x00 30. " VDDS_DV_BANK1 ,PAD Voltage level control for vdds_dv_bank1 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" bitfld.long 0x00 29. " VDDS_DV_BANK3 ,PAD Voltage level control for vdds_dv_bank3 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" textline " " bitfld.long 0x00 28. " VDDS_DV_BANK4 ,PAD Voltage level control for vdds_dv_bank4 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" bitfld.long 0x00 27. " VDDS_DV_BANK5 ,PAD Voltage level control for vdds_dv_bank5 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" bitfld.long 0x00 26. " VDDS_DV_BANK6 ,PAD Voltage level control for vdds_dv_bank6 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" textline " " bitfld.long 0x00 25. " VDDS_DV_C2C ,PAD Voltage level control for vdds_dv_c2c - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" bitfld.long 0x00 24. " VDDS_DV_CAM ,PAD Voltage level control for vdds_dv_cam - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" bitfld.long 0x00 23. " VDDS_DV_GPMC0 ,PAD Voltage level control for vdds_dv_gpmc0 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" textline " " bitfld.long 0x00 22. " VDDS_DV_SDMMC2 ,PAD Voltage level control for vdds_dv_sdmmc2 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" bitfld.long 0x00 21. " VDDS_DV_BANK7 ,PAD Voltage level control for vdds_dv_bank7 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" bitfld.long 0x00 20. " VDDS_DV_GPMC1 ,PAD Voltage level control for vdds_dv_gpmc1 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" textline " " bitfld.long 0x00 19. " VDDS_DV_BANK2_SHARED0 ,PAD Voltage level control for vdds_dv_bank2_shared0 - . - ." "VDDS_=_1.8V,VDDS_=_1.2V" group.long 0x5A8++0x3 line.long 0x00 "CONTROL_SMART1IO_PADCONF_0,SMART1 I/O control 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " ABE_DR0_SC ,Slew rate control for group abe_dr0. Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 28.--29. " CAM_DR0_SC ,Slew rate control for group cam_dr0. Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 22.--23. " GPIO_DR8_SC ,Slew rate control for group gpio_dr8. Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" textline " " bitfld.long 0x00 20.--21. " GPIO_DR9_SC ,Slew rate control for group gpio_dr9. Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 16.--17. " GPMC_DR3_SC ,Slew rate control for group gpmc_dr3. Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 12.--13. " GPIO_63_64_DR0_SC ,Slew rate control for group gpio_63_64_dr0. Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" textline " " bitfld.long 0x00 10.--11. " MCSPI1_DR0_SC ,Slew rate control for group mcspi1_dr0 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 8.--9. " UART1_DR0_SC ,Slew rate control for group uart1_dr0 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 6.--7. " UART3_DR0_SC ,Slew rate control for group uart3_dr0 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " UART3_DR1_SC ,Slew rate control for group uart3_dr1 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" group.long 0x5AC++0x3 line.long 0x00 "CONTROL_SMART1IO_PADCONF_1,SMART1 I/O control 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " ABE_DR0_LB ,Load control for group abe_dr0 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 28.--29. " CAM_DR0_LB ,Load control for group cam_dr0 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 22.--23. " GPIO_DR8_LB ,Load control for group gpio_dr8 - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 20.--21. " GPIO_DR9_LB ,Load control for group gpio_dr9 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 16.--17. " GPMC_DR3_LB ,Load control for group gpmc_dr3 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 12.--13. " GPIO_63_64_DR0_LB ,Load control for group gpio_63_64_dr0 - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 10.--11. " MCSPI1_DR0_LB ,Load control for group mcspi1_dr0 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 8.--9. " UART1_DR0_LB ,Load control for group uart1_dr0 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 6.--7. " UART3_DR0_LB ,Load control for group uart3_dr0 - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " UART3_DR1_LB ,Load control for group uart3_dr1 - . - . - . - ." "0,1,2,3" group.long 0x5B0++0x3 line.long 0x00 "CONTROL_SMART2IO_PADCONF_0,SMART2 I/O control 0 Access conditions. Read: unrestricted, Write: unrestricted" group.long 0x5B4++0x3 line.long 0x00 "CONTROL_SMART2IO_PADCONF_1,SMART2 I/O control 1 Access conditions. Read: unrestricted, Write: unrestricted" group.long 0x5B8++0x3 line.long 0x00 "CONTROL_SMART3IO_PADCONF_0,SMART3 I/O control 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " DMIC_DR0_MB ,50-? output buffer mode control for group dmic_dr0. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 28.--29. " GPIO_DR3_MB ,25-? output buffer mode control for group gpio_dr3. Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 26.--27. " GPIO_DR4_MB ,25-? output buffer mode control for group gpio_dr4. Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " GPIO_DR5_MB ,50-? output buffer mode control for group gpio_dr5. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 22.--23. " GPIO_DR6_MB ,50-? output buffer mode control for group gpio_dr6. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 20.--21. " HSI_DR1_MB ,25-? output buffer mode control for group hsi_dr1. Refer to the I/Os with combined Mode and Load Settings for more information about mode settings." "0,1,2,3" textline " " bitfld.long 0x00 18.--19. " HSI_DR2_MB ,25-? output buffer mode control for group hsi_dr2. Refer to the I/Os with combined Mode and Load Settings for more information about mode settings." "0,1,2,3" bitfld.long 0x00 16.--17. " HSI_DR3_MB ,25-? output buffer mode control for group hsi_dr3. Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 14.--15. " MCBSP2_DR0_MB ,50-? output buffer mode control for group mcbsp2_dr0. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " MCSPI4_DR0_MB ,50-? output buffer mode control for group mcspi4_dr0. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 10.--11. " MCSPI4_DR1_MB ,50-? output buffer mode control for group mcspi4_dr1. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 8.--9. " SDMMC3_DR0_MB ,50-? output buffer mode control for group sdmmc3_dr0. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " SPI2_DR0_MB ,50-? output buffer mode control for group spi2_dr0. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" group.long 0x5BC++0x3 line.long 0x00 "CONTROL_SMART3IO_PADCONF_1,SMART3 I/O control 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " SPI2_DR1_MB ,50-? output buffer mode control for group spi2_dr1. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 28.--29. " SPI2_DR2_MB ,50-? output buffer mode control for group spi2_dr1. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 26.--27. " UART2_DR0_MB ,50-? output buffer mode control for group spi2_dr1. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " UART2_DR1_MB ,50-? output buffer mode control for group spi2_dr1. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 22.--23. " UART4_DR0_MB ,50-? output buffer mode control for group spi2_dr1. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 20.--21. " HSI_DR0_MB ,25-? output buffer mode control for group hsi_dr0. Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " GPMC_DR1_MB ,50-? output buffer mode control for group gpmc_dr1. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 6.--7. " PDM_DR0_MB ,50-? output buffer mode control for group pdm_dr0. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 4.--5. " FREF_DR2_MB ,50-? output buffer mode control for group fref_dr2. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " FREF_DR3_MB ,50-? output buffer mode control for group fref_dr3. Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 0.--1. " USBB1_DR2_MB ,25-? output buffer mode control for group usbb1_dr2. Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" group.long 0x5C0++0x3 line.long 0x00 "CONTROL_SMART3IO_PADCONF_2,SMART3 I/O control 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DMIC_DR0_LB ,50-? output buffer load control dmic_dr0_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 30. " GPIO_DR3_LB ,25-? output buffer load control gpio_dr3_lb Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 29. " GPIO_DR4_LB ,25-? output buffer load control gpio_dr4_lb Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" textline " " bitfld.long 0x00 28. " GPIO_DR5_LB ,50-? output buffer load control gpio_dr5_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 27. " GPIO_DR6_LB ,50-? output buffer load control gpio_dr6_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 26. " HSI_DR1_LB ,25-? output buffer load control hsi_dr1_lb Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" textline " " bitfld.long 0x00 25. " HSI_DR2_LB ,25-? output buffer load control hsi_dr2_lb Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 24. " HSI_DR3_LB ,25-? output buffer load control hsi_dr3_lb Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 23. " MCBSP2_DR0_LB ,50-? output buffer load control mcbsp2_dr0_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" textline " " bitfld.long 0x00 22. " MCSPI4_DR0_LB ,50-? output buffer load control mcspi4_dr0_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 21. " MCSPI4_DR1_LB ,50-? output buffer load control mcspi4_dr1_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 16. " SPI2_DR0_LB ,50-? output buffer load control spi2_dr0_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" textline " " bitfld.long 0x00 15. " SPI2_DR1_LB ,50-? output buffer load control spi2_dr1_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 14. " SPI2_DR2_LB ,50-? output buffer load control spi2_dr2_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 13. " UART2_DR0_LB ,50-? output buffer load control uart2_dr0_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" textline " " bitfld.long 0x00 12. " UART2_DR1_LB ,50-? output buffer load control uart2_dr1_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 11. " UART4_DR0_LB ,50-? output buffer load control uart4_dr0_lb Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 10. " HSI_DR0_LB ,25-? output buffer load control hsi_dr0 Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" textline " " bitfld.long 0x00 9. " FREF_DR3_LB ,50-? output buffer load control fref_dr3 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 8. " GPMC_DR1_LB ,50-? output buffer load control gpmc_dr1 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 7. " PDM_DR0_LB ,50-? output buffer load control pdm_dr0 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" textline " " bitfld.long 0x00 6. " FREF_DR2_LB ,50-? output buffer load control fref_dr2 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 5. " SDMMC3_DR0_LB ,50-? output buffer load control sdmmc3_dr0 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 4. " USBB1_DR2_LB ,25-? output buffer load control usbb1_dr2 Refer to I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" group.long 0x5C4++0x3 line.long 0x00 "CONTROL_USBB_HSIC,USBB HSIC control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " USBB2_DR1_SR ,usbb2 Slew Rate control sr1:sr0 - . - . - . - ." "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 27.--29. " USBB2_DR1_I ,usbb2 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 25.--26. " USBB1_DR1_SR ,usbb1 Slew Rate control sr1:sr0 - . - . - . - ." "Fastest,Slow,Fast,Slowest" textline " " bitfld.long 0x00 22.--24. " USBB1_DR1_I ,usbb1 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 20.--21. " USBB1_HSIC_DATA_WD ,usbb1_hsic_data wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" bitfld.long 0x00 18.--19. " USBB1_HSIC_STROBE_WD ,usbb1_hsic_strobe wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" textline " " bitfld.long 0x00 16.--17. " USBB2_HSIC_DATA_WD ,usbb2_hsic_data wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" bitfld.long 0x00 14.--15. " USBB2_HSIC_STROBE_WD ,usbb2_hsic_strobe wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" bitfld.long 0x00 13. " USBB1_HSIC_DATA__OFFMODE_WD_ENABLE ,usbb1_hsic_data_offmode_wd enable - . - ." "offmode_wd1,offmode_wd1" textline " " bitfld.long 0x00 11.--12. " USBB1_HSIC_DATA__OFFMODE_WD ,usbb1_hsic_data_offmode_wd1:wd0 - . - . - . - ." "Pull_logic_disabled,pull_up,pull_down,3" bitfld.long 0x00 10. " USBB1_HSIC_STROBE__OFFMODE_WD_ENABLE ,usbb1_hsic_strobe_offmode_wd enable - . - ." "offmode_wd1,offmode_wd1" bitfld.long 0x00 8.--9. " USBB1_HSIC_STROBE__OFFMODE_WD ,usbb1_hsic_strobe_offmode_wd1:wd0 - . - . - . - ." "Pull_logic_disabled,pull_up,pull_down,3" textline " " bitfld.long 0x00 7. " USBB2_HSIC_DATA__OFFMODE_WD_ENABLE ,usbb2_hsic_data_offmode_wd enable - . - ." "offmode_wd1,offmode_wd1" bitfld.long 0x00 5.--6. " USBB2_HSIC_DATA__OFFMODE_WD ,usbb2_hsic_data_offmode_wd1:wd0 - . - . - . - ." "Pull_logic_disabled,pull_up,pull_down,3" bitfld.long 0x00 4. " USBB2_HSIC_STROBE__OFFMODE_WD_ENABLE ,usbb2_hsic_strobe_offmode_wd enable - . - ." "offmode_wd1,offmode_wd1" textline " " bitfld.long 0x00 2.--3. " USBB2_HSIC_STROBE__OFFMODE_WD ,usbb2_hsic_strobe_offmode_wd1:wd0 - . - . - . - ." "Pull_logic_disabled,pull_up,pull_down,3" group.long 0x5C8++0x3 line.long 0x00 "CONTROL_SMART3IO_PADCONF_3,SMART3 IO control 3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " SLIMBUS1_DR0_MB ,50-? output buffer mode control for group slimbus1_dr0 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 28.--29. " SLIMBUS1_DR1_MB ,50-? output buffer mode control for group slimbus1_dr1 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 26.--27. " SLIMBUS2_DR0_MB ,50-? output buffer mode control for group slimbus2_dr0 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " SLIMBUS2_DR1_MB ,50-? output buffer mode control for group slimbus2_dr1 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 22.--23. " SLIMBUS2_DR2_MB ,50-? output buffer mode control for group slimbus2_dr2 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" bitfld.long 0x00 20.--21. " SLIMBUS2_DR3_MB ,50-? output buffer mode control for group slimbus2_dr3 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1,2,3" textline " " bitfld.long 0x00 19. " SLIMBUS1_DR0_LB ,50-? output buffer load control for group slimbus1_dr0 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 18. " SLIMBUS2_DR1_LB ,50-? output buffer load control for group slimbus2_dr1 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 17. " SLIMBUS2_DR2_LB ,50-? output buffer load control for group slimbus2_dr2 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" textline " " bitfld.long 0x00 16. " SLIMBUS2_DR3_LB ,50-? output buffer load control for group slimbus2_dr3 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 15. " SLIMBUS1_DR1_LB ,50-? output buffer load control for group slimbus1_dr1 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" bitfld.long 0x00 14. " SLIMBUS2_DR0_LB ,50-? output buffer load control for group slimbus2_dr0 Refer to 50-? output buffer I/Os with combined Mode and Load Settings for more details on mode settings." "0,1" group.long 0x5CC++0x3 line.long 0x00 "CONTROL_SMART2IO_PADCONF_2,SMART2 IO control 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " DPM_DR1_DS ,Drive strength control bit for group dpm_dr1 - . - ." "50_?,25_?" bitfld.long 0x00 30. " DPM_DR2_DS ,Drive strength control bit for group dpm_dr2 - . - ." "50_?,25_?" bitfld.long 0x00 29. " DPM_DR3_DS ,Drive strength control bit for group dpm_dr3 - . - ." "50_?,25_?" textline " " bitfld.long 0x00 28. " GPIO_DR10_DS ,Drive strength control bit for group gpio_dr10 - . - ." "50_?,25_?" bitfld.long 0x00 27. " HSI2_DR0_DS ,Drive strength control bit for group hsi2_dr0 - . - ." "50_?,25_?" bitfld.long 0x00 26. " HSI2_DR1_DS ,Drive strength control bit for group hsi2_dr1 - . - ." "50_?,25_?" textline " " bitfld.long 0x00 25. " HSI2_DR2_DS ,Drive strength control bit for group hsi2_dr2 - . - ." "50_?,25_?" bitfld.long 0x00 24. " SDMMC3_DR0_DS ,Drive strength control bit for group sdmmc3_dr0 - . - ." "50_?,25_?" bitfld.long 0x00 23. " SDMMC4_DR0_DS ,Drive strength control bit for group sdmmc4_dr0 - . - ." "50_?,25_?" textline " " bitfld.long 0x00 22. " SDMMC4_DR1_DS ,Drive strength control bit for group sdmmc4_dr1 - . - ." "50_?,25_?" bitfld.long 0x00 21. " SPI3_DR0_DS ,Drive strength control bit for group spi3_dr0 - . - ." "50_?,25_?" bitfld.long 0x00 20. " SPI3_DR1_DS ,Drive strength control bit for group spi3_dr1 - . - ." "50_?,25_?" textline " " bitfld.long 0x00 19. " UART3_DR2_DS ,Drive strength control bit for group uart3_dr2 - . - ." "50_?,25_?" bitfld.long 0x00 18. " UART3_DR3_DS ,Drive strength control bit for group uart3_dr3 - . - ." "50_?,25_?" bitfld.long 0x00 17. " UART3_DR4_DS ,Drive strength control bit for group uart3_dr4 - . - ." "50_?,25_?" textline " " bitfld.long 0x00 16. " UART3_DR5_DS ,Drive strength control bit for group uart3_dr5 - . - ." "50_?,25_?" bitfld.long 0x00 15. " USBA0_DR0_DS ,Drive strength control bit for group usba0_dr0 - . - ." "50_?,25_?" bitfld.long 0x00 14. " USBA0_DR1_DS ,Drive strength control bit for group usba0_dr1 - . - ." "50_?,25_?" textline " " bitfld.long 0x00 13. " USBA_DR2_DS ,Drive strength control bit for group usba_dr2 - . - ." "50_?,25_?" bitfld.long 0x00 12. " USBB2_DR0_DS ,Drive strength control bit for group usbb2_dr0 - . - ." "50_?,25_?" bitfld.long 0x00 11. " USBB1_DR0_DS ,Drive strength control bit for group usbb1_dr0 - . - ." "50_?,25_?" group.long 0x5D0++0x3 line.long 0x00 "CONTROL_SMART1IO_PADCONF_2,SMART1 IO control 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " KPD_DR0_SC ,Slew rate control for group kpd_dr0 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 28.--29. " KPD_DR1_SC ,Slew rate control for group kpd_dr1 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 26.--27. " KPD_DR2_SC ,Slew rate control for group kpd_dr2 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " KPD_DR3_SC ,Slew rate control for group kpd_dr3 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" bitfld.long 0x00 22.--23. " HDQ_DR0_SC ,Slew rate control for group hdq_dr0 Refer to , section Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings for more details on SR settings." "0,1,2,3" group.long 0x5D4++0x3 line.long 0x00 "CONTROL_SMART1IO_PADCONF_3,SMART1 IO control 3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " KPD_DR0_LB ,Load control for group kpd_dr0 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 28.--29. " KPD_DR1_LB ,Load control for group kpd_dr1 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 26.--27. " KPD_DR2_LB ,Load control for group kpd_dr2 - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " KPD_DR3_LB ,Load control for group kpd_dr3 - . - . - . - ." "0,1,2,3" bitfld.long 0x00 22.--23. " HDQ_DR0_LB ,Load control for group hdq_dr0 - . - . - . - ." "0,1,2,3" group.long 0x5D8++0x3 line.long 0x00 "CONTROL_C2CIO_PADCONF_0,C2C IO control 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " C2C_DR0_LB0 ,Mode selection bit for group c2c_dr0_LB0 - . - ." "0,1" bitfld.long 0x00 30. " C2C_DR1_LB0 ,Mode selection bit for group c2c_dr1_LB0 - . - ." "0,1" bitfld.long 0x00 29. " C2C_DR2_LB0 ,Mode selection bit for group c2c_dr2_LB0 - . - ." "0,1" textline " " bitfld.long 0x00 28. " GPIO_DR0_LB0 ,Mode selection bit for group gpio_dr0_LB0 - . - ." "0,1" bitfld.long 0x00 27. " GPIO_DR1_LB0 ,Mode selection bit for group gpio_dr1_LB0 - . - ." "0,1" bitfld.long 0x00 26. " GPIO_DR2_LB0 ,Mode selection bit for group gpio_dr2_LB0 - . - ." "0,1" textline " " bitfld.long 0x00 25. " GPMC_DR0_LB0 ,Mode selection bit for group gpmc_dr0_LB0 - . - ." "0,1" bitfld.long 0x00 24. " GPMC_DR11_LB0 ,Mode selection bit for group gpmc_dr11_LB0 - . - ." "0,1" bitfld.long 0x00 23. " GPMC_DR10_LB0 ,Mode selection bit for group gpmc_dr10_LB0 - . - ." "0,1" textline " " bitfld.long 0x00 22. " GPMC_DR2_LB0 ,Mode selection bit for group gpmc_dr2_LB0 - . - ." "0,1" bitfld.long 0x00 21. " GPMC_DR4_LB0 ,Mode selection bit for group gpmc_dr4_LB0 - . - ." "0,1" bitfld.long 0x00 20. " GPMC_DR5_LB0 ,Mode selection bit for group gpmc_dr5_LB0 - . - ." "0,1" textline " " bitfld.long 0x00 19. " GPMC_DR6_LB0 ,Mode selection bit for group gpmc_dr6_LB0 - . - ." "0,1" bitfld.long 0x00 18. " GPMC_DR7_LB0 ,Mode selection bit for group gpmc_dr7_LB0 - . - ." "0,1" bitfld.long 0x00 17. " GPMC_DR8_LB0 ,Mode selection bit for group gpmc_dr8_LB0 - . - ." "0,1" textline " " bitfld.long 0x00 16. " GPMC_DR9_LB0 ,Mode selection bit for group gpmc_dr9_LB0 - . - ." "0,1" bitfld.long 0x00 15. " KPD_DR4_LB0 ,Mode selection bit for group kpd_dr4_LB0 - . - ." "0,1" bitfld.long 0x00 14. " KPD_DR5_LB0 ,Mode selection bit for group kpd_dr5_LB0 - . - ." "0,1" textline " " bitfld.long 0x00 13. " SDMMC2_DR0_LB0 ,Mode selection bit for group sdmmc2_dr0_LB0 - . - ." "0,1" bitfld.long 0x00 12. " CMOSEN_C2C_0_FRM_CTRL ,lvcmos receiver enable in 1.2V mode for group c2c_0 - . - ." "lvcmos_rx_disable,lvcmos_rx_enable" bitfld.long 0x00 11. " CMOSEN_C2C_1_FRM_CTRL ,lvcmos receiver enable in 1.2V mode for group c2c_1 - . - ." "lvcmos_rx_disable,lvcmos_rx_enable" textline " " bitfld.long 0x00 9.--10. " C2C_VREF_CCAP ,Selection for coupling cap connection on ivref pad - . - . - . - ." "No_capacitor_connected,1,2,3" bitfld.long 0x00 8. " C2C_INT_VREF_EN ,Internal VREF enable for C2C pads in manual mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " C2C_INT_VREF_AUTO_EN ,Internal VREF enable for C2C pads in auto mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" group.long 0x600++0x3 line.long 0x00 "CONTROL_PBIASLITE,PBIASLITE control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " PBIASLITE1_HIZ_MODE ,Hi-Z MODE of the PBIASLITE1 - . - ." "0,1" bitfld.long 0x00 30. " PBIASLITE1_SUPPLY_HI_OUT ,SUPPLY_HI_OUT from PBIASLITE1 - . - ." "0,1" bitfld.long 0x00 29. " PBIASLITE1_VMODE_ERROR ,VMODE ERROR from PBIASLITE1 - . - ." "0,1" textline " " bitfld.long 0x00 28. " PBIASLITE1_PWRDNZ ,PWRDNZ control to PBIASLITE1. This bit is used to protect the PBIAS1 cell (associated with the gpio_wk0-gpio_wk2 pads I/O cell) when SIM_VDDS is not stable. - . - ." "0,1" bitfld.long 0x00 27. " PBIASLITE1_VMODE ,VMODE control to PBIASLITE1 - . - ." "0,1" bitfld.long 0x00 26. " MMC1_PWRDNZ ,PWRDNZ control to MMC1 IO. This bit is used to protect the MMC1 I/O cell when SDMMC1_VDDS is not stable. - . - ." "Enable,Disbale" textline " " bitfld.long 0x00 25. " MMC1_PBIASLITE_HIZ_MODE ,HIZ_MODE from MMC1 PBIASLITE - . - ." "Enable,Disable" bitfld.long 0x00 24. " MMC1_PBIASLITE_SUPPLY_HI_OUT ,SUPPLY_HI_OUT from MMC1 PBIASLITE - . - ." "1V8,3V" bitfld.long 0x00 23. " MMC1_PBIASLITE_VMODE_ERROR ,VMODE ERROR from MMC1 PBIASLITE - . - ." "VMODE_ERROR0,VMODE_ERROR1" textline " " bitfld.long 0x00 22. " MMC1_PBIASLITE_PWRDNZ ,PWRDNZ control to MMC1 PBIASLITE. This bit is used to protect the MMC1_PBIAS cell (MMC1 I/O cell associated) when SDMMC1_VDDS is not stable. - . - ." "Enable,Disbale" bitfld.long 0x00 21. " MMC1_PBIASLITE_VMODE ,VMODE control to MMC1 PBIASLITE - . - ." "3V,1V8" bitfld.long 0x00 20. " USBC1_ICUSB_PWRDNZ ,PWRDNZ control to USBC1 IO. This bit is used to protect the USBC1_ICUSB I/O cell when SIM_VDDS is not stable. - . - ." "0,1" group.long 0x604++0x3 line.long 0x00 "CONTROL_I2C_0,I2C pads control 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " I2C4_SDA_GLFENB ,Active_high glitch free operation enable pin for i2c4 receiver - . - ." "Disable,Enable" bitfld.long 0x00 29.--30. " I2C4_SDA_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for i2c4 - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 28. " I2C4_SDA_PULLUPRESX ,Active_low internal pull_up resistor enabled for i2c4 - . - ." "Enable,Disable" textline " " bitfld.long 0x00 27. " I2C3_SDA_GLFENB ,Active_high glitch free operation enable pin for i2c3 receiver - . - ." "Disable,Enable" bitfld.long 0x00 25.--26. " I2C3_SDA_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for i2c3 - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 24. " I2C3_SDA_PULLUPRESX ,Active_low internal pull_up resistor enabled for i2c3 - . - ." "Enable,Disable" textline " " bitfld.long 0x00 23. " I2C2_SDA_GLFENB ,Active_high glitch free operation enable pin for i2c2 receiver - . - ." "Disable,Enable" bitfld.long 0x00 21.--22. " I2C2_SDA_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for i2c2 - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 20. " I2C2_SDA_PULLUPRESX ,Active_low internal pull_up resistor enabled for i2c2 - . - ." "Enable,Disable" textline " " bitfld.long 0x00 19. " I2C1_SDA_GLFENB ,Active_high glitch free operation enable pin for i2c1 receiver - . - ." "Disable,Enable" bitfld.long 0x00 17.--18. " I2C1_SDA_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for i2c1 - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 16. " I2C1_SDA_PULLUPRESX ,Active_low internal pull_up resistor enabled for i2c1 - . - ." "Enable,Disable" textline " " bitfld.long 0x00 15. " I2C4_SCL_GLFENB ,Active_high glitch free operation enable pin for i2c4 receiver - . - ." "Disable,Enable" bitfld.long 0x00 13.--14. " I2C4_SCL_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for i2c4 - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 12. " I2C4_SCL_PULLUPRESX ,Active_low internal pull_up resistor enabled for i2c4 - . - ." "Enable,Disable" textline " " bitfld.long 0x00 11. " I2C3_SCL_GLFENB ,Active_high glitch free operation enable pin for i2c3 receiver - . - ." "Disable,Enable" bitfld.long 0x00 9.--10. " I2C3_SCL_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for i2c3 - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 8. " I2C3_SCL_PULLUPRESX ,Active_low internal pull_up resistor enabled for i2c3 - . - ." "Enable,Disable" textline " " bitfld.long 0x00 7. " I2C2_SCL_GLFENB ,Active_high glitch free operation enable pin for i2c2 receiver - . - ." "Disable,Enable" bitfld.long 0x00 5.--6. " I2C2_SCL_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for i2c2 - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 4. " I2C2_SCL_PULLUPRESX ,Active_low internal pull_up resistor enabled for i2c2 - . - ." "Enable,Disable" textline " " bitfld.long 0x00 3. " I2C1_SCL_GLFENB ,Active_high glitch free operation enable pin for i2c1 receiver - . - ." "Disable,Enable" bitfld.long 0x00 1.--2. " I2C1_SCL_LOAD_BITS ,Internal Pull up resistor in Fast or Standard mode /High_speed mode for i2c1 - . - . - . - ." "LB00,LB01,LB10,LB11" bitfld.long 0x00 0. " I2C1_SCL_PULLUPRESX ,Active_low internal pull_up resistor enabled for i2c1 - . - ." "Enable,Disable" group.long 0x608++0x3 line.long 0x00 "CONTROL_CAMERA_RX,CAMERA RX control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30. " CAMERARX_CSI22_LANEENABLE1 ,CSI22 CAMERARX lane 1 enable (CSI22_DX1, CSI22_DY1) - . - ." "Lane_module_disabled,Lane_module_enabled" bitfld.long 0x00 29. " CAMERARX_CSI22_LANEENABLE0 ,CSI22 CAMERARX lane 0 enable (CSI22_DX0, CSI22_DY0) - . - ." "Lane_module_disabled,Lane_module_enabled" bitfld.long 0x00 28. " CAMERARX_CSI21_LANEENABLE4 ,CSI21 CAMERARX lane 4 enable (CSI21_DX4, CSI21_DY4) - . - ." "Lane_module_disabled,Lane_module_enabled" textline " " bitfld.long 0x00 27. " CAMERARX_CSI21_LANEENABLE3 ,CSI21 CAMERARX lane 3 enable (CSI21_DX3, CSI21_DY3) - . - ." "Lane_module_disabled,Lane_module_enabled" bitfld.long 0x00 26. " CAMERARX_CSI21_LANEENABLE2 ,CSI21 CAMERARX lane 2 enable (CSI21_DX2, CSI21_DY2) - . - ." "Lane_module_disabled,Lane_module_enabled" bitfld.long 0x00 25. " CAMERARX_CSI21_LANEENABLE1 ,CSI21 CAMERARX lane 1 enable (CSI21_DX1, CSI21_DY1) - . - ." "Lane_module_disabled,Lane_module_enabled" textline " " bitfld.long 0x00 24. " CAMERARX_CSI21_LANEENABLE0 ,CSI21 CAMERARX lane 0 enable (CSI21_DX0, CSI21_DY0) - . - ." "Lane_module_disabled,Lane_module_enabled" bitfld.long 0x00 21. " CAMERARX_CSI22_CTRLCLKEN ,CSI22 CAMERARX clock enable control - . - ." "Disable,Enable" bitfld.long 0x00 19.--20. " CAMERARX_CSI22_CAMMODE ,CSI22 CAMERARX CAMMODE control - . - . - . - ." "DPHY,CCP2_Data_Strobe,CCP2_Data_Clock,GPI" textline " " bitfld.long 0x00 18. " CAMERARX_CSI21_CTRLCLKEN ,CSI21 CAMERARX clock enable control - . - ." "Disable,Enable" bitfld.long 0x00 16.--17. " CAMERARX_CSI21_CAMMODE ,CSI21 CAMERARX CAMMODE control - . - . - . - ." "DPHY,CCP2_Data_Strobe,CCP2_Data_Clock,GPI" group.long 0x60C++0x3 line.long 0x00 "CONTROL_AVDAC,AVDAC control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " AVDAC_ACEN ,AC coupling enable - . - ." "Disable,Enable" bitfld.long 0x00 30. " AVDAC_TVOUTBYPASS ,TV OUT bypass signal - . - ." "Disable,Enable" bitfld.long 0x00 29. " AVDAC_INPUTINV ,Inversion control for DAC input data ? din[9:0] - . - ." "Disable,Enable" group.long 0x614++0x3 line.long 0x00 "CONTROL_MMC2,MMC2 control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " MMC2_FEEDBACK_CLK_SEL ,Feed_back clock select - . - ." "Internal,External" group.long 0x618++0x3 line.long 0x00 "CONTROL_DSIPHY,DSIPHY control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 29.--31. " DSI2_LANEENABLE ,DSI2 Lane EnableFor each bit, the following settings are valid:. - . - . - . - [31] DSI2 lane 2 enable . - . - [30] DSI2 lane 1 enable . - . - [29] DSI2 lane 0 enable . - ." "Disable,Enable,2,3,4,5,6,7" bitfld.long 0x00 24.--28. " DSI1_LANEENABLE ,DSI1 Lane EnableFor each bit, the following settings are valid:. - . - . - . - [28] DSI1 lane 4 enable . - . - [27] DSI1 lane 3 enable . - . - [26] DSI1 lane 2 enable . - . - [25] DSI1 lane.." "Disable,Enable,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19.--23. " DSI1_PIPD ,DSI1 PD EnableFor each bit, the following settings are valid:. - . - . - . - [23] DSI1 lane 4 PD enable . - . - [22] DSI1 lane 3 PD enable . - . - [21] DSI1 lane 0 PD enable . - . - [20] DS.." "Enable,Disable,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 14.--18. " DSI2_PIPD ,DSI2 PD EnableFor each bit, the following settings are valid:. - . - . - . - [18] RESERVED (Unused) . - . - [17] RESERVED (Unused) . - . - [16] DSI2 lane 0 PD enable . - . - [15] DSI2 lane 2 PD enable . - . - .." "Enable,Disable,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x61C++0x3 line.long 0x00 "CONTROL_MCBSPLP,McBSPLP control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " ALBCTRLRX_FSX ,Analog loop_back control for FSX. This bit is programmable for only the McBSP4 instance. For the remaining three McBSP instances, this bit is hardwired to 1. - . - ." "PIFSR,PIFSX" bitfld.long 0x00 30. " ALBCTRLRX_CLKX ,Analog loop_back control for CLKX. This bit is programmable for only the McBSP4 instance. For the remaining three McBSP instances, this bit is hardwired to 1. - . - ." "PICLKR,PICLKX" group.long 0x620++0x3 line.long 0x00 "CONTROL_USB2PHYCORE,USB2PHYCORE control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " USB2PHY_AUTORESUME_EN ,Auto resume enable - . - ." "0,1" bitfld.long 0x00 30. " USB2PHY_DISCHGDET ,Disable charger detect - . - ." "0,1" bitfld.long 0x00 29. " USB2PHY_GPIOMODE ,GPIO mode - . - ." "0,1" textline " " bitfld.long 0x00 28. " USB2PHY_CHG_DET_EXT_CTL ,Charge detect external control - . - ." "0,1" bitfld.long 0x00 27. " USB2PHY_RDM_PD_CHGDET_EN ,DM Pull down control - . - ." "0,1" bitfld.long 0x00 26. " USB2PHY_RDP_PU_CHGDET_EN ,DP Pull up control - . - ." "0,1" textline " " bitfld.long 0x00 25. " USB2PHY_CHG_VSRC_EN ,VSRC enable on DP line-Host charger case - . - ." "0,1" bitfld.long 0x00 24. " USB2PHY_CHG_ISINK_EN ,ISINK enable on DM line-Host charger case - . - ." "0,1" bitfld.long 0x00 21.--23. " USB2PHY_CHG_DET_STATUS ,Status of charger detection - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20. " USB2PHY_CHG_DET_DM_COMP ,Output of the comparator on DM during the resistor host detect protocol - . - ." "0,1" bitfld.long 0x00 19. " USB2PHY_CHG_DET_DP_COMP ,Output of the comparator on DP during the resistor host detect protocol - . - ." "0,1" bitfld.long 0x00 18. " USB2PHY_DATADET ,Output of the charger detect comparator - . - ." "0,1" textline " " bitfld.long 0x00 17. " USB2PHY_SINKONDP ,When 1 current sink is connected to DP instead of DM - . - ." "0,1" bitfld.long 0x00 16. " USB2PHY_SRCONDM ,When 1 voltage source is connected to DP instead of DM - . - ." "0,1" bitfld.long 0x00 15. " USB2PHY_RESTARTCHGDET ,restartchgdet = 1 for 1 msec cause the CD_START to reset - . - ." "0,1" textline " " bitfld.long 0x00 14. " USB2PHY_CHGDETDONE ,Status indicates that charger detection protocol is over - . - ." "0,1" bitfld.long 0x00 13. " USB2PHY_CHGDETECTED ,Output of the charger detection protocol - . - ." "0,1" bitfld.long 0x00 12. " USB2PHY_MCPCPUEN ,MCPC Pull up enable - . - ." "0,1" textline " " bitfld.long 0x00 11. " USB2PHY_MCPCMODEEN ,MCPC Mode enable - . - ." "Disable_MCPC_mode,Enable_MCPC_mode" bitfld.long 0x00 9. " USB2PHY_UTMIRESETDONE ,UTMI FSM reset status - . - ." "0,1" bitfld.long 0x00 8. " USB2PHY_TXBITSTUFFENABLE ,TX data bit stuff enable - . - ." "DATAOUT_[7,DATAOUT_[7" textline " " bitfld.long 0x00 7. " USB2PHY_DATAPOLARITYN ,Data polarity - . - ." "0,1" bitfld.long 0x00 6. " USBDPLL_FREQLOCK ,Status from USB DPLL" "0,1" bitfld.long 0x00 5. " USB2PHY_RESETDONETCLK ,resetdonetclk status from USB2PHY" "0,1" group.long 0x624++0x3 line.long 0x00 "CONTROL_I2C_1,I2C pads control 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 22. " GPIO66_NMODE ,Active-high selection for GPIO mode - . - ." "Reserved,Normal_(GPIO)_mode" bitfld.long 0x00 20. " GPIO65_NMODE ,Active-high selection for GPIO mode - . - ." "Reserved,Normal_(GPIO)_mode" group.long 0x628++0x3 line.long 0x00 "CONTROL_MMC1,MMC1 control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " SDMMC1_PUSTRENGTH_GRP0 ,Pullstrengh control for sdmmc1_pustrength_grp0 - . - ." "50_100K,10_50K" bitfld.long 0x00 30. " SDMMC1_PUSTRENGTH_GRP1 ,Pullstrengh control for sdmmc1_pustrength_grp1 - . - ." "50_100K,10_50K" bitfld.long 0x00 29. " SDMMC1_PUSTRENGTH_GRP2 ,Pullstrengh control for sdmmc1_pustrength_grp2 - . - ." "50_100K,10_50K" textline " " bitfld.long 0x00 28. " SDMMC1_PUSTRENGTH_GRP3 ,Pullstrengh control for sdmmc1_pustrength_grp3 - . - ." "50_100K,10_50K" bitfld.long 0x00 27. " SDMMC1_DR0_SPEEDCTRL ,Speed control for group sdmmc1_dr0 - . - ." "26Mhz,65MHz" bitfld.long 0x00 26. " SDMMC1_DR1_SPEEDCTRL ,Speed control for group sdmmc1_dr1 - . - ." "26Mhz,65MHz" textline " " bitfld.long 0x00 25. " SDMMC1_DR2_SPEEDCTRL ,Speed control for group sdmmc1_dr2 - . - ." "26Mhz,65MHz" bitfld.long 0x00 24. " USBC1_DR0_SPEEDCTRL ,Speed control for group usbc1_dr0 - . - ." "0,1" bitfld.long 0x00 23. " USB_FD_CDEN ,USB FD pull down select - . - ." "0,1" textline " " bitfld.long 0x00 22. " USBC1_ICUSB_DP_PDDIS ,usbc1_icusb_dp pull down disable - . - ." "0,1" bitfld.long 0x00 21. " USBC1_ICUSB_DM_PDDIS ,usbc1_icusb_dm pull dowm disable - . - ." "0,1" group.long 0x62C++0x3 line.long 0x00 "CONTROL_HSI,HSI control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " HSI1_CALLOOP_SEL ,hsi1 calibration loop select - . - ." "Disable,Enable" bitfld.long 0x00 30. " HSI1_CALMUX_SEL ,hsi1 calibration mux select - . - ." "Disable,Enable" bitfld.long 0x00 29. " HSI2_CALLOOP_SEL ,hsi2 calibration loop select - . - ." "Disable,Enable" textline " " bitfld.long 0x00 28. " HSI2_CALMUX_SEL ,hsi2 calibration mux select - . - ." "Disable,Enable" group.long 0x630++0x3 line.long 0x00 "CONTROL_USB,USB control Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN ,carkit usba0 ulpiphy dat0 auto enable - . - ." "Disable,Enable" bitfld.long 0x00 30. " CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN ,carkit usba0 ulpiphy dat1 auto enable - . - ." "Disable,Enable" group.long 0x634++0x3 line.long 0x00 "CONTROL_HDQ,HDQ control Access conditions. Read: unrestricted, Write: unrestricted" group.long 0x638++0x3 line.long 0x00 "CONTROL_LPDDR2IO1_0,LPDDR2 1 I/O control 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " LPDDR2IO1_GR4_SR ,Group 4 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 27.--29. " LPDDR2IO1_GR4_I ,Group 4 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 25.--26. " LPDDR2IO1_GR4_WD ,Group 4 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 22.--23. " LPDDR2IO1_GR3_SR ,Group 3 Slew Rate control sr1:sr0" "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 19.--21. " LPDDR2IO1_GR3_I ,Group 3 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 17.--18. " LPDDR2IO1_GR3_WD ,Group 3 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" textline " " bitfld.long 0x00 14.--15. " LPDDR2IO1_GR2_SR ,Group 2 Slew Rate control sr1:sr0" "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 11.--13. " LPDDR2IO1_GR2_I ,Group 2 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 9.--10. " LPDDR2IO1_GR2_WD ,Group 2 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" textline " " bitfld.long 0x00 6.--7. " LPDDR2IO1_GR1_SR ,Group 1 Slew Rate control sr1:sr0" "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 3.--5. " LPDDR2IO1_GR1_I ,Group 1 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 1.--2. " LPDDR2IO1_GR1_WD ,Group 1 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" group.long 0x63C++0x3 line.long 0x00 "CONTROL_LPDDR2IO1_1,LPDDR2 1 I/O control 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " LPDDR2IO1_GR8_SR ,Group 8 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 27.--29. " LPDDR2IO1_GR8_I ,Group 8 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 25.--26. " LPDDR2IO1_GR8_WD ,Group 8 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 22.--23. " LPDDR2IO1_GR7_SR ,Group 7 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 19.--21. " LPDDR2IO1_GR7_I ,Group 7 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 17.--18. " LPDDR2IO1_GR7_WD ,Group 7 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 14.--15. " LPDDR2IO1_GR6_SR ,Group 6 Slew Rate control sr1:sr0" "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 11.--13. " LPDDR2IO1_GR6_I ,Group 6 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 9.--10. " LPDDR2IO1_GR6_WD ,Group 6 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" textline " " bitfld.long 0x00 6.--7. " LPDDR2IO1_GR5_SR ,Group 5 Slew Rate control sr1:sr0 - ." "0,1,2,Slowest" bitfld.long 0x00 3.--5. " LPDDR2IO1_GR5_I ,Group 5 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 1.--2. " LPDDR2IO1_GR5_WD ,Group 5 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" group.long 0x640++0x3 line.long 0x00 "CONTROL_LPDDR2IO1_2,LPDDR2 1 I/O control 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " LPDDR2IO1_GR11_SR ,Group 11 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 27.--29. " LPDDR2IO1_GR11_I ,Group 11 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 25.--26. " LPDDR2IO1_GR11_WD ,Group 11 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 22.--23. " LPDDR2IO1_GR10_SR ,Group 10 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 19.--21. " LPDDR2IO1_GR10_I ,Group 10 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 17.--18. " LPDDR2IO1_GR10_WD ,Group 10 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 14.--15. " LPDDR2IO1_GR9_SR ,Group 9 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 11.--13. " LPDDR2IO1_GR9_I ,Group 9 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 9.--10. " LPDDR2IO1_GR9_WD ,Group 9 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" group.long 0x644++0x3 line.long 0x00 "CONTROL_LPDDR2IO1_3,LPDDR2 1 I/O control 3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " LPDDR21_VREF_CA_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 30. " LPDDR21_VREF_CA_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 29. " LPDDR21_VREF_CA_INT_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 28. " LPDDR21_VREF_CA_INT_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 27. " LPDDR21_VREF_CA_INT_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 26. " LPDDR21_VREF_CA_INT_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 25. " LPDDR21_VREF_CA_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 24. " LPDDR21_VREF_CA_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 23. " LPDDR21_VREF_DQ_INT0_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 22. " LPDDR21_VREF_DQ_INT0_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 21. " LPDDR21_VREF_DQ_INT0_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 20. " LPDDR21_VREF_DQ_INT0_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LPDDR21_VREF_DQ_INT1_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 18. " LPDDR21_VREF_DQ_INT1_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 17. " LPDDR21_VREF_DQ_INT1_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 16. " LPDDR21_VREF_DQ_INT1_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 15. " LPDDR21_VREF_DQ_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 14. " LPDDR21_VREF_DQ_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 13. " LPDDR21_VREF_DQ_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 12. " LPDDR21_VREF_DQ_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 11. " LPDDR21_VREF_DQ_INT2_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 10. " LPDDR21_VREF_DQ_INT3_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " LPDDR21_VREF_DQ_INT2_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " LPDDR21_VREF_DQ_INT3_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LPDDR21_VREF_DQ_INT2_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " LPDDR21_VREF_DQ_INT3_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " LPDDR21_VREF_DQ_INT2_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " LPDDR21_VREF_DQ_INT3_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 3. " LPDDR21_INT_VREF_EN_CA ,Internal vref enable for CA in manual mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " LPDDR21_INT_VREF_EN_DQ ,Internal vref enable for DQ in manual mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " LPDDR21_INT_VREF_AUTO_EN_CA ,Internal vref enable for CA in auto mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " LPDDR21_INT_VREF_AUTO_EN_DQ ,Internal vref enable for DQ in auto mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" group.long 0x648++0x3 line.long 0x00 "CONTROL_LPDDR2IO2_0,LPDDR2 2 I/O control 0 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " LPDDR2IO2_GR4_SR ,Group 4 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 27.--29. " LPDDR2IO2_GR4_I ,Group 4 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 25.--26. " LPDDR2IO2_GR4_WD ,Group 4 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 22.--23. " LPDDR2IO2_GR3_SR ,Group 3 Slew Rate control sr1:sr0" "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 19.--21. " LPDDR2IO2_GR3_I ,Group 3 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 17.--18. " LPDDR2IO2_GR3_WD ,Group 3 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" textline " " bitfld.long 0x00 14.--15. " LPDDR2IO2_GR2_SR ,Group 2 Slew Rate control sr1:sr0" "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 11.--13. " LPDDR2IO2_GR2_I ,Group 2 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 9.--10. " LPDDR2IO2_GR2_WD ,Group 2 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" textline " " bitfld.long 0x00 6.--7. " LPDDR2IO2_GR1_SR ,Group 1 Slew Rate control sr1:sr0" "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 3.--5. " LPDDR2IO2_GR1_I ,Group 1 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 1.--2. " LPDDR2IO2_GR1_WD ,Group 1 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" group.long 0x64C++0x3 line.long 0x00 "CONTROL_LPDDR2IO2_1,LPDDR2 2 I/O control 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " LPDDR2IO2_GR8_SR ,Group 8 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 27.--29. " LPDDR2IO2_GR8_I ,Group 8 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 25.--26. " LPDDR2IO2_GR8_WD ,Group 8 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 22.--23. " LPDDR2IO2_GR7_SR ,Group 7 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 19.--21. " LPDDR2IO2_GR7_I ,Group 7 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 17.--18. " LPDDR2IO2_GR7_WD ,Group 7 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 14.--15. " LPDDR2IO2_GR6_SR ,Group 6 Slew Rate control sr1:sr0" "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 11.--13. " LPDDR2IO2_GR6_I ,Group 6 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 9.--10. " LPDDR2IO2_GR6_WD ,Group 6 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" textline " " bitfld.long 0x00 6.--7. " LPDDR2IO2_GR5_SR ,Group 5 Slew Rate control sr1:sr0" "Fastest,Slow,Fast,Slowest" bitfld.long 0x00 3.--5. " LPDDR2IO2_GR5_I ,Group 5 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "1p6Rext,1p33Rext,1p14Rext,Rext,0p88Rext,0p8Rext,0p73Rext,0p67Rext" bitfld.long 0x00 1.--2. " LPDDR2IO2_GR5_WD ,Group 5 Weak driver control wd1:wd0 - . - . - . - ." "None,PU,PD,Keeper" group.long 0x650++0x3 line.long 0x00 "CONTROL_LPDDR2IO2_2,LPDDR2 2 I/O control 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30.--31. " LPDDR2IO2_GR11_SR ,Group 11 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 27.--29. " LPDDR2IO2_GR11_I ,Group 11 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 25.--26. " LPDDR2IO2_GR11_WD ,Group 11 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 22.--23. " LPDDR2IO2_GR10_SR ,Group 10 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 19.--21. " LPDDR2IO2_GR10_I ,Group 10 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 17.--18. " LPDDR2IO2_GR10_WD ,Group 10 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" textline " " bitfld.long 0x00 14.--15. " LPDDR2IO2_GR9_SR ,Group 9 Slew Rate control sr1:sr0" "0,1,2,3" bitfld.long 0x00 11.--13. " LPDDR2IO2_GR9_I ,Group 9 Impedence control i2:i0 - . - . - . - . - . - . - . - ." "for_Drv5,for_Drv6,for_Drv7,for_Drv8,for_Drv9,for_Drv10,for_Drv11,Drv12" bitfld.long 0x00 9.--10. " LPDDR2IO2_GR9_WD ,Group 9 Weak driver control wd1:wd0 - . - . - . - ." "Pull_logic_disabled,Pull_up,Pull_down,3" group.long 0x654++0x3 line.long 0x00 "CONTROL_LPDDR2IO2_3,LPDDR2 2 I/O control 3 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " LPDDR22_VREF_CA_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 30. " LPDDR22_VREF_CA_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 29. " LPDDR22_VREF_CA_INT_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 28. " LPDDR22_VREF_CA_INT_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 27. " LPDDR22_VREF_CA_INT_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 26. " LPDDR22_VREF_CA_INT_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 25. " LPDDR22_VREF_CA_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 24. " LPDDR22_VREF_CA_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 23. " LPDDR22_VREF_DQ_INT0_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 22. " LPDDR22_VREF_DQ_INT0_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 21. " LPDDR22_VREF_DQ_INT0_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 20. " LPDDR22_VREF_DQ_INT0_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LPDDR22_VREF_DQ_INT1_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 18. " LPDDR22_VREF_DQ_INT1_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 17. " LPDDR22_VREF_DQ_INT1_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 16. " LPDDR22_VREF_DQ_INT1_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 15. " LPDDR22_VREF_DQ_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 14. " LPDDR22_VREF_DQ_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 13. " LPDDR22_VREF_DQ_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 12. " LPDDR22_VREF_DQ_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 11. " LPDDR22_VREF_DQ_INT2_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 10. " LPDDR22_VREF_DQ_INT3_CCAP0 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 9. " LPDDR22_VREF_DQ_INT2_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " LPDDR22_VREF_DQ_INT3_CCAP1 ,Selection for coupling cap connection - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LPDDR22_VREF_DQ_INT2_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " LPDDR22_VREF_DQ_INT3_TAP0 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " LPDDR22_VREF_DQ_INT2_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " LPDDR22_VREF_DQ_INT3_TAP1 ,Selection for internal reference voltage drive - . - ." "Disabled,Enabled" bitfld.long 0x00 3. " LPDDR22_INT_VREF_EN_CA ,Internal vref enable for CA in manual mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" bitfld.long 0x00 2. " LPDDR22_INT_VREF_EN_DQ ,Internal vref enable for DQ in manual mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " LPDDR22_INT_VREF_AUTO_EN_CA ,Internal vref enable for CA in auto mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" bitfld.long 0x00 0. " LPDDR22_INT_VREF_AUTO_EN_DQ ,Internal vref enable for DQ in auto mode (if both manual and auto mode is enabled then manual mode takes the priority) - . - ." "Disabled,Enabled" group.long 0x658++0x3 line.long 0x00 "CONTROL_BUS_HOLD,BUS HOLD I/O controls Access conditions. Read: unrestricted, Write: unrestricted" group.long 0x65C++0x3 line.long 0x00 "CONTROL_C2C,C2C controls Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " C2C_SPARE ,C2C spare register bits" group.long 0x660++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW,CORE control spare RW Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW ,Core control spare register bits RW" rgroup.long 0x664++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_R,CORE control spare R Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_R ,Core control spare register bits R" group.long 0x668++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_R_C0,CORE control spare RC Access conditions. Read: unrestricted, Write: unrestricted" eventfld.long 0x00 31. " CORE_CONTROL_SPARE_R_C0 ,Core control spare register bits RC" "0,1" eventfld.long 0x00 30. " CORE_CONTROL_SPARE_R_C1 ,Core control spare register bits RC" "0,1" eventfld.long 0x00 29. " CORE_CONTROL_SPARE_R_C2 ,Core control spare register bits RC" "0,1" textline " " eventfld.long 0x00 28. " CORE_CONTROL_SPARE_R_C3 ,Core control spare register bits RC" "0,1" eventfld.long 0x00 27. " CORE_CONTROL_SPARE_R_C4 ,Core control spare register bits RC" "0,1" eventfld.long 0x00 26. " CORE_CONTROL_SPARE_R_C5 ,Core control spare register bits RC" "0,1" textline " " eventfld.long 0x00 25. " CORE_CONTROL_SPARE_R_C6 ,Core control spare register bits RC" "0,1" eventfld.long 0x00 24. " CORE_CONTROL_SPARE_R_C7 ,Core control spare register bits RC" "0,1" group.long 0x66C++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW1,CORE control spare RW1 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW1 ,Core control spare register bits RW1" group.long 0x670++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW2,CORE control spare RW2 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW2 ,Core control spare register bits RW2" group.long 0x674++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW3,CORE control spare RW3 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW3 ,Core control spare register bits RW3" group.long 0x678++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW4,CORE control spare RW4 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW4 ,Core control spare register bits RW4" group.long 0x67C++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW5,CORE control spare RW5 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW5 ,Core control spare register bits RW5" group.long 0x680++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW6,CORE control spare RW6 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW6 ,Core control spare register bits RW6" group.long 0x684++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW7,CORE control spare RW7 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW7 ,Core control spare register bits RW7" group.long 0x688++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW8,CORE control spare RW8 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW8 ,Core control spare register bits RW8" group.long 0x68C++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_RW9,CORE control spare RW9 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_RW9 ,Core control spare register bits RW9" rgroup.long 0x690++0x3 line.long 0x00 "CONTROL_CORE_CONTROL_SPARE_R1,CORE control spare R1 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " CORE_CONTROL_SPARE_R1 ,Core control spare register bits R1" group.long 0x700++0x3 line.long 0x00 "CONTROL_EFUSE_1,eFuse control 1 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long.byte 0x00 24.--30. 1. " AVDAC_TRIM_BYTE3 ,AVDAC trim byte3 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_avdac_trim_byte_3" hexmask.long.byte 0x00 16.--23. 1. " AVDAC_TRIM_BYTE2 ,AVDAC trim byte2 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_avdac_trim_byte_2" hexmask.long.byte 0x00 8.--15. 1. " AVDAC_TRIM_BYTE1 ,AVDAC trim byte1 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_avdac_trim_byte_1" textline " " hexmask.long.byte 0x00 0.--7. 1. " AVDAC_TRIM_BYTE0 ,AVDAC trim byte0 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_avdac_trim_byte_0" group.long 0x704++0x3 line.long 0x00 "CONTROL_EFUSE_2,eFuse control 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " EFUSE_SMART2TEST_P0 ,Smart2/3/C2C I/O PMOS process compensation bit 0 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_sr_p0" "0,1" bitfld.long 0x00 30. " EFUSE_SMART2TEST_P1 ,Smart2/3/C2C I/O PMOS process compensation bit 1 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_sr_p1" "0,1" bitfld.long 0x00 29. " EFUSE_SMART2TEST_P2 ,Smart2/3/C2C I/O PMOS process compensation bit 2 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_sr_p2" "0,1" textline " " bitfld.long 0x00 28. " EFUSE_SMART2TEST_P3 ,Smart2/3/C2C I/O PMOS process compensation bit 3 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_sr_p3" "0,1" bitfld.long 0x00 27. " EFUSE_SMART2TEST_N0 ,Smart2/3/C2C I/O NMOS process compensation bit 0 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_sr_n0" "0,1" bitfld.long 0x00 26. " EFUSE_SMART2TEST_N1 ,Smart2/3/C2C I/O NMOS process compensation bit 1(Reset value exported from eFuse) Note that reset is exported. Its value is = pi_sr_n1" "0,1" textline " " bitfld.long 0x00 25. " EFUSE_SMART2TEST_N2 ,Smart2/3/C2C I/O NMOS process compensation bit 2 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_sr_n2" "0,1" bitfld.long 0x00 24. " EFUSE_SMART2TEST_N3 ,Smart2/3/C2C I/O NMOS process compensation bit 3 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_sr_n3" "0,1" bitfld.long 0x00 23. " LPDDR2_PTV_N1 ,LPDDR2IO NMOS PTV code bit 1 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_n1" "0,1" textline " " bitfld.long 0x00 22. " LPDDR2_PTV_N2 ,LPDDR2IO NMOS PTV code bit 2 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_n2" "0,1" bitfld.long 0x00 21. " LPDDR2_PTV_N3 ,LPDDR2IO NMOS PTV code bit 3 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_n3" "0,1" bitfld.long 0x00 20. " LPDDR2_PTV_N4 ,LPDDR2IO NMOS PTV code bit 4 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_n4" "0,1" textline " " bitfld.long 0x00 19. " LPDDR2_PTV_N5 ,LPDDR2IO NMOS PTV code bit 5 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_n5" "0,1" bitfld.long 0x00 18. " LPDDR2_PTV_P1 ,LPDDR2IO PMOS PTV code bit 1 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_p1" "0,1" bitfld.long 0x00 17. " LPDDR2_PTV_P2 ,LPDDR2IO PMOS PTV code bit 2 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_p2" "0,1" textline " " bitfld.long 0x00 16. " LPDDR2_PTV_P3 ,LPDDR2IO PMOS PTV code bit 3 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_p3" "0,1" bitfld.long 0x00 15. " LPDDR2_PTV_P4 ,LPDDR2IO PMOS PTV code bit 4 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_p4" "0,1" bitfld.long 0x00 14. " LPDDR2_PTV_P5 ,LPDDR2IO PMOS PTV code bit 5 (Reset value exported from eFuse) Note that reset is exported. Its value is = pi_lpddr2_p5" "0,1" rgroup.long 0x708++0x3 line.long 0x00 "CONTROL_EFUSE_3,eFuse control 3 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long.byte 0x00 24.--31. 1. " STD_FUSE_SPARE_1 ,std eFuse spare bits (Read Only) Note that reset is exported. Its value is = pi_std_fuse_spare1" hexmask.long.byte 0x00 16.--23. 1. " STD_FUSE_SPARE_2 ,std eFuse spare bits (Read Only) Note that reset is exported. Its value is = pi_std_fuse_spare2" hexmask.long.byte 0x00 8.--15. 1. " STD_FUSE_SPARE_3 ,std eFuse spare bits (Read Only) Note that reset is exported. Its value is = pi_std_fuse_spare3" textline " " hexmask.long.byte 0x00 0.--7. 1. " STD_FUSE_SPARE_4 ,std eFuse spare bits (Read Only) Note that reset is exported. Its value is = pi_std_fuse_spare4" group.long 0x70C++0x3 line.long 0x00 "CONTROL_EFUSE_4,eFuse control 4 Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long.byte 0x00 24.--31. 1. " STD_FUSE_SPARE_5 ,std eFuse spare bits (RW) Note that reset is exported. Its value is = pi_std_fuse_spare5" hexmask.long.byte 0x00 16.--23. 1. " STD_FUSE_SPARE_6 ,std eFuse spare bits (RW) Note that reset is exported. Its value is = pi_std_fuse_spare6" hexmask.long.byte 0x00 8.--15. 1. " STD_FUSE_SPARE_7 ,std eFuse spare bits (RW) Note that reset is exported. Its value is = pi_std_fuse_spare7" textline " " hexmask.long.byte 0x00 0.--7. 1. " STD_FUSE_SPARE_8 ,std eFuse spare bits (RW) Note that reset is exported. Its value is = pi_std_fuse_spare8" tree.end tree "SYSCTRL_GENERAL_WKUP" base ad:0x4A30C000 tree "Channel_0" width 38. group.long 0x460++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_0,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x464++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_1,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x468++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_2,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x46C++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_3,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x470++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_4,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x474++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_5,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x478++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_6,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x47C++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_7,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x480++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_8,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x484++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_9,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x488++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_10,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x48C++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_11,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x490++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_12,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x494++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_13,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x498++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_14,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x49C++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_15,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4A0++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_16,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4A4++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_17,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4A8++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_18,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4AC++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_19,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4B0++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_20,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4B4++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_21,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4B8++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_22,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4BC++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_23,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4C0++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_24,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4C4++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_25,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4C8++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_26,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4CC++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_27,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4D0++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_28,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4D4++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_29,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4D8++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_30,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" group.long 0x4DC++0x3 line.long 0x00 "CONTROL_WKUP_CONF_DEBUG_SEL_TST_i_31,Select mode for debug port Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 0. " MODE ,Select one of the following signals: - . - ." "hwobs_int_prm_i,hwobs_int_cm1_i" tree.end textline "" width 43. rgroup.long 0x0++0x3 line.long 0x00 "CONTROL_GEN_WKUP_REVISION,Control module revision identifier Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "CONTROL_GEN_WKUP_HWINFO,Information about the IP module hardware configuration that is, typically the module HDL generics (if any). Access conditions. Read: unrestricted, Write: unrestricted" hexmask.long 0x00 0.--31. 1. " IP_HWINFO ,IP-module dependent" group.long 0x10++0x3 line.long 0x00 "CONTROL_GEN_WKUP_SYSCONFIG,Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 2.--3. " IP_SYSCONFIG_IDLEMODE ,Select the local clock-gating strategy - . - . 0x2,0x3: Clock is automatically gated when there is no access to the Control Module through L4-interconnect. - ." "0,1,2,3" group.long 0x10C++0x3 line.long 0x00 "CONTROL_OCPREG_SPARE,Spare Register Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 31. " OCPREG_SPARE31 ,Spare register 31" "0,1" bitfld.long 0x00 30. " OCPREG_SPARE30 ,Spare register 30" "0,1" bitfld.long 0x00 29. " OCPREG_SPARE29 ,Spare register 29" "0,1" textline " " bitfld.long 0x00 28. " OCPREG_SPARE28 ,Spare register 28" "0,1" bitfld.long 0x00 27. " OCPREG_SPARE27 ,Spare register 27" "0,1" bitfld.long 0x00 26. " OCPREG_SPARE26 ,Spare register 26" "0,1" textline " " bitfld.long 0x00 25. " OCPREG_SPARE25 ,Spare register 25" "0,1" bitfld.long 0x00 24. " OCPREG_SPARE24 ,Spare register 24" "0,1" bitfld.long 0x00 23. " OCPREG_SPARE23 ,Spare register 23" "0,1" textline " " bitfld.long 0x00 22. " OCPREG_SPARE22 ,Spare register 22" "0,1" bitfld.long 0x00 21. " OCPREG_SPARE21 ,Spare register 21" "0,1" bitfld.long 0x00 20. " OCPREG_SPARE20 ,Spare register 20" "0,1" textline " " bitfld.long 0x00 19. " OCPREG_SPARE19 ,Spare register 19" "0,1" bitfld.long 0x00 18. " OCPREG_SPARE18 ,Spare register 18" "0,1" bitfld.long 0x00 17. " OCPREG_SPARE17 ,Spare register 17" "0,1" textline " " bitfld.long 0x00 16. " OCPREG_SPARE16 ,Spare register 16" "0,1" bitfld.long 0x00 15. " OCPREG_SPARE15 ,Spare register 15" "0,1" bitfld.long 0x00 14. " OCPREG_SPARE14 ,Spare register 14" "0,1" textline " " bitfld.long 0x00 13. " OCPREG_SPARE13 ,Spare register 13" "0,1" bitfld.long 0x00 12. " OCPREG_SPARE12 ,Spare register 12" "0,1" bitfld.long 0x00 11. " OCPREG_SPARE11 ,Spare register 11" "0,1" textline " " bitfld.long 0x00 10. " OCPREG_SPARE10 ,Spare register 10" "0,1" bitfld.long 0x00 9. " OCPREG_SPARE9 ,Spare register 9" "0,1" bitfld.long 0x00 8. " OCPREG_SPARE8 ,Spare register 8" "0,1" textline " " bitfld.long 0x00 7. " OCPREG_SPARE7 ,Spare register 7" "0,1" bitfld.long 0x00 6. " OCPREG_SPARE6 ,Spare register 6" "0,1" bitfld.long 0x00 5. " OCPREG_SPARE5 ,Spare register 5" "0,1" textline " " bitfld.long 0x00 4. " OCPREG_SPARE4 ,Spare register 4" "0,1" bitfld.long 0x00 3. " OCPREG_SPARE3 ,Spare register 3" "0,1" bitfld.long 0x00 2. " OCPREG_SPARE2 ,Spare register 2" "0,1" textline " " bitfld.long 0x00 1. " OCPREG_SPARE1 ,Spare register 1" "0,1" group.long 0x110++0x3 line.long 0x00 "CONTROL_WKUP_PROT_EMIF1_SDRAM_CONFIG_REG,Protection EMIF1 SDRAM configuration register 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 29.--31. " EMIF1_SDRAM_TYPE ,SDRAM type selection: - Set to 0x4 for LPDDR2-S4. . - . - Set to 0x5 for LPDDR2-S2. . - . - All other values are reserved. . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " EMIF1_SDRAM_IBANK_POS ,Internal bank position: - Set to 0x0 to assign internal bank address bits from the L3 address as shown in, 64-Byte Linear Read Starting at Address 0x0, and , 64-Byte Linear Read Starting at Address 0x8 (LPDDR2-S2), in .." "0,1,2,3" bitfld.long 0x00 23. " EMIF1_SDRAM_DDR2_DDQS ,DDR2 differential DQS enable: - Set to 0 for single ended DQS. . - . - Set to 1 for differential DQS. . - . - This bit is only for DDR2 mode; because the device supports LPDDR2, this bit is don?t care. . - ." "0,1" textline " " bitfld.long 0x00 20. " EMIF1_SDRAM_DDR_DISABLE_DLL ,Disable DLL select: - Set to 0x0 to enable DLL inside SDRAM. . - . - Set to 0x1 to disable DLL inside SDRAM. . - ." "0,1" bitfld.long 0x00 14.--15. " EMIF1_SDRAM_NARROW_MODE ,SDRAM data bus width: - Set to 0x0 for 64-bit width. . - . - Set to 0x1 for 32-bit width. . - . - Set to 0x2 for 16-bit width. . - . - All other values are reserved. . - ." "0,1,2,3" bitfld.long 0x00 10.--13. " EMIF1_SDRAM_CL ,CAS latency (RL latency). The value of this field defines the CAS latency to be used when accessing connected SDRAM devices:Supported for LPDDR2-SDRAM:. - . - . - . - . - . - . - . - All other values are reserved. . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7.--9. " EMIF1_SDRAM_ROWSIZE ,Row size. Defines the number of row address bits of connected SDRAM devices: - Set to 0x0 for 9 row bits. . - . - Set to 0x1 for 10 row bits. . - . - Set to 0x2 for 11 row bits. . - . - Set to 0x3 for 12 row bits. . - . - .." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " EMIF1_SDRAM_IBANK ,Internal bank setup. Defines number of banks inside connected SDRAM devices: - Set to 0x0 for 1 bank. . - . - Set to 0x1 for 2 banks. . - . - Set to 0x2 for 4 banks. . - . - Set to 0x3 for 8 banks. . - . - All other va.." "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " EMIF1_SDRAM_EBANK ,External CS setup. Defines whether SDRAM accesses will use 1 or 2 CS lines. Set to 0 to use pad_cs_o_n[0] only: - Set to 0x0 to use only pad_cs_o_n[0]. . - . Set to 0x1 to use pad_cs_o_n[1:0].. - . - This bit is automatically s.." "0,1" textline " " bitfld.long 0x00 0.--2. " EMIF1_SDRAM_PAGESIZE ,Page size. Defines the internal page size of the connected SDRAM devices: - Set to 0x0 for 256-word page (8 column bits). . - . - Set to 0x1 for 512-word page (9 column bits). . - . - Set to 0x2 for 1024-word page (10 colu.." "0,1,2,3,4,5,6,7" group.long 0x114++0x3 line.long 0x00 "CONTROL_WKUP_PROT_EMIF1_SDRAM_CONFIG2_REG,Protection EMIF1 SDRAM configuration register 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30. " EMIF1_SDRAM_CS1NVMEN ,CS1 LPDDR2-NVM enable: - Set to 0x1 if LPDDR2-NVM is connected to CS1. . - . - This bit is automatically set to 0x0 if the sdram_type field in the SDRAM Config register is not set to LPDDR2. . - ." "0,1" bitfld.long 0x00 4.--5. " EMIF1_SDRAM_RDBNUM ,Row buffer setup. Defines the number of row buffers inside the connected LPDDR2-NVM devices: - Set to 0x0 for 1 row buffer. . - . - Set to 0x1 for 2 row buffers. . - . - Set to 0x2 for 4 row buffers. . - . - Set to 0x3.." "0,1,2,3" bitfld.long 0x00 0.--2. " EMIF1_SDRAM_RDBSIZE ,Row data buffer size. Defines the row data buffer size of connected LPDDR2-NVM devices: - Set to 0x0 for 32 bytes. . - . - Set to 0x1 for 64 bytes. . - . - Set to 0x2 for 128 bytes. . - . - Set to 0x3 for 256 bytes. . - . - Set.." "0,1,2,3,4,5,6,7" group.long 0x118++0x3 line.long 0x00 "CONTROL_WKUP_PROT_EMIF2_SDRAM_CONFIG_REG,Protection EMIF2 SDRAM configuration register 1 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 29.--31. " EMIF2_SDRAM_TYPE ,SDRAM type selection: - Set to 0x4 for LPDDR2-S4. . - . - Set to 0x5 for LPDDR2-S2. . - . - All other values are reserved. . - ." "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " EMIF2_SDRAM_IBANK_POS ,Internal bank position: - Set to 0x0 to assign internal bank address bits from the L3 address as shown in, 64-Byte Linear Read Starting at Address 0x0, and , 64-Byte Linear Read Starting at Address 0x8 (LPDDR2-S2), in .." "0,1,2,3" bitfld.long 0x00 23. " EMIF2_SDRAM_DDR2_DDQS ,DDR2 differential DQS enable: - Set to 0 for single ended DQS. . - . - Set to 1 for differential DQS. . - . - This bit is only for DDR2 mode; because the device supports LPDDR2, this bit is don?t care. . - ." "0,1" textline " " bitfld.long 0x00 20. " EMIF2_SDRAM_DDR_DISABLE_DLL ,Disable DLL select: - Set to 0x0 to enable DLL inside SDRAM. . - . - Set to 0x1 to disable DLL inside SDRAM. . - ." "0,1" bitfld.long 0x00 14.--15. " EMIF2_SDRAM_NARROW_MODE ,SDRAM data bus width: - Set to 0x0 for 64-bit width. . - . - Set to 0x1 for 32-bit width. . - . - Set to 0x2 for 16-bit width. . - . - All other values are reserved. . - ." "0,1,2,3" bitfld.long 0x00 10.--13. " EMIF2_SDRAM_CL ,CAS latency (RL latency). The value of this field defines the CAS latency to be used when accessing connected SDRAM devices:Supported for LPDDR2-SDRAM:. - . - . - . - . - . - . - . - All other values are reserved. . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7.--9. " EMIF2_SDRAM_ROWSIZE ,Row size. Defines the number of row address bits of connected SDRAM devices: - Set to 0x0 for 9 row bits. . - . - Set to 0x1 for 10 row bits. . - . - Set to 0x2 for 11 row bits. . - . - Set to 0x3 for 12 row bits. . - . - .." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " EMIF2_SDRAM_IBANK ,Internal bank setup. Defines number of banks inside connected SDRAM devices: - Set to 0x0 for 1 bank. . - . - Set to 0x1 for 2 banks. . - . - Set to 0x2 for 4 banks. . - . - Set to 0x3 for 8 banks. . - . - All other va.." "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " EMIF2_SDRAM_EBANK ,External CS setup. Defines whether SDRAM accesses will use 1 or 2 CS lines. Set to 0 to use pad_cs_o_n[0] only: - Set to 0x0 to use only pad_cs_o_n[0]. . - . Set to 0x1 to use pad_cs_o_n[1:0].. - . - This bit is automatically s.." "0,1" textline " " bitfld.long 0x00 0.--2. " EMIF2_SDRAM_PAGESIZE ,Page size. Defines the internal page size of the connected SDRAM devices: - Set to 0x0 for 256-word page (8 column bits). . - . - Set to 0x1 for 512-word page (9 column bits). . - . - Set to 0x2 for 1024-word page (10 colu.." "0,1,2,3,4,5,6,7" group.long 0x11C++0x3 line.long 0x00 "CONTROL_WKUP_PROT_EMIF2_SDRAM_CONFIG2_REG,Protection EMIF1 SDRAM configuration register 2 Access conditions. Read: unrestricted, Write: unrestricted" bitfld.long 0x00 30. " EMIF2_SDRAM_CS1NVMEN ,CS1 LPDDR2-NVM enable: - Set to 0x1 if LPDDR2-NVM is connected to CS1. . - . - This bit is automatically set to 0x0 if the sdram_type field in the SDRAM Config register is not set to LPDDR2. . - ." "0,1" bitfld.long 0x00 4.--5. " EMIF2_SDRAM_RDBNUM ,Row buffer setup. Defines the number of row buffers inside the connected LPDDR2-NVM devices: - Set to 0x0 for 1 row buffer. . - . - Set to 0x1 for 2 row buffers. . - . - Set to 0x2 for 4 row buffers. . - . - Set to 0x3.." "0,1,2,3" bitfld.long 0x00 0.--2. " EMIF2_SDRAM_RDBSIZE ,Row data buffer size. Defines the row data buffer size of connected LPDDR2-NVM devices: - Set to 0x0 for 32 bytes. . - . - Set to 0x1 for 64 bytes. . - . - Set to 0x2 for 128 bytes. . - . - Set to 0x3 for 256 bytes. . - . - Set.." "0,1,2,3,4,5,6,7" tree.end tree.end tree.open "Mailbox" tree "System_Mailbox_L4_CFGInterconnect" base ad:0x4A0F4000 tree "Channel_0" width 27. rgroup.long 0x80++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x10C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x108++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x104++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x100++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debu.." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x40++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xC0++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_1" width 27. rgroup.long 0x84++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x11C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x118++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x114++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x110++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debu.." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x44++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xC4++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_2" width 27. rgroup.long 0x88++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x12C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x128++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x124++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x120++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debu.." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x48++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xC8++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_3" width 24. rgroup.long 0x8C++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x4C++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xCC++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_4" width 24. rgroup.long 0x90++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x50++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xD0++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_5" width 24. rgroup.long 0x94++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x54++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xD4++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_6" width 24. rgroup.long 0x98++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x58++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xD8++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_7" width 24. rgroup.long 0x9C++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x5C++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xDC++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end textline "" width 19. rgroup.long 0x0++0x3 line.long 0x00 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x00 2.--3. " SIDLEMODE ,Idle Mode - . - . - . - ." "b00,b01,b10,b11" bitfld.long 0x00 0. " SOFTRESET ,Softreset - . - . - . - ." "b0,b1" tree.end tree.open "IVAHD_Mailbox_ICONT" tree "IVAHD_Mailbox_L3Interconnect" base ad:0x5A05A800 tree "Channel_0" width 27. rgroup.long 0x80++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x10C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x108++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x104++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x100++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debu.." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x40++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xC0++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_1" width 27. rgroup.long 0x84++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x11C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x118++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x114++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x110++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debu.." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x44++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xC4++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_2" width 27. rgroup.long 0x88++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x12C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x128++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x124++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x120++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debu.." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x48++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xC8++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_3" width 27. rgroup.long 0x8C++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x13C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x138++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x134++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x130++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debu.." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x4C++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xCC++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_4" width 24. rgroup.long 0x90++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x50++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xD0++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_5" width 24. rgroup.long 0x94++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x54++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xD4++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end textline "" width 19. rgroup.long 0x0++0x3 line.long 0x00 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x00 2.--3. " SIDLEMODE ,Idle Mode - . - . - . - ." "b00,b01,b10,b11" bitfld.long 0x00 0. " SOFTRESET ,Softreset - . - . - . - ." "b0,b1" tree.end tree.end tree.end tree.open "MMU" tree "CORTEXM3_L2MMU" base ad:0x55082000 width 18. rgroup.long 0x0++0x3 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the L3 interconnect interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode 00 Functional and Interconnect clocks can be switched off" "0,1,2,3" bitfld.long 0x00 3.--4. " IDLEMODE ,IdleMode - . - . - . - ." "SfIdle,SnIdle,SsIdle,Res" bitfld.long 0x00 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0 - . - . - . - ." "always_r_/_nofun_w,never_r_/_rstMode_w" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Internal interconnect clock gating strategy - . - ." "clkfree,autoClkGate" rgroup.long 0x14++0x3 line.long 0x00 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "rstongoing,rstcomp" group.long 0x18++0x3 line.long 0x00 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." eventfld.long 0x00 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB - . - . - . - ." "nMHF_r_/_MHFstat_w,MHF_r_/_rMHFstat_w" eventfld.long 0x00 3. " TABLEWALKFAULT ,Error response received during a Table Walk - . - . - . - ." "nTWF_r_/_TWFstat_w,TWF_r_/_rTWFstat_w" eventfld.long 0x00 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled) - . - . - . - ." "nEMUM_r_/_Estat_w,EMUM_r_/_rEstat_w" textline " " eventfld.long 0x00 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault) - . - . - . - ." "nFault_r_/_Fstat_w,Fault_r_/_rFstat_w" eventfld.long 0x00 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled) - . - . - . - ." "nTLBM_r_/_Mstat_w,TLBM_r_/_rMstat_w" group.long 0x1C++0x3 line.long 0x00 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x00 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB - . - ." "MHFltMAsk,MHFltGInt" bitfld.long 0x00 3. " TABLEWALKFAULT ,Error response received during a Table Walk - . - ." "TWLFltMAsk,TWLFltGInt" bitfld.long 0x00 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled) - . - ." "EMUMFltMask,EMUMFltGInt" textline " " bitfld.long 0x00 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault) - . - ." "TranFltMask,TranFltGInt" bitfld.long 0x00 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled) - . - ." "TrMissIntM,TrMissGInt" rgroup.long 0x40++0x3 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. " TWLRUNNING ,Table Walking Logic is running - . - ." "TWLComp,TWLRun" group.long 0x44++0x3 line.long 0x00 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x00 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk - . - ." "EMUdis,EMUen" bitfld.long 0x00 2. " TWLENABLE ,Table Walking Logic enable - . - ." "TWLdis,TWLen" bitfld.long 0x00 1. " MMUENABLE ,MMU enable - . - ." "MMUdis,MMUen" rgroup.long 0x48++0x3 line.long 0x00 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x00 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.long 0x4C++0x3 line.long 0x00 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x00 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.long 0x50++0x3 line.long 0x00 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x00 10.--14. " BASEVALUE ,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software Write value : TLB entry to be updated by software, Read value : TLB entry that will be updated by table walk logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x3 line.long 0x00 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x00 0. " LDTLBITEM ,Write (load) data in the TLB - . - . - . - ." "always_r_/_noeffect_w,never_r_/_ldTLB_w" group.long 0x58++0x3 line.long 0x00 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x00 12.--31. 1. " VATAG ,Virtual address tag" bitfld.long 0x00 3. " P ,Preserved bit - . - ." "CanFlush,NoFlush" bitfld.long 0x00 2. " V ,Valid bit - . - ." "Invalid,Valid" textline " " bitfld.long 0x00 0.--1. " PAGESIZE ,Page size - . - . - . - ." "Section,Large,Small,Super" group.long 0x5C++0x3 line.long 0x00 "MMU_RAM,This register holds a RAM entry" hexmask.long.tbyte 0x00 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" bitfld.long 0x00 9. " ENDIANNESS ,Endianness of the page - . - ." "Little,Big" bitfld.long 0x00 7.--8. " ELEMENTSIZE ,Element size of the page (8, 16, 32, no translation) - . - . - . - ." "Byte,Short,Long,None" textline " " bitfld.long 0x00 6. " MIXED ,Mixed page attribute (use CPU element size) - . - ." "TLBes,CPUes" group.long 0x60++0x3 line.long 0x00 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x00 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set - . - . - . - ." "rtn0_r_/_nft_w,never_r_/_flush_w" group.long 0x64++0x3 line.long 0x00 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x00 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected - . - . - . - ." "always_r_/_nofun_w,never_r_/_flushTLB_w" rgroup.long 0x68++0x3 line.long 0x00 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x00 12.--31. 1. " VATAG ,Virtual address tag" bitfld.long 0x00 3. " P ,Preserved bit - . - ." "CanFlush,NoFlush" bitfld.long 0x00 2. " V ,Valid bit - . - ." "Invalid,Valid" textline " " bitfld.long 0x00 0.--1. " PAGESIZE ,Page size - . - . - . - ." "Section,Large,Small,Super" rgroup.long 0x6C++0x3 line.long 0x00 "MMU_READ_RAM,This register reads RAM data from a RAM entry" hexmask.long.tbyte 0x00 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" bitfld.long 0x00 9. " ENDIANNESS ,Endianness of the page - . - ." "Little,Big" bitfld.long 0x00 7.--8. " ELEMENTSIZE ,Element size of the page (8, 16, 32, no translation) - . - . - . - ." "Byte,Short,Long,None" textline " " bitfld.long 0x00 6. " MIXED ,Mixed page attribute (use CPU element size) - . - ." "TLBes,CPUes" rgroup.long 0x70++0x3 line.long 0x00 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x00 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" rgroup.long 0x80++0x3 line.long 0x00 "MMU_FAULT_PC,Capture first fault PC value, controlled by[0] FAULTINDICATION. Notes: The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to Posted-write. All this des.." hexmask.long 0x00 0.--31. 1. " PC ,CPU program counter value where cause MMU fault" group.long 0x84++0x3 line.long 0x00 "MMU_FAULT_STATUS," bitfld.long 0x00 4.--7. " MMU_FAULT_TRANS_ID ,Master ID who cause a fault - . - . - . - . - . - . - . - . - . Read 0x9 to 0xF: reserved (for both Cortex-M3 MMU and DSP MMU). - ." "DMA_RD1,DMA_RD2,DMA_WR1,DMA_WR2,CACHE_MISC,CACHE_CPU,CACHE_DMA,7,MMU_HW_TBL_WALK,9,10,11,12,13,14,15" bitfld.long 0x00 3. " RD_WR ,indicates read or write" "0,1" bitfld.long 0x00 1.--2. " MMU_FAULT_TYPE ,MReq Type[1:0] - . - . - ." "LD_ST,FETCH,DMA,3" textline " " eventfld.long 0x00 0. " FAULTINDICATION ,indicates a MMU fault" "0,1" group.long 0x88++0x3 line.long 0x00 "MMU_GP_REG,Bus-error back response enable register. For more information about the register usage, see section L2 MMU, part of the Dual Cortex-M3 MPU chapter." bitfld.long 0x00 0. " BUS_ERR_BACK_EN ,Bus-error back response enable bit - . - ." "0,1" tree.end tree "DSP_MMU" base ad:0x4A066000 width 18. rgroup.long 0x0++0x3 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the L3 interconnect interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode 00 Functional and Interconnect clocks can be switched off" "0,1,2,3" bitfld.long 0x00 3.--4. " IDLEMODE ,IdleMode - . - . - . - ." "SfIdle,SnIdle,SsIdle,Res" bitfld.long 0x00 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0 - . - . - . - ." "always_r_/_nofun_w,never_r_/_rstMode_w" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Internal interconnect clock gating strategy - . - ." "clkfree,autoClkGate" rgroup.long 0x14++0x3 line.long 0x00 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "rstongoing,rstcomp" group.long 0x18++0x3 line.long 0x00 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." eventfld.long 0x00 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB - . - . - . - ." "nMHF_r_/_MHFstat_w,MHF_r_/_rMHFstat_w" eventfld.long 0x00 3. " TABLEWALKFAULT ,Error response received during a Table Walk - . - . - . - ." "nTWF_r_/_TWFstat_w,TWF_r_/_rTWFstat_w" eventfld.long 0x00 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled) - . - . - . - ." "nEMUM_r_/_Estat_w,EMUM_r_/_rEstat_w" textline " " eventfld.long 0x00 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault) - . - . - . - ." "nFault_r_/_Fstat_w,Fault_r_/_rFstat_w" eventfld.long 0x00 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled) - . - . - . - ." "nTLBM_r_/_Mstat_w,TLBM_r_/_rMstat_w" group.long 0x1C++0x3 line.long 0x00 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x00 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB - . - ." "MHFltMAsk,MHFltGInt" bitfld.long 0x00 3. " TABLEWALKFAULT ,Error response received during a Table Walk - . - ." "TWLFltMAsk,TWLFltGInt" bitfld.long 0x00 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled) - . - ." "EMUMFltMask,EMUMFltGInt" textline " " bitfld.long 0x00 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault) - . - ." "TranFltMask,TranFltGInt" bitfld.long 0x00 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled) - . - ." "TrMissIntM,TrMissGInt" rgroup.long 0x40++0x3 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. " TWLRUNNING ,Table Walking Logic is running - . - ." "TWLComp,TWLRun" group.long 0x44++0x3 line.long 0x00 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x00 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk - . - ." "EMUdis,EMUen" bitfld.long 0x00 2. " TWLENABLE ,Table Walking Logic enable - . - ." "TWLdis,TWLen" bitfld.long 0x00 1. " MMUENABLE ,MMU enable - . - ." "MMUdis,MMUen" rgroup.long 0x48++0x3 line.long 0x00 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x00 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.long 0x4C++0x3 line.long 0x00 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x00 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.long 0x50++0x3 line.long 0x00 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x00 10.--14. " BASEVALUE ,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software Write value : TLB entry to be updated by software, Read value : TLB entry that will be updated by table walk logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x3 line.long 0x00 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x00 0. " LDTLBITEM ,Write (load) data in the TLB - . - . - . - ." "always_r_/_noeffect_w,never_r_/_ldTLB_w" group.long 0x58++0x3 line.long 0x00 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x00 12.--31. 1. " VATAG ,Virtual address tag" bitfld.long 0x00 3. " P ,Preserved bit - . - ." "CanFlush,NoFlush" bitfld.long 0x00 2. " V ,Valid bit - . - ." "Invalid,Valid" textline " " bitfld.long 0x00 0.--1. " PAGESIZE ,Page size - . - . - . - ." "Section,Large,Small,Super" group.long 0x5C++0x3 line.long 0x00 "MMU_RAM,This register holds a RAM entry" hexmask.long.tbyte 0x00 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" bitfld.long 0x00 9. " ENDIANNESS ,Endianness of the page - . - ." "Little,Big" bitfld.long 0x00 7.--8. " ELEMENTSIZE ,Element size of the page (8, 16, 32, no translation) - . - . - . - ." "Byte,Short,Long,None" textline " " bitfld.long 0x00 6. " MIXED ,Mixed page attribute (use CPU element size) - . - ." "TLBes,CPUes" group.long 0x60++0x3 line.long 0x00 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x00 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set - . - . - . - ." "rtn0_r_/_nft_w,never_r_/_flush_w" group.long 0x64++0x3 line.long 0x00 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x00 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected - . - . - . - ." "always_r_/_nofun_w,never_r_/_flushTLB_w" rgroup.long 0x68++0x3 line.long 0x00 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x00 12.--31. 1. " VATAG ,Virtual address tag" bitfld.long 0x00 3. " P ,Preserved bit - . - ." "CanFlush,NoFlush" bitfld.long 0x00 2. " V ,Valid bit - . - ." "Invalid,Valid" textline " " bitfld.long 0x00 0.--1. " PAGESIZE ,Page size - . - . - . - ." "Section,Large,Small,Super" rgroup.long 0x6C++0x3 line.long 0x00 "MMU_READ_RAM,This register reads RAM data from a RAM entry" hexmask.long.tbyte 0x00 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" bitfld.long 0x00 9. " ENDIANNESS ,Endianness of the page - . - ." "Little,Big" bitfld.long 0x00 7.--8. " ELEMENTSIZE ,Element size of the page (8, 16, 32, no translation) - . - . - . - ." "Byte,Short,Long,None" textline " " bitfld.long 0x00 6. " MIXED ,Mixed page attribute (use CPU element size) - . - ." "TLBes,CPUes" rgroup.long 0x70++0x3 line.long 0x00 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x00 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" rgroup.long 0x80++0x3 line.long 0x00 "MMU_FAULT_PC,Capture first fault PC value, controlled by[0] FAULTINDICATION. Notes: The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to Posted-write. All this des.." hexmask.long 0x00 0.--31. 1. " PC ,CPU program counter value where cause MMU fault" group.long 0x84++0x3 line.long 0x00 "MMU_FAULT_STATUS," bitfld.long 0x00 4.--7. " MMU_FAULT_TRANS_ID ,Master ID who cause a fault - . - . - . - . - . - . - . - . - . Read 0x9 to 0xF: reserved (for both Cortex-M3 MMU and DSP MMU). - ." "DMA_RD1,DMA_RD2,DMA_WR1,DMA_WR2,CACHE_MISC,CACHE_CPU,CACHE_DMA,7,MMU_HW_TBL_WALK,9,10,11,12,13,14,15" bitfld.long 0x00 3. " RD_WR ,indicates read or write" "0,1" bitfld.long 0x00 1.--2. " MMU_FAULT_TYPE ,MReq Type[1:0] - . - . - ." "LD_ST,FETCH,DMA,3" textline " " eventfld.long 0x00 0. " FAULTINDICATION ,indicates a MMU fault" "0,1" group.long 0x88++0x3 line.long 0x00 "DSPSS_MMU_GPR,This register controls the DSP MMU hardware debug output multiplexer. It also controls force-idle request generation. For more information about the use of this register, see, Control Module." bitfld.long 0x00 15. " FORCE_IDLE_REQ ,Force-idle request to see existence of pending bus request. This bit must be used only for debug purposes, not in functional mode." "0,1" bitfld.long 0x00 0.--3. " HWDEBUG_MUX ,Control HWDEBUG output MUX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.end tree.open "Spinlock" tree "Spinlock" base ad:0x4A0F6000 tree "REG_Bundle_0" width 24. group.long 0x800++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_0,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x804++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_1,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x808++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_2,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x80C++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_3,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x810++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_4,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x814++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_5,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x818++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_6,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x81C++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_7,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x820++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_8,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x824++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_9,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x828++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_10,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x82C++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_11,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x830++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_12,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x834++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_13,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x838++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_14,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x83C++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_15,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x840++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_16,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x844++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_17,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x848++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_18,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x84C++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_19,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x850++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_20,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x854++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_21,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x858++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_22,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x85C++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_23,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x860++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_24,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x864++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_25,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x868++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_26,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x86C++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_27,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x870++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_28,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x874++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_29,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x878++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_30,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" group.long 0x87C++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_i_31,This register contains the state of one lock." bitfld.long 0x00 0. " TAKEN ,Lock State - . - . - . - ." "0,1" tree.end textline "" width 20. rgroup.long 0x0++0x3 line.long 0x00 "SPINLOCK_REVISION,This register contains the IP revision code" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "SPINLOCK_SYSCONFIG,This register controls the various parameters of the L4-CFG interface. Note that most fields are read-only." bitfld.long 0x00 8. " CLOCKACTIVITY ,Indicates whether the module requires the interface clock when in IDLE mode. - . - ." "0,1" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management (IDLE request/acknowledgement control). - . - . - . - ." "0,1,2,3" bitfld.long 0x00 2. " ENWAKEUP ,Asynchronous wakeup gereration. - . - ." "0,1" textline " " bitfld.long 0x00 1. " SOFTRESET ,Module software reset. - . - ." "No_action,1" bitfld.long 0x00 0. " AUTOGATING ,Internal interface clock gating strategy. - . - ." "0,1" rgroup.long 0x14++0x3 line.long 0x00 "SPINLOCK_SYSTATUS,This register provides status information about this instance of the Spinlock module." hexmask.long.byte 0x00 24.--31. 1. " NUMLOCKS ,Number of lock registers implemeted. - . - . - . - ." bitfld.long 0x00 15. " IU7 ,In-Use flag 7. Reads always return 0." "0,1" bitfld.long 0x00 14. " IU6 ,In-Use flag 6. Reads always return 0." "0,1" textline " " bitfld.long 0x00 13. " IU5 ,In-Use flag 5. Reads always return 0." "0,1" bitfld.long 0x00 12. " IU4 ,In-Use flag 4. Reads always return 0." "0,1" bitfld.long 0x00 11. " IU3 ,In-Use flag 3. Reads always return 0." "0,1" textline " " bitfld.long 0x00 10. " IU2 ,In-Use flag 2. Reads always return 0." "0,1" bitfld.long 0x00 9. " IU1 ,In-Use flag 1. Reads always return 0." "0,1" bitfld.long 0x00 8. " IU0 ,In-Use flag 0, covering lock registers 0 - 31. - . - ." "0,1" textline " " bitfld.long 0x00 0. " RESETDONE ,Reset done status. - . - ." "Reset_in_progress.,Reset_is_completed." tree.end tree.end tree.open "General_Purpose_Timers" tree.open "GPTIMER5_DSP" tree "GPTIMER5_Cortex_A9" base ad:0x40138000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER6_Cortex_A9" base ad:0x4013A000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER7_Cortex_A9" base ad:0x4013C000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER8_Cortex_A9" base ad:0x4013E000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER3_L4Interconnect" base ad:0x48034000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER4_L4Interconnect" base ad:0x48036000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER9_L4Interconnect" base ad:0x4803E000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER11_L4Interconnect" base ad:0x48088000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER5_L3Interconnect" base ad:0x49038000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER6_L3Interconnect" base ad:0x4903A000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER7_L3Interconnect" base ad:0x4903C000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree "GPTIMER8_L3Interconnect" base ad:0x4903E000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT_TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 0. " SOFTRESET ,Software reset - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "GPT_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for CaptureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software" "0,1" group.long 0x28++0x3 line.long 0x00 "GPT_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, eve.." bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for captureRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for OverflowRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for MatchRead 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" group.long 0x2C++0x3 line.long 0x00 "GPT_IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Set IRQ enable." "0,1" group.long 0x30++0x3 line.long 0x00 "GPT_IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for CompareRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for OverflowRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for MatchRead 0: IRQ event is disabled.Write 0: No action Read 1: IRQ event is enabled.Write 1: Clear IRQ enable." "0,1" group.long 0x34++0x3 line.long 0x00 "GPT_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wake-up generation for Compare - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wake-up generation for Overflow - . - ." "Wake-up_disabled,Wake-up_enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wake-up generation for Match - . - ." "Wake-up_disabled,Wake-up_enabled" group.long 0x38++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x3C++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x40++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x44++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x48++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x4C++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x58++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" tree.end tree.end tree.open "GPTIMER2_L4Interconnect" tree "GPTIMER2_L4Interconnect" base ad:0x48032000 width 18. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT1MS_TIOCP_CFG,This register controls the various parameters of the OCP interface." bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity - . - . - . - ." "0,1,2,3" bitfld.long 0x00 5. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 3.--4. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control - . - ." "0,1" bitfld.long 0x00 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "Normal_mode,1" bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 clock gating strategy - . - ." "0,1" rgroup.long 0x14++0x3 line.long 0x00 "GPT_TISTAT,This register provides status information about the module, excluding interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "0,Reset_complete" group.long 0x18++0x3 line.long 0x00 "GPT_TISR,The timer status register is used to determine which of the timer events requested an interrupt." bitfld.long 0x00 2. " TCAR_IT_FLAG ,Indicates when an external pulse transition of the correct polarity is detected on external pin GPTi_EVENT_CAPTURE - . - ." "0,Capture_interrupt_request" bitfld.long 0x00 1. " OVF_IT_FLAG ,TCRR overflow - . - ." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,The compare result of TCRR and TMAR - . - ." "0,Compare_interrupt_pending" group.long 0x1C++0x3 line.long 0x00 "GPT_TIER,This register controls (enable/disable) the interrupt events." bitfld.long 0x00 2. " TCAR_IT_ENA ,Capture interrupt enable - . - ." "0,Enable_capture_interrupt." bitfld.long 0x00 1. " OVF_IT_ENA ,Overflow interrupt enable - . - ." "0,1" bitfld.long 0x00 0. " MAT_IT_ENA ,Match interrupt enable - . - ." "Disable_match_interrupt.,Enable_match_interrupt." group.long 0x20++0x3 line.long 0x00 "GPT_TWER,This register controls (enable/disable) the wake-up feature on specific interrupt events." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Capture wake-up enable - . - ." "Disable_capture_wake-up.,Enable_capture_wake-up." bitfld.long 0x00 1. " OVF_WUP_ENA ,Overflow wake-up enable - . - ." "Disable_overflow_wake-up.,Enable_overflow_wake-up." bitfld.long 0x00 0. " MAT_WUP_ENA ,Match wake-up enable - . - ." "Disable_match_wake-up.,Enable_match_wake-up." group.long 0x24++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x28++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x2C++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x30++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x34++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x38++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x3C++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x40++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x44++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" group.long 0x48++0x3 line.long 0x00 "GPT_TPIR,This register is used for 1-ms tick generation. The TPIR register holds the value of the positive increment. The value of this register is added to the value of TCVR to determine whether next value loaded in TCRR is the subperiod value or the .." hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment" group.long 0x4C++0x3 line.long 0x00 "GPT_TNIR,This register is used for 1-ms tick generation. The TNIR register holds the value of the negative increment. The value of this register is added to the value of the TCVR to determine whether next value loaded in TCRR is the subperiod value or .." hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment" group.long 0x50++0x3 line.long 0x00 "GPT_TCVR,This register is used for 1-ms tick generation. The TCVR register determines whether next value loaded in TCRR is the subperiod value or the overperiod value." hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE ,Value of CVR counter" group.long 0x54++0x3 line.long 0x00 "GPT_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE ,Number of overflow events" group.long 0x58++0x3 line.long 0x00 "GPT_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts" tree.end tree "GPTIMER10_L4Interconnect" base ad:0x48086000 width 18. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT1MS_TIOCP_CFG,This register controls the various parameters of the OCP interface." bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity - . - . - . - ." "0,1,2,3" bitfld.long 0x00 5. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 3.--4. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control - . - ." "0,1" bitfld.long 0x00 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "Normal_mode,1" bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 clock gating strategy - . - ." "0,1" rgroup.long 0x14++0x3 line.long 0x00 "GPT_TISTAT,This register provides status information about the module, excluding interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "0,Reset_complete" group.long 0x18++0x3 line.long 0x00 "GPT_TISR,The timer status register is used to determine which of the timer events requested an interrupt." bitfld.long 0x00 2. " TCAR_IT_FLAG ,Indicates when an external pulse transition of the correct polarity is detected on external pin GPTi_EVENT_CAPTURE - . - ." "0,Capture_interrupt_request" bitfld.long 0x00 1. " OVF_IT_FLAG ,TCRR overflow - . - ." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,The compare result of TCRR and TMAR - . - ." "0,Compare_interrupt_pending" group.long 0x1C++0x3 line.long 0x00 "GPT_TIER,This register controls (enable/disable) the interrupt events." bitfld.long 0x00 2. " TCAR_IT_ENA ,Capture interrupt enable - . - ." "0,Enable_capture_interrupt." bitfld.long 0x00 1. " OVF_IT_ENA ,Overflow interrupt enable - . - ." "0,1" bitfld.long 0x00 0. " MAT_IT_ENA ,Match interrupt enable - . - ." "Disable_match_interrupt.,Enable_match_interrupt." group.long 0x20++0x3 line.long 0x00 "GPT_TWER,This register controls (enable/disable) the wake-up feature on specific interrupt events." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Capture wake-up enable - . - ." "Disable_capture_wake-up.,Enable_capture_wake-up." bitfld.long 0x00 1. " OVF_WUP_ENA ,Overflow wake-up enable - . - ." "Disable_overflow_wake-up.,Enable_overflow_wake-up." bitfld.long 0x00 0. " MAT_WUP_ENA ,Match wake-up enable - . - ." "Disable_match_wake-up.,Enable_match_wake-up." group.long 0x24++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x28++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x2C++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x30++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x34++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x38++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x3C++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x40++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x44++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" group.long 0x48++0x3 line.long 0x00 "GPT_TPIR,This register is used for 1-ms tick generation. The TPIR register holds the value of the positive increment. The value of this register is added to the value of TCVR to determine whether next value loaded in TCRR is the subperiod value or the .." hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment" group.long 0x4C++0x3 line.long 0x00 "GPT_TNIR,This register is used for 1-ms tick generation. The TNIR register holds the value of the negative increment. The value of this register is added to the value of the TCVR to determine whether next value loaded in TCRR is the subperiod value or .." hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment" group.long 0x50++0x3 line.long 0x00 "GPT_TCVR,This register is used for 1-ms tick generation. The TCVR register determines whether next value loaded in TCRR is the subperiod value or the overperiod value." hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE ,Value of CVR counter" group.long 0x54++0x3 line.long 0x00 "GPT_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE ,Number of overflow events" group.long 0x58++0x3 line.long 0x00 "GPT_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts" tree.end tree "GPTIMER1_L4Interconnect" base ad:0x4A318000 width 18. rgroup.long 0x0++0x3 line.long 0x00 "GPT_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "GPT1MS_TIOCP_CFG,This register controls the various parameters of the OCP interface." bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity - . - . - . - ." "0,1,2,3" bitfld.long 0x00 5. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 3.--4. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control - . - ." "0,1" bitfld.long 0x00 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "Normal_mode,1" bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 clock gating strategy - . - ." "0,1" rgroup.long 0x14++0x3 line.long 0x00 "GPT_TISTAT,This register provides status information about the module, excluding interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "0,Reset_complete" group.long 0x18++0x3 line.long 0x00 "GPT_TISR,The timer status register is used to determine which of the timer events requested an interrupt." bitfld.long 0x00 2. " TCAR_IT_FLAG ,Indicates when an external pulse transition of the correct polarity is detected on external pin GPTi_EVENT_CAPTURE - . - ." "0,Capture_interrupt_request" bitfld.long 0x00 1. " OVF_IT_FLAG ,TCRR overflow - . - ." "0,1" bitfld.long 0x00 0. " MAT_IT_FLAG ,The compare result of TCRR and TMAR - . - ." "0,Compare_interrupt_pending" group.long 0x1C++0x3 line.long 0x00 "GPT_TIER,This register controls (enable/disable) the interrupt events." bitfld.long 0x00 2. " TCAR_IT_ENA ,Capture interrupt enable - . - ." "0,Enable_capture_interrupt." bitfld.long 0x00 1. " OVF_IT_ENA ,Overflow interrupt enable - . - ." "0,1" bitfld.long 0x00 0. " MAT_IT_ENA ,Match interrupt enable - . - ." "Disable_match_interrupt.,Enable_match_interrupt." group.long 0x20++0x3 line.long 0x00 "GPT_TWER,This register controls (enable/disable) the wake-up feature on specific interrupt events." bitfld.long 0x00 2. " TCAR_WUP_ENA ,Capture wake-up enable - . - ." "Disable_capture_wake-up.,Enable_capture_wake-up." bitfld.long 0x00 1. " OVF_WUP_ENA ,Overflow wake-up enable - . - ." "Disable_overflow_wake-up.,Enable_overflow_wake-up." bitfld.long 0x00 0. " MAT_WUP_ENA ,Match wake-up enable - . - ." "Disable_match_wake-up.,Enable_match_wake-up." group.long 0x24++0x3 line.long 0x00 "GPT_TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x00 14. " GPO_CFG ,General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, . - . - ." "GPTi_PORGPOCFG_drives_0.,GPTi_PORGPOCFG_drives_1." bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second) - . - ." "0,1" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on GPTi_PWM_out output pin - . - ." "Pulse_modulation,Toggle_modulation" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on GPTi_PWM_out output pin - . - . - . - ." "No_trigger,Trigger_on_overflow.,2,?..." bitfld.long 0x00 8.--9. " TCM ,Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) - . - . - . - ." "No_capture,1,2,3" bitfld.long 0x00 7. " SCPWM ,Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off. - . - ." "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable - . - ." "0,1" bitfld.long 0x00 5. " PRE ,Prescaler enable - . - ." "0,1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Autoreload mode - . - ." "One_shot_timer,Autoreload_timer" bitfld.long 0x00 0. " ST ,Start/stop timer control - . - ." "0,Start_timer" group.long 0x28++0x3 line.long 0x00 "GPT_TCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.long 0x2C++0x3 line.long 0x00 "GPT_TLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onGPT_TTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.long 0x30++0x3 line.long 0x00 "GPT_TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Writing to the TTGR register causes theGPT_TCRR to be loaded from GPT_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the GPT_TCLR register." rgroup.long 0x34++0x3 line.long 0x00 "GPT_TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x00 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theGPT_TMAR register." "0,1" bitfld.long 0x00 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theGPT_TTGR register." "0,1" bitfld.long 0x00 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theGPT_TLDR register." "0,1" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theGPT_TCRR register." "0,1" bitfld.long 0x00 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theGPT_TCLR register." "0,1" group.long 0x38++0x3 line.long 0x00 "GPT_TMAR,The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" rgroup.long 0x3C++0x3 line.long 0x00 "GPT_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.long 0x40++0x3 line.long 0x00 "GPT_TSICR,Timer synchronous interface control register" bitfld.long 0x00 2. " POSTED ,Posted mode selection - . - ." "0,Posted_mode_active" bitfld.long 0x00 1. " SFT ,This bit resets all the functional part of the module. - . - ." "0,1" rgroup.long 0x44++0x3 line.long 0x00 "GPT_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" group.long 0x48++0x3 line.long 0x00 "GPT_TPIR,This register is used for 1-ms tick generation. The TPIR register holds the value of the positive increment. The value of this register is added to the value of TCVR to determine whether next value loaded in TCRR is the subperiod value or the .." hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment" group.long 0x4C++0x3 line.long 0x00 "GPT_TNIR,This register is used for 1-ms tick generation. The TNIR register holds the value of the negative increment. The value of this register is added to the value of the TCVR to determine whether next value loaded in TCRR is the subperiod value or .." hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment" group.long 0x50++0x3 line.long 0x00 "GPT_TCVR,This register is used for 1-ms tick generation. The TCVR register determines whether next value loaded in TCRR is the subperiod value or the overperiod value." hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE ,Value of CVR counter" group.long 0x54++0x3 line.long 0x00 "GPT_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE ,Number of overflow events" group.long 0x58++0x3 line.long 0x00 "GPT_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts" tree.end tree.end tree.end tree.open "Watchdog_Timers" tree.open "WDTIMER3_DSP" tree "WDTIMER3_Cortex_A9" base ad:0x40130000 width 17. rgroup.long 0x0++0x3 line.long 0x00 "WDT_WIDR,IP revision identifier" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "WDT_WDSC,This register controls the various parameters of the L4 interface." bitfld.long 0x00 5. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 3.--4. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "No_action,Initiate_software_reset." rgroup.long 0x14++0x3 line.long 0x00 "WDT_WDST,This register provides status information about the module." bitfld.long 0x00 0. " RESETDONE ,Internal module reset monitoring - . - ." "0,Reset_completed" group.long 0x18++0x3 line.long 0x00 "WDT_WISR,This register shows which interrupt events are pending inside the module." eventfld.long 0x00 1. " DLY_IT_FLAG ,Pending delay interrupt status. - . - . - . - ." "Status_unchanged,Status_bit_cleared" eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status. - . - . - . - ." "Status_unchanged,Status_bit_cleared" group.long 0x1C++0x3 line.long 0x00 "WDT_WIER,This register controls (enable/disable) the interrupt events." bitfld.long 0x00 1. " DLY_IT_ENA ,Delay interrupt enable/disable - . - ." "Disable_delay_interrupt.,Enable_delay_interrupt." bitfld.long 0x00 0. " OVF_IT_ENA ,Overflow interrupt enable/disable - . - ." "0,1" group.long 0x20++0x3 line.long 0x00 "WDT_WWER,This register controls (enable/disable) the wake-up events." bitfld.long 0x00 1. " DLY_WK_ENA ,Delay wake-up enable - . - ." "Disable_delay_wakeup.,Enable_delay_wakeup." bitfld.long 0x00 0. " OVF_WK_ENA ,Overflow wake-up enable - . - ." "Disable_overflow_wakeup.,Enable_overflow_wakeup." group.long 0x24++0x3 line.long 0x00 "WDT_WCLR,This register controls the prescaler stage of the counter." bitfld.long 0x00 5. " PRE ,Prescaler enable/disable configuration - . - ." "Prescaler_disabled,Prescaler_enabled" bitfld.long 0x00 2.--4. " PTV ,Prescaler value The timer counter is prescaled with the value: 2. Example: PTV = 3 -&gt; counter increases value if started after 8 functional clock periods. On reset, it is loaded from PI_PTV_RESET_VALUE input port." "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "WDT_WCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of the timer counter register" group.long 0x2C++0x3 line.long 0x00 "WDT_WLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " TIMER_LOAD ,Value of the timer load register" group.long 0x30++0x3 line.long 0x00 "WDT_WTGR,Writing a different value than the one already written in this register does a watchdog counter reload." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Value of the trigger register" rgroup.long 0x34++0x3 line.long 0x00 "WDT_WWPS,This register contains the write posting bits for all writeable functional registers." bitfld.long 0x00 5. " W_PEND_WDLY ,Write pending for register WDLY - . - ." "0,Register_write_pending" bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR - . - ." "0,Register_write_pending" bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR - . - ." "0,Register_write_pending" textline " " bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR - . - ." "0,Register_write_pending" bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR - . - ." "0,Register_write_pending" bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR - . - ." "0,Register_write_pending" group.long 0x44++0x3 line.long 0x00 "WDT_WDLY,This register holds the delay value that controls the internal pre-overflow event detection." hexmask.long 0x00 0.--31. 1. " WDLY_VALUE ,Value of the delay register" group.long 0x48++0x3 line.long 0x00 "WDT_WSPR,This register holds the start-stop value that controls the internal start-stop FSM." hexmask.long 0x00 0.--31. 1. " WSPR_VALUE ,Value of the start-stop register" group.long 0x54++0x3 line.long 0x00 "WDT_WIRQSTATRAW,IRQ unmasked status, status set per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 1. " EVENT_DLY ,Settable raw status for delay event - . - . - . - ." "No_event_pending,Set_event_(debug)" bitfld.long 0x00 0. " EVENT_OVF ,Settable raw status for overflow event - . - . - . - ." "No_event_pending,Set_event_(debug)" group.long 0x58++0x3 line.long 0x00 "WDT_WIRQSTAT,IRQ masked status, status clear per-event enabled interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if .." eventfld.long 0x00 1. " EVENT_DLY ,Clearable, enabled status for delay event - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 0. " EVENT_OVF ,Clearable, enabled status for overflow event - . - . - . - ." "No_action,Clear_(raw)_event" group.long 0x5C++0x3 line.long 0x00 "WDT_WIRQENSET,IRQ enable set per-event interrupt enable bit vector, line 0. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 1. " ENABLE_DLY ,Enable for delay event - . - . - . - ." "No_action,Enable_interrupt." bitfld.long 0x00 0. " ENABLE_OVF ,Enable for overflow event - . - . - . - ." "No_action,Enable_interrupt." group.long 0x60++0x3 line.long 0x00 "WDT_WIRQENCLR,IRQ enable clear per-event interrupt enable bit vector, line 0. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 1. " ENABLE_DLY ,Enable for delay event - . - . - . - ." "No_action,Disable_interrupt." eventfld.long 0x00 0. " ENABLE_OVF ,Enable for overflow event - . - . - . - ." "No_action,Disable_interrupt." group.long 0x64++0x3 line.long 0x00 "WDT_WIRQWAKEEN,This register controls (enable/disable) the wake-up events." bitfld.long 0x00 1. " DLY_WK_ENA ,Enable delay wake-up - . - ." "Disable_delay_wakeup,Enable_delay_wakeup" bitfld.long 0x00 0. " OVF_WK_ENA ,Enable overflow wakeup - . - ." "Disable_overflow_wakeup,Enable_overflow_wakeup" tree.end tree "WDTIMER3_L3Interconnect" base ad:0x49030000 width 17. rgroup.long 0x0++0x3 line.long 0x00 "WDT_WIDR,IP revision identifier" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "WDT_WDSC,This register controls the various parameters of the L4 interface." bitfld.long 0x00 5. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 3.--4. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "No_action,Initiate_software_reset." rgroup.long 0x14++0x3 line.long 0x00 "WDT_WDST,This register provides status information about the module." bitfld.long 0x00 0. " RESETDONE ,Internal module reset monitoring - . - ." "0,Reset_completed" group.long 0x18++0x3 line.long 0x00 "WDT_WISR,This register shows which interrupt events are pending inside the module." eventfld.long 0x00 1. " DLY_IT_FLAG ,Pending delay interrupt status. - . - . - . - ." "Status_unchanged,Status_bit_cleared" eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status. - . - . - . - ." "Status_unchanged,Status_bit_cleared" group.long 0x1C++0x3 line.long 0x00 "WDT_WIER,This register controls (enable/disable) the interrupt events." bitfld.long 0x00 1. " DLY_IT_ENA ,Delay interrupt enable/disable - . - ." "Disable_delay_interrupt.,Enable_delay_interrupt." bitfld.long 0x00 0. " OVF_IT_ENA ,Overflow interrupt enable/disable - . - ." "0,1" group.long 0x20++0x3 line.long 0x00 "WDT_WWER,This register controls (enable/disable) the wake-up events." bitfld.long 0x00 1. " DLY_WK_ENA ,Delay wake-up enable - . - ." "Disable_delay_wakeup.,Enable_delay_wakeup." bitfld.long 0x00 0. " OVF_WK_ENA ,Overflow wake-up enable - . - ." "Disable_overflow_wakeup.,Enable_overflow_wakeup." group.long 0x24++0x3 line.long 0x00 "WDT_WCLR,This register controls the prescaler stage of the counter." bitfld.long 0x00 5. " PRE ,Prescaler enable/disable configuration - . - ." "Prescaler_disabled,Prescaler_enabled" bitfld.long 0x00 2.--4. " PTV ,Prescaler value The timer counter is prescaled with the value: 2. Example: PTV = 3 -&gt; counter increases value if started after 8 functional clock periods. On reset, it is loaded from PI_PTV_RESET_VALUE input port." "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "WDT_WCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of the timer counter register" group.long 0x2C++0x3 line.long 0x00 "WDT_WLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " TIMER_LOAD ,Value of the timer load register" group.long 0x30++0x3 line.long 0x00 "WDT_WTGR,Writing a different value than the one already written in this register does a watchdog counter reload." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Value of the trigger register" rgroup.long 0x34++0x3 line.long 0x00 "WDT_WWPS,This register contains the write posting bits for all writeable functional registers." bitfld.long 0x00 5. " W_PEND_WDLY ,Write pending for register WDLY - . - ." "0,Register_write_pending" bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR - . - ." "0,Register_write_pending" bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR - . - ." "0,Register_write_pending" textline " " bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR - . - ." "0,Register_write_pending" bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR - . - ." "0,Register_write_pending" bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR - . - ." "0,Register_write_pending" group.long 0x44++0x3 line.long 0x00 "WDT_WDLY,This register holds the delay value that controls the internal pre-overflow event detection." hexmask.long 0x00 0.--31. 1. " WDLY_VALUE ,Value of the delay register" group.long 0x48++0x3 line.long 0x00 "WDT_WSPR,This register holds the start-stop value that controls the internal start-stop FSM." hexmask.long 0x00 0.--31. 1. " WSPR_VALUE ,Value of the start-stop register" group.long 0x54++0x3 line.long 0x00 "WDT_WIRQSTATRAW,IRQ unmasked status, status set per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 1. " EVENT_DLY ,Settable raw status for delay event - . - . - . - ." "No_event_pending,Set_event_(debug)" bitfld.long 0x00 0. " EVENT_OVF ,Settable raw status for overflow event - . - . - . - ." "No_event_pending,Set_event_(debug)" group.long 0x58++0x3 line.long 0x00 "WDT_WIRQSTAT,IRQ masked status, status clear per-event enabled interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if .." eventfld.long 0x00 1. " EVENT_DLY ,Clearable, enabled status for delay event - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 0. " EVENT_OVF ,Clearable, enabled status for overflow event - . - . - . - ." "No_action,Clear_(raw)_event" group.long 0x5C++0x3 line.long 0x00 "WDT_WIRQENSET,IRQ enable set per-event interrupt enable bit vector, line 0. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 1. " ENABLE_DLY ,Enable for delay event - . - . - . - ." "No_action,Enable_interrupt." bitfld.long 0x00 0. " ENABLE_OVF ,Enable for overflow event - . - . - . - ." "No_action,Enable_interrupt." group.long 0x60++0x3 line.long 0x00 "WDT_WIRQENCLR,IRQ enable clear per-event interrupt enable bit vector, line 0. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 1. " ENABLE_DLY ,Enable for delay event - . - . - . - ." "No_action,Disable_interrupt." eventfld.long 0x00 0. " ENABLE_OVF ,Enable for overflow event - . - . - . - ." "No_action,Disable_interrupt." group.long 0x64++0x3 line.long 0x00 "WDT_WIRQWAKEEN,This register controls (enable/disable) the wake-up events." bitfld.long 0x00 1. " DLY_WK_ENA ,Enable delay wake-up - . - ." "Disable_delay_wakeup,Enable_delay_wakeup" bitfld.long 0x00 0. " OVF_WK_ENA ,Enable overflow wakeup - . - ." "Disable_overflow_wakeup,Enable_overflow_wakeup" tree.end tree "WDTIMER2_L4Interconnect" base ad:0x4A314000 width 17. rgroup.long 0x0++0x3 line.long 0x00 "WDT_WIDR,IP revision identifier" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "WDT_WDSC,This register controls the various parameters of the L4 interface." bitfld.long 0x00 5. " EMUFREE ,Emulation mode - . - ." "0,1" bitfld.long 0x00 3.--4. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 1. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "No_action,Initiate_software_reset." rgroup.long 0x14++0x3 line.long 0x00 "WDT_WDST,This register provides status information about the module." bitfld.long 0x00 0. " RESETDONE ,Internal module reset monitoring - . - ." "0,Reset_completed" group.long 0x18++0x3 line.long 0x00 "WDT_WISR,This register shows which interrupt events are pending inside the module." eventfld.long 0x00 1. " DLY_IT_FLAG ,Pending delay interrupt status. - . - . - . - ." "Status_unchanged,Status_bit_cleared" eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status. - . - . - . - ." "Status_unchanged,Status_bit_cleared" group.long 0x1C++0x3 line.long 0x00 "WDT_WIER,This register controls (enable/disable) the interrupt events." bitfld.long 0x00 1. " DLY_IT_ENA ,Delay interrupt enable/disable - . - ." "Disable_delay_interrupt.,Enable_delay_interrupt." bitfld.long 0x00 0. " OVF_IT_ENA ,Overflow interrupt enable/disable - . - ." "0,1" group.long 0x20++0x3 line.long 0x00 "WDT_WWER,This register controls (enable/disable) the wake-up events." bitfld.long 0x00 1. " DLY_WK_ENA ,Delay wake-up enable - . - ." "Disable_delay_wakeup.,Enable_delay_wakeup." bitfld.long 0x00 0. " OVF_WK_ENA ,Overflow wake-up enable - . - ." "Disable_overflow_wakeup.,Enable_overflow_wakeup." group.long 0x24++0x3 line.long 0x00 "WDT_WCLR,This register controls the prescaler stage of the counter." bitfld.long 0x00 5. " PRE ,Prescaler enable/disable configuration - . - ." "Prescaler_disabled,Prescaler_enabled" bitfld.long 0x00 2.--4. " PTV ,Prescaler value The timer counter is prescaled with the value: 2. Example: PTV = 3 -&gt; counter increases value if started after 8 functional clock periods. On reset, it is loaded from PI_PTV_RESET_VALUE input port." "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "WDT_WCRR,This register holds the value of the internal counter." hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER ,Value of the timer counter register" group.long 0x2C++0x3 line.long 0x00 "WDT_WLDR,This register holds the timer load value." hexmask.long 0x00 0.--31. 1. " TIMER_LOAD ,Value of the timer load register" group.long 0x30++0x3 line.long 0x00 "WDT_WTGR,Writing a different value than the one already written in this register does a watchdog counter reload." hexmask.long 0x00 0.--31. 1. " TTGR_VALUE ,Value of the trigger register" rgroup.long 0x34++0x3 line.long 0x00 "WDT_WWPS,This register contains the write posting bits for all writeable functional registers." bitfld.long 0x00 5. " W_PEND_WDLY ,Write pending for register WDLY - . - ." "0,Register_write_pending" bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR - . - ." "0,Register_write_pending" bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR - . - ." "0,Register_write_pending" textline " " bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR - . - ." "0,Register_write_pending" bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR - . - ." "0,Register_write_pending" bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR - . - ." "0,Register_write_pending" group.long 0x44++0x3 line.long 0x00 "WDT_WDLY,This register holds the delay value that controls the internal pre-overflow event detection." hexmask.long 0x00 0.--31. 1. " WDLY_VALUE ,Value of the delay register" group.long 0x48++0x3 line.long 0x00 "WDT_WSPR,This register holds the start-stop value that controls the internal start-stop FSM." hexmask.long 0x00 0.--31. 1. " WSPR_VALUE ,Value of the start-stop register" group.long 0x54++0x3 line.long 0x00 "WDT_WIRQSTATRAW,IRQ unmasked status, status set per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 1. " EVENT_DLY ,Settable raw status for delay event - . - . - . - ." "No_event_pending,Set_event_(debug)" bitfld.long 0x00 0. " EVENT_OVF ,Settable raw status for overflow event - . - . - . - ." "No_event_pending,Set_event_(debug)" group.long 0x58++0x3 line.long 0x00 "WDT_WIRQSTAT,IRQ masked status, status clear per-event enabled interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if .." eventfld.long 0x00 1. " EVENT_DLY ,Clearable, enabled status for delay event - . - . - . - ." "No_action,Clear_(raw)_event" eventfld.long 0x00 0. " EVENT_OVF ,Clearable, enabled status for overflow event - . - . - . - ." "No_action,Clear_(raw)_event" group.long 0x5C++0x3 line.long 0x00 "WDT_WIRQENSET,IRQ enable set per-event interrupt enable bit vector, line 0. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 1. " ENABLE_DLY ,Enable for delay event - . - . - . - ." "No_action,Enable_interrupt." bitfld.long 0x00 0. " ENABLE_OVF ,Enable for overflow event - . - . - . - ." "No_action,Enable_interrupt." group.long 0x60++0x3 line.long 0x00 "WDT_WIRQENCLR,IRQ enable clear per-event interrupt enable bit vector, line 0. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 1. " ENABLE_DLY ,Enable for delay event - . - . - . - ." "No_action,Disable_interrupt." eventfld.long 0x00 0. " ENABLE_OVF ,Enable for overflow event - . - . - . - ." "No_action,Disable_interrupt." group.long 0x64++0x3 line.long 0x00 "WDT_WIRQWAKEEN,This register controls (enable/disable) the wake-up events." bitfld.long 0x00 1. " DLY_WK_ENA ,Enable delay wake-up - . - ." "Disable_delay_wakeup,Enable_delay_wakeup" bitfld.long 0x00 0. " OVF_WK_ENA ,Enable overflow wakeup - . - ." "Disable_overflow_wakeup,Enable_overflow_wakeup" tree.end tree.end tree.end tree.open "_32_kHz_Synchronized_Timer" tree "_32KTimer" base ad:0x4A304000 width 21. rgroup.long 0x0++0x3 line.long 0x00 "32KSYNCNT_REV,This register contains the sync counter IP revision code." hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x4++0x3 line.long 0x00 "32KSYNCNT_SYSCONFIG,This register is used for IDLE modes only." hexmask.long 0x00 5.--31. 1. " Reserved ,Reads return 0." bitfld.long 0x00 3.--4. " IDLEMODE ,Power management REQ/ACK control" "0,1,2,3" bitfld.long 0x00 0.--2. " Reserved ,Reads return 0." "0,1,2,3,4,5,6,7" rgroup.long 0x10++0x3 line.long 0x00 "32KSYNCNT_CR,This register contains the 32-kHz sync counter value." hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE ,Counter register value" tree.end tree.end tree.open "High_Speed_Multiport_USB_Host_Subsystem" tree "OHCI" base ad:0x4A064800 width 20. rgroup.long 0x0++0x3 line.long 0x00 "HCREVISION,OHCI revision number" hexmask.long.byte 0x00 0.--7. 1. " REV ,OHCI specification revision the OHCI revision number upon which the USB host controller is based. Examples: 0x10 for 1.0, 0x21 for 2.1" group.long 0x4++0x3 line.long 0x00 "HCCONTROL,HC operating mode register" bitfld.long 0x00 10. " RWE ,Remote wake-up enable - This bit is used to enable or disable the remote wakeup feature upon detection of upstream resume signaling. . - ." "0,1" bitfld.long 0x00 9. " RWC ,Remote wake-up connected. - This bit indicates whether the host controller supports remote wakeup signaling. . - ." "0,1" bitfld.long 0x00 8. " IR ,Interrupt routing - This bit determines the routing of interrupts generated by events registered in. . - . - . - ." "0,1" textline " " bitfld.long 0x00 6.--7. " HCFS ,Host controller functional state - . - . - . - ." "UsbReset,UsbResume,UsbOper,UsbSusp" bitfld.long 0x00 5. " BLE ,Bulk list processing enable - . - ." "BLE_0,BLE_1" bitfld.long 0x00 4. " CLE ,Control list processing enable - . - ." "CLE_ctrl,CLE_en" textline " " bitfld.long 0x00 3. " IE ,Isochronous ED processing enabled by host controller driver - . - ." "IE_notprss,IE_prss" bitfld.long 0x00 2. " PLE ,Periodic list enable - . - ." "PLE_notprss,PLE_prss" bitfld.long 0x00 0.--1. " CBSR ,Control/bulk service ratio. Specifies the ratio between control and bulk EDs processed in a frame. - . - . - . - ." "OneCntED,TwoCntED,ThreeCntED,FourCntED" group.long 0x8++0x3 line.long 0x00 "HCCOMMANDSTATUS,HC command and status" bitfld.long 0x00 16.--17. " SOC ,Scheduling overrun count - This is used to monitor any persistent scheduling problems. . - . - These bits are incremented on each scheduling overrun error. It is initialized to 0x0 and wraps around at 0x3. . - ." "0,1,2,3" bitfld.long 0x00 3. " OCR ,Ownership change request. - This bit is set to request a change of control of the host controller. . - ." "0,1" bitfld.long 0x00 2. " BLF ,Bulk list filled - This bit is used to indicate whether there are any TDs on the bulk list. It is set whenever it adds a TD to an ED in the bulk list. . - ." "0,1" textline " " bitfld.long 0x00 1. " CLF ,Control list filled - This bit is used to indicate whether there are any TDs on the control list. It is set whenever it adds a TD to an ED in the control list. . - ." "0,1" bitfld.long 0x00 0. " HCR ,Host controller reset (software reset). Set this bit to initiate a USB host controller reset. This resets most USB host controller OHCI registers. OHCI register accesses must not be attempted until a read of this register returns a.." "HCR_0,HCR_1" group.long 0xC++0x3 line.long 0x00 "HCINTERRUPTSTATUS,HC interrupt status" bitfld.long 0x00 30. " OC ,Ownership change - This bit is set when the[3] OCR bit is set. . - . - . - . - ." "0,1" bitfld.long 0x00 6. " RHSC ,Root hub status change When 0x1: A root hub status change has occurred. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" bitfld.long 0x00 5. " FNO ,Frame number overflow When 0x1: A frame number overflow has occurred. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" textline " " bitfld.long 0x00 4. " UE ,Unrecoverable error When 0x1: An unrecoverable error has occurred. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" bitfld.long 0x00 3. " RD ,Resume detected When 0x1: A downstream device has issued a resume request. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" bitfld.long 0x00 2. " SF ,Start of frame When 0x1: A SOF has been issued. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" textline " " bitfld.long 0x00 1. " WDH ,Write done head When 0x1: The USB host controller has updated the HCDONEHEAD register. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" bitfld.long 0x00 0. " SO ,Scheduling overrun When 0x1: A scheduling overrun has occurred. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" group.long 0x10++0x3 line.long 0x00 "HCINTERRUPTENABLE,HC interrupt enable" bitfld.long 0x00 31. " MIE ,Master interrupt enable When 0x1: Allows other enabled OHCI interrupt sources to propagate to the device interrupt controller When 0x0: OHCI interrupt sources are ignored. Write 0x0: No effect Write 0x1: Sets this bit" "0,1" bitfld.long 0x00 30. " OC ,Ownership change - . - ." "0,1" bitfld.long 0x00 6. " RHSC ,Root hub status change When 0x1 and MIE is 0x1: Allows root hub status change interrupts to propagate to the device interrupt controller When 0x0 or MIE is 0x0: Root hub status change interrupts do not propagate. Write 0x0: No effe.." "0,1" textline " " bitfld.long 0x00 5. " FNO ,Frame number overflow When 0x1 and MIE is 0x1: Allows FNO interrupts to propagate to the device interrupt controller When 0x0 or MIE is 0x0: FNO interrupts do not propagate. Write 0x0: No effect Write 0x1: Sets this bit" "0,1" bitfld.long 0x00 4. " UE ,Unrecoverable error When 0x1 and MIE is 0x1: Allows UE interrupts to propagate to the device interrupt controller When 0x0 or MIE is 0x0: UE interrupts do not propagate. Write 0x0: No effect Write 0x1: Sets this bit" "0,1" bitfld.long 0x00 3. " RD ,Resume detected When 0x1 and MIE is 0x1: Allows RD interrupts to propagate to the device interrupt controller When 0x0 or MIE is 0x0: RD interrupts do not propagate. Write 0x0: No effect Write 0x1: Sets this bit" "0,1" textline " " bitfld.long 0x00 2. " SF ,Start of frame When 0x1 and MIE is 0x1: Allows SF interrupts to propagate to the device interrupt controller When 0x0 or MIE is 0x0: SF interrupts do not propagate. Write 0x0: No effect Write 0x1: Sets this bit" "0,1" bitfld.long 0x00 1. " WDH ,Write done head When 0x1 and MIE is 0x1: Allows WDH interrupts to propagate to the device interrupt controller When 0x0 or MIE is 0x0: WDH interrupts do not propagate. Write 0x0: No effect Write 0x1: Sets this bit" "0,1" bitfld.long 0x00 0. " SO ,Scheduling overrun When 0x1 and MIE is 0x1: Allows SO interrupts to propagate to the device interrupt controller When 0x0 or MIE is 0x0: SO interrupts do not propagate. Write 0x0: No effect Write 0x1: Sets this bit" "0,1" group.long 0x14++0x3 line.long 0x00 "HCINTERRUPTDISABLE,HC interrupt disable" bitfld.long 0x00 31. " MIE ,Master interrupt enable Always reads 0x0. Write 0x0: No effect Write 0x1: Clears the HCINTERRUPTENABLE MIE bit" "0,1" bitfld.long 0x00 30. " OC ,Ownership change. - . - ." "0,1" bitfld.long 0x00 6. " RHSC ,Root hub status change Always reads 0x0. Write 0x0: No effect Write 0x1: Clears the HCINTERRUPTENABLE RHSC bit" "0,1" textline " " bitfld.long 0x00 5. " FNO ,Frame number overflow Always reads 0x0. Write 0x0: No effect Write 0x1: Clears the HCINTERRUPTENABLE FNO bit" "0,1" bitfld.long 0x00 4. " UE ,Unrecoverable error Always reads 0x0. Write 0x0: No effect Write 0x1: Clears the HCINTERRUPTENABLE UE bit" "0,1" bitfld.long 0x00 3. " RD ,Resume detected Always reads 0x0. Write 0x0: No effect Write 0x1: Clears the HCINTERRUPTENABLE RD bit" "0,1" textline " " bitfld.long 0x00 2. " SF ,Start of frame Always reads 0x0. Write 0x0: No effect Write 0x1: Clears the HCINTERRUPTENABLE SF bit" "0,1" bitfld.long 0x00 1. " WDH ,Write done head Always reads 0x0. Write 0x0: No effect Write 0x1: Clears the HCINTERRUPTENABLE WDH bit" "0,1" bitfld.long 0x00 0. " SO ,Scheduling overrun Always reads 0x0. Write 0x0: No effect Write 0x1: Clears the HCINTERRUPTENABLE SO bit" "0,1" group.long 0x18++0x3 line.long 0x00 "HCHCCA,HC HCCA address register" hexmask.long.tbyte 0x00 8.--31. 1. " HCCA ,Physical address of the beginning of the HCCA" rgroup.long 0x1C++0x3 line.long 0x00 "HCPERIODCURRENTED,HC current periodic register" hexmask.long 0x00 4.--31. 1. " PCED ,Physical address of current ED on the periodic ED list" group.long 0x20++0x3 line.long 0x00 "HCCONTROLHEADED,HC head control register" hexmask.long 0x00 4.--31. 1. " CHED ,Physical address of head ED on the control ED list" group.long 0x24++0x3 line.long 0x00 "HCCONTROLCURRENTED,HC current control register" hexmask.long 0x00 4.--31. 1. " CCED ,Physical address of current ED on the control ED list" group.long 0x28++0x3 line.long 0x00 "HCBULKHEADED,HC head bulk register" hexmask.long 0x00 4.--31. 1. " BHED ,Physical address of head ED on the bulk ED list" group.long 0x2C++0x3 line.long 0x00 "HCBULKCURRENTED,HC current bulk register" hexmask.long 0x00 4.--31. 1. " BCED ,Physical address of current ED on the bulk ED list" rgroup.long 0x30++0x3 line.long 0x00 "HCDONEHEAD,HC head done register" hexmask.long 0x00 4.--31. 1. " DH ,Physical address of last TD that was added to the Done queue" group.long 0x34++0x3 line.long 0x00 "HCFMINTERVAL,HC frame interval register" bitfld.long 0x00 31. " FIT ,Frame interval toggle - This bit is toggled whenever it loads a new value to FI. . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " FSMPS ,Largest data packet size for full-speed packets, bit times - This field specifies a value which is loaded into the largest data packet counter at the beginning of each frame. . - ." hexmask.long.word 0x00 0.--13. 1. " FI ,Frame interval. Number of 12-MHz clocks in the USB frame. The nominal value is set to 11,999, to give a 1-ms frame." rgroup.long 0x38++0x3 line.long 0x00 "HCFMREMAINING,HC frame remaining register" bitfld.long 0x00 31. " FRT ,Frame remaining toggleThis bit is used for the synchronization between[13:0] FI and FR.. - . - This bit is loaded from the[31] FIT bit whenever FR reaches 0. . - ." "0,1" hexmask.long.word 0x00 0.--13. 1. " FR ,Frame remainingThis counter is decremented at each bit time. When it reaches 0, it is reset by loading the value of the USBHOST.[13:0] FI bit field at the next bit time boundary.. - ." rgroup.long 0x3C++0x3 line.long 0x00 "HCFMNUMBER,HC frame number register" hexmask.long.word 0x00 0.--15. 1. " FN ,Frame number - This is incremented when is reloaded. It is rolled over to 0x0000 after 0xFFFF. . - ." group.long 0x40++0x3 line.long 0x00 "HCPERIODICSTART,HC periodic start register" hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic start. The host controller driver must program this value to be about 10 percent less than the frame interval field value so that control and bulk EDs have priority for the first 10 percent of the frame; then periodic EDs have priori.." group.long 0x44++0x3 line.long 0x00 "HCLSTHRESHOLD,HC low-speed threshold register" hexmask.long.word 0x00 0.--11. 1. " LST ,Low-speed threshold" group.long 0x48++0x3 line.long 0x00 "HCRHDESCRIPTORA,HC root hub A register" hexmask.long.byte 0x00 24.--31. 1. " POTPG ,Power-on to power-good time. Defines the minimum amount of time (2 ms * POTPG) between the USB host controller turning on power to a downstream port and when the USB host can access the downstream device." bitfld.long 0x00 12. " NOCP ,No overcurrent protection. This function is not supported at the device level. - . - ." "NOCP_0,NOCP_1" bitfld.long 0x00 11. " OCPM ,Overcurrent protection mode. This function is not supported at the device level." "0,1" textline " " bitfld.long 0x00 10. " DT ,Device type Always reads 0x0: Indicates that the USB host controller implemented is not a compound device." "0,1" bitfld.long 0x00 9. " NPS ,No power switching - . - ." "VbPowSwSup,VbPowSwNSup" bitfld.long 0x00 8. " PSM ,Power switching mode - . - ." "APoPwSTime,InPorPowSw" textline " " hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number of downstream ports These bits specify the number of downstream ports supported by the root hub. It is implementation-specific. The minimum number of ports is 1. The maximum number of ports supported by OHCI is 15." group.long 0x4C++0x3 line.long 0x00 "HCRHDESCRIPTORB,HC root hub B register" hexmask.long.word 0x00 16.--31. 1. " PPCM ,Port power control mask. Each bit defines whether a corresponding downstream port has port power controlled by the global power control. When set, the port's power state is only affected by per-port power control. When cleared, the port is co.." hexmask.long.word 0x00 0.--15. 1. " DR ,Device removable. Each bit defines whether a corresponding downstream port has a removable device. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 0: Reserved, bit 1: Device attached.." group.long 0x50++0x3 line.long 0x00 "HCRHSTATUS,HC root hub status register" bitfld.long 0x00 31. " CRWE ,Clear remote wakeup enable Write 0x0: No effect Write 0x1: Clears the device remote wake-up enable bit" "0,1" bitfld.long 0x00 16. " LPSC ,Local power status change Always reads 0x0: The root hub does not support the local power status feature. Write 0x0: No effect Write 0x1: Sets port power status bits for all ports, if power switching mode is 0. Sets port power stat.." "0,1" bitfld.long 0x00 15. " DRWE ,Device remote wake-up enable. Enables a connect status change event as a resume event, causing a USB suspend to USB resume state transition and sets the resume detected interrupt status bit. Read 0x1: Connect status change is a rem.." "0,1" textline " " bitfld.long 0x00 0. " LPS ,Local power status Always reads 0x0 Write 0x0: No effect Write 0x1: When in global power mode (power switching mode = 0), turns off power to all ports. If in per-port power mode (power switching mode = 1), turns of power to those ports whose .." "0,1" group.long 0x54++0x3 line.long 0x00 "HCRHPORTSTATUS_1,HC port 1 status and control register" bitfld.long 0x00 20. " PRSC ,Port 1 reset status change. This bit is set when the port 1 port reset status bit has changed. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" bitfld.long 0x00 18. " PSSC ,Port 1 suspends status change. Set when the port leaves the suspend state; that is, after the full resume sequence has completed. - . - . - . - ." "0,1" bitfld.long 0x00 17. " PESC ,Port 1 enable status change. This bit is set when the port 1 port enable status has changed. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" textline " " bitfld.long 0x00 16. " CSC ,Port 1 connect status change. This bit is set when the port1 port current connect status has changed due to a connect or disconnect event. If current connect status is 0 when a set port reset, set port enable, or set port suspend write occurs.." "0,1" bitfld.long 0x00 9. " LSDA_CPP ,Port 1 low-speed device attached/clear port power. This bit is valid only when port 1 current connect status is 1. Read 0x0: A full-speed device is attached to port 1. Read 0x1: A low-speed device is attached to port 1. Write 0x0: .." "0,1" bitfld.long 0x00 8. " PPS_SPP ,Port 1 port power status/set port power Read 0x0: Port 1 power is enabled. Read 0x1: Port 1 power is not enabled. Write 0x0: No effect Write 0x1: Sets the port 1 port power status bit" "0,1" textline " " bitfld.long 0x00 4. " PRS_SPR ,Port 1 port reset status/set port reset Read 0x0: USB reset is not being sent to port 1. Read 0x1: Port 1 is signaling the USB reset. Write 0x0: No effect Write 0x1: Sets the port 1 port reset status bit and causes the USB host controller to .." "0,1" bitfld.long 0x00 2. " PSS_SPS ,Port 1 port suspend status/set port suspend. This bit is cleared automatically at the end of the USB resume sequence and also at the end of the USB reset sequence. Write 0x0: No effect Read 0x0: Port 1 is not in the USB suspend sta.." "0,1" bitfld.long 0x00 1. " PES_SPE ,Port 1 port enable status/set port enable. This bit is automatically set at completion of port 1 USB reset if it was not already set before the USB reset completed, and is automatically set at the end of a USB suspend if the port w.." "0,1" textline " " bitfld.long 0x00 0. " CCS_CPE ,Port 1 current connection status/clear port enable Read 0x0: No USB device is attached to port 1. Read 0x1: A USB device is currently attached to port 1. Write 0x0: No effect Write 0x1: Clears the port 1 port enable bit Note: This bit is set .." "0,1" group.long 0x58++0x3 line.long 0x00 "HCRHPORTSTATUS_2,HC port 2 status and control register" bitfld.long 0x00 20. " PRSC ,Port 2 reset status change. This bit is set when the port 2 port reset status bit has changed. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" bitfld.long 0x00 18. " PSSC ,Port 2 suspend status change. Set when the port leaves the suspend state; that is, after the full resume sequence has completed. - . - . - . - ." "0,1" bitfld.long 0x00 17. " PESC ,Port 2 enable status change. This bit is set when the port 2 port enable status has changed. Write 0x0: No effect Write 0x1: Clears this bit" "0,1" textline " " bitfld.long 0x00 16. " CSC ,Port 2 connect status change. This bit is set when the port 2 port current connect status has changed due to a connect or disconnect event. If current connect status is 0 when a set port reset, set port enable, or set port suspend write occur.." "0,1" bitfld.long 0x00 9. " LSDA_CPP ,Port 2 low-speed device attached/clear port power. This bit is valid only when port 2 current connect status is 1. Read 0x0: A full-speed device is attached to port 2. Read 0x1: A low-speed device is attached to port 2. Write 0x0: .." "0,1" bitfld.long 0x00 8. " PPS_SPP ,Port 2 port power status/set port power Read 0x0: Port 2 power is enabled. Read 0x1: Port 2 power is not enabled. Write 0x0: No effect Write 0x1: Sets the port 2 port power status bit" "0,1" textline " " bitfld.long 0x00 4. " PRS_SPR ,Port 2 port reset status/set port reset Read 0x0: USB reset is not being sent to port 2. Read 0x1: Port 2 is signaling the USB reset. Write 0x0: No effect Write 0x1: Sets the port 2 port reset status bit and causes the USB host controller to .." "0,1" bitfld.long 0x00 2. " PSS_SPS ,Port 2 port suspend status/set port suspend. This bit is cleared automatically at the end of the USB resume sequence and also at the end of the USB reset sequence. Write 0x0: No effect Read 0x0: Port 2 is not in the USB suspend sta.." "0,1" bitfld.long 0x00 1. " PES_SPE ,Port 2 port enable status/set port enable. This bit is automatically set at completion of port 2 USB reset if it was not already set before the USB reset completed, and is automatically set at the end of a USB suspend if the port w.." "0,1" textline " " bitfld.long 0x00 0. " CCS_CPE ,Port 2 current connection status/clear port enable Read 0x0: No USB device is attached to port 2. Read 0x1: A USB device is currently attached to port 2. Write 0x0: No effect Write 0x1: Clears the port 2 port enable bit This bit is set to 1 i.." "0,1" tree.end tree "EHCI" base ad:0x4A064C00 tree "Channel_0" width 12. group.long 0x54++0x3 line.long 0x00 "PORTSC_i_0,Port status/control" hexmask.long.byte 0x00 25.--31. 1. " DEVICEADDRESS ,The USB device address for the device attached to and immediately downstream from the associated root port. R/W only if LPM is enabled; otherwise, R." bitfld.long 0x00 23.--24. " SUSPENDSTATUS ,Addition for LPM support.Indicates status of L1 suspend request:. - . - . - . - . - ." "Success,Not_yet,Not_supported,Time-out/error" bitfld.long 0x00 21. " WDE ,Wake on disconnect enable - This field is 0 if the PP bit is 0. . - . - ." "0,1" textline " " bitfld.long 0x00 20. " WCE ,Wake on connect enable - This field is 0 if the PP bit is 0. . - . - ." "0,1" bitfld.long 0x00 16.--19. " PTC ,Port test controlThe port is operating in specific test modes as indicated by the specific value. The encoding of the test mode bits are:. - . - . - . - . - . - . - . Others: Reserved. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PIC ,Port indicator control (not implemented)" "0,1,2,3" textline " " bitfld.long 0x00 13. " PO ,Port owner - This bit unconditionally goes to 0x0 when the USBHOST.[0] CF bit makes a transition from 0 to 1. This bit unconditionally goes to 0 whenever the USBHOST.[0] CF bit is 0. . - . - ." "0,1" bitfld.long 0x00 12. " PP ,Port powerThe function of this bit depends on the value of the USBHOST.[4] PPC bit. The behavior is as follows:. - . - PPC PP Operation . - . - 0x0 0x0 Forbidden . - . - 0x0 0x1 Host controller does not have port power. .." "0,1" bitfld.long 0x00 10.--11. " LS ,Line statusThese bits reflect the current logical levels of the D+ (bit 11) and D? (bit 10) signal lines. This field is valid only when the port enable bit is 0 and the current connect status bit is set to 1. The encoding of the bit.." "0,1,2,3" textline " " bitfld.long 0x00 9. " SUSPENDL1 ,When this bit is set to 1, an LPM token is generated. - . - ." "Suspend_using_L2,1" bitfld.long 0x00 8. " PR ,Port reset - This field is 0 if the PP bit is 0. . - . - . - . - . Write 0x1 when at 0x0: The bus reset sequence is started.. - ." "0,1" bitfld.long 0x00 7. " SUS ,Suspend - This field is 0 if the PP bit is 0. . - . 0x0 when PED = 0x1: Port enabled. - . 0x1 when PED = 0x1: Port in suspend state. - . - ." "0,1" textline " " bitfld.long 0x00 6. " FPR ,Force port resume - This field is 0 if the PP bit is 0. . - . - . - ." "0,1" bitfld.long 0x00 3. " PEDC ,Port enabled/disabled change - This field is 0 if the PP bit is 0. . - . - . - . - ." "0,1" bitfld.long 0x00 2. " PED ,Port enabled/disabled - Software cannot enable a port by setting this bit to 1. The host controller only sets this to 1 when the reset sequence determines that the attached device is a high-speed device. . - . - Ports can be disable.." "0,1" textline " " bitfld.long 0x00 1. " CSC ,Connect status change - Indicates a change has occurred in the port CCS bit. . - . - This field is 0 if the PP bit is 0. . - . - . - . - ." "0,1" bitfld.long 0x00 0. " CCS ,Current connect status - This value reflects the current state of the port, and may not correspond directly to the event that caused the CSC bit to be set. . - . - This field is 0 if the PP bit is 0. . - . - . - ." "0,1" group.long 0x58++0x3 line.long 0x00 "PORTSC_i_1,Port status/control" hexmask.long.byte 0x00 25.--31. 1. " DEVICEADDRESS ,The USB device address for the device attached to and immediately downstream from the associated root port. R/W only if LPM is enabled; otherwise, R." bitfld.long 0x00 23.--24. " SUSPENDSTATUS ,Addition for LPM support.Indicates status of L1 suspend request:. - . - . - . - . - ." "Success,Not_yet,Not_supported,Time-out/error" bitfld.long 0x00 21. " WDE ,Wake on disconnect enable - This field is 0 if the PP bit is 0. . - . - ." "0,1" textline " " bitfld.long 0x00 20. " WCE ,Wake on connect enable - This field is 0 if the PP bit is 0. . - . - ." "0,1" bitfld.long 0x00 16.--19. " PTC ,Port test controlThe port is operating in specific test modes as indicated by the specific value. The encoding of the test mode bits are:. - . - . - . - . - . - . - . Others: Reserved. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PIC ,Port indicator control (not implemented)" "0,1,2,3" textline " " bitfld.long 0x00 13. " PO ,Port owner - This bit unconditionally goes to 0x0 when the USBHOST.[0] CF bit makes a transition from 0 to 1. This bit unconditionally goes to 0 whenever the USBHOST.[0] CF bit is 0. . - . - ." "0,1" bitfld.long 0x00 12. " PP ,Port powerThe function of this bit depends on the value of the USBHOST.[4] PPC bit. The behavior is as follows:. - . - PPC PP Operation . - . - 0x0 0x0 Forbidden . - . - 0x0 0x1 Host controller does not have port power. .." "0,1" bitfld.long 0x00 10.--11. " LS ,Line statusThese bits reflect the current logical levels of the D+ (bit 11) and D? (bit 10) signal lines. This field is valid only when the port enable bit is 0 and the current connect status bit is set to 1. The encoding of the bit.." "0,1,2,3" textline " " bitfld.long 0x00 9. " SUSPENDL1 ,When this bit is set to 1, an LPM token is generated. - . - ." "Suspend_using_L2,1" bitfld.long 0x00 8. " PR ,Port reset - This field is 0 if the PP bit is 0. . - . - . - . - . Write 0x1 when at 0x0: The bus reset sequence is started.. - ." "0,1" bitfld.long 0x00 7. " SUS ,Suspend - This field is 0 if the PP bit is 0. . - . 0x0 when PED = 0x1: Port enabled. - . 0x1 when PED = 0x1: Port in suspend state. - . - ." "0,1" textline " " bitfld.long 0x00 6. " FPR ,Force port resume - This field is 0 if the PP bit is 0. . - . - . - ." "0,1" bitfld.long 0x00 3. " PEDC ,Port enabled/disabled change - This field is 0 if the PP bit is 0. . - . - . - . - ." "0,1" bitfld.long 0x00 2. " PED ,Port enabled/disabled - Software cannot enable a port by setting this bit to 1. The host controller only sets this to 1 when the reset sequence determines that the attached device is a high-speed device. . - . - Ports can be disable.." "0,1" textline " " bitfld.long 0x00 1. " CSC ,Connect status change - Indicates a change has occurred in the port CCS bit. . - . - This field is 0 if the PP bit is 0. . - . - . - . - ." "0,1" bitfld.long 0x00 0. " CCS ,Current connect status - This value reflects the current state of the port, and may not correspond directly to the event that caused the CSC bit to be set. . - . - This field is 0 if the PP bit is 0. . - . - . - ." "0,1" group.long 0x5C++0x3 line.long 0x00 "PORTSC_i_2,Port status/control" hexmask.long.byte 0x00 25.--31. 1. " DEVICEADDRESS ,The USB device address for the device attached to and immediately downstream from the associated root port. R/W only if LPM is enabled; otherwise, R." bitfld.long 0x00 23.--24. " SUSPENDSTATUS ,Addition for LPM support.Indicates status of L1 suspend request:. - . - . - . - . - ." "Success,Not_yet,Not_supported,Time-out/error" bitfld.long 0x00 21. " WDE ,Wake on disconnect enable - This field is 0 if the PP bit is 0. . - . - ." "0,1" textline " " bitfld.long 0x00 20. " WCE ,Wake on connect enable - This field is 0 if the PP bit is 0. . - . - ." "0,1" bitfld.long 0x00 16.--19. " PTC ,Port test controlThe port is operating in specific test modes as indicated by the specific value. The encoding of the test mode bits are:. - . - . - . - . - . - . - . Others: Reserved. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PIC ,Port indicator control (not implemented)" "0,1,2,3" textline " " bitfld.long 0x00 13. " PO ,Port owner - This bit unconditionally goes to 0x0 when the USBHOST.[0] CF bit makes a transition from 0 to 1. This bit unconditionally goes to 0 whenever the USBHOST.[0] CF bit is 0. . - . - ." "0,1" bitfld.long 0x00 12. " PP ,Port powerThe function of this bit depends on the value of the USBHOST.[4] PPC bit. The behavior is as follows:. - . - PPC PP Operation . - . - 0x0 0x0 Forbidden . - . - 0x0 0x1 Host controller does not have port power. .." "0,1" bitfld.long 0x00 10.--11. " LS ,Line statusThese bits reflect the current logical levels of the D+ (bit 11) and D? (bit 10) signal lines. This field is valid only when the port enable bit is 0 and the current connect status bit is set to 1. The encoding of the bit.." "0,1,2,3" textline " " bitfld.long 0x00 9. " SUSPENDL1 ,When this bit is set to 1, an LPM token is generated. - . - ." "Suspend_using_L2,1" bitfld.long 0x00 8. " PR ,Port reset - This field is 0 if the PP bit is 0. . - . - . - . - . Write 0x1 when at 0x0: The bus reset sequence is started.. - ." "0,1" bitfld.long 0x00 7. " SUS ,Suspend - This field is 0 if the PP bit is 0. . - . 0x0 when PED = 0x1: Port enabled. - . 0x1 when PED = 0x1: Port in suspend state. - . - ." "0,1" textline " " bitfld.long 0x00 6. " FPR ,Force port resume - This field is 0 if the PP bit is 0. . - . - . - ." "0,1" bitfld.long 0x00 3. " PEDC ,Port enabled/disabled change - This field is 0 if the PP bit is 0. . - . - . - . - ." "0,1" bitfld.long 0x00 2. " PED ,Port enabled/disabled - Software cannot enable a port by setting this bit to 1. The host controller only sets this to 1 when the reset sequence determines that the attached device is a high-speed device. . - . - Ports can be disable.." "0,1" textline " " bitfld.long 0x00 1. " CSC ,Connect status change - Indicates a change has occurred in the port CCS bit. . - . - This field is 0 if the PP bit is 0. . - . - . - . - ." "0,1" bitfld.long 0x00 0. " CCS ,Current connect status - This value reflects the current state of the port, and may not correspond directly to the event that caused the CSC bit to be set. . - . - This field is 0 if the PP bit is 0. . - . - . - ." "0,1" tree.end textline "" width 18. rgroup.long 0x0++0x3 line.long 0x00 "HCCAPBASE,Host controller capability register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,Interface version number. It contains a BCD encoding of the EHCI revision number supported by this host controller.[7:4] Major revision. - . [3:0] Minor revision. - ." hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability register length" rgroup.long 0x4++0x3 line.long 0x00 "HCSPARAMS,Host controller structural parameters" bitfld.long 0x00 16. " P_INDICATOR ,Port indicator support indication - This bit indicates whether the ports support port indicator control. . - . - ." "0,1" bitfld.long 0x00 12.--15. " N_CC ,Number of companion controllers - This field indicates the number of companion controllers associated with this USB 2.0 host controller. . - . - . Others: There are companion USB 1.1 host controller(s). Port-ownership.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " N_PCC ,Number of ports per companion controller - This field indicates the number of ports supported per companion host controller. It is used to indicate the port routing configuration to system software. . - . - For example, if N_PORTS ha.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " PRR ,Port routing rules - The first N_PCC ports are routed to the lowest-numbered function companion host controller, the next N_PCC ports are routed to the next lowest-function companion controller, and so on. . - ." "0,1" bitfld.long 0x00 4. " PPC ,Port power control - This field indicates whether the host controller implementation includes port power control. . - . - . - ." "0,1" bitfld.long 0x00 0.--3. " N_PORTS ,Number of downstream ports - This field specifies the number of physical downstream ports implemented on this host controller. . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x8++0x3 line.long 0x00 "HCCPARAMS,Host controller capability parameters" bitfld.long 0x00 17. " LPM ,Link power management capability - . - ." "0,1" hexmask.long.byte 0x00 8.--15. 1. " EECP ,EHCI extended capabilities pointer - This field indicates the existence of a capabilities list. . - . - . Others: The offset in PCI configuration space of the first EHCI extended capability.. - ." bitfld.long 0x00 4.--7. " IST ,Isochronous scheduling threshold - This field indicates where software can reliably update the isochronous schedule in relation to the current position of the executing host controller. . - . - The host controller can hold one microf.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 2. " ASPC ,Asynchronous schedule park capability - . The feature can be disabled or enabled and set to a specific level by using the USBHOST.[11]ASPME bit and the USBHOST.[9:8] ASPMC bit field.. - ." "0,1" bitfld.long 0x00 1. " PFLF ,Programmable frame list flag - . - ." "0,1" bitfld.long 0x00 0. " BIT64AC ,64-bit addressing capability - This field documents the addressing range capability of this implementation. . - . - . - ." "0,1" group.long 0x10++0x3 line.long 0x00 "USBCMD,USB command" bitfld.long 0x00 24.--27. " HIRD ,Host-initiated resume duration. - If LPM is enabled, this field is RW; otherwise, it is R. . - . The minimum for K-state during resume from LPM:. - . - . - Each increment adds 75 ?s. . - ." "50_?s,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control - This field is used by the system software to select the maximum rate at which the host controller issues interrupts. The only valid values are defined below. If software writes an invalid val.." bitfld.long 0x00 11. " ASPME ,Asynchronous schedule park mode enable - . - ." "0,1" textline " " bitfld.long 0x00 8.--9. " ASPMC ,Asynchronous schedule park mode count - It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the asynchronous schedule before continuing traversal of the .." "0,1,2,3" bitfld.long 0x00 7. " LHCR ,Light host controller reset - It allows the driver to reset the EHCI controller without affecting the state of the ports or the relationship to the companion host controllers. . - . - . - ." "0,1" bitfld.long 0x00 6. " IAAD ,Interrupt on async advance doorbell - This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. . - . - . - Software must not write 1 to this bit wh.." "0,1" textline " " bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable - This bit controls whether the host controller skips processing the asynchronous schedule. . - . - . - ." "0,1" bitfld.long 0x00 4. " PSE ,Periodic schedule enable - This bit controls whether the host controller skips processing the periodic schedule. . - . - . - ." "0,1" bitfld.long 0x00 2.--3. " FLS ,Frame list size - This field specifies the size of the frame list. The size of the frame list controls which bits in the frame index register should be used for the frame list current index. . - . - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 1. " HCR ,Host controller reset - This control bit is used by software to reset the host controller. Write . - . - . - This bit is set to 0 by the host controller when the reset process is complete. . - ." "0,1" bitfld.long 0x00 0. " RS ,Run/stop - . - ." "0,1" group.long 0x14++0x3 line.long 0x00 "USBSTS,USB status" bitfld.long 0x00 15. " ASS ,Asynchronous schedule status - The bit reports the current real status of the asynchronous schedule. . - . - . - ." "0,1" bitfld.long 0x00 14. " PSS ,Periodic schedule status - The bit reports the current real status of the periodic schedule. . - . - . - ." "0,1" bitfld.long 0x00 13. " REC ,Reclamation - It is used to detect an empty asynchronous schedule. . - ." "0,1" textline " " bitfld.long 0x00 12. " HCH ,Host controller halted - This bit is a 0 whenever the USBHOST.[0] RS bit is a 1. The host controller sets this bit to 1 after it has stopped executing as a result of the RS bit being set to 0, either by software or by the host controlle.." "0,1" bitfld.long 0x00 5. " IAA ,Interrupt on async advance - System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by setting the USBHOST.[6] IAAD bit to 1. This stat.." "0,1" bitfld.long 0x00 4. " HSE ,Host system error - The host controller sets this bit to 1 when a serious error occurs during a host system access involving the host controller module. . - ." "0,1" textline " " bitfld.long 0x00 3. " FLR ,Frame list rollover - The host controller sets this bit to 1 when the USBHOST. rolls over from its maximum value to 0. The exact value at which the rollover occurs depends on the frame list size. . - ." "0,1" bitfld.long 0x00 2. " PCD ,Port change detect - The host controller sets this bit to 1 when any port for which the USBHOST.[13] PO bit is set to 0 has a change bit transition from 0 to 1 or a USBHOST.[6] FPR bit transition from 0 to 1. . - . - .." "0,1" bitfld.long 0x00 1. " USBEI ,USB error interrupt - The host controller sets this bit to 1 when completion of a USB transaction results in an error condition. . - ." "0,1" textline " " bitfld.long 0x00 0. " USBI ,USB interrupt - The host controller sets this bit to 1 on completion of a USB transaction, which results in the retirement of a transfer descriptor that had its IOC bit set. . - . - The host controller also sets this bit to 1 when a sho.." "0,1" group.long 0x18++0x3 line.long 0x00 "USBINTR,USB interrupt enable" bitfld.long 0x00 5. " IAAE ,Interrupt on async advance enable - ." "0,1" bitfld.long 0x00 4. " HSEE ,Host system error enable - ." "0,1" bitfld.long 0x00 3. " FLRE ,Frame list rollover enable - ." "0,1" textline " " bitfld.long 0x00 2. " PCIE ,Port change interrupt enable - ." "0,1" bitfld.long 0x00 1. " USBEIE ,USB error interrupt enable - ." "0,1" bitfld.long 0x00 0. " USBIE ,USB interrupt enable - ." "0,1" group.long 0x1C++0x3 line.long 0x00 "FRINDEX,USB frame index" hexmask.long.word 0x00 0.--13. 1. " FI ,Frame index - The value in this register is incremented at the end of each time frame. . - ." rgroup.long 0x20++0x3 line.long 0x00 "CTRLDSSEGMENT,4G segment selector" hexmask.long 0x00 0.--31. 1. " CDSS ,This 32-bit register corresponds to the most-significant address bits [63:32] for all EHCI data structures." group.long 0x24++0x3 line.long 0x00 "PERIODICLISTBASE,Frame list base address" hexmask.long.tbyte 0x00 12.--31. 1. " BAL ,Base address (low) - These bits correspond to memory address signals. . - ." group.long 0x28++0x3 line.long 0x00 "ASYNCLISTADDR,Next asynchronous list address" hexmask.long 0x00 5.--31. 1. " LPL ,Link pointer low - It contains the address of the next asynchronous queue head to be executed. . - ." group.long 0x50++0x3 line.long 0x00 "CONFIGFLAG,Configured flag register" bitfld.long 0x00 0. " CF ,Configure flag - This bit controls the default port-routing control logic. . - . - . - ." "0,1" group.long 0x90++0x3 line.long 0x00 "INSNREG00,Implementation-specific register 0" hexmask.long.word 0x00 1.--13. 1. " UFRAME_CNT ,1-microframe length value, to reduce simulation time. SIMULATIONS ONLY, NOT AN ACTUAL REGISTER." bitfld.long 0x00 0. " EN ,Enable of this register" "0,1" group.long 0x94++0x3 line.long 0x00 "INSNREG01,Implementation-specific register 1" hexmask.long.word 0x00 16.--31. 1. " OUT_THRESHOLD ,Programmable output packet buffer threshold, in 32-bit words" hexmask.long.word 0x00 0.--15. 1. " IN_THRESHOLD ,Programmable input packet buffer threshold, in 32-bit words" group.long 0x98++0x3 line.long 0x00 "INSNREG02,Implementation-specific register 2" hexmask.long.word 0x00 0.--11. 1. " BUF_DEPTH ,Programmable packet buffer depth, in 32-bit words" group.long 0x9C++0x3 line.long 0x00 "INSNREG03,Implementation-specific register 3" bitfld.long 0x00 0. " BRK_MEM_TRSF ,Break memory transfer, in conjunction withINSNREG01 - . - ." "Dis,En" group.long 0xA0++0x3 line.long 0x00 "INSNREG04,Implementation-specific register 4" bitfld.long 0x00 4. " NAK_FIX_DIS ,Disable NAK fix (don't touch)" "0,1" bitfld.long 0x00 2. " SHORT_PORT_ENUM ,Scale down port enumeration time (debug)" "0,1" bitfld.long 0x00 1. " HCCPARAMS_WRE ,Make read-onlyHCCPARAMS register writable (debug)" "0,1" textline " " bitfld.long 0x00 0. " HCSPARAMS_WRE ,Make read-onlyHCSPARAMS register writable (debug)" "0,1" group.long 0xA4++0x3 line.long 0x00 "INSNREG05_ULPI,Implementation-specific register 5. Register functionality for ULPI mode." bitfld.long 0x00 31. " CONTROL ,Control/status of the ULPI register access - . - . - ." "No_effect,Start_ULPI_access" bitfld.long 0x00 24.--27. " PORTSEL ,- . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. " OPSEL ,- . - ." "0,1,2,3" textline " " bitfld.long 0x00 16.--21. " REGADD ,ULPI direct register address, for any value different than 0x2F. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 8.--15. 1. " EXTREGADD ,Address for extended register accesses. Don't care for direct accesses." hexmask.long.byte 0x00 0.--7. 1. " RDWRDATA ,Read/write data of (resp. read/write) register access" group.long 0xA4++0x3 line.long 0x00 "INSNREG05_UTMI,Implementation-specific register 5. Register functionality for UTMI mode." bitfld.long 0x00 17. " VBUSY ,- . - ." "done,busy" bitfld.long 0x00 13.--16. " VPORT ,Vendor interface port selection - . - ." "0,P1,P2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12. " VCONTROLLOADM ,UTMI VcontrolLoadM output (active-low) - . - ." "load,noaction" textline " " bitfld.long 0x00 8.--11. " VCONTROL ,UTMI Vcontrol output, to be loaded into the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VSTATUS ,UTMI Vstatus input image, from PHY" group.long 0xA8++0x3 line.long 0x00 "INSNREG06,AHB error status" bitfld.long 0x00 31. " ERRORCAP ,Indicator that an AHB error was encountered and values were captured - . - . - . - ." "noerror_/_clear,error_/_noaction" bitfld.long 0x00 9.--11. " HBURST ,HBURST Value of the control phase at which the AHB error occurred" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--8. " BEATSEXP ,Number of beats expected in the burst at which the AHB error occurred. Valid values are 0 to 16." "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" textline " " bitfld.long 0x00 0.--3. " BEATSCOMP ,Number of successfully completed beats in the current burst before the AHB error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xAC++0x3 line.long 0x00 "INSNREG07,AHB master error address" hexmask.long 0x00 0.--31. 1. " MASTERERRADD ,AHB master error address" group.long 0xB0++0x3 line.long 0x00 "INSNREG08," hexmask.long.word 0x00 0.--15. 1. " NEWBITFIELD1 ," tree.end tree "HSUSBHOST" base ad:0x4A064000 tree "Channel_0" width 20. group.long 0x100++0x3 line.long 0x00 "UHH_SAR_CNTX_i_0,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x104++0x3 line.long 0x00 "UHH_SAR_CNTX_i_1,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x108++0x3 line.long 0x00 "UHH_SAR_CNTX_i_2,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x10C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_3,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x110++0x3 line.long 0x00 "UHH_SAR_CNTX_i_4,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x114++0x3 line.long 0x00 "UHH_SAR_CNTX_i_5,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x118++0x3 line.long 0x00 "UHH_SAR_CNTX_i_6,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x11C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_7,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x120++0x3 line.long 0x00 "UHH_SAR_CNTX_i_8,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x124++0x3 line.long 0x00 "UHH_SAR_CNTX_i_9,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x128++0x3 line.long 0x00 "UHH_SAR_CNTX_i_10,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x12C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_11,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x130++0x3 line.long 0x00 "UHH_SAR_CNTX_i_12,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x134++0x3 line.long 0x00 "UHH_SAR_CNTX_i_13,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x138++0x3 line.long 0x00 "UHH_SAR_CNTX_i_14,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x13C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_15,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x140++0x3 line.long 0x00 "UHH_SAR_CNTX_i_16,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x144++0x3 line.long 0x00 "UHH_SAR_CNTX_i_17,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x148++0x3 line.long 0x00 "UHH_SAR_CNTX_i_18,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x14C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_19,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x150++0x3 line.long 0x00 "UHH_SAR_CNTX_i_20,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x154++0x3 line.long 0x00 "UHH_SAR_CNTX_i_21,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x158++0x3 line.long 0x00 "UHH_SAR_CNTX_i_22,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x15C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_23,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x160++0x3 line.long 0x00 "UHH_SAR_CNTX_i_24,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x164++0x3 line.long 0x00 "UHH_SAR_CNTX_i_25,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x168++0x3 line.long 0x00 "UHH_SAR_CNTX_i_26,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x16C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_27,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x170++0x3 line.long 0x00 "UHH_SAR_CNTX_i_28,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x174++0x3 line.long 0x00 "UHH_SAR_CNTX_i_29,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x178++0x3 line.long 0x00 "UHH_SAR_CNTX_i_30,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x17C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_31,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x180++0x3 line.long 0x00 "UHH_SAR_CNTX_i_32,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x184++0x3 line.long 0x00 "UHH_SAR_CNTX_i_33,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x188++0x3 line.long 0x00 "UHH_SAR_CNTX_i_34,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x18C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_35,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x190++0x3 line.long 0x00 "UHH_SAR_CNTX_i_36,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x194++0x3 line.long 0x00 "UHH_SAR_CNTX_i_37,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x198++0x3 line.long 0x00 "UHH_SAR_CNTX_i_38,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x19C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_39,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1A0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_40,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1A4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_41,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1A8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_42,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1AC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_43,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1B0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_44,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1B4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_45,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1B8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_46,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1BC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_47,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1C0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_48,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1C4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_49,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1C8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_50,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1CC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_51,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1D0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_52,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1D4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_53,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1D8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_54,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1DC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_55,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1E0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_56,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1E4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_57,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1E8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_58,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1EC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_59,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1F0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_60,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1F4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_61,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1F8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_62,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x1FC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_63,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x200++0x3 line.long 0x00 "UHH_SAR_CNTX_i_64,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x204++0x3 line.long 0x00 "UHH_SAR_CNTX_i_65,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x208++0x3 line.long 0x00 "UHH_SAR_CNTX_i_66,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x20C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_67,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x210++0x3 line.long 0x00 "UHH_SAR_CNTX_i_68,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x214++0x3 line.long 0x00 "UHH_SAR_CNTX_i_69,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x218++0x3 line.long 0x00 "UHH_SAR_CNTX_i_70,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x21C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_71,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x220++0x3 line.long 0x00 "UHH_SAR_CNTX_i_72,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x224++0x3 line.long 0x00 "UHH_SAR_CNTX_i_73,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x228++0x3 line.long 0x00 "UHH_SAR_CNTX_i_74,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x22C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_75,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x230++0x3 line.long 0x00 "UHH_SAR_CNTX_i_76,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x234++0x3 line.long 0x00 "UHH_SAR_CNTX_i_77,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x238++0x3 line.long 0x00 "UHH_SAR_CNTX_i_78,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x23C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_79,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x240++0x3 line.long 0x00 "UHH_SAR_CNTX_i_80,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x244++0x3 line.long 0x00 "UHH_SAR_CNTX_i_81,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x248++0x3 line.long 0x00 "UHH_SAR_CNTX_i_82,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x24C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_83,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x250++0x3 line.long 0x00 "UHH_SAR_CNTX_i_84,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x254++0x3 line.long 0x00 "UHH_SAR_CNTX_i_85,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x258++0x3 line.long 0x00 "UHH_SAR_CNTX_i_86,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x25C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_87,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x260++0x3 line.long 0x00 "UHH_SAR_CNTX_i_88,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x264++0x3 line.long 0x00 "UHH_SAR_CNTX_i_89,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x268++0x3 line.long 0x00 "UHH_SAR_CNTX_i_90,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x26C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_91,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x270++0x3 line.long 0x00 "UHH_SAR_CNTX_i_92,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x274++0x3 line.long 0x00 "UHH_SAR_CNTX_i_93,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x278++0x3 line.long 0x00 "UHH_SAR_CNTX_i_94,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x27C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_95,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x280++0x3 line.long 0x00 "UHH_SAR_CNTX_i_96,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x284++0x3 line.long 0x00 "UHH_SAR_CNTX_i_97,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x288++0x3 line.long 0x00 "UHH_SAR_CNTX_i_98,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x28C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_99,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x290++0x3 line.long 0x00 "UHH_SAR_CNTX_i_100,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x294++0x3 line.long 0x00 "UHH_SAR_CNTX_i_101,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x298++0x3 line.long 0x00 "UHH_SAR_CNTX_i_102,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x29C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_103,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2A0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_104,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2A4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_105,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2A8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_106,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2AC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_107,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2B0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_108,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2B4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_109,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2B8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_110,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2BC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_111,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2C0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_112,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2C4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_113,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2C8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_114,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2CC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_115,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2D0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_116,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2D4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_117,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2D8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_118,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2DC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_119,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2E0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_120,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2E4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_121,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2E8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_122,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2EC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_123,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2F0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_124,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2F4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_125,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2F8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_126,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x2FC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_127,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x300++0x3 line.long 0x00 "UHH_SAR_CNTX_i_128,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x304++0x3 line.long 0x00 "UHH_SAR_CNTX_i_129,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x308++0x3 line.long 0x00 "UHH_SAR_CNTX_i_130,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x30C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_131,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x310++0x3 line.long 0x00 "UHH_SAR_CNTX_i_132,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x314++0x3 line.long 0x00 "UHH_SAR_CNTX_i_133,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x318++0x3 line.long 0x00 "UHH_SAR_CNTX_i_134,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x31C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_135,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x320++0x3 line.long 0x00 "UHH_SAR_CNTX_i_136,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x324++0x3 line.long 0x00 "UHH_SAR_CNTX_i_137,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x328++0x3 line.long 0x00 "UHH_SAR_CNTX_i_138,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x32C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_139,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x330++0x3 line.long 0x00 "UHH_SAR_CNTX_i_140,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x334++0x3 line.long 0x00 "UHH_SAR_CNTX_i_141,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x338++0x3 line.long 0x00 "UHH_SAR_CNTX_i_142,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x33C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_143,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x340++0x3 line.long 0x00 "UHH_SAR_CNTX_i_144,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x344++0x3 line.long 0x00 "UHH_SAR_CNTX_i_145,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x348++0x3 line.long 0x00 "UHH_SAR_CNTX_i_146,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x34C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_147,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x350++0x3 line.long 0x00 "UHH_SAR_CNTX_i_148,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x354++0x3 line.long 0x00 "UHH_SAR_CNTX_i_149,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x358++0x3 line.long 0x00 "UHH_SAR_CNTX_i_150,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x35C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_151,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x360++0x3 line.long 0x00 "UHH_SAR_CNTX_i_152,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x364++0x3 line.long 0x00 "UHH_SAR_CNTX_i_153,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x368++0x3 line.long 0x00 "UHH_SAR_CNTX_i_154,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x36C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_155,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x370++0x3 line.long 0x00 "UHH_SAR_CNTX_i_156,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x374++0x3 line.long 0x00 "UHH_SAR_CNTX_i_157,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x378++0x3 line.long 0x00 "UHH_SAR_CNTX_i_158,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x37C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_159,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x380++0x3 line.long 0x00 "UHH_SAR_CNTX_i_160,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x384++0x3 line.long 0x00 "UHH_SAR_CNTX_i_161,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x388++0x3 line.long 0x00 "UHH_SAR_CNTX_i_162,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x38C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_163,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x390++0x3 line.long 0x00 "UHH_SAR_CNTX_i_164,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x394++0x3 line.long 0x00 "UHH_SAR_CNTX_i_165,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x398++0x3 line.long 0x00 "UHH_SAR_CNTX_i_166,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x39C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_167,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3A0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_168,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3A4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_169,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3A8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_170,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3AC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_171,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3B0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_172,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3B4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_173,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3B8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_174,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3BC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_175,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3C0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_176,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3C4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_177,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3C8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_178,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3CC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_179,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3D0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_180,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3D4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_181,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3D8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_182,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3DC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_183,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3E0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_184,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3E4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_185,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3E8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_186,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3EC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_187,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3F0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_188,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3F4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_189,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3F8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_190,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x3FC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_191,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x400++0x3 line.long 0x00 "UHH_SAR_CNTX_i_192,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x404++0x3 line.long 0x00 "UHH_SAR_CNTX_i_193,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x408++0x3 line.long 0x00 "UHH_SAR_CNTX_i_194,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x40C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_195,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x410++0x3 line.long 0x00 "UHH_SAR_CNTX_i_196,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x414++0x3 line.long 0x00 "UHH_SAR_CNTX_i_197,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x418++0x3 line.long 0x00 "UHH_SAR_CNTX_i_198,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x41C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_199,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x420++0x3 line.long 0x00 "UHH_SAR_CNTX_i_200,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x424++0x3 line.long 0x00 "UHH_SAR_CNTX_i_201,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x428++0x3 line.long 0x00 "UHH_SAR_CNTX_i_202,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x42C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_203,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x430++0x3 line.long 0x00 "UHH_SAR_CNTX_i_204,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x434++0x3 line.long 0x00 "UHH_SAR_CNTX_i_205,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x438++0x3 line.long 0x00 "UHH_SAR_CNTX_i_206,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x43C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_207,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x440++0x3 line.long 0x00 "UHH_SAR_CNTX_i_208,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x444++0x3 line.long 0x00 "UHH_SAR_CNTX_i_209,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x448++0x3 line.long 0x00 "UHH_SAR_CNTX_i_210,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x44C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_211,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x450++0x3 line.long 0x00 "UHH_SAR_CNTX_i_212,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x454++0x3 line.long 0x00 "UHH_SAR_CNTX_i_213,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x458++0x3 line.long 0x00 "UHH_SAR_CNTX_i_214,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x45C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_215,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x460++0x3 line.long 0x00 "UHH_SAR_CNTX_i_216,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x464++0x3 line.long 0x00 "UHH_SAR_CNTX_i_217,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x468++0x3 line.long 0x00 "UHH_SAR_CNTX_i_218,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x46C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_219,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x470++0x3 line.long 0x00 "UHH_SAR_CNTX_i_220,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x474++0x3 line.long 0x00 "UHH_SAR_CNTX_i_221,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x478++0x3 line.long 0x00 "UHH_SAR_CNTX_i_222,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x47C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_223,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x480++0x3 line.long 0x00 "UHH_SAR_CNTX_i_224,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x484++0x3 line.long 0x00 "UHH_SAR_CNTX_i_225,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x488++0x3 line.long 0x00 "UHH_SAR_CNTX_i_226,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x48C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_227,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x490++0x3 line.long 0x00 "UHH_SAR_CNTX_i_228,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x494++0x3 line.long 0x00 "UHH_SAR_CNTX_i_229,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x498++0x3 line.long 0x00 "UHH_SAR_CNTX_i_230,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x49C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_231,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4A0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_232,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4A4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_233,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4A8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_234,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4AC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_235,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4B0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_236,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4B4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_237,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4B8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_238,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4BC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_239,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4C0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_240,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4C4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_241,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4C8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_242,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4CC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_243,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4D0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_244,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4D4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_245,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4D8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_246,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4DC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_247,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4E0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_248,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4E4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_249,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4E8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_250,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4EC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_251,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4F0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_252,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4F4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_253,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4F8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_254,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x4FC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_255,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x500++0x3 line.long 0x00 "UHH_SAR_CNTX_i_256,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x504++0x3 line.long 0x00 "UHH_SAR_CNTX_i_257,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x508++0x3 line.long 0x00 "UHH_SAR_CNTX_i_258,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x50C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_259,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x510++0x3 line.long 0x00 "UHH_SAR_CNTX_i_260,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x514++0x3 line.long 0x00 "UHH_SAR_CNTX_i_261,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x518++0x3 line.long 0x00 "UHH_SAR_CNTX_i_262,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x51C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_263,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x520++0x3 line.long 0x00 "UHH_SAR_CNTX_i_264,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x524++0x3 line.long 0x00 "UHH_SAR_CNTX_i_265,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x528++0x3 line.long 0x00 "UHH_SAR_CNTX_i_266,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x52C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_267,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x530++0x3 line.long 0x00 "UHH_SAR_CNTX_i_268,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x534++0x3 line.long 0x00 "UHH_SAR_CNTX_i_269,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x538++0x3 line.long 0x00 "UHH_SAR_CNTX_i_270,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x53C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_271,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x540++0x3 line.long 0x00 "UHH_SAR_CNTX_i_272,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x544++0x3 line.long 0x00 "UHH_SAR_CNTX_i_273,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x548++0x3 line.long 0x00 "UHH_SAR_CNTX_i_274,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x54C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_275,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x550++0x3 line.long 0x00 "UHH_SAR_CNTX_i_276,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x554++0x3 line.long 0x00 "UHH_SAR_CNTX_i_277,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x558++0x3 line.long 0x00 "UHH_SAR_CNTX_i_278,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x55C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_279,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x560++0x3 line.long 0x00 "UHH_SAR_CNTX_i_280,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x564++0x3 line.long 0x00 "UHH_SAR_CNTX_i_281,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x568++0x3 line.long 0x00 "UHH_SAR_CNTX_i_282,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x56C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_283,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x570++0x3 line.long 0x00 "UHH_SAR_CNTX_i_284,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x574++0x3 line.long 0x00 "UHH_SAR_CNTX_i_285,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x578++0x3 line.long 0x00 "UHH_SAR_CNTX_i_286,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x57C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_287,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x580++0x3 line.long 0x00 "UHH_SAR_CNTX_i_288,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x584++0x3 line.long 0x00 "UHH_SAR_CNTX_i_289,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x588++0x3 line.long 0x00 "UHH_SAR_CNTX_i_290,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x58C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_291,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x590++0x3 line.long 0x00 "UHH_SAR_CNTX_i_292,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x594++0x3 line.long 0x00 "UHH_SAR_CNTX_i_293,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x598++0x3 line.long 0x00 "UHH_SAR_CNTX_i_294,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x59C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_295,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5A0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_296,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5A4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_297,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5A8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_298,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5AC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_299,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5B0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_300,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5B4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_301,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5B8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_302,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5BC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_303,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5C0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_304,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5C4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_305,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5C8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_306,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5CC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_307,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5D0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_308,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5D4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_309,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5D8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_310,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5DC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_311,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5E0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_312,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5E4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_313,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5E8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_314,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5EC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_315,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5F0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_316,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5F4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_317,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5F8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_318,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x5FC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_319,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x600++0x3 line.long 0x00 "UHH_SAR_CNTX_i_320,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x604++0x3 line.long 0x00 "UHH_SAR_CNTX_i_321,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x608++0x3 line.long 0x00 "UHH_SAR_CNTX_i_322,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x60C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_323,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x610++0x3 line.long 0x00 "UHH_SAR_CNTX_i_324,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x614++0x3 line.long 0x00 "UHH_SAR_CNTX_i_325,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x618++0x3 line.long 0x00 "UHH_SAR_CNTX_i_326,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x61C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_327,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x620++0x3 line.long 0x00 "UHH_SAR_CNTX_i_328,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x624++0x3 line.long 0x00 "UHH_SAR_CNTX_i_329,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x628++0x3 line.long 0x00 "UHH_SAR_CNTX_i_330,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x62C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_331,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x630++0x3 line.long 0x00 "UHH_SAR_CNTX_i_332,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x634++0x3 line.long 0x00 "UHH_SAR_CNTX_i_333,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x638++0x3 line.long 0x00 "UHH_SAR_CNTX_i_334,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x63C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_335,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x640++0x3 line.long 0x00 "UHH_SAR_CNTX_i_336,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x644++0x3 line.long 0x00 "UHH_SAR_CNTX_i_337,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x648++0x3 line.long 0x00 "UHH_SAR_CNTX_i_338,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x64C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_339,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x650++0x3 line.long 0x00 "UHH_SAR_CNTX_i_340,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x654++0x3 line.long 0x00 "UHH_SAR_CNTX_i_341,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x658++0x3 line.long 0x00 "UHH_SAR_CNTX_i_342,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x65C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_343,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x660++0x3 line.long 0x00 "UHH_SAR_CNTX_i_344,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x664++0x3 line.long 0x00 "UHH_SAR_CNTX_i_345,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x668++0x3 line.long 0x00 "UHH_SAR_CNTX_i_346,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x66C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_347,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x670++0x3 line.long 0x00 "UHH_SAR_CNTX_i_348,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x674++0x3 line.long 0x00 "UHH_SAR_CNTX_i_349,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x678++0x3 line.long 0x00 "UHH_SAR_CNTX_i_350,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x67C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_351,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x680++0x3 line.long 0x00 "UHH_SAR_CNTX_i_352,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x684++0x3 line.long 0x00 "UHH_SAR_CNTX_i_353,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x688++0x3 line.long 0x00 "UHH_SAR_CNTX_i_354,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x68C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_355,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x690++0x3 line.long 0x00 "UHH_SAR_CNTX_i_356,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x694++0x3 line.long 0x00 "UHH_SAR_CNTX_i_357,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x698++0x3 line.long 0x00 "UHH_SAR_CNTX_i_358,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x69C++0x3 line.long 0x00 "UHH_SAR_CNTX_i_359,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6A0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_360,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6A4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_361,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6A8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_362,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6AC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_363,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6B0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_364,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6B4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_365,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6B8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_366,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6BC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_367,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6C0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_368,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6C4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_369,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6C8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_370,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6CC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_371,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6D0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_372,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6D4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_373,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6D8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_374,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6DC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_375,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6E0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_376,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6E4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_377,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6E8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_378,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6EC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_379,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6F0++0x3 line.long 0x00 "UHH_SAR_CNTX_i_380,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6F4++0x3 line.long 0x00 "UHH_SAR_CNTX_i_381,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6F8++0x3 line.long 0x00 "UHH_SAR_CNTX_i_382,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x6FC++0x3 line.long 0x00 "UHH_SAR_CNTX_i_383,Save and restore context array. Array size is indicated in. When in SAR mode, read out to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" tree.end textline "" width 16. rgroup.long 0x0++0x3 line.long 0x00 "UHH_REVISION,USB high-speed host (UHH) revision identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" rgroup.long 0x4++0x3 line.long 0x00 "UHH_HWINFO,Information on host hardware configuration" hexmask.long.word 0x00 0.--9. 1. " SAR_CNTX_SIZE ,Save-and-restore context size, in 32-bit words; that is, number of 32-bit registers with significant context information, mapped from offset 0x100 upward." group.long 0x10++0x3 line.long 0x00 "UHH_SYSCONFIG,OCP standard system configuration register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Mstandby/Mwait/[Mwakeup] initiator power-management interface configuration - . - . - . - ." "forcestandby,nostandby,smartstandby,smartstandby_wakeup" bitfld.long 0x00 2.--3. " IDLEMODE ,Sidlereq/Sidleack(1:0)/[Swakeup] target power management interface configuration. - . - . - . - ." "forceidle,noidle,smartidle,smartidle_wakeup" bitfld.long 0x00 0. " SOFTRESET ,Module software reset - . - . - . - ." "no_action_/_nothing_pending,do_reset_/_reset_pending" rgroup.long 0x14++0x3 line.long 0x00 "UHH_SYSSTATUS,Module-specific system status" bitfld.long 0x00 2. " EHCI_RESETDONE ,Indicates when the EHCI HS host is out of reset - . - ." "done,reset" bitfld.long 0x00 1. " OHCI_RESETDONE ,Indicates when the OHCI FS/LS host is out of reset - . - ." "done,reset" group.long 0x40++0x3 line.long 0x00 "UHH_HOSTCONFIG,Static configuration of the USB HS host" bitfld.long 0x00 31. " APP_START_CLK ,When the OHCI clocks are suspended, the system must assert this signal to start the clocks (12 and 48 MHz). - This must be deasserted after the clocks are started and before the host is suspended again. . - . - (Host is suspende.." "0,1" bitfld.long 0x00 18.--19. " P2_MODE ,Port 2 interface configuration. Each bit corresponds to an internal 'strap' signal, and output: Bit 0 = ulpi_bypass Bit 1 = hsic_en - . - . - . - ." "ulpi,utmi,forbidden,hsic" bitfld.long 0x00 16.--17. " P1_MODE ,Port 1 interface configuration. Each bit corresponds to an internal 'strap' signal, and output: Bit 0 = ulpi_bypass Bit 1 = hsic_en - . - . - . - ." "ulpi,utmi,forbidden,hsic" textline " " bitfld.long 0x00 9. " P2_CONNECT_STATUS ,Connection status for port 2 - . - ." "disc,con" bitfld.long 0x00 8. " P1_CONNECT_STATUS ,Connection status for port 1 - . - ." "disc,con" bitfld.long 0x00 5. " ENA_INCR_ALIGN ,Force alignment of bursts to the respective burst-size boundaries - . - ." "dis,en" textline " " bitfld.long 0x00 4. " ENA_INCR16 ,Control the use of INCR16-type bursts (in AHB sense) - . - ." "dis,en" bitfld.long 0x00 3. " ENA_INCR8 ,Control the use of INCR8-type bursts (in AHB sense) - . - ." "dis,en" bitfld.long 0x00 2. " ENA_INCR4 ,Control the use of INCR4-type bursts (in AHB sense) - . - ." "dis,en" textline " " bitfld.long 0x00 1. " AUTOPPD_ON_OVERCUR_EN ,Configure reaction upon port overcurrent condition. This function is not supported at the device level. - . - ." "dis,en" group.long 0x44++0x3 line.long 0x00 "UHH_DEBUG_CSR,Debug control and status for the EHCI, OHCI hosts" bitfld.long 0x00 18. " OHCI_CCS_2 ,Current connect status of port 2 - . - ." "disconnected,connected" bitfld.long 0x00 17. " OHCI_CCS_1 ,Current connect status of port 1 - . - ." "disconnected,connected" bitfld.long 0x00 16. " OHCI_GLOBALSUSPEND ,OHCI global suspend status, asserted 5 ms after the suspend order. - . - ." "active,suspended" textline " " bitfld.long 0x00 7. " OCHI_CNTSEL ,Selection of a shorter '1 ms' counter in OHCI host, to speed up long USB phases such as reset, resume, etc. (used only for simulation) - . - ." "noaction,speedup" bitfld.long 0x00 6. " EHCI_SIMULATION_MODE ,Sets the PHY to nondriving mode (used only for simulation) - . - ." "noaction,phy_nodrive" bitfld.long 0x00 0.--5. " EHCI_FLADJ ,EHCI host frame length adjust. Modify only when EHCI Bit FieldUSBSTS.HCHalted = 1 Field value + 59,488 = 60,000 by default = Number of 60-MHz UTMI/ULPI clock cycles per 1 ms USB frame = Number of 480-MHz HS bits per 125 ?s HS.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "USBTLLHS_config" base ad:0x4A062000 tree "Channel_0" width 22. group.long 0x40++0x3 line.long 0x00 "TLL_CHANNEL_CONF_i_0,Control and Status register for channel i." bitfld.long 0x00 28.--29. " FSLSLINESTATE ,Line state for Full/low speed serial modes Bit 1 = D?/ Bit0 = D+ - . - . - . - ." "SE0,FSJ,FSK,SE1" bitfld.long 0x00 24.--27. " FSLSMODE ,Multiple-mode serial interface's mode select. Only when main channel mode is serial. No effect in other main modes. - . - . - . - . - . - . - . - . - . - ." "6pin_datse0,6pin_vpvm,3pin,4pin,6pin_datse0_tll,6pin_vpvm_tll,3pin_tll,4pin_tll,8,9,2pin_datse0_tll,2pin_vpvm_tll,12,13,14,15" bitfld.long 0x00 20. " TESTTXSE0 ,Force-Se0 transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) or = TestTxen = 1 (TX = hiz) - . - ." "diff,se0" textline " " bitfld.long 0x00 19. " TESTTXDAT ,Differential data transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) or = TestTxen = 1 (TX = hiz) or TestSe0 = 1 (TX = se0) - . - ." "FSK,FSJ" bitfld.long 0x00 18. " TESTTXEN ,Differential data transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) - . - ." "Drive,Hiz" bitfld.long 0x00 17. " TESTEN ,Enable manual test override for serial mode TX path (from local controller UTMI port) - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 16. " DRVVBUS ,VBUS-drive for ChanMode = serial * In TLL config, write 1 to emulate serial-side VBUS drive * In PHY config, write 1 to report 'VBUS valid' status (of actual VBUS) to UTMI controller - . - ." "NoDrive,Drive" bitfld.long 0x00 15. " CHRGVBUS ,VBUS-drive for ChanMode = serial * In TLL config, write 1 to emulate serial-side VBUS charge/pullup (OTG) * In PHY config, write 1 to reports 'session valid' status (of actual VBUS) to UTMI controller - . - ." "NoCharge,Charge" bitfld.long 0x00 11. " ULPINOBITSTUFF ,Disable bitstuff emulation in ULPI TLL for ULPI ChanMode - . - ." "BitStuff,NoBitStuff" textline " " bitfld.long 0x00 10. " ULPIAUTOIDLE ,For ChanMode = ULPI TLL only. Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode (low-power, 3-pin serial, 6-pin serial). No effect in ULPI input clock mode. - . - ." "AlwaysOn,AutoIdle" bitfld.long 0x00 9. " UTMIAUTOIDLE ,For ChanMode = ULPI TLL only. Allow the UTMI clock (output) to be stopped when UTMII goes to suspended mode (suspendm = 0) - . - ." "AlwaysOn,AutoIdle" bitfld.long 0x00 7. " ULPIOUTCLKMODE ,ULPI clocking mode select for ULPI TLL ChanMode. Hardcoded, for legacy only. - ." "0,out" textline " " bitfld.long 0x00 6. " TLLFULLSPEED ,Sets PHY speed emulation in TLL (full/slow), which determines the line to pull up upon connect. The two connect source controls are: input m(N)_tllpuen, register field TllConnect. - . - ." "LS,FS" bitfld.long 0x00 5. " TLLCONNECT ,Emulation of Full/Low-Speed connect (that is, D+ resp D? pullup) for serial TLL modes. Speed is determined by field TllSpeed. - . - ." "Unconnected,Connected" bitfld.long 0x00 4. " TLLATTACH ,Emulates cable attach/detach for all serial TLL modes: * ChanMode = serial, in TLL mode (FsLsMode) * ChanMode = ULPI, in serial mode (6pin/3pin TLL) - . - ." "Detached,Attached" textline " " bitfld.long 0x00 3. " UTMIISADEV ,Select the cable end 'seen' by UTMI side of TLL, i.e. the emulated USB cable's orientation. The host must always be on A-side, peripheral on B-side. Reset value depends on generic DEFUTMIISHOST. - . - ." "UTMI_B,UTMI_A" bitfld.long 0x00 1.--2. " CHANMODE ,Main channel mode selection - . - . - . - ." "ulpi,serial,transp,?..." bitfld.long 0x00 0. " CHANEN ,Active-high channel enable. A disabled channel is unclocked and kept under reset. - . - ." "Disabled,Enabled" group.long 0x400++0x3 line.long 0x00 "USBTLL_SAR_CNTX_j_0,Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" tree.end tree "Channel_1" width 22. group.long 0x44++0x3 line.long 0x00 "TLL_CHANNEL_CONF_i_1,Control and Status register for channel i." bitfld.long 0x00 28.--29. " FSLSLINESTATE ,Line state for Full/low speed serial modes Bit 1 = D?/ Bit0 = D+ - . - . - . - ." "SE0,FSJ,FSK,SE1" bitfld.long 0x00 24.--27. " FSLSMODE ,Multiple-mode serial interface's mode select. Only when main channel mode is serial. No effect in other main modes. - . - . - . - . - . - . - . - . - . - ." "6pin_datse0,6pin_vpvm,3pin,4pin,6pin_datse0_tll,6pin_vpvm_tll,3pin_tll,4pin_tll,8,9,2pin_datse0_tll,2pin_vpvm_tll,12,13,14,15" bitfld.long 0x00 20. " TESTTXSE0 ,Force-Se0 transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) or = TestTxen = 1 (TX = hiz) - . - ." "diff,se0" textline " " bitfld.long 0x00 19. " TESTTXDAT ,Differential data transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) or = TestTxen = 1 (TX = hiz) or TestSe0 = 1 (TX = se0) - . - ." "FSK,FSJ" bitfld.long 0x00 18. " TESTTXEN ,Differential data transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) - . - ." "Drive,Hiz" bitfld.long 0x00 17. " TESTEN ,Enable manual test override for serial mode TX path (from local controller UTMI port) - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 16. " DRVVBUS ,VBUS-drive for ChanMode = serial * In TLL config, write 1 to emulate serial-side VBUS drive * In PHY config, write 1 to report 'VBUS valid' status (of actual VBUS) to UTMI controller - . - ." "NoDrive,Drive" bitfld.long 0x00 15. " CHRGVBUS ,VBUS-drive for ChanMode = serial * In TLL config, write 1 to emulate serial-side VBUS charge/pullup (OTG) * In PHY config, write 1 to reports 'session valid' status (of actual VBUS) to UTMI controller - . - ." "NoCharge,Charge" bitfld.long 0x00 11. " ULPINOBITSTUFF ,Disable bitstuff emulation in ULPI TLL for ULPI ChanMode - . - ." "BitStuff,NoBitStuff" textline " " bitfld.long 0x00 10. " ULPIAUTOIDLE ,For ChanMode = ULPI TLL only. Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode (low-power, 3-pin serial, 6-pin serial). No effect in ULPI input clock mode. - . - ." "AlwaysOn,AutoIdle" bitfld.long 0x00 9. " UTMIAUTOIDLE ,For ChanMode = ULPI TLL only. Allow the UTMI clock (output) to be stopped when UTMII goes to suspended mode (suspendm = 0) - . - ." "AlwaysOn,AutoIdle" bitfld.long 0x00 7. " ULPIOUTCLKMODE ,ULPI clocking mode select for ULPI TLL ChanMode. Hardcoded, for legacy only. - ." "0,out" textline " " bitfld.long 0x00 6. " TLLFULLSPEED ,Sets PHY speed emulation in TLL (full/slow), which determines the line to pull up upon connect. The two connect source controls are: input m(N)_tllpuen, register field TllConnect. - . - ." "LS,FS" bitfld.long 0x00 5. " TLLCONNECT ,Emulation of Full/Low-Speed connect (that is, D+ resp D? pullup) for serial TLL modes. Speed is determined by field TllSpeed. - . - ." "Unconnected,Connected" bitfld.long 0x00 4. " TLLATTACH ,Emulates cable attach/detach for all serial TLL modes: * ChanMode = serial, in TLL mode (FsLsMode) * ChanMode = ULPI, in serial mode (6pin/3pin TLL) - . - ." "Detached,Attached" textline " " bitfld.long 0x00 3. " UTMIISADEV ,Select the cable end 'seen' by UTMI side of TLL, i.e. the emulated USB cable's orientation. The host must always be on A-side, peripheral on B-side. Reset value depends on generic DEFUTMIISHOST. - . - ." "UTMI_B,UTMI_A" bitfld.long 0x00 1.--2. " CHANMODE ,Main channel mode selection - . - . - . - ." "ulpi,serial,transp,?..." bitfld.long 0x00 0. " CHANEN ,Active-high channel enable. A disabled channel is unclocked and kept under reset. - . - ." "Disabled,Enabled" group.long 0x404++0x3 line.long 0x00 "USBTLL_SAR_CNTX_j_1,Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x408++0x3 line.long 0x00 "USBTLL_SAR_CNTX_j_2,Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x40C++0x3 line.long 0x00 "USBTLL_SAR_CNTX_j_3,Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x410++0x3 line.long 0x00 "USBTLL_SAR_CNTX_j_4,Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x414++0x3 line.long 0x00 "USBTLL_SAR_CNTX_j_5,Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" group.long 0x418++0x3 line.long 0x00 "USBTLL_SAR_CNTX_j_6,Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." hexmask.long 0x00 0.--31. 1. " CNTX ,Context bits" tree.end textline "" width 18. rgroup.long 0x0++0x3 line.long 0x00 "USBTLL_REVISION,OCP standard revision number, BCD encoded" hexmask.long 0x00 0.--31. 1. " REVISION ,Revision number" rgroup.long 0x4++0x3 line.long 0x00 "USBTLL_HWINFO,Information on hardware configuration of host" hexmask.long.byte 0x00 0.--7. 1. " SAR_CNTX_SIZE ,Save-and-Restore context size, in 32-bit words, i.e. number of 32-bit registers with significant context information, mapped from offset 0x400 upward." group.long 0x10++0x3 line.long 0x00 "USBTLL_SYSCONFIG,OCP standard system configuration register" bitfld.long 0x00 8. " CLOCKACTIVITY ,Enable autogating of OCP-derived internal clocks while module is idle. - . - ." "0,1" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management control. Idle Req/ack control - . - . - ." "forceidle,noidle,smartidle,3" bitfld.long 0x00 2. " ENAWAKEUP ,Asynchronous wake-up generation control (Swakeup) - . - ." "disabled,enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Module software reset - . - ." "no_action,do_reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal autogating control - . - ." "disabled,enabled" rgroup.long 0x14++0x3 line.long 0x00 "USBTLL_SYSSTATUS,OCP standard system status register" bitfld.long 0x00 0. " RESETDONE ,Indicates when the module has entirely come out of reset - . - ." "ongoing,done" group.long 0x18++0x3 line.long 0x00 "USBTLL_IRQSTATUS,OCP standard IRQ status vector. Write 1 to clear a bit." bitfld.long 0x00 2. " ACCESS_ERROR ,Access error to ULPI register over OCP: USB clock must run for that type of access to succeed. - . - ." "NoEvent,Pending" bitfld.long 0x00 1. " FCLK_END ,Functional clock is no longer requested for USB clocking - . - ." "NoEvent,Pending" bitfld.long 0x00 0. " FCLK_START ,Functional clock is requested for USB clocking - . - ." "NoEvent,Pending" group.long 0x1C++0x3 line.long 0x00 "USBTLL_IRQENABLE,OCP standard IRQ enable vector" bitfld.long 0x00 2. " ACCESS_ERROR_EN ,Enable IRQ generation upon access error to ULPI register over L3 interconnect - . - ." "Masked,Enabled" bitfld.long 0x00 1. " FCLK_END_EN ,IRQ event mask for FCLK_END interrupt (seeUSBTLL_IRQSTATUS[1]) - . - ." "Masked,Enabled" bitfld.long 0x00 0. " FCLK_START_EN ,IRQ event mask for FCLK_START interrupt (seeUSBTLL_IRQSTATUS[0]) - . - ." "Masked,Enabled" group.long 0x30++0x3 line.long 0x00 "TLL_SHARED_CONF,Common control register for all TLL channels" bitfld.long 0x00 1. " FCLK_REQ ,Functional clock request, ORed from all channels depending on their respective USB bus state. Combined with the Fclk_is_on status to generate fclk_start/end IRQs. - . - ." "NoRequest,Request" bitfld.long 0x00 0. " FCLK_IS_ON ,Status of the functional clock input, provided by the system to the TLL module. The TLL module will only use that clock if the current status indicated that it is ready. Combined with the Fclk_request to generate fclk_start/end IRQs. - ..." "not_ready,ready" tree.end tree "USBTLLHS_ULPI" base ad:0x4A062800 tree "Channel_0" width 26. rgroup.byte 0x15++0x0 line.byte 0x00 "DEBUG_i_0,Indicates the current value of various signals useful for debugging." bitfld.byte 0x00 0.--1. " LINE_STATE ,Current state of the USB line: D+ (bit 0) and D? (bit 1). - . - . - . - ." "0,1,2,3" group.byte 0x2F++0x0 line.byte 0x00 "EXTENDED_SET_ACCESS_i_0,This address is used to access the extended register set; that is, addresses above 0x40." hexmask.byte 0x00 0.--7. 1. " SET_ACCESS ,This bit field is used to access the extended register set; that is, addresses above 0x40." group.byte 0x6++0x0 line.byte 0x00 "FUNCTION_CTRL_CLR_i_0,Controls UTMI function settings of the PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend: Puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit. - . - ." "0,1" bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset. Autocleared. Does not reset the ULPI interface or ULPI register set. - . - ." "0,1" bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit - . - ." "0,1,2,3" textline " " bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5-k? pull-up resistor and 45-? HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown. - . - ." "0,1" bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed. - . - ." "0,1,2,3" group.byte 0x5++0x0 line.byte 0x00 "FUNCTION_CTRL_SET_i_0,Controls UTMI function settings of the PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend: Puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit. - . - ." "0,1" bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset. Autocleared. Does not reset the ULPI interface or ULPI register set. - . - ." "0,1" bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit. - . - ." "0,1,2,3" textline " " bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5-k? pullup resistor and 45-? HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown. - . - ." "0,1" bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed. - . - ." "0,1,2,3" group.byte 0x4++0x0 line.byte 0x00 "FUNCTION_CTRL_i_0,Controls UTMI function settings of the PHY. Read/write address." bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend: puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit. - . - ." "LowPowerMode,NotSuspended" bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset. Auto-cleared. Does not reset the ULPI interface or ULPI register set. - . - ." "NoReset,Reset" bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit - . - . - . - ." "Opmode00,Opmode01,Opmode10,Opmode11" textline " " bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5-k? HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown. - . - ." "hs,fs" bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed. - . - . - . - ." "XcrSelect00,XcrSelect01,XcrSelect10,XcrSelect11" group.byte 0x9++0x0 line.byte 0x00 "INTERFACE_CTRL_CLR_i_0,Enables alternative interfaces and PHY features. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data. - . - ." "0,1" bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling. On by default. - . - ." "0,1" bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes (6-pin/3-pin). - . - ." "0,1" textline " " bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Autocleared when serial mode is exited. - . - ." "0,1" bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Autocleared when serial mode is exited. - . - ." "0,1" group.byte 0x8++0x0 line.byte 0x00 "INTERFACE_CTRL_SET_i_0,Enables alternative interfaces and PHY features. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data. - . - ." "0,1" bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling. On by default. - . - ." "0,1" bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes (6-pin/3-pin). - . - ." "0,1" textline " " bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Autocleared when serial mode is exited. - . - ." "0,1" bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Autocleared when serial mode is exited. - . - ." "0,1" group.byte 0x7++0x0 line.byte 0x00 "INTERFACE_CTRL_i_0,Enables alternative interfaces and PHY features. Read/write address." bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data. - . - ." "Enabled,Disabled" bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling. On by default. - . - ." "Disabled,Enabled" bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes (6-pin/3-pin). - . - ." "Suspend,KeepActive" textline " " bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Auto-cleared when serial mode is exited. - . - ." "Disabled,Enabled" bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Auto-cleared when serial mode is exited. - . - ." "Disabled,Enabled" group.byte 0xC++0x0 line.byte 0x00 "OTG_CTRL_CLR_i_0,Controls UTMI+ OTG functions of the PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." bitfld.byte 0x00 5. " DRVVBUS ,Drive 5 V on VBUS - . - ." "0,1" bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP. - . - ." "0,1" bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor, until the session-end VBUS state is reached. - . - ." "0,1" textline " " bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15k pulldown resistor on D? - . - ." "0,1" bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15k? pulldown resistor on D+ - . - ." "0,1" bitfld.byte 0x00 0. " IDPULLUP ,Pullup to the (OTG) ID line to allow its sampling - . - ." "0,1" group.byte 0xB++0x0 line.byte 0x00 "OTG_CTRL_SET_i_0,Controls UTMI+ OTG functions of the PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." bitfld.byte 0x00 5. " DRVVBUS ,Drive 5 V on VBUS - . - ." "0,1" bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP. - . - ." "0,1" bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor, until the session-end VBUS state is reached. - . - ." "0,1" textline " " bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15-k? pulldown resistor on D? - . - ." "0,1" bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15-k? pulldown resistor on D+ - . - ." "0,1" bitfld.byte 0x00 0. " IDPULLUP ,Pullup to the (OTG) ID line to allow its sampling - . - ." "0,1" group.byte 0xA++0x0 line.byte 0x00 "OTG_CTRL_i_0,Controls UTMI+ OTG functions of the PHY. Read/write address." bitfld.byte 0x00 5. " DRVVBUS ,Drive 5 V on VBUS - . - ." "noaction,drive" bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP. - . - ." "noaction,charge" bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor, until the session-end VBUS state is reached. - . - ." "NoAction,Discharge" textline " " bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15-k? pulldown resistor on D? - . - ." "Disabled,Enabled" bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15-k? pulldown resistor on D+ - . - ." "Disabled,Enabled" bitfld.byte 0x00 0. " IDPULLUP ,Pullup to the (OTG) ID line to allow its sampling - . - ." "Disable,Enable" rgroup.byte 0x3++0x0 line.byte 0x00 "PRODUCT_ID_HI_i_0,Upper byte of 16-bit product ID Value is set for all channels. Default is" hexmask.byte 0x00 0.--7. 1. " PRODUCT_ID_HI ," rgroup.byte 0x2++0x0 line.byte 0x00 "PRODUCT_ID_LO_i_0,Lower byte of 16-bit product ID Value is set for all channels. Default is" hexmask.byte 0x00 0.--7. 1. " PRODUCT_ID_LO ," group.byte 0x18++0x0 line.byte 0x00 "SCRATCH_REGISTER_CLR_i_0,Register byte for register access testing purposes. Value has no functional effect on PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/write ad.." hexmask.byte 0x00 0.--7. 1. " SCRATCH ,Scratch data Write 1 to a bit to clear it to 0. Writing 0 has no effect on bit value." group.byte 0x17++0x0 line.byte 0x00 "SCRATCH_REGISTER_SET_i_0,Register byte for register access testing purposes. Value has no functional effect on PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write addres.." hexmask.byte 0x00 0.--7. 1. " SCRATCH ,Scratch data Write 1 to a bit to set it to 1. Writing 0 has no effect on bit value." group.byte 0x16++0x0 line.byte 0x00 "SCRATCH_REGISTER_i_0,Register byte for register access testing purposes. Value has no functional effect on PHY. Read/write address." hexmask.byte 0x00 0.--7. 1. " SCRATCH ,Scratch data" group.byte 0x12++0x0 line.byte 0x00 "USB_INT_EN_FALL_CLR_i_0,Enables an interrupt event notification when the corresponding status bit changes from high to low. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/.." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" group.byte 0x11++0x0 line.byte 0x00 "USB_INT_EN_FALL_SET_i_0,Enables an interrupt event notification when the corresponding status bit changes from high to low. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/wri.." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" group.byte 0x10++0x0 line.byte 0x00 "USB_INT_EN_FALL_i_0,Enables an interrupt event notification when the corresponding status bit changes from high to low. By default, all transitions are enabled. Read/write address." bitfld.byte 0x00 4. " IDGND_FALL ,Generate an interrupt event notification when IdGnd changes from high to low. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1." "0,1" bitfld.byte 0x00 3. " SESSEND_FALL ,Generate an interrupt event notification when SessEnd changes from high to low." "0,1" bitfld.byte 0x00 2. " SESSVALID_FALL ,Generate an interrupt event notification when SessValid changes from high to low. SessValid is the same as UTMI+ AValid." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_FALL ,Generate an interrupt event notification when VbusValid changes from high to low." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_FALL ,Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)." "0,1" group.byte 0xF++0x0 line.byte 0x00 "USB_INT_EN_RISE_CLR_i_0,Enables an interrupt event notification when the corresponding status bit changes from low to high. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See the field description at the r.." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" group.byte 0xE++0x0 line.byte 0x00 "USB_INT_EN_RISE_SET_i_0,Enables an interrupt event notification when the corresponding status bit changes from low to high. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/wri.." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" group.byte 0xD++0x0 line.byte 0x00 "USB_INT_EN_RISE_i_0,Enables an interrupt event notification when the corresponding status bit changes from low to high. By default, all transitions are enabled. Read/write address." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" rgroup.byte 0x38++0x0 line.byte 0x00 "USB_INT_LATCH_NOCLR_i_0,Set by unmasked changes on the corresponding status bits to generate the ULPI interrupt. Debug, nonstandard address to the standard register: Register is not cleared on read. See field description at the 'clear-on-read' address .." bitfld.byte 0x00 4. " IDGND_LATCH ,Set to 1 by the PHY when an unmasked event occurs on IdGnd." "0,1" bitfld.byte 0x00 3. " SESSEND_LATCH ,Set to 1 by the PHY when an unmasked event occurs on SessEnd." "0,1" bitfld.byte 0x00 2. " SESSVALID_LATCH ,Set to 1 by the PHY when an unmasked event occurs on SessValid. SessValid is the same as UTMI+ AValid." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_LATCH ,Set to 1 by the PHY when an unmasked event occurs on VbusValid." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_LATCH ,Set to 1 by the PHY when an unmasked event occurs on Hostdisconnect. Applicable only in host mode." "0,1" rgroup.byte 0x14++0x0 line.byte 0x00 "USB_INT_LATCH_i_0,Set by unmasked changes on the corresponding status bits to generate the ULPI interrupt. Cleared upon read, and when low-power mode, serial mode, or carkit mode are entered." bitfld.byte 0x00 4. " IDGND_LATCH ,Set to 1 by the PHY when an unmasked event occurs on IdGnd. Cleared when this register is read." "0,1" bitfld.byte 0x00 3. " SESSEND_LATCH ,Set to 1 by the PHY when an unmasked event occurs on SessEnd. Cleared when this register is read." "0,1" bitfld.byte 0x00 2. " SESSVALID_LATCH ,Set to 1 by the PHY when an unmasked event occurs on SessValid. Cleared when this register is read. SessValid is the same as UTMI+ AValid." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_LATCH ,Set to 1 by the PHY when an unmasked event occurs on VbusValid. Cleared when this register is read." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_LATCH ,Set to 1 by the PHY when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode." "0,1" rgroup.byte 0x13++0x0 line.byte 0x00 "USB_INT_STATUS_i_0,Indicates the current value of the interrupt source signal." bitfld.byte 0x00 4. " IDGND ,Value of UTMI+ IdDig output. Undefined unless IdPullup = 1 - . - ." "IdA,IdB" bitfld.byte 0x00 3. " SESSEND ,Current value of UTMI+ SessEnd output. - . - ." "notended,ended" bitfld.byte 0x00 2. " SESSVALID ,Current value of UTMI+ SessValid output. SessValid is the same as UTMI+ AValid. - . - ." "notvalid,valid" textline " " bitfld.byte 0x00 1. " VBUSVALID ,Current value of UTMI+ VbusValid output. - . - ." "notvalid,valid" bitfld.byte 0x00 0. " HOSTDISCONNECT ,Current value of UTMI+ Hostdisconnect output. Applicable only in host mode. Automatically reset to 0 when low-power mode is entered. - . - ." "NotDisconnected,Disconnected" group.byte 0x32++0x0 line.byte 0x00 "UTMI_VCONTROL_EN_CLR_i_0,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/clear address (write 1 to a bit to cle.." hexmask.byte 0x00 0.--7. 1. " VC ,User-defined UTMI control data byte" group.byte 0x31++0x0 line.byte 0x00 "UTMI_VCONTROL_EN_SET_i_0,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1 Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/set address (write 1 to a bit to set it.." bitfld.byte 0x00 7. " VC7_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 6. " VC6_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 5. " VC5_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" textline " " bitfld.byte 0x00 4. " VC4_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 3. " VC3_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 2. " VC2_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" textline " " bitfld.byte 0x00 1. " VC1_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 0. " VC0_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" group.byte 0x30++0x0 line.byte 0x00 "UTMI_VCONTROL_EN_i_0,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1 Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/write address. Lowest VCS_CTRL_WIDTH (HDL g.." bitfld.byte 0x00 7. " VC7_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 6. " VC6_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 5. " VC5_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" textline " " bitfld.byte 0x00 4. " VC4_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 3. " VC3_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 2. " VC2_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" textline " " bitfld.byte 0x00 1. " VC1_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 0. " VC0_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" rgroup.byte 0x34++0x0 line.byte 0x00 "UTMI_VCONTROL_LATCH_i_0,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. Set by unmasked changes on the corresponding vcontrol_status bits to generate the ULPI ALT interrupt. Cleared upon read, and when .." bitfld.byte 0x00 7. " VC7_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 6. " VC6_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 5. " VC5_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" textline " " bitfld.byte 0x00 4. " VC4_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 3. " VC3_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 2. " VC2_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" textline " " bitfld.byte 0x00 1. " VC1_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 0. " VC0_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" group.byte 0x33++0x0 line.byte 0x00 "UTMI_VCONTROL_STATUS_i_0,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vcontrol vector byte is sent by the UTMI controller (other side of TLL) to its PHY (emulated here by the TLL). Alte.." hexmask.byte 0x00 0.--7. 1. " VC ,User-defined UTMI Control data byte" group.byte 0x37++0x0 line.byte 0x00 "UTMI_VSTATUS_CLR_i_0,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): informati.." hexmask.byte 0x00 0.--7. 1. " VS ,User-defined UTMI status data byte: Write 0x0: No effect on bit value Write 0x1: Clear the bit to 0." group.byte 0x36++0x0 line.byte 0x00 "UTMI_VSTATUS_SET_i_0,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): informati.." hexmask.byte 0x00 0.--7. 1. " VS ,User-defined UTMI status data byte Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." group.byte 0x35++0x0 line.byte 0x00 "UTMI_VSTATUS_i_0,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): information w.." hexmask.byte 0x00 0.--7. 1. " VS ,User-defined UTMI status data byte" rgroup.byte 0x1++0x0 line.byte 0x00 "VENDOR_ID_HI_i_0,Upper byte of USB-IF-supplied 16-bit vendor ID Value is set for all channels. Default is Texas-Instruments Vendor ID = 0x0451." hexmask.byte 0x00 0.--7. 1. " VENDOR_ID_HI ," rgroup.byte 0x0++0x0 line.byte 0x00 "VENDOR_ID_LO_i_0,Lower byte of USB-IF-supplied 16-bit vendor ID Value is set for all channels. Default is Texas Instruments Vendor ID = 0x0451." hexmask.byte 0x00 0.--7. 1. " VENDOR_ID_LO ," group.byte 0x3D++0x0 line.byte 0x00 "VENDOR_INT_EN_CLR_i_0,Vendor-specific interrupt enables (mask) for miscellaneous ULPI alt_int events. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the .." bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm. - . - ." "0,1" group.byte 0x3C++0x0 line.byte 0x00 "VENDOR_INT_EN_SET_i_0,Vendor-specific interrupt enable bit (mask) for miscellaneous ULPI alt_int events. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the sa.." bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm. - . - ." "0,1" group.byte 0x3B++0x0 line.byte 0x00 "VENDOR_INT_EN_i_0,Vendor-specific interrupt enables (mask) for miscellaneous ULPI alt_int events. Read/write address." bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm. - . - ." "disabled,enabled" rgroup.byte 0x3F++0x0 line.byte 0x00 "VENDOR_INT_LATCH_i_0,Vendor-specific interrupt latches for miscellaneous ULPI alt_int events. Cleared upon read, and when low-power mode, serial mode or carkit mode are entered." bitfld.byte 0x00 0. " P2P_LATCH ,PHY-to-PHY ULPI wake-up event latch. Set when ULPI is in low-power mode (suspendm = 0) and UTMI is active (suspendm = 1). - . - ." "noevent,active" rgroup.byte 0x3E++0x0 line.byte 0x00 "VENDOR_INT_STATUS_i_0,Vendor-specific interrupt sources for miscellaneous ULPI alt_int events" bitfld.byte 0x00 0. " UTMI_SUSPENDM ,UTMI suspendm status (active-low), source of TLL PHY-to-PHY wake-up interrupt. - . - ." "suspended,active" tree.end tree "Channel_1" width 26. rgroup.byte 0x115++0x0 line.byte 0x00 "DEBUG_i_1,Indicates the current value of various signals useful for debugging." bitfld.byte 0x00 0.--1. " LINE_STATE ,Current state of the USB line: D+ (bit 0) and D? (bit 1). - . - . - . - ." "0,1,2,3" group.byte 0x12F++0x0 line.byte 0x00 "EXTENDED_SET_ACCESS_i_1,This address is used to access the extended register set; that is, addresses above 0x40." hexmask.byte 0x00 0.--7. 1. " SET_ACCESS ,This bit field is used to access the extended register set; that is, addresses above 0x40." group.byte 0x106++0x0 line.byte 0x00 "FUNCTION_CTRL_CLR_i_1,Controls UTMI function settings of the PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend: Puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit. - . - ." "0,1" bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset. Autocleared. Does not reset the ULPI interface or ULPI register set. - . - ." "0,1" bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit - . - ." "0,1,2,3" textline " " bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5-k? pull-up resistor and 45-? HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown. - . - ." "0,1" bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed. - . - ." "0,1,2,3" group.byte 0x105++0x0 line.byte 0x00 "FUNCTION_CTRL_SET_i_1,Controls UTMI function settings of the PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend: Puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit. - . - ." "0,1" bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset. Autocleared. Does not reset the ULPI interface or ULPI register set. - . - ." "0,1" bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit. - . - ." "0,1,2,3" textline " " bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5-k? pullup resistor and 45-? HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown. - . - ." "0,1" bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed. - . - ." "0,1,2,3" group.byte 0x104++0x0 line.byte 0x00 "FUNCTION_CTRL_i_1,Controls UTMI function settings of the PHY. Read/write address." bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend: puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit. - . - ." "LowPowerMode,NotSuspended" bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset. Auto-cleared. Does not reset the ULPI interface or ULPI register set. - . - ." "NoReset,Reset" bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit - . - . - . - ." "Opmode00,Opmode01,Opmode10,Opmode11" textline " " bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5-k? HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown. - . - ." "hs,fs" bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed. - . - . - . - ." "XcrSelect00,XcrSelect01,XcrSelect10,XcrSelect11" group.byte 0x109++0x0 line.byte 0x00 "INTERFACE_CTRL_CLR_i_1,Enables alternative interfaces and PHY features. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data. - . - ." "0,1" bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling. On by default. - . - ." "0,1" bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes (6-pin/3-pin). - . - ." "0,1" textline " " bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Autocleared when serial mode is exited. - . - ." "0,1" bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Autocleared when serial mode is exited. - . - ." "0,1" group.byte 0x108++0x0 line.byte 0x00 "INTERFACE_CTRL_SET_i_1,Enables alternative interfaces and PHY features. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data. - . - ." "0,1" bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling. On by default. - . - ." "0,1" bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes (6-pin/3-pin). - . - ." "0,1" textline " " bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Autocleared when serial mode is exited. - . - ." "0,1" bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Autocleared when serial mode is exited. - . - ." "0,1" group.byte 0x107++0x0 line.byte 0x00 "INTERFACE_CTRL_i_1,Enables alternative interfaces and PHY features. Read/write address." bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data. - . - ." "Enabled,Disabled" bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling. On by default. - . - ." "Disabled,Enabled" bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes (6-pin/3-pin). - . - ." "Suspend,KeepActive" textline " " bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Auto-cleared when serial mode is exited. - . - ." "Disabled,Enabled" bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Auto-cleared when serial mode is exited. - . - ." "Disabled,Enabled" group.byte 0x10C++0x0 line.byte 0x00 "OTG_CTRL_CLR_i_1,Controls UTMI+ OTG functions of the PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." bitfld.byte 0x00 5. " DRVVBUS ,Drive 5 V on VBUS - . - ." "0,1" bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP. - . - ." "0,1" bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor, until the session-end VBUS state is reached. - . - ." "0,1" textline " " bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15k pulldown resistor on D? - . - ." "0,1" bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15k? pulldown resistor on D+ - . - ." "0,1" bitfld.byte 0x00 0. " IDPULLUP ,Pullup to the (OTG) ID line to allow its sampling - . - ." "0,1" group.byte 0x10B++0x0 line.byte 0x00 "OTG_CTRL_SET_i_1,Controls UTMI+ OTG functions of the PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." bitfld.byte 0x00 5. " DRVVBUS ,Drive 5 V on VBUS - . - ." "0,1" bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP. - . - ." "0,1" bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor, until the session-end VBUS state is reached. - . - ." "0,1" textline " " bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15-k? pulldown resistor on D? - . - ." "0,1" bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15-k? pulldown resistor on D+ - . - ." "0,1" bitfld.byte 0x00 0. " IDPULLUP ,Pullup to the (OTG) ID line to allow its sampling - . - ." "0,1" group.byte 0x10A++0x0 line.byte 0x00 "OTG_CTRL_i_1,Controls UTMI+ OTG functions of the PHY. Read/write address." bitfld.byte 0x00 5. " DRVVBUS ,Drive 5 V on VBUS - . - ." "noaction,drive" bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP. - . - ." "noaction,charge" bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor, until the session-end VBUS state is reached. - . - ." "NoAction,Discharge" textline " " bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15-k? pulldown resistor on D? - . - ." "Disabled,Enabled" bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15-k? pulldown resistor on D+ - . - ." "Disabled,Enabled" bitfld.byte 0x00 0. " IDPULLUP ,Pullup to the (OTG) ID line to allow its sampling - . - ." "Disable,Enable" rgroup.byte 0x103++0x0 line.byte 0x00 "PRODUCT_ID_HI_i_1,Upper byte of 16-bit product ID Value is set for all channels. Default is" hexmask.byte 0x00 0.--7. 1. " PRODUCT_ID_HI ," rgroup.byte 0x102++0x0 line.byte 0x00 "PRODUCT_ID_LO_i_1,Lower byte of 16-bit product ID Value is set for all channels. Default is" hexmask.byte 0x00 0.--7. 1. " PRODUCT_ID_LO ," group.byte 0x118++0x0 line.byte 0x00 "SCRATCH_REGISTER_CLR_i_1,Register byte for register access testing purposes. Value has no functional effect on PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/write ad.." hexmask.byte 0x00 0.--7. 1. " SCRATCH ,Scratch data Write 1 to a bit to clear it to 0. Writing 0 has no effect on bit value." group.byte 0x117++0x0 line.byte 0x00 "SCRATCH_REGISTER_SET_i_1,Register byte for register access testing purposes. Value has no functional effect on PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write addres.." hexmask.byte 0x00 0.--7. 1. " SCRATCH ,Scratch data Write 1 to a bit to set it to 1. Writing 0 has no effect on bit value." group.byte 0x116++0x0 line.byte 0x00 "SCRATCH_REGISTER_i_1,Register byte for register access testing purposes. Value has no functional effect on PHY. Read/write address." hexmask.byte 0x00 0.--7. 1. " SCRATCH ,Scratch data" group.byte 0x112++0x0 line.byte 0x00 "USB_INT_EN_FALL_CLR_i_1,Enables an interrupt event notification when the corresponding status bit changes from high to low. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/.." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" group.byte 0x111++0x0 line.byte 0x00 "USB_INT_EN_FALL_SET_i_1,Enables an interrupt event notification when the corresponding status bit changes from high to low. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/wri.." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" group.byte 0x110++0x0 line.byte 0x00 "USB_INT_EN_FALL_i_1,Enables an interrupt event notification when the corresponding status bit changes from high to low. By default, all transitions are enabled. Read/write address." bitfld.byte 0x00 4. " IDGND_FALL ,Generate an interrupt event notification when IdGnd changes from high to low. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1." "0,1" bitfld.byte 0x00 3. " SESSEND_FALL ,Generate an interrupt event notification when SessEnd changes from high to low." "0,1" bitfld.byte 0x00 2. " SESSVALID_FALL ,Generate an interrupt event notification when SessValid changes from high to low. SessValid is the same as UTMI+ AValid." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_FALL ,Generate an interrupt event notification when VbusValid changes from high to low." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_FALL ,Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)." "0,1" group.byte 0x10F++0x0 line.byte 0x00 "USB_INT_EN_RISE_CLR_i_1,Enables an interrupt event notification when the corresponding status bit changes from low to high. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See the field description at the r.." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" group.byte 0x10E++0x0 line.byte 0x00 "USB_INT_EN_RISE_SET_i_1,Enables an interrupt event notification when the corresponding status bit changes from low to high. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/wri.." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" group.byte 0x10D++0x0 line.byte 0x00 "USB_INT_EN_RISE_i_1,Enables an interrupt event notification when the corresponding status bit changes from low to high. By default, all transitions are enabled. Read/write address." bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50ms after IdPullup is set to 1. - . - ." "0,1" bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification when SessEnd changes from low to high. - . - ." "0,1" bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid. - . - ." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification when VbusValid changes from low to high. - . - ." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). - . - ." "0,1" rgroup.byte 0x138++0x0 line.byte 0x00 "USB_INT_LATCH_NOCLR_i_1,Set by unmasked changes on the corresponding status bits to generate the ULPI interrupt. Debug, nonstandard address to the standard register: Register is not cleared on read. See field description at the 'clear-on-read' address .." bitfld.byte 0x00 4. " IDGND_LATCH ,Set to 1 by the PHY when an unmasked event occurs on IdGnd." "0,1" bitfld.byte 0x00 3. " SESSEND_LATCH ,Set to 1 by the PHY when an unmasked event occurs on SessEnd." "0,1" bitfld.byte 0x00 2. " SESSVALID_LATCH ,Set to 1 by the PHY when an unmasked event occurs on SessValid. SessValid is the same as UTMI+ AValid." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_LATCH ,Set to 1 by the PHY when an unmasked event occurs on VbusValid." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_LATCH ,Set to 1 by the PHY when an unmasked event occurs on Hostdisconnect. Applicable only in host mode." "0,1" rgroup.byte 0x114++0x0 line.byte 0x00 "USB_INT_LATCH_i_1,Set by unmasked changes on the corresponding status bits to generate the ULPI interrupt. Cleared upon read, and when low-power mode, serial mode, or carkit mode are entered." bitfld.byte 0x00 4. " IDGND_LATCH ,Set to 1 by the PHY when an unmasked event occurs on IdGnd. Cleared when this register is read." "0,1" bitfld.byte 0x00 3. " SESSEND_LATCH ,Set to 1 by the PHY when an unmasked event occurs on SessEnd. Cleared when this register is read." "0,1" bitfld.byte 0x00 2. " SESSVALID_LATCH ,Set to 1 by the PHY when an unmasked event occurs on SessValid. Cleared when this register is read. SessValid is the same as UTMI+ AValid." "0,1" textline " " bitfld.byte 0x00 1. " VBUSVALID_LATCH ,Set to 1 by the PHY when an unmasked event occurs on VbusValid. Cleared when this register is read." "0,1" bitfld.byte 0x00 0. " HOSTDISCONNECT_LATCH ,Set to 1 by the PHY when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode." "0,1" rgroup.byte 0x113++0x0 line.byte 0x00 "USB_INT_STATUS_i_1,Indicates the current value of the interrupt source signal." bitfld.byte 0x00 4. " IDGND ,Value of UTMI+ IdDig output. Undefined unless IdPullup = 1 - . - ." "IdA,IdB" bitfld.byte 0x00 3. " SESSEND ,Current value of UTMI+ SessEnd output. - . - ." "notended,ended" bitfld.byte 0x00 2. " SESSVALID ,Current value of UTMI+ SessValid output. SessValid is the same as UTMI+ AValid. - . - ." "notvalid,valid" textline " " bitfld.byte 0x00 1. " VBUSVALID ,Current value of UTMI+ VbusValid output. - . - ." "notvalid,valid" bitfld.byte 0x00 0. " HOSTDISCONNECT ,Current value of UTMI+ Hostdisconnect output. Applicable only in host mode. Automatically reset to 0 when low-power mode is entered. - . - ." "NotDisconnected,Disconnected" group.byte 0x132++0x0 line.byte 0x00 "UTMI_VCONTROL_EN_CLR_i_1,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/clear address (write 1 to a bit to cle.." hexmask.byte 0x00 0.--7. 1. " VC ,User-defined UTMI control data byte" group.byte 0x131++0x0 line.byte 0x00 "UTMI_VCONTROL_EN_SET_i_1,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1 Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/set address (write 1 to a bit to set it.." bitfld.byte 0x00 7. " VC7_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 6. " VC6_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 5. " VC5_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" textline " " bitfld.byte 0x00 4. " VC4_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 3. " VC3_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 2. " VC2_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" textline " " bitfld.byte 0x00 1. " VC1_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 0. " VC0_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" group.byte 0x130++0x0 line.byte 0x00 "UTMI_VCONTROL_EN_i_1,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1 Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/write address. Lowest VCS_CTRL_WIDTH (HDL g.." bitfld.byte 0x00 7. " VC7_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 6. " VC6_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 5. " VC5_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" textline " " bitfld.byte 0x00 4. " VC4_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 3. " VC3_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 2. " VC2_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" textline " " bitfld.byte 0x00 1. " VC1_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" bitfld.byte 0x00 0. " VC0_EN ,Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." "0,1" rgroup.byte 0x134++0x0 line.byte 0x00 "UTMI_VCONTROL_LATCH_i_1,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. Set by unmasked changes on the corresponding vcontrol_status bits to generate the ULPI ALT interrupt. Cleared upon read, and when .." bitfld.byte 0x00 7. " VC7_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 6. " VC6_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 5. " VC5_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" textline " " bitfld.byte 0x00 4. " VC4_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 3. " VC3_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 2. " VC2_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" textline " " bitfld.byte 0x00 1. " VC1_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" bitfld.byte 0x00 0. " VC0_CHANGE ,Unmasked change on vcontrol_status bit" "0,1" group.byte 0x133++0x0 line.byte 0x00 "UTMI_VCONTROL_STATUS_i_1,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vcontrol vector byte is sent by the UTMI controller (other side of TLL) to its PHY (emulated here by the TLL). Alte.." hexmask.byte 0x00 0.--7. 1. " VC ,User-defined UTMI Control data byte" group.byte 0x137++0x0 line.byte 0x00 "UTMI_VSTATUS_CLR_i_1,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): informati.." hexmask.byte 0x00 0.--7. 1. " VS ,User-defined UTMI status data byte: Write 0x0: No effect on bit value Write 0x1: Clear the bit to 0." group.byte 0x136++0x0 line.byte 0x00 "UTMI_VSTATUS_SET_i_1,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): informati.." hexmask.byte 0x00 0.--7. 1. " VS ,User-defined UTMI status data byte Write 0x0: No effect on bit value Write 0x1: Set the bit to 1." group.byte 0x135++0x0 line.byte 0x00 "UTMI_VSTATUS_i_1,Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): information w.." hexmask.byte 0x00 0.--7. 1. " VS ,User-defined UTMI status data byte" rgroup.byte 0x101++0x0 line.byte 0x00 "VENDOR_ID_HI_i_1,Upper byte of USB-IF-supplied 16-bit vendor ID Value is set for all channels. Default is Texas-Instruments Vendor ID = 0x0451." hexmask.byte 0x00 0.--7. 1. " VENDOR_ID_HI ," rgroup.byte 0x100++0x0 line.byte 0x00 "VENDOR_ID_LO_i_1,Lower byte of USB-IF-supplied 16-bit vendor ID Value is set for all channels. Default is Texas Instruments Vendor ID = 0x0451." hexmask.byte 0x00 0.--7. 1. " VENDOR_ID_LO ," group.byte 0x13D++0x0 line.byte 0x00 "VENDOR_INT_EN_CLR_i_1,Vendor-specific interrupt enables (mask) for miscellaneous ULPI alt_int events. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the .." bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm. - . - ." "0,1" group.byte 0x13C++0x0 line.byte 0x00 "VENDOR_INT_EN_SET_i_1,Vendor-specific interrupt enable bit (mask) for miscellaneous ULPI alt_int events. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the sa.." bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm. - . - ." "0,1" group.byte 0x13B++0x0 line.byte 0x00 "VENDOR_INT_EN_i_1,Vendor-specific interrupt enables (mask) for miscellaneous ULPI alt_int events. Read/write address." bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm. - . - ." "disabled,enabled" rgroup.byte 0x13F++0x0 line.byte 0x00 "VENDOR_INT_LATCH_i_1,Vendor-specific interrupt latches for miscellaneous ULPI alt_int events. Cleared upon read, and when low-power mode, serial mode or carkit mode are entered." bitfld.byte 0x00 0. " P2P_LATCH ,PHY-to-PHY ULPI wake-up event latch. Set when ULPI is in low-power mode (suspendm = 0) and UTMI is active (suspendm = 1). - . - ." "noevent,active" rgroup.byte 0x13E++0x0 line.byte 0x00 "VENDOR_INT_STATUS_i_1,Vendor-specific interrupt sources for miscellaneous ULPI alt_int events" bitfld.byte 0x00 0. " UTMI_SUSPENDM ,UTMI suspendm status (active-low), source of TLL PHY-to-PHY wake-up interrupt. - . - ." "suspended,active" tree.end tree.end tree.end tree.open "High_Speed_USB_OTG_Controller" tree "HSUSBOTG" base ad:0x4A0AB000 width 16. group.long 0x400++0x3 line.long 0x00 "OTG_REVISION,OCP standard USB OTG HS core revision number" group.long 0x404++0x3 line.long 0x00 "OTG_SYSCONFIG,OCP standard configuration" bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management control. Standby/wait control - . - . - ." "0,1,2,3" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management control. Req/ack control - . - . - . - ." "0,1,2,3" bitfld.long 0x00 2. " ENABLEWAKEUP ,Enable wakeup capability. - . - ." "Wakeup_disabled,Wakeup_enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset bit - ." "0,1" bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit - . - ." "Clock_always_runnning,1" rgroup.long 0x408++0x3 line.long 0x00 "OTG_SYSSTATUS,OCP standard status" bitfld.long 0x00 0. " RESETDONE ,Reset done - . - ." "Reset_is_ongoing,Reset_is_finished." group.long 0x40C++0x3 line.long 0x00 "OTG_INTERFSEL,USB OTG HS interface selection. The interface selection has to be done before the PHY is activated and is not allowed to change when the PHY clock is already running." bitfld.long 0x00 0.--2. " PHYSEL ,PHY interface selection - . - . - ." "0,1,2,3,4,5,6,7" group.long 0x410++0x3 line.long 0x00 "OTG_SIMENABLE,Enable simulation acceleration features. WARNING: For simulations only, since those features have an impact on USB protocol." bitfld.long 0x00 0. " TM1 ,Test Mode 1 enabling (timer shortcuts)" "0,1" group.long 0x414++0x3 line.long 0x00 "OTG_FORCESTDBY,Enabling MSTANDBY in FORCESTANDBY mode. Programming this register will impact SmartStandby functionality." bitfld.long 0x00 0. " ENABLEFORCE ,Enabling MSTANDBY to go high" "0,1" group.long 0x418++0x3 line.long 0x00 "OTG_BIGENDIAN,Enable BIG ENDIANESS for OCP MASTER" bitfld.long 0x00 0. " BIG_ENDIAN ,Enable BIG ENDIAN in OCP MASTER" "0,1" tree.end tree "OCP2SCP" base ad:0x4A0AD000 width 19. rgroup.long 0x0++0x3 line.long 0x00 "OCP2SCP_REVISION,IP revision identifier" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision number" group.long 0x10++0x3 line.long 0x00 "OCP2SCP_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,Module power management control - . - . - . - ." "0,1,2,?..." bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. During reads, it always returns 0. - . - ." "Normal_mode,1" bitfld.long 0x00 0. " AUTOIDLE ,OCP clock-gating control - . - ." "0,1" rgroup.long 0x14++0x3 line.long 0x00 "OCP2SCP_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,0: Internal reset is on-going. - ." "0,Reset_is_complete." group.long 0x18++0x3 line.long 0x00 "OCP2SCP_TIMING,Timing configuration register" bitfld.long 0x00 7.--9. " DIVISIONRATIO ,Division ratio of the SCP clock in relation to the OCP input clock. When the value 0x0 is programmed, and the transaction to be made is a valid transaction on the SCP interface, the value of DIVISIONRATIO is set to 0x7 by hardware to av.." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " SYNC1 ,Number of SCP clock cycles defining SYNC1 delay" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " SYNC2 ,Number of SCP clock cycles defining the SYNC2 delay. When the value 0x0 is programmed, and the transaction to be made is a valid transaction on the SCP interface, SYNC2 is set to the minimum allowed value 0x1 to avoid a block on t.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "USBPHY" base ad:0x4A0AD080 width 30. group.long 0x0++0x3 line.long 0x00 "USBPHY_TERMINATION_CONTROL,Contains bits related to control of terminations in USBPHY" bitfld.long 0x00 29. " ALWAYS_UPDATE ,When set to 1, the calibration code is updated immediately after a code computation without waiting for idle periods." "0,1" bitfld.long 0x00 28. " RTERM_CAL_DONE ,Rterm calibration is done. First time cal is done this bit gets set and gets reset at a restart cal. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 24.--27. " FS_CODE_SEL ,FS Code selection control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " USE_RTERM_RMX_REG ,Override termination resistor trim code with RTERM_RMX from this register" "0,1" hexmask.long.byte 0x00 14.--20. 1. " RTERM_RMX ,When read, this field returns the current Termination resistor trim code. Read value is valid only if VDDLDO is on. The value written to this field is used as Termination resistor trim code if bit 21 is set to 1" bitfld.long 0x00 11.--13. " HS_CODE_SEL ,HS Code selection control. A higher positive value (for example, +3 -- 011) reduces the termination resistance and improves the vertical eye opening. - HS_CODE_SEL Offset Value Termination Calibrated Value . - . - 000.." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 10. " RTERM_COMP_OUT ,Master loop comparator output. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 9. " RESTART_RTERM_CAL ,Restart the rterm calibration. the calibration restarts on any toggle 0-1 or 1-0 on this bit." "0,1" bitfld.long 0x00 8. " DISABLE_TEMP_TRACK ,Disables the temperature tracking function of the termination calibration" "0,1" textline " " bitfld.long 0x00 7. " USE_RTERM_CAL_REG ,When 1, the rterm cal code is overridden by values in RTERM_CAL" "0,1" hexmask.long.byte 0x00 0.--6. 1. " RTERM_CAL ,When read this field returns the current rterm calibration code. Read value is valid only if VDDLDO is on. The value written to this filed is used as rterm calibration code if the bit USE_RTERM_CAL_REG is 1." group.long 0x4++0x3 line.long 0x00 "USBPHY_RX_CALIB,Contains bits related to RX calibration" bitfld.long 0x00 31. " RESTART_HSRX_CAL ,Restart the HSRX calibration state machine when this bit goes from 0 to 1." "0,1" bitfld.long 0x00 30. " USE_HS_OFF_REG ,Override HS offset correction with HS_OFF_CODE when set to 1" "0,1" bitfld.long 0x00 24.--29. " HS_OFF_CODE ,HS offset code, this code is forced when bit 30 is 1. Code is updated from calibration logic when bit 30 = 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 23. " HSRX_COMP_OUT ,The output of the HSRX comparator. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 22. " HSRX_CAL_DONE ,Signal that indicates that the HSRX calibration is done. This gets reset at every restart. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 21. " USE_SQ_OFF_DAC1 ,Override Squelch offset DAC1 code when '1'" "0,1" textline " " bitfld.long 0x00 15.--20. " SQ_OFF_CODE_DAC1 ,When read returns current Sq offset code for DAC1, if VDDLDO is on. When written this is used as Sq offset code for DAC1 when USE_SQ_OFF_DAC1 = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14. " USE_SQ_OFF_DAC2 ,Override Squelch offset DAC2 code when '1'" "0,1" bitfld.long 0x00 9.--13. " SQ_OFF_CODE_DAC2 ,When read returns current Sq offset code for DAC2, if VDDLDO is on. When written this is used as Sq offset code for DAC2 when USE_SQ_OFF_DAC2 = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8. " USE_SQ_OFF_DAC3 ,Override Squelch offset DAC3 code when 1" "0,1" bitfld.long 0x00 3.--7. " SQ_OFF_CODE_DAC3 ,When read returns current Sq offset code for DAC3, if VDDLDO is on. When written this is used as Sq offset code for DAC3 when USE_SQ_OFF_DAC3 = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " SQ_COMP_OUT ,Sq comp output.Read value is valid only if VDDLDO is on." "0,1" textline " " bitfld.long 0x00 1. " SQ_CAL_DONE ,Sq calibration is done when this bit = 1. See RESTART_SQ_CAL for more description. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 0. " RESTART_SQ_CAL ,The squelch calibration continuously goes through restart cycles when this bit is 1." "0,1" group.long 0x8++0x3 line.long 0x00 "USBPHY_DLLHS_2,Second DLLHS control register. Bits 4:0 are unrelated to the DLLHS and are linestate filter settings." hexmask.long.byte 0x00 24.--31. 1. " DLLHS_CNTRL_LDO ," hexmask.long.byte 0x00 16.--23. 1. " DLLHS_STATUS_LDO ," bitfld.long 0x00 4. " LINESTATE_DEBOUNCE_EN ,Enables the linestate debounce filter" "0,1" textline " " bitfld.long 0x00 0.--3. " LINESTATE_DEBOUNCE_CNTL ,Used for control of the linestate debounce filter when going from syncronous to async linestate." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC++0x3 line.long 0x00 "USBPHY_RX_TEST_2,Second receiver test register" bitfld.long 0x00 31. " HSOSREVERSAL ,Swaps the dataout from HSOS" "0,1" bitfld.long 0x00 30. " HSOSBITINVERSION ,Inverts the HSOS bits" "0,1" bitfld.long 0x00 29. " PHYCLKOUTINVERSION ,This inverts the phase for the PHYCLKOUT" "0,1" textline " " bitfld.long 0x00 28. " RXPIDERR ,Flags if the RX data packet has PID error. NOT IMPLEMENTED." "0,1" bitfld.long 0x00 27. " USEINTDATAOUT ,This will bypass the analog and will send data packet to controller incase of receiver (Faking the receive data). data used will be INTDATAOUTREG" "0,1" hexmask.long.word 0x00 11.--26. 1. " INTDATAOUTREG ,This register will be loaded through OCP and this data will be given to the controller if USEINTDATAOUT is set to 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " CDR_TESTOUT ,CDR debug bits. Read value is valid only if VDDLDO is on." group.long 0x10++0x3 line.long 0x00 "USBPHY_TX_TEST_CHRG_DET,TX test register and also charger detect register" bitfld.long 0x00 31. " TXSYNCERR ,Sync error on TX data. NOT IMPLEMENTED." "0,1" hexmask.long.word 0x00 15.--30. 1. " UTMIDATATX ,Stores Last 2 byte of transmit data coming from the controller. NOT IMPLEMENTED ." bitfld.long 0x00 13. " TXPIDERR ,Flags if the TX packet has PID error. NOT IMPLEMENTED." "0,1" textline " " bitfld.long 0x00 12. " USE_CHGDET_DPDMSW ,Use bits 11:8 as override bits" "0,1" bitfld.long 0x00 11. " CHGDET_DPSW0EN ,Overrides the same named A/D interface signal for the charger detect block" "0,1" bitfld.long 0x00 10. " CHGDET_DPSW1EN ,Overrides the same named A/D interface signal for the charger detect block. Read value is valid only if VCHGLDO is on." "0,1" textline " " bitfld.long 0x00 9. " CHGDET_DMSW0EN ,Overrides the same named A/D interface signal for the charger detect block. Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 8. " CHGDET_DMSW1EN ,Overrides the same named A/D interface signal for the charger detect block..Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 6. " RDPPDCHGDETEN ,When set to 1 connects a 15K (+/- 30%) pulldown resistor on DP. Read value is valid only if VCHGLDO is on." "0,1" textline " " bitfld.long 0x00 5. " RDMPDCHGDETEN ,When set to 1 connects a 15K (+/- 30%) pulldown resistor on DM. Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 4. " RDPPUCHGDETEN ,When set to 1 connects a 150K (+/- 30%) pullup resistor on DP. Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 3. " RDMPUCHGDETEN ,When set to 1 connects a 150K (+/- 30%) pullup resistor on DM. Read value is valid only if VCHGLDO is on." "0,1" textline " " bitfld.long 0x00 2. " USE_CHG_DET_PU_REG ,Use bits 4:3 from this register" "0,1" bitfld.long 0x00 1. " USE_CHG_DET_PD_REG ,Use bits 6:5 from this register." "0,1" group.long 0x14++0x3 line.long 0x00 "USBPHY_CHRG_DET,This is the charger detect register. This register is not used in the dead battery case." bitfld.long 0x00 29. " USE_CHG_DET_REG ,Use bits 28:24 and 18:17 from this register" "0,1" bitfld.long 0x00 28. " DIS_CHG_DET ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 27. " SRC_ON_DM ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" textline " " bitfld.long 0x00 26. " SINK_ON_DP ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 25. " CHG_DET_EXT_CTL ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 24. " RESTART_CHG_DET ,Restart the charger detection protocol when this goes from 0 to 1" "0,1" textline " " bitfld.long 0x00 23. " CHG_DET_DONE ,Charger detect protocol has completed" "0,1" bitfld.long 0x00 22. " CHG_DETECTED ,Same signal as CE pin" "0,1" bitfld.long 0x00 21. " DATA_DET ,Output of the data det comparator" "0,1" textline " " bitfld.long 0x00 18. " CHG_ISINK_EN ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 17. " CHG_VSRC_EN ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 16. " COMP_DP ,Comparator on the DP line value" "0,1" textline " " bitfld.long 0x00 15. " COMP_DM ,Comparator on the DM line value" "0,1" bitfld.long 0x00 13.--14. " CHG_DET_OSC_CNTRL ,Charger detect osc control" "0,1,2,3" bitfld.long 0x00 7.--12. " CHG_DET_TIMER ,Charger detect timer control." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 3.--4. " CHG_DET_ICTRL ,Charger detect current control" "0,1,2,3" bitfld.long 0x00 1.--2. " CHG_DET_VCTRL ,Charger detect voltage buffer control" "0,1,2,3" bitfld.long 0x00 0. " FOR_CE ,Force CE = 1 when this bit is set" "0,1" group.long 0x18++0x3 line.long 0x00 "USBPHY_PWR_CNTL,Includes all the power control bits" bitfld.long 0x00 31. " RESETDONETCLK ,Goes high when the RESET is synchronized to TCLK" "0,1" bitfld.long 0x00 30. " RESET_DONE_VMAIN ,Goes high when LDO domain is up, PLL LOCK is available, and utmi_reset is deasserted." "0,1" bitfld.long 0x00 29. " VMAIN_GLOBAL_RESET_DONE ,Goes high when LDO domain is up and PLL LOCK is available." "0,1" textline " " bitfld.long 0x00 28. " RESETDONEMCLK ,Goes high when the RESET is synchronized to MCLK" "0,1" bitfld.long 0x00 27. " RESETDONE_CHGDET ,Goes high when the RESET is synchronized to charger detect oscillator clock domain" "0,1" hexmask.long.word 0x00 12.--26. 1. " LDOPWRCOUNTER ,This is the value of the counter used for LDO power up. RESET to default." textline " " bitfld.long 0x00 11. " FORCEPLLSLOWCLK ,Forces the PLL to the slow clk mode" "0,1" bitfld.long 0x00 10. " FORCELDOON ,Forces the LDO to be ON." "0,1" bitfld.long 0x00 9. " FORCEPLLON ,Forces the PLL to be ON." "0,1" textline " " bitfld.long 0x00 6. " PLLLOCK ,Lock signal from the PLL" "0,1" bitfld.long 0x00 5. " USEPLLLOCK ,This signal is used to indicate to the Phy, not to do any clock related activity until PLLLOCK = 1.This is not the default option. 0 - do not use PLLLOCK. 1 - use PLLLOCK as a clock gate." "0,1" bitfld.long 0x00 4. " USE_DATAPOLARITYN_REG ,1 - use bit 3 as override for the DATAPOLARITYN signal." "0,1" textline " " bitfld.long 0x00 3. " DATAPOLARITYN ,Override value of datapolarityn" "0,1" bitfld.long 0x00 2. " USE_PD_REG ,Use bit 1 from this register as PD override when set to 1" "0,1" bitfld.long 0x00 1. " PD ,Override value for PD" "0,1" group.long 0x1C++0x3 line.long 0x00 "USBPHY_UTMI_INTERFACE_CNTL_1,register to override UTMI interface control pins." bitfld.long 0x00 31. " USEUTMIDATAREG ,Use datain from UTMI interface register" "0,1" hexmask.long.word 0x00 15.--30. 1. " UTMIDATAIN ,Override value for the UTMIDATAIN" bitfld.long 0x00 13. " USEDATABUSREG ,When set to 1 use bit 12 from register instead of interface" "0,1" textline " " bitfld.long 0x00 12. " DATABUS16OR8 ,Override value for UTMI signal DATABUS16OR8" "0,1" bitfld.long 0x00 11. " USEOPMODEREG ,When set to 1 use bits 10:9 from register instead of interface" "0,1" bitfld.long 0x00 9.--10. " OPMODE ,Override value for UTMI signal OPMODE[1:0]" "0,1,2,3" textline " " bitfld.long 0x00 8. " OVERRIDESUSRESET ,Override the suspend and reset values. Use bits 6 and 7" "0,1" bitfld.long 0x00 7. " SUSPENDM ,Override value for UTMI signal SUSPENDM" "0,1" bitfld.long 0x00 6. " UTMIRESET ,Override value for UTMI signal UTMIRESET" "0,1" textline " " bitfld.long 0x00 5. " OVERRIDEXCVRSEL ,When set to 1 use bits 4:3 from register instead of interface" "0,1" bitfld.long 0x00 3.--4. " XCVRSEL ,Override value for UTMI signal XCVRSEL[1:0]" "0,1,2,3" bitfld.long 0x00 2. " USETXVALIDREG ,When set to 1 use bits 1:0 from register instead of interface" "0,1" textline " " bitfld.long 0x00 1. " TXVALID ,Override value for UTMI signal TXVALID" "0,1" bitfld.long 0x00 0. " TXVALIDH ,Override value for UTMI signal TXVALIDH" "0,1" group.long 0x20++0x3 line.long 0x00 "USBPHY_UTMI_INTERFACE_CNTL_2,UTMI interface override and observe register 2" bitfld.long 0x00 31. " RXRCV ,Read for UTMI signal. Read value is valid only if VDDLDO is on. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 30. " RXDP ,Read for UTMI signal. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 29. " RXDM ,Read for UTMI signal. Read value is valid only if VDDLDO is on." "0,1" textline " " bitfld.long 0x00 28. " HOSTDISCONNECT ,Read for UTMI signal. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 26.--27. " LINESTATE ,Read for UTMI signal. Read value is valid only if VDDLDO is on." "0,1,2,3" bitfld.long 0x00 25. " RXVALID ,Read for UTMI signal. Read value is valid only if VDDLDO is on." "0,1" textline " " bitfld.long 0x00 24. " RXVALIDH ,Read for UTMI signal. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 23. " RXACTIVE ,Read for UTMI signal. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 22. " RXERROR ,Read for UTMI signal. Read value is valid only if VDDLDO is on." "0,1" textline " " bitfld.long 0x00 21. " TXREADY ,Read for UTMI signal. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 20. " UTMIRESETDONE ,Read for UTMIRESETDONE signal" "0,1" bitfld.long 0x00 19. " USEBITSTUFFREG ,When set to 1 use bits 18-17 from register instead of interface" "0,1" textline " " bitfld.long 0x00 18. " TXBITSTUFFENABLE ,Override value for signal TXBITSTUFFENABLE" "0,1" bitfld.long 0x00 17. " TXBITSTUFFENABLEH ,Override value for pin TXBITSTUFFENABLE" "0,1" bitfld.long 0x00 16. " USETERMCONTROLREG ,When set to 1, bits 15:13 from register are used instead of interface" "0,1" textline " " bitfld.long 0x00 15. " TERMSEL ,Override value for signal TERMSEL" "0,1" bitfld.long 0x00 14. " DPPULLDOWN ,Override value for signal DPPULLDOWN" "0,1" bitfld.long 0x00 13. " DMPULLDOWN ,Override value for signal DMPULLDOWN" "0,1" textline " " bitfld.long 0x00 9. " USEREGSERIALMODE ,When set to 1 use bits 8:5 from register instead of interface" "0,1" bitfld.long 0x00 8. " TXSE0 ,Override value for signal TXSE0" "0,1" bitfld.long 0x00 7. " TXDAT ,Override value for signal TXDAT" "0,1" textline " " bitfld.long 0x00 6. " FSLSSERIALMODE ,Override value for signal FSLSSERIALMODE" "0,1" bitfld.long 0x00 5. " TXENABLEN ,Override value for signal TXENABLEN" "0,1" bitfld.long 0x00 0. " SIG_BYPASS_SUSPENDMPULSE_INCR ,If the suspend signal is asserted for a short time, it is pulse-extended so that the sampling logic samples it reliably. - . - ." "Pulse_extension_active,Bypass_pulse_extension" group.long 0x24++0x3 line.long 0x00 "USBPHY_BIST,COntains bits related to the built in self test of the phy" bitfld.long 0x00 31. " BIST_START ,When set to 1 the BIST mode is started." "0,1" bitfld.long 0x00 30. " REDUCED_SWING ,When 1 the TX swing is reduced in BIST mode" "0,1" bitfld.long 0x00 29. " BIST_CRC_CALC_EN ,Enables CRC calculation during BIST when set to 1" "0,1" textline " " hexmask.long.word 0x00 20.--28. 1. " BIST_PKT_LENGTH ,Address for which BIST to select" bitfld.long 0x00 19. " LOOPBACK_EN ,Enables the loopback mode" "0,1" bitfld.long 0x00 16.--18. " BIST_OP_PHASE_SEL ,Selects which phase to use for data transmission during BIST" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " SWEEP_EN ,Enables freq sweep on CDR" "0,1" bitfld.long 0x00 12.--14. " SWEEP_MODE ,Selects the freq sweep mode." "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " BIST_PASS ,Indicates that the BIST has passed. Read value is valid only if VDDLDO is on." "0,1" textline " " bitfld.long 0x00 10. " BIST_BUSY ,Indicates that BIST is running. Read value is valid only if VDDLDO is on." "0,1" bitfld.long 0x00 5.--6. " OP_CODE ," "0,1,2,3" bitfld.long 0x00 4. " RX_TEST_MODE ," "0,1" textline " " bitfld.long 0x00 2. " INTER_PKT_DELAY_TEST ," "0,1" bitfld.long 0x00 1. " HS_ALL_ONES_TEST ," "0,1" bitfld.long 0x00 0. " USE_BIST_TX_PHASES ,When set to 1 bits 18:16 are activated for choosing the transmitting phase." "0,1" group.long 0x28++0x3 line.long 0x00 "USBPHY_BIST_CRC,CRC code for BIST test" hexmask.long 0x00 0.--31. 1. " BIST_CRC ,The CRC value from the BIST." group.long 0x2C++0x3 line.long 0x00 "USBPHY_CDR_BIST2,clock data recovery register and BIST register 2" bitfld.long 0x00 31. " CDR_EXE_EN ,CDR debug bits" "0,1" bitfld.long 0x00 28.--30. " CDR_EXE_MODE ,CDR debug bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--27. " NUM_DECISIONS ,CDR debug bits" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--11. " BIST_START_ADDR ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " BIST_END_ADDR ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30++0x3 line.long 0x00 "USBPHY_GPIO,GPIO mode configurations and reads" bitfld.long 0x00 31. " USEGPIOMODEREG ,When set to 1 use bits 31:24 from this register instead of primary inputs" "0,1" bitfld.long 0x00 30. " GPIOMODE ,Overrides the corresponding primary input" "0,1" bitfld.long 0x00 29. " DPGPIOGZ ,Overrides the corresponding primary input" "0,1" textline " " bitfld.long 0x00 28. " DMGPIOGZ ,Overrides the corresponding primary input" "0,1" bitfld.long 0x00 27. " DPGPIOA ,Overrides the corresponding primary input" "0,1" bitfld.long 0x00 26. " DMGPIOA ,Overrides the corresponding primary input" "0,1" textline " " bitfld.long 0x00 25. " DPGPIOY ,The GPIO Y output is stored here" "0,1" bitfld.long 0x00 24. " DMGPIOY ,The GPIO Y output is stored here" "0,1" bitfld.long 0x00 23. " GPIO1P8VCONFIG ,Overrides the corresponding primary input" "0,1" textline " " bitfld.long 0x00 20.--22. " GPIOCONFIG ,Used for configuring the GPIOs." "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " DMGPIOPIPD ,GPIO mode DM pull-down enabled. Overrides the corresponding primary input" "0,1" bitfld.long 0x00 18. " DPGPIOPIPD ,GPIO mode DP pull-down enabled. Overrides the corresponding primary input." "0,1" group.long 0x34++0x3 line.long 0x00 "USBPHY_DLLHS,Bits for control and debug of the DLL inside the USBPHY" bitfld.long 0x00 28. " DLLHS_LOCK ,Read the AFE output by this name" "0,1" bitfld.long 0x00 22.--27. " DLLHS_GENERATED_CODE ,Read the AFE output by this name.Read value is valid only if VDDLDO is on." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21. " DLL_SEL_CODE_PHS ,Connect to DLLHS_TEST_LDO[0] on AFE interface." "0,1" textline " " bitfld.long 0x00 19.--20. " DLL_LOCKCHK ,Connect to DLLHS_TEST_LDO[2:1] on AFE interface." "0,1,2,3" bitfld.long 0x00 16.--18. " DLL_SEL_COD ,Connect to DLLHS_TEST_LDO[5:3] on AFE interface." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " DLL_PHS0_8 ,Connect to DLLHS_TEST_LDO[6] on AFE interface." "0,1" textline " " bitfld.long 0x00 9.--14. " DLL_FORCED_CODE ,Connect to the pin of this name on AFE interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8. " FORCE_DLL_CODE ,Connect to DLLHS_TEST_LDO[11] on AFE interface." "0,1" bitfld.long 0x00 6.--7. " DLL_RATE ,Connect to DLLHS_TEST_LDO[8:7] on AFE interface." "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " DLL_FILT ,Connect to DLLHS_TEST_LDO[10:9] on AFE interface." "0,1,2,3" bitfld.long 0x00 3. " DLL_CDR_MODE ,Connect to the pin of this name on AFE interface." "0,1" bitfld.long 0x00 2. " DLL_IDLE ,Connect to DLLHS_TEST_LDO[12] on AFE interface." "0,1" textline " " bitfld.long 0x00 1. " DLL_FREEZE ,Connect to DLLHS_TEST_LDO[13] on AFE interface." "0,1" group.long 0x38++0x3 line.long 0x00 "USBPHY_USB2PHYCM_TRIM,Contains trim bit overrides for the USBPHYCM" bitfld.long 0x00 31. " USEBGTRIM ,When set to 1 bits 30:16 are used as the trim value for the USBPHYCM bandgap" "0,1" hexmask.long.word 0x00 16.--30. 1. " BGTRIM ,Override value for the BGTRIM value" bitfld.long 0x00 15. " USE_SW_TRIM ,Use bits 14:8 to override the switch cap trim value." "0,1" textline " " hexmask.long.byte 0x00 8.--14. 1. " SWTRIM ,Override value for the switch cap trim value." bitfld.long 0x00 7. " USE_NWELLTRIM_REG ,Override NWELL resistor trim using NWELLTRIM_CODE" "0,1" bitfld.long 0x00 4.--6. " NWELLTRIM_CODE ,NWELL resistor trim code." "0,1,2,3,4,5,6,7" group.long 0x3C++0x3 line.long 0x00 "USBPHY_USB2PHYCM_CONFIG,Configuration and status register for the USBPHYCM and LDO" hexmask.long.byte 0x00 24.--31. 1. " CONFIGURECM ,Connects to the CONFIGURECM pins." bitfld.long 0x00 18.--23. " CMSTATUS ,Reads the CMSTATUS bits." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 2.--17. 1. " LDOCONFIG ,The LDOCONFIG bit settings." textline " " bitfld.long 0x00 0.--1. " LDOSTATUS ,Reads the LDOSTATUS bits." "0,1,2,3" group.long 0x40++0x3 line.long 0x00 "USBPHY_USBOTG," hexmask.long.word 0x00 16.--31. 1. " TESTOTGCONFIG ,Used to control the OTG module if used." hexmask.long.word 0x00 6.--15. 1. " TESTOTGSTATUS ,The OTG status bits (if OTG macro is used)" group.long 0x44++0x3 line.long 0x00 "USBPHY_AD_INTERFACE_REG1,All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name. All the bits of this register, except the over-ride bits return a '0' on read, if VDDLDO is off." bitfld.long 0x00 31. " USE_AD_DATA_REG ,Override for bits 30:29" "0,1" bitfld.long 0x00 30. " HS_TX_DATA ," "0,1" bitfld.long 0x00 29. " FS_TX_DATA ," "0,1" textline " " bitfld.long 0x00 28. " TEST_PRE_EN_CNTRL ,Override for bits 27:25" "0,1" bitfld.long 0x00 27. " SQ_PRE_EN ," "0,1" bitfld.long 0x00 26. " HS_TX_PRE_EN ," "0,1" textline " " bitfld.long 0x00 25. " HS_RX_PRE_EN ," "0,1" bitfld.long 0x00 24. " TEST_EN_CNTRL ,Override for bits 23:19" "0,1" bitfld.long 0x00 23. " HS_TX_EN ," "0,1" textline " " bitfld.long 0x00 22. " FS_RX_EN ," "0,1" bitfld.long 0x00 20. " SQ_EN ," "0,1" bitfld.long 0x00 19. " HS_RX_EN ," "0,1" textline " " bitfld.long 0x00 18. " TEST_HS_MODE ,Override for bits 17:16" "0,1" bitfld.long 0x00 17. " HS_HV_SW ," "0,1" bitfld.long 0x00 16. " HS_CHIRP ," "0,1" textline " " bitfld.long 0x00 15. " TEST_FS_MODE ,Override for bits 14:12" "0,1" bitfld.long 0x00 14. " FSTX_GZ ," "0,1" bitfld.long 0x00 13. " FSTX_PRE_EN ," "0,1" textline " " bitfld.long 0x00 11. " TEST_SQ_CAL_CONTROL ,Override for bits 10:8" "0,1" bitfld.long 0x00 10. " SQ_CAL_EN3 ," "0,1" bitfld.long 0x00 9. " SQ_CAL_EN1 ," "0,1" textline " " bitfld.long 0x00 8. " SQ_CAL_EN2 ," "0,1" bitfld.long 0x00 7. " TEST_RTERM_CAL_CONTROL ,Override for bits 6" "0,1" bitfld.long 0x00 6. " RTERM_CAL_EN ," "0,1" textline " " bitfld.long 0x00 5. " DLL_RX_DATA ," "0,1" bitfld.long 0x00 4. " DISCON_DETECT ," "0,1" bitfld.long 0x00 3. " USE_LSHOST_REG ,Use bit 2 for this reg" "0,1" textline " " bitfld.long 0x00 2. " LSHOSTMODE ," "0,1" bitfld.long 0x00 1. " LSFS_RX_DATA ," "0,1" bitfld.long 0x00 0. " SQUELCH ," "0,1" group.long 0x48++0x3 line.long 0x00 "USBPHY_AD_INTERFACE_REG2,All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name. All the bits of this register, except the override bits return a '0' on read, if VDDLDO is off." bitfld.long 0x00 31. " USE_SUSP_DRV_REG ,Use bits 30:27 from this register as overrides" "0,1" bitfld.long 0x00 30. " SUS_DRV_DP_DATA ," "0,1" bitfld.long 0x00 29. " SUS_DRV_DP_EN ," "0,1" textline " " bitfld.long 0x00 28. " SUS_DRV_DM_DATA ," "0,1" bitfld.long 0x00 27. " SUS_DRV_DM_EN ," "0,1" bitfld.long 0x00 26. " USE_DISCON_REG ,Use bits 25:24 from this register as override" "0,1" textline " " bitfld.long 0x00 25. " DISCON_EN ," "0,1" bitfld.long 0x00 24. " DISCON_PRE_EN ," "0,1" bitfld.long 0x00 18.--22. " SPARE_OUT_CORE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 17. " SERX_DP_CORE ," "0,1" bitfld.long 0x00 16. " SERX_DM_CORE ," "0,1" bitfld.long 0x00 15. " USE_HSRX_CAL_EN_REG ,Use bit 14 from this register as override" "0,1" textline " " bitfld.long 0x00 14. " HSRX_CAL_EN ," "0,1" bitfld.long 0x00 13. " USE_RPU_RPD_REG ,Use override from bits 12:7" "0,1" bitfld.long 0x00 12. " RPU_DP_SW1_EN_CORE ," "0,1" textline " " bitfld.long 0x00 11. " RPU_DP_SW2_EN_CORE ," "0,1" bitfld.long 0x00 10. " RPU_DM_SW1_EN_CORE ," "0,1" bitfld.long 0x00 9. " RPU_DM_SW2_EN_CORE ," "0,1" textline " " bitfld.long 0x00 8. " DP_PULLDOWN_EN_CORE ," "0,1" bitfld.long 0x00 7. " DM_PULLDOWN_EN_CORE ," "0,1" bitfld.long 0x00 6. " DP_DM_5V_SHORT ," "0,1" textline " " bitfld.long 0x00 1.--5. " SPARE_IN_CORE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " PORZ ,Read only bit - the PORZ generated from the digital registered on the A-D interface." "0,1" group.long 0x4C++0x3 line.long 0x00 "USBPHY_AD_INTERFACE_REG3,All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name. All the bits of this register, except the override bits return a '0' on read, if VDDLDO is off." bitfld.long 0x00 31. " USE_HSOS_DATA_REG ,Use bits 30:23 in this register as bypass bits" "0,1" hexmask.long.byte 0x00 23.--30. 1. " HSOS_DATA ," bitfld.long 0x00 22. " USE_FS_REG3 ,Use bits 21:20 as bypass bits" "0,1" textline " " bitfld.long 0x00 21. " FSTX_MODE ," "0,1" bitfld.long 0x00 20. " FSTX_SE0 ," "0,1" bitfld.long 0x00 19. " USE_HS_TERM_RES_REG ,Use bit 18 as override bit" "0,1" textline " " bitfld.long 0x00 18. " HS_TERM_RES ," "0,1" hexmask.long.byte 0x00 10.--17. 1. " SPARE_IN_LDO ," hexmask.long.byte 0x00 2.--9. 1. " SPARE_OUT_LDO ," textline " " bitfld.long 0x00 1. " USE_FARCORE_REG ,Use bit 0 from this register as bypass" "0,1" bitfld.long 0x00 0. " FARCORE ," "0,1" group.long 0x50++0x3 line.long 0x00 "USBPHY_ANA_CONFIG1,Used to configure and debug the analog blocks." hexmask.long.word 0x00 17.--31. 1. " SQ_CTRL_REG ," bitfld.long 0x00 14.--16. " FS_SLEW ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " HS_PRE_EMP_CNTRL ," "0,1,2,3" textline " " hexmask.long.byte 0x00 5.--11. 1. " HSFSTX_TEST ," bitfld.long 0x00 0.--4. " PROTECT_TEST ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x3 line.long 0x00 "USBPHY_ANA_CONFIG2,Used to configure and debug the analog blocks." bitfld.long 0x00 27.--31. " RTERM_CAL_TEST ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 20.--26. 1. " REF_GEN_TEST ,NOT IMPLEMENTED" bitfld.long 0x00 18.--19. " FSRX_TEST ," "0,1,2,3" textline " " bitfld.long 0x00 15.--17. " RTERM_TEST ,0x0 is default 0x3 decreases the termination impedance by 2 to 3% (can be used to get 1 to 1.5% better eye vertical opening)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11.--14. " DISCON_TEST ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--10. " HSRX_TEST ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 3.--5. " SERX_TEST ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--2. " SERX_HYST_CNTRL ," "0,1,2,3" bitfld.long 0x00 0. " SQ_LPMODEZ ," "0,1" tree.end tree.end tree.open "Full_Speed_USB_Host_Controller" tree "USBFSHOST" base ad:0x4A0A9000 width 20. group.long 0x0++0x3 line.long 0x00 "HCREVISION,OHCI revision number" group.long 0x4++0x3 line.long 0x00 "HCCONTROL,HC operating mode register" bitfld.long 0x00 10. " RWE ,Remote wake-up enable" "0,1" bitfld.long 0x00 9. " RWC ,Remote wake up connected." "0,1" bitfld.long 0x00 8. " IR ,Interrupt routing." "0,1" textline " " bitfld.long 0x00 6.--7. " HCFS ,Host controller functional state - . - . - . - ." "UsbReset,UsbResume,UsbOper,UsbSusp" bitfld.long 0x00 5. " BLE ,Bulk list processing enable - . - ." "BLE_0,BLE_1" bitfld.long 0x00 4. " CLE ,Control list processing enable - . - ." "CLE_ctrl,CLE_en" textline " " bitfld.long 0x00 3. " IE ,Isochronous ED processing enabled by host controller driver. - . - ." "IE_notprss,IE_prss" bitfld.long 0x00 2. " PLE ,Periodic list enable - . - ." "PLE_notprss,PLE_prss" bitfld.long 0x00 0.--1. " CBSR ,Control/bulk service ratio. Specifies the ratio between control and bulk EDs processedin a frame. - . - . - . - ." "OneCntED,TwoCntED,ThreeCntED,FourCntED" group.long 0x8++0x3 line.long 0x00 "HCCOMMANDSTATUS,HC Command and status" bitfld.long 0x00 16.--17. " SOC ,Scheduling overrun count" "0,1,2,3" bitfld.long 0x00 3. " OCR ,Ownership change request" "0,1" bitfld.long 0x00 2. " BLF ,Bulk list filled" "0,1" textline " " bitfld.long 0x00 1. " CLF ,Control list filled" "0,1" bitfld.long 0x00 0. " HCR ,Host controller reset (software reset)Set this bit to initiate a USB host controller reset. This resets most USB host controller OHCI registers. OHCI register accesses must not be attempted until a read of this register .." "HCR_0,HCR_1" group.long 0xC++0x3 line.long 0x00 "HCINTERRUPTSTATUS,HC Interrupt status" bitfld.long 0x00 30. " OC ,Ownership change" "0,1" bitfld.long 0x00 6. " RHSC ,Root hub status changeWhen 0x1: A root hub status change has occurred.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" bitfld.long 0x00 5. " FNO ,Frame number overflowWhen 0x1: A frame number overflow has occurred.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" textline " " bitfld.long 0x00 4. " UE ,Unrecoverable error.When 0x1: An unrecoverable error has occurred.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" bitfld.long 0x00 3. " RD ,Resume detected.When 0x1: A downstream device has issued a resume request.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" bitfld.long 0x00 2. " SF ,Start of frame.When 0x1: A SOF has been issued.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" textline " " bitfld.long 0x00 1. " WDH ,Write done headWhen 0x1: the USB host controller has updated the HCDONEHEAD register.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" bitfld.long 0x00 0. " SO ,Scheduling overrunWhen 0x1: A scheduling overrun has occurred.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" group.long 0x10++0x3 line.long 0x00 "HCINTERRUPTENABLE,HC Interrupt Enable" bitfld.long 0x00 31. " MIE ,Master interrupt enableWhen 0x1: Allows other enabled OHCI interrupt sources to propagate to the device interrupt controller.When 0x0: OHCI interrupt sources are ignored.Write 0x0: No effectWrite 0x1: Sets this bit" "0,1" bitfld.long 0x00 30. " OC ,Ownership change" "0,1" bitfld.long 0x00 6. " RHSC ,Root hub status changeWhen 0x1 and MIE is 0x1: Allows root hub status change interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: root hub status change interrupts do not propagate.Write 0x0: No e.." "0,1" textline " " bitfld.long 0x00 5. " FNO ,Frame number overflow.When 0x1 and MIE is 0x1: Allows FNO interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: FNO interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit" "0,1" bitfld.long 0x00 4. " UE ,Unrecoverable error.When 0x1 and MIE is 0x1: Allows UE interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: UE interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit" "0,1" bitfld.long 0x00 3. " RD ,Resume detected.When 0x1 and MIE is 0x1: Allows RD interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: RD interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit" "0,1" textline " " bitfld.long 0x00 2. " SF ,Start of frameWhen 0x1 and MIE is 0x1: Allows SF interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: SF interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit" "0,1" bitfld.long 0x00 1. " WDH ,Write done headWhen 0x1 and MIE is 0x1: Allows WDH interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: WDH interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit" "0,1" bitfld.long 0x00 0. " SO ,Scheduling overrun.When 0x1 and MIE is 0x1: Allows SO interrupts to propagate to the device interrupt controller.When 0x0 or MIE is 0x0: SO interrupts do not propagate.Write 0x0: No effectWrite 0x1: Sets this bit" "0,1" group.long 0x14++0x3 line.long 0x00 "HCINTERRUPTDISABLE,HC Interrupt disable" bitfld.long 0x00 31. " MIE ,Master interrupt enableAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE MIE bit" "0,1" bitfld.long 0x00 30. " OC ,Ownership change" "0,1" bitfld.long 0x00 6. " RHSC ,Root hub status changeAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE RHSC bit" "0,1" textline " " bitfld.long 0x00 5. " FNO ,Frame number overflowAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE FNO bit" "0,1" bitfld.long 0x00 4. " UE ,Unrecoverable errorAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE UE bit" "0,1" bitfld.long 0x00 3. " RD ,Resume detectedAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE RD bit" "0,1" textline " " bitfld.long 0x00 2. " SF ,Start of frameAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE SF bit" "0,1" bitfld.long 0x00 1. " WDH ,Write done headAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE WDH bit" "0,1" bitfld.long 0x00 0. " SO ,Scheduling overrunAlways reads 0x0Write 0x0: No effectWrite 0x1: Clears the HCINTERRUPTENABLE SO bit" "0,1" group.long 0x18++0x3 line.long 0x00 "HCHCCA,HC HCCA address register" hexmask.long.tbyte 0x00 8.--31. 1. " HCCA ,Physical address of the beginning of the HCCA" rgroup.long 0x1C++0x3 line.long 0x00 "HCPERIODCURRENTED,HC Current periodic register" hexmask.long 0x00 4.--31. 1. " PCED ,Physical address of current ED on the periodic ED list" group.long 0x20++0x3 line.long 0x00 "HCCONTROLHEADED,HC head control register" hexmask.long 0x00 4.--31. 1. " CHED ,Physical address of head ED on the control ED list" group.long 0x24++0x3 line.long 0x00 "HCCONTROLCURRENTED,HC current control register" hexmask.long 0x00 4.--31. 1. " CCED ,Physical address of current ED on the control ED list" group.long 0x28++0x3 line.long 0x00 "HCBULKHEADED,HC head bulk register" hexmask.long 0x00 4.--31. 1. " BHED ,Physical address of head ED on the bulk ED list" group.long 0x2C++0x3 line.long 0x00 "HCBULKCURRENTED,HC current bulk register" hexmask.long 0x00 4.--31. 1. " BCED ,Physical address of current ED on the bulk ED list" rgroup.long 0x30++0x3 line.long 0x00 "HCDONEHEAD,HC head done register" hexmask.long 0x00 4.--31. 1. " DH ,Physical address of last TD that was added to the done queue" group.long 0x34++0x3 line.long 0x00 "HCFMINTERVAL,HC Frame Interval register" bitfld.long 0x00 31. " FIT ,Frame interval toggle" "0,1" hexmask.long.word 0x00 16.--30. 1. " FSMPS ,Largest data packet size for full-speed packets, bit times." hexmask.long.word 0x00 0.--13. 1. " FI ,Frame intervalNumber of 12-MHz clocks in the USB frame. The nominal value is set to 11,999 to give a 1-ms frame." rgroup.long 0x38++0x3 line.long 0x00 "HCFMREMAINING,HC Frame-remaining register" bitfld.long 0x00 31. " FRT ,Frame remaining toggle" "0,1" hexmask.long.word 0x00 0.--13. 1. " FR ,Frame remaining" rgroup.long 0x3C++0x3 line.long 0x00 "HCFMNUMBER,HC Frame number register" hexmask.long.word 0x00 0.--15. 1. " FN ,Frame number" group.long 0x40++0x3 line.long 0x00 "HCPERIODICSTART,HC Periodic start register" hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic startThe host controller driver must program this value to be about 10% less than the frame interval field value so that control and bulk EDs have priority for the first 10% of the frame; then periodic EDs have priority.." group.long 0x44++0x3 line.long 0x00 "HCLSTHRESHOLD,HC low-speed threshold register" hexmask.long.word 0x00 0.--11. 1. " LST ,Low-speed threshold." group.long 0x48++0x3 line.long 0x00 "HCRHDESCRIPTORA,HC root hub A register" hexmask.long.byte 0x00 24.--31. 1. " POTPG ,Power-on to power-good timeDefines the minimum length of time (2 ms * POTPG) between the USB host controller turning on power to a downstream port, and when the USB host can access the downstream device." bitfld.long 0x00 12. " NOCP ,No overcurrent protection - . - ." "NOCP_0,NOCP_1" bitfld.long 0x00 11. " OCPM ,Overcurrent protection mode" "0,1" textline " " bitfld.long 0x00 10. " DT ,Device typeAlways reads 0x0: Indicates that the USB host controller implemented is not a compound device" "0,1" bitfld.long 0x00 9. " NPS ,No power switching - . - ." "VbPowSwSup,VbPowSwNSup" bitfld.long 0x00 8. " PSM ,Power switching mode - . - ." "APoPwSTime,InPorPowSw" textline " " hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number of downstream ports." group.long 0x4C++0x3 line.long 0x00 "HCRHDESCRIPTORB,HC root hub B register" bitfld.long 0x00 17. " PPCM ,Port power control maskThis bit defines whether downstream port #1 has port power controlled by the global power control. When set. the port power state is only affected by per-port power control. When cleared the port is contro.." "0,1" bitfld.long 0x00 1. " DR ,Device removableThis bit defines whether the downstream port has a removable device. When cleared, the attached device is removable. When set, the attached device is not removable. bit 1: Device attached to port #1" "0,1" group.long 0x50++0x3 line.long 0x00 "HCRHSTATUS,HC root hub status register" bitfld.long 0x00 31. " CRWE ,Clear remote wake-up enableWrite 0x0: No effectWrite 0x1: Clears the device remote wake-up enable bit" "0,1" bitfld.long 0x00 17. " OCIC ,Overcurrent indication changeThis bit is automatically set when the overcurrent indicator bit changes.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" bitfld.long 0x00 16. " LPSC ,Local power status changeAlways reads 0x0: The root hub does not support the local power status feature.Write 0x0: No effectWrite 0x1: Sets port power status bits for all ports, if power switching mode is 0. Sets port power st.." "0,1" textline " " bitfld.long 0x00 15. " DRWE ,Device remote wake-up enableEnables a connect status change event as a resume event, causing a USB suspend to USB resume state transition and sets the resume detected interrupt status bit.Read 0x1: Connect status change is a rem.." "0,1" bitfld.long 0x00 1. " OCI ,Overcurrent indicator. Reports global overcurrent indication if global overcurrent reporting is selected. If per-port overcurrent protection is implemented, this bit is always 0. - . - ." "OCI_0,OCI_1" bitfld.long 0x00 0. " LPS ,Local power status.Always reads 0x0Write 0x0: No effectWrite 0x1: When in global power mode (power switching mode = 0), turns off power to all ports. If in per-port power mode (power switching mode = 1), turns of power to those po.." "0,1" group.long 0x54++0x3 line.long 0x00 "HCRHPORTSTATUS,HC Port 1 status and control register" bitfld.long 0x00 20. " PRSC ,Port 1 reset status changeThis bit is set when the Port 1 port reset status bit has changed.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" bitfld.long 0x00 19. " OCIC ,Port 1 overcurrent indicator changeThis bit is set when the Port 1 port overcurrent indicator has changed.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" bitfld.long 0x00 18. " PSSC ,Port 1 suspend status changeThis bit is set when the Port1 port suspend status has changed.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" textline " " bitfld.long 0x00 17. " PESC ,Port 1 enable status changeThis bit is set when the Port1 port enable status has changed.Write 0x0: No effectWrite 0x1: Clears this bit" "0,1" bitfld.long 0x00 16. " CSC ,Port 1 connect status changeThis bit is set when the Port1 port current connect status has changed due to a connect or disconnect event. If current connect status is 0 when a set port reset, set port enable, or set port .." "0,1" bitfld.long 0x00 9. " LSDA_CPP ,Port 1 low-speed device attached/clear port power. This bit is valid only when port 1 current connect status is 1.Read 0x0: A full-speed device is attached to port 1.Read 0x1: A low-speed device is attached to port 1.Write 0x0.." "0,1" textline " " bitfld.long 0x00 8. " PPS_SPP ,Port 1 port power status/set port power.Read 0x0: Port 1 power is off.Read 0x1: Port 1 power is on.Write 0x0: No effectWrite 0x1: Sets the port 1 port power status bit" "0,1" bitfld.long 0x00 4. " PRS_SPR ,Port 1 port reset status/set port reset.Read 0x0: USB reset is not being sent to port 1.Read 0x1: Port 1 is signaling the USB reset.Write 0x0: No effectWrite 0x1: Sets the port 1 port reset status bit and causes the USB .." "0,1" bitfld.long 0x00 3. " POCI_CSS ,Port 1 port overcurrent indicator/clear suspend statusRead 0x0: No port 1 port overcurrent condition has occurred.Read 0x1: A port 1 port overcurrent condition has occurred.Write 0x0: No effectWrite 0x1: When port 1 port suspe.." "0,1" textline " " bitfld.long 0x00 2. " PSS_SPS ,Port 1 port suspend status/set port suspendThis bit is cleared automatically at the end of the USB resume sequence and also at the end of the USB reset sequence.Write 0x0: No effectRead 0x0: Port 1 is not in the USB suspend stat.." "0,1" bitfld.long 0x00 1. " PES_SPE ,Port 1 port enable status/set port enableThis bit is automatically set at completion of port 1 USB reset, if it was not already set before the USB reset completed, and is automatically set at the end of a USB suspend, if.." "0,1" bitfld.long 0x00 0. " CCS_CPE ,Port 1 current connection status/clear port enableRead 0x0: No USB device is attached to port 1.Read 0x1: Port 1 currently has a USB device attached.Write 0x0: No effectWrite 0x1: Clears the port 1 port enable bitNote: This bi.." "0,1" rgroup.long 0x200++0x3 line.long 0x00 "HCOCPREV," hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x204++0x3 line.long 0x00 "HCOCPHWI,Hardware information register, maintains the IP modules hardware configuration. The fields can be set to different values through parameters." hexmask.long 0x00 0.--31. 1. " INFO ,IP-module dependent. Information about the IP module hardware configuration, that is, typically the module HDL generics (if any)." group.long 0x210++0x3 line.long 0x00 "HCOCPSYS,OCP system configuration register holds the OCP power down control fields that controls the clock management." bitfld.long 0x00 9. " APPLICATIONSTARTCLOCK ,1: RCFG_SUSPEND_O output port is masked and this output port is held low (1'b0)0: RCFG_SUSPEND_O port functions normally, that is, it indicates the SUSPEND mode." "0,1" bitfld.long 0x00 8. " SIMULATIONSCALEDOWN ,1: Simulation runs in time scaled down mode.0: Simulation runs in real time. NOTE: This bit should not be set to 1 in actual hardware." "0,1" bitfld.long 0x00 4.--5. " STANDBY_MODE ,Standby mode, controls the way USBFSHOST handles the STANDBY protocol.The application can program this field in the following configurations 2'b00 : Force standby 2'b01: Not supported (No-Standby) 2'b10: Smart standby 2'b11: S.." "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " IDLE_MODE ,The idle mode controls the way USBFSHOST handles the IDLE protocol.The application can program this field in the following configurations 2'b00: Force Idle 2'b01: Not supported (No-Idle) 2'b10: Smart-Idle 2'b11: Smart-Idle wake .." "0,1,2,3" bitfld.long 0x00 1. " SOFT_RESET ,Setting this bit to 1 resets the entire IP, except for OCP-IDLE, OCP-STANDBY, and OCP-DISCONNECT logic.This bit remains set until the IP comes out of soft reset." "0,1" tree.end tree.end tree.open "Multimaster_High_Speed_I2C_Controller" tree.open "I2C3" tree "I2C3" base ad:0x48060000 width 21. rgroup.long 0x0++0x3 line.long 0x00 "I2C_REVNB_LO,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "I2C_REVNB_HI,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.word 0x10++0x1 line.word 0x00 "I2C_SYSC,System Configuration register" bitfld.word 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits - . - . - . - ." "Both_off,Ocp_on,Sys_on,Both_on" bitfld.word 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits - . - . - . - ." "Force_idle,No_idle,Smart_idle,Smartidle_wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SRST ,SoftReset bit - . - ." "Normal,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Autoidle bit - . - ." "Disabled,Enabled" group.word 0x24++0x1 line.word 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.word 0x00 14. " XDR ,Transmit draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " bitfld.word 0x00 11. " ROVR ,Receive overrun status.Writing into this bit has no effect. - . - ." "Normal,Received" bitfld.word 0x00 10. " XUDF ,Transmit underflow status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" bitfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status. - . - ." "No_action,Recognized" textline " " bitfld.word 0x00 8. " BF ,Bus Free IRQ status. - . - ." "No_action,Free" bitfld.word 0x00 7. " AERR ,Access Error IRQ status. - . - ." "No_action,Error" bitfld.word 0x00 6. " STC ,Start Condition IRQ status. - . - ." "No_action,Detected" textline " " bitfld.word 0x00 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. - . - ." "Not_detected,Detected" bitfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" bitfld.word 0x00 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" bitfld.word 0x00 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. - . - ." "Normal,Detected" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x28++0x1 line.word 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" eventfld.word 0x00 14. " XDR ,Transmit draining IRQ enabled status. - . - ." "Disabled,Enabled" eventfld.word 0x00 13. " RDR ,Receive draining IRQ enabled status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy enabled status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " eventfld.word 0x00 11. " ROVR ,Receive overrun enabled status.Writing into this bit has no effect. - . - ." "Normal,Received" eventfld.word 0x00 10. " XUDF ,Transmit underflow enabled status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ enabled status. - . - ." "No_action,Recognized" textline " " eventfld.word 0x00 8. " BF ,Bus Free IRQ enabled status. - . - ." "No_action,Free" eventfld.word 0x00 7. " AERR ,Access Error IRQ enabled status. - . - ." "No_action,Error" eventfld.word 0x00 6. " STC ,Start Condition IRQ enabled status. - . - ." "No_action,Detected" textline " " eventfld.word 0x00 5. " GC ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. Write 1 to clear. - . - ." "Not_detected,Detected" eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" textline " " eventfld.word 0x00 2. " ARDY ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 1. " NACK ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write 1 to clear this bit. - . - ." "Normal,Detected" eventfld.word 0x00 0. " AL ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x2C++0x1 line.word 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "0,1" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "0,1" bitfld.word 0x00 11. " ROVR ,Receive overrun enable set. - . - ." "0,1" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable set. - . - ." "0,1" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "0,1" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "0,1" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "0,1" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "0,1" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "0,1" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "0,1" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "0,1" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "0,1" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "0,1" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "0,1" group.word 0x30++0x1 line.word 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "0,1" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "0,1" bitfld.word 0x00 11. " ROVR ,Receive overrun enable clear. - . - ." "0,1" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable clear. - . - ." "0,1" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "0,1" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "0,1" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "0,1" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "0,1" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "0,1" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "0,1" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "0,1" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "0,1" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "0,1" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "0,1" group.word 0x34++0x1 line.word 0x00 "I2C_WE,I2C wakeup enable vector." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x38++0x1 line.word 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.word 0x00 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set." "Disabled,Enabled" group.word 0x3C++0x1 line.word 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.word 0x00 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set." "Disabled,Enabled" group.word 0x40++0x1 line.word 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.word 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared" group.word 0x44++0x1 line.word 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.word 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared" group.word 0x48++0x1 line.word 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x4C++0x1 line.word 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x84++0x1 line.word 0x00 "I2C_IE,I2C interrupt enable vector (legacy)." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun enable set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "Disabled,Enabled" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "Disabled,Enabled" group.word 0x88++0x1 line.word 0x00 "I2C_STAT,I2C interrupt status vector (legacy)." eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status. - . - ." "Disabled,Enabled" eventfld.word 0x00 13. " RDR ,Receive draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " eventfld.word 0x00 11. " ROVR ,Receive overrun status.Writing into this bit has no effect. - . - ." "Normal,Received" eventfld.word 0x00 10. " XUDF ,Transmit underflow status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status. - . - ." "No_action,Recognized" textline " " eventfld.word 0x00 8. " BF ,Bus Free IRQ status. - . - ." "No_action,Free" eventfld.word 0x00 7. " AERR ,Access Error IRQ status. - . - ." "No_action,Error" eventfld.word 0x00 6. " STC ,Start Condition IRQ status. - . - ." "No_action,Detected" textline " " eventfld.word 0x00 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. Write 1 to clear. - . - ." "Not_detected,Detected" eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" textline " " eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write 1 to clear this bit. - . - ." "Normal,Detected" eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x90++0x1 line.word 0x00 "I2C_SYSS,System Status register" bitfld.word 0x00 0. " RDONE ,Reset done bit - . - ." "Ongoing,Reset" group.word 0x94++0x1 line.word 0x00 "I2C_BUF,Buffer Configuration register" bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable - . - ." "Disabled,Enabled" bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear - . - ." "Normal,Reset" bitfld.word 0x00 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable - . - ." "Disabled,Enabled" bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear - . - ." "Normal,Reset" bitfld.word 0x00 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x98++0x1 line.word 0x00 "I2C_CNT,Data counter register" hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count Because the transfer length for DCOUNT = 0x0000 is 65536, the module does not allow the initiation of zero-data-byte transfers." hgroup.word 0x9C++0x1 hide.word 0x00 "I2C_DATA,Data access register" in group.word 0xA4++0x1 line.word 0x00 "I2C_CON,I2C configuration register." bitfld.word 0x00 15. " I2C_EN ,I2C module enable. - . - ." "Disabled,Enabled" bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection. - . - . - . - ." "Fast/Standard,High_Speed,SCCB,?..." bitfld.word 0x00 11. " STB ,Start byte mode (master mode only). - . - ." "Normal_mode,Start_byte_mode" textline " " bitfld.word 0x00 10. " MST ,Master/slave mode. - . - ." "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmitter/Receiver mode (master mode only). - . - ." "Receiver_mode,Transmitter_mode" bitfld.word 0x00 8. " XSA ,Expand Slave address. - . - ." "7-bit,10-bit" textline " " bitfld.word 0x00 7. " XOA0 ,Expand Own address 0. - . - ." "7-bit,10-bit" bitfld.word 0x00 6. " XOA1 ,Expand Own address 1. - . - ." "7-bit,10-bit" bitfld.word 0x00 5. " XOA2 ,Expand Own address 2. - . - ." "7-bit,10-bit" textline " " bitfld.word 0x00 4. " XOA3 ,Expand Own address 3. - . - ." "7-bit,10-bit" bitfld.word 0x00 1. " STP ,Stop condition (master mode only). - . - ." "0,Stop_condition_queried" bitfld.word 0x00 0. " STT ,Start condition (master mode only). - . - ." "0,Start_condition_queried" group.word 0xA8++0x1 line.word 0x00 "I2C_OA,Own address register" bitfld.word 0x00 13.--15. " MCODE ,Master Code" "0,1,2,3,4,5,6,7" hexmask.word 0x00 0.--9. 1. " OA ,Own address" group.word 0xAC++0x1 line.word 0x00 "I2C_SA,Slave address register" hexmask.word 0x00 0.--9. 1. " SA ,Slave address" group.word 0xB0++0x1 line.word 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 .............................. 0xFF: Divide by 256" group.word 0xB4++0x1 line.word 0x00 "I2C_SCLL,I2C SCL Low Time Register." hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,High Speed mode SCL low time" hexmask.word.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time." group.word 0xB8++0x1 line.word 0x00 "I2C_SCLH,I2C SCL High Time Register." hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,High Speed mode SCL high time" hexmask.word.byte 0x00 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time." group.word 0xBC++0x1 line.word 0x00 "I2C_SYSTEST,I2C System Test Register." bitfld.word 0x00 15. " ST_EN ,System test enable. - . - ." "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running mode (on breakpoint) - . - ." "Stop,Free" bitfld.word 0x00 12.--13. " TMODE ,Test mode select. - . - . - . - ." "Functional,Reserved,Test,Loopback" textline " " bitfld.word 0x00 11. " SSB ,Set status bits from 0 to 14. - . - ." "No_action,Set" bitfld.word 0x00 8. " SCL_I_FUNC ,SCL line input value (functional mode). - . - ." "Low,High" bitfld.word 0x00 7. " SCL_O_FUNC ,SCL line output value (functional mode). - . - ." "Low,High" textline " " bitfld.word 0x00 6. " SDA_I_FUNC ,SDA line input value (functional mode). - . - ." "Low,High" bitfld.word 0x00 5. " SDA_O_FUNC ,SDA line output value (functional mode). - . - ." "Low,High" bitfld.word 0x00 4. " SCCB_E_O ,SCCB_E line sense output value. - . - ." "Low,High" textline " " bitfld.word 0x00 3. " SCL_I ,SCL line sense input value - . - ." "Low,High" bitfld.word 0x00 2. " SCL_O ,SCL line drive output value. - . - ." "Low,High" bitfld.word 0x00 1. " SDA_I ,SDA line sense input value. - . - ." "Low,High" textline " " bitfld.word 0x00 0. " SDA_O ,SDA line drive output value. - . - ." "Low,High" rgroup.word 0xC0++0x1 line.word 0x00 "I2C_BUFSTAT,I2C Buffer Status Register." bitfld.word 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth." "0,1,2,3" bitfld.word 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 0.--5. " TXSTAT ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0xC4++0x1 line.word 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1" group.word 0xC8++0x1 line.word 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2" group.word 0xCC++0x1 line.word 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3" rgroup.word 0xD0++0x1 line.word 0x00 "I2C_ACTOA,I2C Active Own Address Register." bitfld.word 0x00 3. " OA3_ACT ,Own Address 3 active. - . - ." "Not_active,Active" bitfld.word 0x00 2. " OA2_ACT ,Own Address 2 active. - . - ." "Not_active,Active" bitfld.word 0x00 1. " OA1_ACT ,Own Address 1 active. - . - ." "Not_active,Active" textline " " bitfld.word 0x00 0. " OA0_ACT ,Own Address 0 active. - . - ." "Not_active,Active" group.word 0xD4++0x1 line.word 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.word 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3. - . - ." "Not_locked,Locked" bitfld.word 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2. - . - ." "Not_locked,Locked" bitfld.word 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1. - . - ." "Not_locked,Locked" textline " " bitfld.word 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0. - . - ." "Not_locked,Locked" tree.end tree "I2C1" base ad:0x48070000 width 21. rgroup.long 0x0++0x3 line.long 0x00 "I2C_REVNB_LO,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "I2C_REVNB_HI,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.word 0x10++0x1 line.word 0x00 "I2C_SYSC,System Configuration register" bitfld.word 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits - . - . - . - ." "Both_off,Ocp_on,Sys_on,Both_on" bitfld.word 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits - . - . - . - ." "Force_idle,No_idle,Smart_idle,Smartidle_wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SRST ,SoftReset bit - . - ." "Normal,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Autoidle bit - . - ." "Disabled,Enabled" group.word 0x24++0x1 line.word 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.word 0x00 14. " XDR ,Transmit draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " bitfld.word 0x00 11. " ROVR ,Receive overrun status.Writing into this bit has no effect. - . - ." "Normal,Received" bitfld.word 0x00 10. " XUDF ,Transmit underflow status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" bitfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status. - . - ." "No_action,Recognized" textline " " bitfld.word 0x00 8. " BF ,Bus Free IRQ status. - . - ." "No_action,Free" bitfld.word 0x00 7. " AERR ,Access Error IRQ status. - . - ." "No_action,Error" bitfld.word 0x00 6. " STC ,Start Condition IRQ status. - . - ." "No_action,Detected" textline " " bitfld.word 0x00 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. - . - ." "Not_detected,Detected" bitfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" bitfld.word 0x00 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" bitfld.word 0x00 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. - . - ." "Normal,Detected" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x28++0x1 line.word 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" eventfld.word 0x00 14. " XDR ,Transmit draining IRQ enabled status. - . - ." "Disabled,Enabled" eventfld.word 0x00 13. " RDR ,Receive draining IRQ enabled status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy enabled status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " eventfld.word 0x00 11. " ROVR ,Receive overrun enabled status.Writing into this bit has no effect. - . - ." "Normal,Received" eventfld.word 0x00 10. " XUDF ,Transmit underflow enabled status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ enabled status. - . - ." "No_action,Recognized" textline " " eventfld.word 0x00 8. " BF ,Bus Free IRQ enabled status. - . - ." "No_action,Free" eventfld.word 0x00 7. " AERR ,Access Error IRQ enabled status. - . - ." "No_action,Error" eventfld.word 0x00 6. " STC ,Start Condition IRQ enabled status. - . - ." "No_action,Detected" textline " " eventfld.word 0x00 5. " GC ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. Write 1 to clear. - . - ." "Not_detected,Detected" eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" textline " " eventfld.word 0x00 2. " ARDY ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 1. " NACK ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write 1 to clear this bit. - . - ." "Normal,Detected" eventfld.word 0x00 0. " AL ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x2C++0x1 line.word 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "0,1" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "0,1" bitfld.word 0x00 11. " ROVR ,Receive overrun enable set. - . - ." "0,1" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable set. - . - ." "0,1" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "0,1" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "0,1" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "0,1" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "0,1" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "0,1" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "0,1" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "0,1" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "0,1" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "0,1" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "0,1" group.word 0x30++0x1 line.word 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "0,1" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "0,1" bitfld.word 0x00 11. " ROVR ,Receive overrun enable clear. - . - ." "0,1" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable clear. - . - ." "0,1" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "0,1" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "0,1" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "0,1" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "0,1" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "0,1" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "0,1" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "0,1" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "0,1" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "0,1" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "0,1" group.word 0x34++0x1 line.word 0x00 "I2C_WE,I2C wakeup enable vector." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x38++0x1 line.word 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.word 0x00 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set." "Disabled,Enabled" group.word 0x3C++0x1 line.word 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.word 0x00 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set." "Disabled,Enabled" group.word 0x40++0x1 line.word 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.word 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared" group.word 0x44++0x1 line.word 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.word 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared" group.word 0x48++0x1 line.word 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x4C++0x1 line.word 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x84++0x1 line.word 0x00 "I2C_IE,I2C interrupt enable vector (legacy)." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun enable set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "Disabled,Enabled" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "Disabled,Enabled" group.word 0x88++0x1 line.word 0x00 "I2C_STAT,I2C interrupt status vector (legacy)." eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status. - . - ." "Disabled,Enabled" eventfld.word 0x00 13. " RDR ,Receive draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " eventfld.word 0x00 11. " ROVR ,Receive overrun status.Writing into this bit has no effect. - . - ." "Normal,Received" eventfld.word 0x00 10. " XUDF ,Transmit underflow status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status. - . - ." "No_action,Recognized" textline " " eventfld.word 0x00 8. " BF ,Bus Free IRQ status. - . - ." "No_action,Free" eventfld.word 0x00 7. " AERR ,Access Error IRQ status. - . - ." "No_action,Error" eventfld.word 0x00 6. " STC ,Start Condition IRQ status. - . - ." "No_action,Detected" textline " " eventfld.word 0x00 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. Write 1 to clear. - . - ." "Not_detected,Detected" eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" textline " " eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write 1 to clear this bit. - . - ." "Normal,Detected" eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x90++0x1 line.word 0x00 "I2C_SYSS,System Status register" bitfld.word 0x00 0. " RDONE ,Reset done bit - . - ." "Ongoing,Reset" group.word 0x94++0x1 line.word 0x00 "I2C_BUF,Buffer Configuration register" bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable - . - ." "Disabled,Enabled" bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear - . - ." "Normal,Reset" bitfld.word 0x00 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable - . - ." "Disabled,Enabled" bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear - . - ." "Normal,Reset" bitfld.word 0x00 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x98++0x1 line.word 0x00 "I2C_CNT,Data counter register" hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count Because the transfer length for DCOUNT = 0x0000 is 65536, the module does not allow the initiation of zero-data-byte transfers." hgroup.word 0x9C++0x1 hide.word 0x00 "I2C_DATA,Data access register" in group.word 0xA4++0x1 line.word 0x00 "I2C_CON,I2C configuration register." bitfld.word 0x00 15. " I2C_EN ,I2C module enable. - . - ." "Disabled,Enabled" bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection. - . - . - . - ." "Fast/Standard,High_Speed,SCCB,?..." bitfld.word 0x00 11. " STB ,Start byte mode (master mode only). - . - ." "Normal_mode,Start_byte_mode" textline " " bitfld.word 0x00 10. " MST ,Master/slave mode. - . - ." "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmitter/Receiver mode (master mode only). - . - ." "Receiver_mode,Transmitter_mode" bitfld.word 0x00 8. " XSA ,Expand Slave address. - . - ." "7-bit,10-bit" textline " " bitfld.word 0x00 7. " XOA0 ,Expand Own address 0. - . - ." "7-bit,10-bit" bitfld.word 0x00 6. " XOA1 ,Expand Own address 1. - . - ." "7-bit,10-bit" bitfld.word 0x00 5. " XOA2 ,Expand Own address 2. - . - ." "7-bit,10-bit" textline " " bitfld.word 0x00 4. " XOA3 ,Expand Own address 3. - . - ." "7-bit,10-bit" bitfld.word 0x00 1. " STP ,Stop condition (master mode only). - . - ." "0,Stop_condition_queried" bitfld.word 0x00 0. " STT ,Start condition (master mode only). - . - ." "0,Start_condition_queried" group.word 0xA8++0x1 line.word 0x00 "I2C_OA,Own address register" bitfld.word 0x00 13.--15. " MCODE ,Master Code" "0,1,2,3,4,5,6,7" hexmask.word 0x00 0.--9. 1. " OA ,Own address" group.word 0xAC++0x1 line.word 0x00 "I2C_SA,Slave address register" hexmask.word 0x00 0.--9. 1. " SA ,Slave address" group.word 0xB0++0x1 line.word 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 .............................. 0xFF: Divide by 256" group.word 0xB4++0x1 line.word 0x00 "I2C_SCLL,I2C SCL Low Time Register." hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,High Speed mode SCL low time" hexmask.word.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time." group.word 0xB8++0x1 line.word 0x00 "I2C_SCLH,I2C SCL High Time Register." hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,High Speed mode SCL high time" hexmask.word.byte 0x00 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time." group.word 0xBC++0x1 line.word 0x00 "I2C_SYSTEST,I2C System Test Register." bitfld.word 0x00 15. " ST_EN ,System test enable. - . - ." "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running mode (on breakpoint) - . - ." "Stop,Free" bitfld.word 0x00 12.--13. " TMODE ,Test mode select. - . - . - . - ." "Functional,Reserved,Test,Loopback" textline " " bitfld.word 0x00 11. " SSB ,Set status bits from 0 to 14. - . - ." "No_action,Set" bitfld.word 0x00 8. " SCL_I_FUNC ,SCL line input value (functional mode). - . - ." "Low,High" bitfld.word 0x00 7. " SCL_O_FUNC ,SCL line output value (functional mode). - . - ." "Low,High" textline " " bitfld.word 0x00 6. " SDA_I_FUNC ,SDA line input value (functional mode). - . - ." "Low,High" bitfld.word 0x00 5. " SDA_O_FUNC ,SDA line output value (functional mode). - . - ." "Low,High" bitfld.word 0x00 4. " SCCB_E_O ,SCCB_E line sense output value. - . - ." "Low,High" textline " " bitfld.word 0x00 3. " SCL_I ,SCL line sense input value - . - ." "Low,High" bitfld.word 0x00 2. " SCL_O ,SCL line drive output value. - . - ." "Low,High" bitfld.word 0x00 1. " SDA_I ,SDA line sense input value. - . - ." "Low,High" textline " " bitfld.word 0x00 0. " SDA_O ,SDA line drive output value. - . - ." "Low,High" rgroup.word 0xC0++0x1 line.word 0x00 "I2C_BUFSTAT,I2C Buffer Status Register." bitfld.word 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth." "0,1,2,3" bitfld.word 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 0.--5. " TXSTAT ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0xC4++0x1 line.word 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1" group.word 0xC8++0x1 line.word 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2" group.word 0xCC++0x1 line.word 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3" rgroup.word 0xD0++0x1 line.word 0x00 "I2C_ACTOA,I2C Active Own Address Register." bitfld.word 0x00 3. " OA3_ACT ,Own Address 3 active. - . - ." "Not_active,Active" bitfld.word 0x00 2. " OA2_ACT ,Own Address 2 active. - . - ." "Not_active,Active" bitfld.word 0x00 1. " OA1_ACT ,Own Address 1 active. - . - ." "Not_active,Active" textline " " bitfld.word 0x00 0. " OA0_ACT ,Own Address 0 active. - . - ." "Not_active,Active" group.word 0xD4++0x1 line.word 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.word 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3. - . - ." "Not_locked,Locked" bitfld.word 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2. - . - ." "Not_locked,Locked" bitfld.word 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1. - . - ." "Not_locked,Locked" textline " " bitfld.word 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0. - . - ." "Not_locked,Locked" tree.end tree "I2C2" base ad:0x48072000 width 21. rgroup.long 0x0++0x3 line.long 0x00 "I2C_REVNB_LO,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "I2C_REVNB_HI,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.word 0x10++0x1 line.word 0x00 "I2C_SYSC,System Configuration register" bitfld.word 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits - . - . - . - ." "Both_off,Ocp_on,Sys_on,Both_on" bitfld.word 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits - . - . - . - ." "Force_idle,No_idle,Smart_idle,Smartidle_wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SRST ,SoftReset bit - . - ." "Normal,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Autoidle bit - . - ." "Disabled,Enabled" group.word 0x24++0x1 line.word 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.word 0x00 14. " XDR ,Transmit draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " bitfld.word 0x00 11. " ROVR ,Receive overrun status.Writing into this bit has no effect. - . - ." "Normal,Received" bitfld.word 0x00 10. " XUDF ,Transmit underflow status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" bitfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status. - . - ." "No_action,Recognized" textline " " bitfld.word 0x00 8. " BF ,Bus Free IRQ status. - . - ." "No_action,Free" bitfld.word 0x00 7. " AERR ,Access Error IRQ status. - . - ." "No_action,Error" bitfld.word 0x00 6. " STC ,Start Condition IRQ status. - . - ." "No_action,Detected" textline " " bitfld.word 0x00 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. - . - ." "Not_detected,Detected" bitfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" bitfld.word 0x00 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" bitfld.word 0x00 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. - . - ." "Normal,Detected" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x28++0x1 line.word 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" eventfld.word 0x00 14. " XDR ,Transmit draining IRQ enabled status. - . - ." "Disabled,Enabled" eventfld.word 0x00 13. " RDR ,Receive draining IRQ enabled status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy enabled status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " eventfld.word 0x00 11. " ROVR ,Receive overrun enabled status.Writing into this bit has no effect. - . - ." "Normal,Received" eventfld.word 0x00 10. " XUDF ,Transmit underflow enabled status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ enabled status. - . - ." "No_action,Recognized" textline " " eventfld.word 0x00 8. " BF ,Bus Free IRQ enabled status. - . - ." "No_action,Free" eventfld.word 0x00 7. " AERR ,Access Error IRQ enabled status. - . - ." "No_action,Error" eventfld.word 0x00 6. " STC ,Start Condition IRQ enabled status. - . - ." "No_action,Detected" textline " " eventfld.word 0x00 5. " GC ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. Write 1 to clear. - . - ." "Not_detected,Detected" eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" textline " " eventfld.word 0x00 2. " ARDY ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 1. " NACK ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write 1 to clear this bit. - . - ." "Normal,Detected" eventfld.word 0x00 0. " AL ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x2C++0x1 line.word 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "0,1" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "0,1" bitfld.word 0x00 11. " ROVR ,Receive overrun enable set. - . - ." "0,1" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable set. - . - ." "0,1" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "0,1" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "0,1" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "0,1" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "0,1" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "0,1" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "0,1" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "0,1" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "0,1" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "0,1" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "0,1" group.word 0x30++0x1 line.word 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "0,1" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "0,1" bitfld.word 0x00 11. " ROVR ,Receive overrun enable clear. - . - ." "0,1" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable clear. - . - ." "0,1" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "0,1" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "0,1" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "0,1" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "0,1" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "0,1" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "0,1" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "0,1" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "0,1" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "0,1" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "0,1" group.word 0x34++0x1 line.word 0x00 "I2C_WE,I2C wakeup enable vector." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x38++0x1 line.word 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.word 0x00 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set." "Disabled,Enabled" group.word 0x3C++0x1 line.word 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.word 0x00 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set." "Disabled,Enabled" group.word 0x40++0x1 line.word 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.word 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared" group.word 0x44++0x1 line.word 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.word 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared" group.word 0x48++0x1 line.word 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x4C++0x1 line.word 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x84++0x1 line.word 0x00 "I2C_IE,I2C interrupt enable vector (legacy)." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun enable set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "Disabled,Enabled" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "Disabled,Enabled" group.word 0x88++0x1 line.word 0x00 "I2C_STAT,I2C interrupt status vector (legacy)." eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status. - . - ." "Disabled,Enabled" eventfld.word 0x00 13. " RDR ,Receive draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " eventfld.word 0x00 11. " ROVR ,Receive overrun status.Writing into this bit has no effect. - . - ." "Normal,Received" eventfld.word 0x00 10. " XUDF ,Transmit underflow status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status. - . - ." "No_action,Recognized" textline " " eventfld.word 0x00 8. " BF ,Bus Free IRQ status. - . - ." "No_action,Free" eventfld.word 0x00 7. " AERR ,Access Error IRQ status. - . - ." "No_action,Error" eventfld.word 0x00 6. " STC ,Start Condition IRQ status. - . - ." "No_action,Detected" textline " " eventfld.word 0x00 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. Write 1 to clear. - . - ." "Not_detected,Detected" eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" textline " " eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write 1 to clear this bit. - . - ." "Normal,Detected" eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x90++0x1 line.word 0x00 "I2C_SYSS,System Status register" bitfld.word 0x00 0. " RDONE ,Reset done bit - . - ." "Ongoing,Reset" group.word 0x94++0x1 line.word 0x00 "I2C_BUF,Buffer Configuration register" bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable - . - ." "Disabled,Enabled" bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear - . - ." "Normal,Reset" bitfld.word 0x00 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable - . - ." "Disabled,Enabled" bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear - . - ." "Normal,Reset" bitfld.word 0x00 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x98++0x1 line.word 0x00 "I2C_CNT,Data counter register" hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count Because the transfer length for DCOUNT = 0x0000 is 65536, the module does not allow the initiation of zero-data-byte transfers." hgroup.word 0x9C++0x1 hide.word 0x00 "I2C_DATA,Data access register" in group.word 0xA4++0x1 line.word 0x00 "I2C_CON,I2C configuration register." bitfld.word 0x00 15. " I2C_EN ,I2C module enable. - . - ." "Disabled,Enabled" bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection. - . - . - . - ." "Fast/Standard,High_Speed,SCCB,?..." bitfld.word 0x00 11. " STB ,Start byte mode (master mode only). - . - ." "Normal_mode,Start_byte_mode" textline " " bitfld.word 0x00 10. " MST ,Master/slave mode. - . - ." "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmitter/Receiver mode (master mode only). - . - ." "Receiver_mode,Transmitter_mode" bitfld.word 0x00 8. " XSA ,Expand Slave address. - . - ." "7-bit,10-bit" textline " " bitfld.word 0x00 7. " XOA0 ,Expand Own address 0. - . - ." "7-bit,10-bit" bitfld.word 0x00 6. " XOA1 ,Expand Own address 1. - . - ." "7-bit,10-bit" bitfld.word 0x00 5. " XOA2 ,Expand Own address 2. - . - ." "7-bit,10-bit" textline " " bitfld.word 0x00 4. " XOA3 ,Expand Own address 3. - . - ." "7-bit,10-bit" bitfld.word 0x00 1. " STP ,Stop condition (master mode only). - . - ." "0,Stop_condition_queried" bitfld.word 0x00 0. " STT ,Start condition (master mode only). - . - ." "0,Start_condition_queried" group.word 0xA8++0x1 line.word 0x00 "I2C_OA,Own address register" bitfld.word 0x00 13.--15. " MCODE ,Master Code" "0,1,2,3,4,5,6,7" hexmask.word 0x00 0.--9. 1. " OA ,Own address" group.word 0xAC++0x1 line.word 0x00 "I2C_SA,Slave address register" hexmask.word 0x00 0.--9. 1. " SA ,Slave address" group.word 0xB0++0x1 line.word 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 .............................. 0xFF: Divide by 256" group.word 0xB4++0x1 line.word 0x00 "I2C_SCLL,I2C SCL Low Time Register." hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,High Speed mode SCL low time" hexmask.word.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time." group.word 0xB8++0x1 line.word 0x00 "I2C_SCLH,I2C SCL High Time Register." hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,High Speed mode SCL high time" hexmask.word.byte 0x00 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time." group.word 0xBC++0x1 line.word 0x00 "I2C_SYSTEST,I2C System Test Register." bitfld.word 0x00 15. " ST_EN ,System test enable. - . - ." "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running mode (on breakpoint) - . - ." "Stop,Free" bitfld.word 0x00 12.--13. " TMODE ,Test mode select. - . - . - . - ." "Functional,Reserved,Test,Loopback" textline " " bitfld.word 0x00 11. " SSB ,Set status bits from 0 to 14. - . - ." "No_action,Set" bitfld.word 0x00 8. " SCL_I_FUNC ,SCL line input value (functional mode). - . - ." "Low,High" bitfld.word 0x00 7. " SCL_O_FUNC ,SCL line output value (functional mode). - . - ." "Low,High" textline " " bitfld.word 0x00 6. " SDA_I_FUNC ,SDA line input value (functional mode). - . - ." "Low,High" bitfld.word 0x00 5. " SDA_O_FUNC ,SDA line output value (functional mode). - . - ." "Low,High" bitfld.word 0x00 4. " SCCB_E_O ,SCCB_E line sense output value. - . - ." "Low,High" textline " " bitfld.word 0x00 3. " SCL_I ,SCL line sense input value - . - ." "Low,High" bitfld.word 0x00 2. " SCL_O ,SCL line drive output value. - . - ." "Low,High" bitfld.word 0x00 1. " SDA_I ,SDA line sense input value. - . - ." "Low,High" textline " " bitfld.word 0x00 0. " SDA_O ,SDA line drive output value. - . - ." "Low,High" rgroup.word 0xC0++0x1 line.word 0x00 "I2C_BUFSTAT,I2C Buffer Status Register." bitfld.word 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth." "0,1,2,3" bitfld.word 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 0.--5. " TXSTAT ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0xC4++0x1 line.word 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1" group.word 0xC8++0x1 line.word 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2" group.word 0xCC++0x1 line.word 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3" rgroup.word 0xD0++0x1 line.word 0x00 "I2C_ACTOA,I2C Active Own Address Register." bitfld.word 0x00 3. " OA3_ACT ,Own Address 3 active. - . - ." "Not_active,Active" bitfld.word 0x00 2. " OA2_ACT ,Own Address 2 active. - . - ." "Not_active,Active" bitfld.word 0x00 1. " OA1_ACT ,Own Address 1 active. - . - ." "Not_active,Active" textline " " bitfld.word 0x00 0. " OA0_ACT ,Own Address 0 active. - . - ." "Not_active,Active" group.word 0xD4++0x1 line.word 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.word 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3. - . - ." "Not_locked,Locked" bitfld.word 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2. - . - ." "Not_locked,Locked" bitfld.word 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1. - . - ." "Not_locked,Locked" textline " " bitfld.word 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0. - . - ." "Not_locked,Locked" tree.end tree "I2C4" base ad:0x48350000 width 21. rgroup.long 0x0++0x3 line.long 0x00 "I2C_REVNB_LO,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "I2C_REVNB_HI,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.word 0x10++0x1 line.word 0x00 "I2C_SYSC,System Configuration register" bitfld.word 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits - . - . - . - ." "Both_off,Ocp_on,Sys_on,Both_on" bitfld.word 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits - . - . - . - ." "Force_idle,No_idle,Smart_idle,Smartidle_wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SRST ,SoftReset bit - . - ." "Normal,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Autoidle bit - . - ." "Disabled,Enabled" group.word 0x24++0x1 line.word 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.word 0x00 14. " XDR ,Transmit draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " bitfld.word 0x00 11. " ROVR ,Receive overrun status.Writing into this bit has no effect. - . - ." "Normal,Received" bitfld.word 0x00 10. " XUDF ,Transmit underflow status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" bitfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status. - . - ." "No_action,Recognized" textline " " bitfld.word 0x00 8. " BF ,Bus Free IRQ status. - . - ." "No_action,Free" bitfld.word 0x00 7. " AERR ,Access Error IRQ status. - . - ." "No_action,Error" bitfld.word 0x00 6. " STC ,Start Condition IRQ status. - . - ." "No_action,Detected" textline " " bitfld.word 0x00 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. - . - ." "Not_detected,Detected" bitfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" bitfld.word 0x00 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. - . - ." "Not_ready,Ready" bitfld.word 0x00 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. - . - ." "Normal,Detected" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x28++0x1 line.word 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" eventfld.word 0x00 14. " XDR ,Transmit draining IRQ enabled status. - . - ." "Disabled,Enabled" eventfld.word 0x00 13. " RDR ,Receive draining IRQ enabled status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy enabled status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " eventfld.word 0x00 11. " ROVR ,Receive overrun enabled status.Writing into this bit has no effect. - . - ." "Normal,Received" eventfld.word 0x00 10. " XUDF ,Transmit underflow enabled status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ enabled status. - . - ." "No_action,Recognized" textline " " eventfld.word 0x00 8. " BF ,Bus Free IRQ enabled status. - . - ." "No_action,Free" eventfld.word 0x00 7. " AERR ,Access Error IRQ enabled status. - . - ." "No_action,Error" eventfld.word 0x00 6. " STC ,Start Condition IRQ enabled status. - . - ." "No_action,Detected" textline " " eventfld.word 0x00 5. " GC ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. Write 1 to clear. - . - ." "Not_detected,Detected" eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" textline " " eventfld.word 0x00 2. " ARDY ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 1. " NACK ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write 1 to clear this bit. - . - ." "Normal,Detected" eventfld.word 0x00 0. " AL ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x2C++0x1 line.word 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "0,1" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "0,1" bitfld.word 0x00 11. " ROVR ,Receive overrun enable set. - . - ." "0,1" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable set. - . - ." "0,1" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "0,1" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "0,1" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "0,1" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "0,1" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "0,1" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "0,1" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "0,1" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "0,1" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "0,1" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable set. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "0,1" group.word 0x30++0x1 line.word 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "0,1" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "0,1" bitfld.word 0x00 11. " ROVR ,Receive overrun enable clear. - . - ." "0,1" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable clear. - . - ." "0,1" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "0,1" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "0,1" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "0,1" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "0,1" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "0,1" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "0,1" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "0,1" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "0,1" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "0,1" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable clear. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "0,1" group.word 0x34++0x1 line.word 0x00 "I2C_WE,I2C wakeup enable vector." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x38++0x1 line.word 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.word 0x00 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set." "Disabled,Enabled" group.word 0x3C++0x1 line.word 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.word 0x00 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set." "Disabled,Enabled" group.word 0x40++0x1 line.word 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.word 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared" group.word 0x44++0x1 line.word 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.word 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared" group.word 0x48++0x1 line.word 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x4C++0x1 line.word 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.word 0x00 14. " XDR ,Transmit Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR ,Receive Draining wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " AAS ,Address as slave IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF ,Bus Free IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 6. " STC ,Start Condition IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC ,General call IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 2. " ARDY ,Register access ready IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 1. " NACK ,No acknowledgment IRQ wakeup set. - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL ,Arbitration lost IRQ wakeup set. - . - ." "Disabled,Enabled" group.word 0x84++0x1 line.word 0x00 "I2C_IE,I2C interrupt enable vector (legacy)." bitfld.word 0x00 14. " XDR_IE ,Transmit Draining interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[XDR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 13. " RDR_IE ,Receive Draining interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[RDR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 11. " ROVR ,Receive overrun enable set. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 10. " XUDF ,Transmit underflow enable set. - . - ." "Disabled,Enabled" bitfld.word 0x00 9. " ASS_IE ,Addressed as Slave interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AAS]. - . - ." "Disabled,Enabled" bitfld.word 0x00 8. " BF_IE ,Bus Free interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[BF]. - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AERR_IE ,Access Error interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AERR]. - . - ." "Disabled,Enabled" bitfld.word 0x00 6. " STC_IE ,Start Condition interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[STC]. - . - ." "Disabled,Enabled" bitfld.word 0x00 5. " GC_IE ,General call Interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[GC] - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[XRDY] - . - ." "Disabled,Enabled" bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[RRDY] - . - ." "Disabled,Enabled" bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[ARDY] - . - ." "Disabled,Enabled" textline " " bitfld.word 0x00 1. " NACK_IE ,No acknowledgement interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[NACK] - . - ." "Disabled,Enabled" bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable. Mask or unmask the interrupt signaled by bit inI2C_STAT[AL] - . - ." "Disabled,Enabled" group.word 0x88++0x1 line.word 0x00 "I2C_STAT,I2C interrupt status vector (legacy)." eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status. - . - ." "Disabled,Enabled" eventfld.word 0x00 13. " RDR ,Receive draining IRQ status. - . - ." "Disabled,Enabled" bitfld.word 0x00 12. " BB ,Bus busy status.Writing into this bit has no effect. - . - ." "Not_busy,Busy" textline " " eventfld.word 0x00 11. " ROVR ,Receive overrun status.Writing into this bit has no effect. - . - ." "Normal,Received" eventfld.word 0x00 10. " XUDF ,Transmit underflow status.Writing into this bit has no effect. - . - ." "No_underflow,Underflow" eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status. - . - ." "No_action,Recognized" textline " " eventfld.word 0x00 8. " BF ,Bus Free IRQ status. - . - ." "No_action,Free" eventfld.word 0x00 7. " AERR ,Access Error IRQ status. - . - ." "No_action,Error" eventfld.word 0x00 6. " STC ,Start Condition IRQ status. - . - ." "No_action,Detected" textline " " eventfld.word 0x00 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to MPUSS. Write 1 to clear. - . - ." "Not_detected,Detected" eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" textline " " eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to MPUSS. Write 1 to clear. - . - ." "Not_ready,Ready" eventfld.word 0x00 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS. Write 1 to clear this bit. - . - ." "Normal,Detected" eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. - . - ." "Normal,Detected" group.word 0x90++0x1 line.word 0x00 "I2C_SYSS,System Status register" bitfld.word 0x00 0. " RDONE ,Reset done bit - . - ." "Ongoing,Reset" group.word 0x94++0x1 line.word 0x00 "I2C_BUF,Buffer Configuration register" bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable - . - ." "Disabled,Enabled" bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear - . - ." "Normal,Reset" bitfld.word 0x00 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable - . - ." "Disabled,Enabled" bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear - . - ." "Normal,Reset" bitfld.word 0x00 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x98++0x1 line.word 0x00 "I2C_CNT,Data counter register" hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count Because the transfer length for DCOUNT = 0x0000 is 65536, the module does not allow the initiation of zero-data-byte transfers." hgroup.word 0x9C++0x1 hide.word 0x00 "I2C_DATA,Data access register" in group.word 0xA4++0x1 line.word 0x00 "I2C_CON,I2C configuration register." bitfld.word 0x00 15. " I2C_EN ,I2C module enable. - . - ." "Disabled,Enabled" bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection. - . - . - . - ." "Fast/Standard,High_Speed,SCCB,?..." bitfld.word 0x00 11. " STB ,Start byte mode (master mode only). - . - ." "Normal_mode,Start_byte_mode" textline " " bitfld.word 0x00 10. " MST ,Master/slave mode. - . - ." "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmitter/Receiver mode (master mode only). - . - ." "Receiver_mode,Transmitter_mode" bitfld.word 0x00 8. " XSA ,Expand Slave address. - . - ." "7-bit,10-bit" textline " " bitfld.word 0x00 7. " XOA0 ,Expand Own address 0. - . - ." "7-bit,10-bit" bitfld.word 0x00 6. " XOA1 ,Expand Own address 1. - . - ." "7-bit,10-bit" bitfld.word 0x00 5. " XOA2 ,Expand Own address 2. - . - ." "7-bit,10-bit" textline " " bitfld.word 0x00 4. " XOA3 ,Expand Own address 3. - . - ." "7-bit,10-bit" bitfld.word 0x00 1. " STP ,Stop condition (master mode only). - . - ." "0,Stop_condition_queried" bitfld.word 0x00 0. " STT ,Start condition (master mode only). - . - ." "0,Start_condition_queried" group.word 0xA8++0x1 line.word 0x00 "I2C_OA,Own address register" bitfld.word 0x00 13.--15. " MCODE ,Master Code" "0,1,2,3,4,5,6,7" hexmask.word 0x00 0.--9. 1. " OA ,Own address" group.word 0xAC++0x1 line.word 0x00 "I2C_SA,Slave address register" hexmask.word 0x00 0.--9. 1. " SA ,Slave address" group.word 0xB0++0x1 line.word 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 .............................. 0xFF: Divide by 256" group.word 0xB4++0x1 line.word 0x00 "I2C_SCLL,I2C SCL Low Time Register." hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,High Speed mode SCL low time" hexmask.word.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time." group.word 0xB8++0x1 line.word 0x00 "I2C_SCLH,I2C SCL High Time Register." hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,High Speed mode SCL high time" hexmask.word.byte 0x00 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time." group.word 0xBC++0x1 line.word 0x00 "I2C_SYSTEST,I2C System Test Register." bitfld.word 0x00 15. " ST_EN ,System test enable. - . - ." "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running mode (on breakpoint) - . - ." "Stop,Free" bitfld.word 0x00 12.--13. " TMODE ,Test mode select. - . - . - . - ." "Functional,Reserved,Test,Loopback" textline " " bitfld.word 0x00 11. " SSB ,Set status bits from 0 to 14. - . - ." "No_action,Set" bitfld.word 0x00 8. " SCL_I_FUNC ,SCL line input value (functional mode). - . - ." "Low,High" bitfld.word 0x00 7. " SCL_O_FUNC ,SCL line output value (functional mode). - . - ." "Low,High" textline " " bitfld.word 0x00 6. " SDA_I_FUNC ,SDA line input value (functional mode). - . - ." "Low,High" bitfld.word 0x00 5. " SDA_O_FUNC ,SDA line output value (functional mode). - . - ." "Low,High" bitfld.word 0x00 4. " SCCB_E_O ,SCCB_E line sense output value. - . - ." "Low,High" textline " " bitfld.word 0x00 3. " SCL_I ,SCL line sense input value - . - ." "Low,High" bitfld.word 0x00 2. " SCL_O ,SCL line drive output value. - . - ." "Low,High" bitfld.word 0x00 1. " SDA_I ,SDA line sense input value. - . - ." "Low,High" textline " " bitfld.word 0x00 0. " SDA_O ,SDA line drive output value. - . - ." "Low,High" rgroup.word 0xC0++0x1 line.word 0x00 "I2C_BUFSTAT,I2C Buffer Status Register." bitfld.word 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth." "0,1,2,3" bitfld.word 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 0.--5. " TXSTAT ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0xC4++0x1 line.word 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1" group.word 0xC8++0x1 line.word 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2" group.word 0xCC++0x1 line.word 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3" rgroup.word 0xD0++0x1 line.word 0x00 "I2C_ACTOA,I2C Active Own Address Register." bitfld.word 0x00 3. " OA3_ACT ,Own Address 3 active. - . - ." "Not_active,Active" bitfld.word 0x00 2. " OA2_ACT ,Own Address 2 active. - . - ." "Not_active,Active" bitfld.word 0x00 1. " OA1_ACT ,Own Address 1 active. - . - ." "Not_active,Active" textline " " bitfld.word 0x00 0. " OA0_ACT ,Own Address 0 active. - . - ." "Not_active,Active" group.word 0xD4++0x1 line.word 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.word 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3. - . - ." "Not_locked,Locked" bitfld.word 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2. - . - ." "Not_locked,Locked" bitfld.word 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1. - . - ." "Not_locked,Locked" textline " " bitfld.word 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0. - . - ." "Not_locked,Locked" tree.end tree.end tree.end tree.open "HDQ_1_Wire" tree "HDQ_1_Wire" base ad:0x480B2000 width 17. rgroup.long 0x0++0x3 line.long 0x00 "HDQ_REVISION,This register contains the IP revision code" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x4++0x3 line.long 0x00 "HDQ_TX_DATA,This register contains the data to be transmitted." hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data (used in both HDQ and 1-Wire modes)" rgroup.long 0x8++0x3 line.long 0x00 "HDQ_RX_DATA,This register contains the data to be received." hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Receive data (used in both HDQ and 1-Wire modes)" group.long 0xC++0x3 line.long 0x00 "HDQ_CTRL_STATUS,This register provides status information about the module." bitfld.long 0x00 7. " ONE_WIRE_SINGLE_BIT ,Single-bit mode for 1-Wire0x0: Disabled 0x1: Enabled" "0,1" bitfld.long 0x00 6. " INTERRUPTMASK ,Interrupt masking bit0x0: Interrupts disable 0x1: Interrupts enable" "0,1" bitfld.long 0x00 5. " CLOCKENABLE ,Power-down mode bit0x0: Clock disable (power down)0x1: Clock enable" "0,1" textline " " bitfld.long 0x00 4. " GO ,Go bit. Write 1 to start the appropriate operation. Bit returns to 0 after the operation is complete if INTERRUPTMASK = 0x1." "0,1" bitfld.long 0x00 3. " PRESENCEDETECT ,Slave presence indicator. Actual only just after initialization time-out. Used in 1-Wire mode. Read-only flag.0x0: No slave detected0x1: Slave detected" "0,1" bitfld.long 0x00 2. " INITIALIZATION ,Write 1 to send initialization pulse. Bit returns to 0 after pulse is sent." "0,1" textline " " bitfld.long 0x00 1. " DIR ,DIR bit, determines if next command is read or write0x0: Write 0x1: Read" "0,1" bitfld.long 0x00 0. " MODE ,Mode selection bit0x0: HDQ mode 0x1: 1-Wire mode" "0,1" rgroup.long 0x10++0x3 line.long 0x00 "HDQ_INT_STATUS,This register controls interrupts status" bitfld.long 0x00 2. " TXCOMPLETE ,TX-complete interrupt flag.Set to 1 if cause of interrupt. Set to 0 when register read." "0,1" bitfld.long 0x00 1. " RXCOMPLETE ,Read-complete interrupt flag.Set to 1 if cause of interrupt. Set to 0 when register read." "0,1" bitfld.long 0x00 0. " TIMEOUT ,Presence detect/timeout interrupt flag.In 1-Wire mode, set to 1 if slave's presence detected. In HDQ mode, set to 1 if timeout on read occurs. Set to 0 when register read." "0,1" group.long 0x14++0x3 line.long 0x00 "HDQ_SYSCONFIG,This register controls various bits" bitfld.long 0x00 1. " SOFTRESET ,Start soft reset sequence.0x0: Disabled 0x1: Enabled" "0,1" bitfld.long 0x00 0. " AUTOIDLE ,Interconnect idle.0x0: Module clock is free-running. 0x1: Module is in power saving mode: Clock is running only when module is accessed or inside logic is in function to process events." "0,1" rgroup.long 0x18++0x3 line.long 0x00 "HDQ_SYSSTATUS,This register monitors the reset sequence." bitfld.long 0x00 0. " RESETDONE ,Reset monitoring.0x0: The module is currently performing its reset. When the module is in power-down mode, set to 0 to indicate this fact. 0x1: The module has finished its reset." "0,1" tree.end tree.end tree.open "UART_IrDA_CIR" tree.open "UART3" tree "UART3" base ad:0x48020000 width 23. group.long 0x0++0x3 line.long 0x00 "UART_DLL,This register, with, stores the 14-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.byte 0x00 0.--7. 1. " CLOCK_LSB ,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved t.." hexmask.long.byte 0x00 0.--7. 1. " RHR ,Receive holding register" wgroup.long 0x0++0x3 line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The THR is a 64-byte FIFO. The local host (LH) writes data to the THR. The data is placed in the transmit shift register where it is shift.." hexmask.long.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.long 0x4++0x3 line.long 0x00 "UART_DLH,This register, with, stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." bitfld.long 0x00 0.--5. " CLOCK_MSB ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4++0x3 line.long 0x00 "UART_IER,Interrupt enable register" bitfld.long 0x00 7. " CTS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 6. " RTS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 5. " XOFF_IT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SLEEP_MODE ,- . - ." "Disabled,Enabled" bitfld.long 0x00 3. " MODEM_STS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 2. " LINE_STS_IT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " THR_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 0. " RHR_IT ,- . - ." "Disabled,Enabled" group.long 0x8++0x3 line.long 0x00 "UART_EFR,Enhanced feature register" bitfld.long 0x00 7. " AUTO_CTS_EN ,Auto-CTS enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " AUTO_RTS_EN ,Auto-RTS enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " SPECIAL_CHAR_DETECT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " ENHANCED_EN ,Enhanced functions write enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--3. " SW_FLOW_CONTROL ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See." "No_transmit/No_receive,No_transmit/Rx_comp._XON2;XOFF2,No_transmit/Rx_comp._XON1;XOFF1,No_transmit/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON2;XOFF2/No_receive,Tx_XON2;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON2;XOFF2/Rx_comp._XON1;XOFF1,Tx_XON2;XOFF2/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XOFF1/No_receive,Tx_XON1;XOFF1/Rx_comp._XON2;XOFF2,Tx_XON1;XOFF1/Rx_comp._XON1;XOFF1,Tx_XON1;XOFF1/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/No_receive,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON1;XOFF1,Tx/Rx_comp._XON1;XON2:XOFF1;XOFF2" wgroup.long 0x8++0x3 line.long 0x00 "UART_FCR,FIFO control register" bitfld.long 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If UART_SCR[7] = 0 and UART_TLR[7:4] != 0000, RX_FIFO_TRIG is not co.." "8,16,56,60" bitfld.long 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If UART_SCR[6] = 0 and UART_TLR[3:0] != 0000, TX_FIFO_T.." "8,16,32,56" bitfld.long 0x00 3. " DMA_MODE ,This register is considered ifUART_SCR[0] = 0. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TX_FIFO_CLEAR ,- . - ." "No_effect,Clear" bitfld.long 0x00 1. " RX_FIFO_CLEAR ,- . - ." "No_effect,Clear" bitfld.long 0x00 0. " FIFO_EN ,- . - ." "Disabled,Enabled" rgroup.long 0x8++0x3 line.long 0x00 "UART_IIR,Interrupt identification register." bitfld.long 0x00 6.--7. " FCR_MIRROR ,Mirror the contents ofUART_FCR[0] on both bits." "0,1,2,3" bitfld.long 0x00 1.--5. " IT_TYPE ,Read 0x0: Modem interrupt. Priority = 4 - . - . - . - . - . - ." "0,THR,RHR,Receiver_line_status_error,4,5,Rx_time-out,7,XOFF/special_character,9,10,11,12,13,14,15,CTS/RTS/DSR_change,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " IT_PENDING ,Read 0x0: An interrupt is pending. - ." "0,Not_pending" group.long 0xC++0x3 line.long 0x00 "UART_LCR,Line control register" bitfld.long 0x00 7. " DIV_EN ,- . - ." "Disabled,Enabled" bitfld.long 0x00 6. " BREAK_EN ,Break control bit - . - ." "Normal,Forced_low" bitfld.long 0x00 5. " PARITY_TYPE2 ,Selects the forced parity format (ifUART_LCR[3] = 1). If UART_LCR[5] = 1 and UART_LCR[4] = 0, the parity bit is forced to 1 in the transmitted and received data. If UART_LCR[5] = 1 and UART_LCR.." "No_parity,Odd_parity" textline " " bitfld.long 0x00 4. " PARITY_TYPE1 ,- . - ." "0,1" bitfld.long 0x00 3. " PARITY_EN ,0x0: No parity - ." "0,1" bitfld.long 0x00 2. " NB_STOP ,Specifies the number of stop-bits - . - ." "1,1.5" textline " " bitfld.long 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received - . - . - . - ." "5,6,7,8" group.long 0x10++0x3 line.long 0x00 "UART_MCR,Modem control register" bitfld.long 0x00 6. " TCR_TLR ,0x0: No action - ." "0,Enabled" bitfld.long 0x00 5. " XON_EN ,0x0: Disable XON any function. - ." "0,Enabled" bitfld.long 0x00 4. " LOOPBACK_EN ,0x0: Normal operating mode - ." "0,Enabled" textline " " bitfld.long 0x00 3. " CD_STS_CH ,0x0: In loopback, forces DCD* input high and IRQ outputs to inactive state - ." "0,Low" bitfld.long 0x00 2. " RI_STS_CH ,0x0: In loopback, forces RI* input high - ." "0,Low" bitfld.long 0x00 1. " RTS ,In loopback, controls theUART_MSR[4] bit. If auto-RTS is enabled, the RTS* output is controlled by hardware flow control. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DTR ,0x0: Force DTR* output to inactive (high). - ." "0,Enabled" group.long 0x10++0x3 line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address" hexmask.long.byte 0x00 0.--7. 1. " XON_WORD1 ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x00 "UART_LSR,Line status register" bitfld.long 0x00 7. " RX_FIFO_STS ,Read 0x0: Normal operation - ." "0,Error" bitfld.long 0x00 6. " TX_SR_E ,Read 0x0: Transmitter hold (TX FIFO) and shift registers are not empty. - ." "0,Empty" bitfld.long 0x00 5. " TX_FIFO_E ,Read 0x0: Transmit hold register (TX FIFO) is not empty. - ." "0,Empty" textline " " bitfld.long 0x00 4. " RX_BI ,Read 0x0: No break condition - ." "0,Detected" bitfld.long 0x00 3. " RX_FE ,Read 0x0: No framing error in data RX FIFO - ." "0,Error" bitfld.long 0x00 2. " RX_PE ,Read 0x0: No parity error in data from RX FIFO - ." "0,Error" textline " " bitfld.long 0x00 1. " RX_OE ,Read 0x0: No overrun error - ." "0,Error" bitfld.long 0x00 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO - ." "0,One_data" group.long 0x14++0x3 line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.byte 0x00 0.--7. 1. " XON_WORD2 ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x00 "UART_MSR,Modem status register. UART mode only." bitfld.long 0x00 7. " NCD_STS ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent toUART_MCR[3]." "0,1" bitfld.long 0x00 6. " NRI_STS ,This bit is the complement of the RI* input. In loopback mode, it is equivalent toUART_MCR[2]." "0,1" bitfld.long 0x00 5. " NDSR_STS ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent toUART_MCR[0]." "0,1" textline " " bitfld.long 0x00 4. " NCTS_STS ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent toUART_MCR[1]." "0,1" bitfld.long 0x00 3. " DCD_STS ,Indicates that DCD* input (orUART_MCR[3] in loopback) changed. Cleared on a read." "0,1" bitfld.long 0x00 2. " RI_STS ,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high. Cleared on a read." "0,1" textline " " bitfld.long 0x00 1. " DSR_STS ,- ." "0,1" bitfld.long 0x00 0. " CTS_STS ,- ." "0,1" group.long 0x18++0x3 line.long 0x00 "UART_TCR,Transmission control register" bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_START ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.long 0x00 0.--3. " RX_FIFO_TRIG_HALT ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.long 0x18++0x3 line.long 0x00 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD1 ,Stores the 8-bit XOFF1 character used in UART modes" group.long 0x1C++0x3 line.long 0x00 "UART_SPR,Scratchpad register" hexmask.long.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" group.long 0x1C++0x3 line.long 0x00 "UART_TLR,Trigger level register" bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD2 ,Stores the 8-bit XOFF2 character used in UART modes." group.long 0x20++0x3 line.long 0x00 "UART_MDR1,Mode definition register 1" bitfld.long 0x00 7. " FRAME_END_MODE ,IrDA mode only - . - ." "Frame-length,EOT" bitfld.long 0x00 6. " SIP_MODE ,MIR/FIR modes only - . - ." "Manual_SIP,Automatic_SIP" bitfld.long 0x00 5. " SCT ,Store and control the transmission. - . - ." "THR,ACREG[2]" textline " " bitfld.long 0x00 4. " SET_TXIR ,Used to configure the infrared transceiver - . - ." "TXIR_low,IRTX_high" bitfld.long 0x00 3. " IR_SLEEP ,0x0: IrDA/CIR sleep mode disabled - ." "0,Enabled" bitfld.long 0x00 0.--2. " MODE_SELECT ,0x0: UART 16x mode - . - . - . - . - . - . - ." "0,Reserved,UART_16x_auto-baud,UART_13x,Reserved,Reserved,Reserved,Disabled" group.long 0x24++0x3 line.long 0x00 "UART_MDR2,Mode definition register 2" bitfld.long 0x00 7. " SET_TXIR_ALT ,Provide alternate function for MDR1[4] (SET_TXIR). - . - ." "Normal,Alternate" bitfld.long 0x00 6. " IRRXINVERT ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes. - . - ." "Inversion_is_performed.,1" bitfld.long 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit: - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 3. " UART_PULSE ,UART mode only. Allows pulse shaping in UART mode. - . - ." "Normal_UART_mode,1" bitfld.long 0x00 1.--2. " STS_FIFO_TRIG ,IR-IrDA mode only. Frame status FIFO threshold select: - . - . - . - ." "1_entry,4_entries,7_entries,8_entries" bitfld.long 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt. When theUART_IIR[5] interrupt occurs, the meaning of the interrupt is: - . - ." "0,1" rgroup.long 0x28++0x3 line.long 0x00 "UART_SFLSR,Status FIFO line status register" bitfld.long 0x00 4. " OE_ERROR ,Read 0x1: Overrun error in RX FIFO when frame at top of RX FIFO was received Top of RX FIFO = Next frame to be read from RX FIFO" "No_error,Error" bitfld.long 0x00 3. " FRAME_TOO_LONG_ERROR ,Read 0x1: Frame-length too long error in frame at top of RX FIFO" "No_error,Error" bitfld.long 0x00 2. " ABORT_DETECT ,Read 0x1: Abort pattern detected in frame at top of RX FIFO" "No_error,Error" textline " " bitfld.long 0x00 1. " CRC_ERROR ,Read 0x1: CRC error in frame at top of RX FIFO" "No_error,Error" wgroup.long 0x28++0x3 line.long 0x00 "UART_TXFLL,Transmit frame length register low" hexmask.long.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x00 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exi.." hexmask.long.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.long 0x2C++0x3 line.long 0x00 "UART_TXFLH,Transmit frame length register high" bitfld.long 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long 0x30++0x3 line.long 0x00 "UART_RXFLL,Received frame length register low" hexmask.long.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x00 "UART_SFREGL,Status FIFO register low" hexmask.long.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.long 0x34++0x3 line.long 0x00 "UART_RXFLH,Received frame length register high" bitfld.long 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x34++0x3 line.long 0x00 "UART_SFREGH,Status FIFO register high" bitfld.long 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "UART_BLR,BOF control register" bitfld.long 0x00 7. " STS_FIFO_RESET ,Status FIFO reset. This bit is self-clearing." "No_reset,Reset" bitfld.long 0x00 6. " XBOF_TYPE ,SIR xBOF select - . - ." "0xFF,0xC0" rgroup.long 0x38++0x3 line.long 0x00 "UART_UASR,UART autobauding status register" bitfld.long 0x00 6.--7. " PARITY_TYPE ,Read 0x0: No parity identified - . - . - ." "0,Parity_space,Even,Odd" bitfld.long 0x00 5. " BIT_BY_CHAR ,Read 0x0: 7-bit character identified - ." "0,8" bitfld.long 0x00 0.--4. " SPEED ,Used to report the speed identified - . - . - . - . - . - . - . - . - . - . - ." "No_speed,115_200,57_600,38_400,28_800,19_200,14_400,9_600,4_800,2_400,1_200,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3C++0x3 line.long 0x00 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." bitfld.long 0x00 7. " PULSE_TYPE ,SIR pulse width select - . - ." "3/16_of_baud-rate,1.6_us" bitfld.long 0x00 6. " SD_MOD ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. - . - ." "High,Low" bitfld.long 0x00 5. " DIS_IR_RX ,0x0: Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation) - ." "0,Yes" textline " " bitfld.long 0x00 4. " DIS_TX_UNDERRUN ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4] = 1, garbage data is sent over TX line. - . - ." "No,Yes" bitfld.long 0x00 3. " SEND_SIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end .." "No_action,Sent" bitfld.long 0x00 2. " SCTX_EN ,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit, the TX state-machine starts frame transmission. This bit is self-clearing." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ABORT_EN ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and MDR1[5] = 1, UART IrDA starts a new t.." "Disabled,Enabled" bitfld.long 0x00 0. " EOT_EN ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes t.." "Disabled,Enabled" group.long 0x40++0x3 line.long 0x00 "UART_SCR,Supplementary control register" bitfld.long 0x00 7. " RX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger RX level - ." "0,Enabled" bitfld.long 0x00 6. " TX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger TX level - ." "0,Enabled" bitfld.long 0x00 5. " DSR_IT ,0x0: Disables DSR* interrupt - ." "0,Enabled" textline " " bitfld.long 0x00 4. " RX_CTS_DSR_WAKE_UP_ENABLE ,0x0: Disables the wake-up interrupt and clears SSR[1] - ." "0,Enabled" bitfld.long 0x00 3. " TX_EMPTY_CTL_IT ,0x0: Normal mode for THR interrupt (see UART mode interrupts table) - ." "0,Interrupt" bitfld.long 0x00 1.--2. " DMA_MODE_2 ,Used to specify the DMA mode valid if theUART_SCR[0] bit = 1 - . - . - . - ." "No_DMA,UART_nDMA_REQ[0/1]_in_TX/RX;,UART_nDMA_REQ[0]_in_RX,UART_nDMA_REQ[0]_in_TX" textline " " bitfld.long 0x00 0. " DMA_MODE_CTL ,0x0: The DMA_MODE is set withUART_FCR[3]. - ." "0,UART_SCR[2:1]" group.long 0x44++0x3 line.long 0x00 "UART_SSR,Supplementary status register" bitfld.long 0x00 2. " DMA_COUNTER_RST ,0x0: The DMA counter will not be reset if the corresponding FIFO is reset (through FCR[1] or FCR[2]). - ." "0,Reset" bitfld.long 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Read 0x0: No falling edge event on RX, CTS*, and DSR* - ." "0,Occurred" bitfld.long 0x00 0. " TX_FIFO_FULL ,Read 0x0: TX FIFO is not full. - ." "0,Full" group.long 0x48++0x3 line.long 0x00 "UART_EBLR,BOF length register" hexmask.long.byte 0x00 0.--7. 1. " EBLR ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x00 "UART_MVR,Module version register" hexmask.long 0x00 0.--31. 1. " REV ,Revision number" group.long 0x54++0x3 line.long 0x00 "UART_SYSC,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,Power management req/ack control ref: OCP Design Guidelines Version 1.1 - . - . - . - ." "Force_idle,No-idle,Smart_idle,?..." bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0. - . - ." "No_reset,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy - . - ." "Running,Gated" rgroup.long 0x58++0x3 line.long 0x00 "UART_SYSS,System status register" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "Not_completed,Completed" group.long 0x5C++0x3 line.long 0x00 "UART_WER,Wake-up enable register" bitfld.long 0x00 7. " TX_WAKEUP_EN ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 6. " EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 5. " EVENT_5_RHR_INTERRUPT ,0x0: Event is not allowed to wake up the system. - ." "0,1" textline " " bitfld.long 0x00 4. " EVENT_4_RX_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 3. " EVENT_3_DCD_CD_ACTIVITY ,0x0: Event is not allowed to wake up the system - ." "0,1" bitfld.long 0x00 2. " EVENT_2_RI_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" textline " " bitfld.long 0x00 1. " EVENT_1_DSR_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 0. " EVENT_0_CTS_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" group.long 0x60++0x3 line.long 0x00 "UART_CFPS,Carrier frequency prescaler" hexmask.long.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple). Examples for CFPS values: - Target Freq (kHz) CFPS (decimal) Actual Freq (kHz) . - . - 30 133 30.08 . - . - 32.75 122 32.79 . - . - 36 111 36.04 . - . - 36.7 109 36.69 . - .." rgroup.long 0x64++0x3 line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Shows the number of received bytes in the RX FIFO" rgroup.long 0x68++0x3 line.long 0x00 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0x3 line.long 0x00 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x00 1. " EN_TXFIFO_EMPTY ,Enables TX FIFO empty corresponding interrupt - . - ." "Enabled,Disabled" bitfld.long 0x00 0. " EN_RXFIFO_EMPTY ,Enables RX FIFO empty corresponding interrupt - . - ." "Enabled,Disabled" group.long 0x70++0x3 line.long 0x00 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x00 1. " TXFIFO_EMPTY_STS ,Used to generate interrupt if the TX_FIFO is empty (software flow control) - . - ." "No_interrupt,Interrupt" bitfld.long 0x00 0. " RXFIFO_EMPTY_STS ,Used to generate interrupt if the RX_FIFO is empty (software flow control) - . - ." "No_interrupt,Interrupt" group.long 0x74++0x3 line.long 0x00 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if nondefault frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal to or higher then 6." group.long 0x80++0x3 line.long 0x00 "UART_MDR3,Mode definition register 3" bitfld.long 0x00 2. " SET_DMA_TX_THRESHOLD ,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register." "0,1" bitfld.long 0x00 1. " NONDEFAULT_FREQ ,Used to enable the NONDEFAULT fclk frequencies. - . - ." "0,1" bitfld.long 0x00 0. " DISABLE_CIR_RX_DEMOD ,Used to enable CIR RX demodulation. - . - ." "0,1" group.long 0x84++0x3 line.long 0x00 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register." bitfld.long 0x00 0.--5. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "UART1" base ad:0x4806A000 width 23. group.long 0x0++0x3 line.long 0x00 "UART_DLL,This register, with, stores the 14-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.byte 0x00 0.--7. 1. " CLOCK_LSB ,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved t.." hexmask.long.byte 0x00 0.--7. 1. " RHR ,Receive holding register" wgroup.long 0x0++0x3 line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The THR is a 64-byte FIFO. The local host (LH) writes data to the THR. The data is placed in the transmit shift register where it is shift.." hexmask.long.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.long 0x4++0x3 line.long 0x00 "UART_DLH,This register, with, stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." bitfld.long 0x00 0.--5. " CLOCK_MSB ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4++0x3 line.long 0x00 "UART_IER,Interrupt enable register" bitfld.long 0x00 7. " CTS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 6. " RTS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 5. " XOFF_IT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SLEEP_MODE ,- . - ." "Disabled,Enabled" bitfld.long 0x00 3. " MODEM_STS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 2. " LINE_STS_IT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " THR_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 0. " RHR_IT ,- . - ." "Disabled,Enabled" group.long 0x8++0x3 line.long 0x00 "UART_EFR,Enhanced feature register" bitfld.long 0x00 7. " AUTO_CTS_EN ,Auto-CTS enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " AUTO_RTS_EN ,Auto-RTS enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " SPECIAL_CHAR_DETECT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " ENHANCED_EN ,Enhanced functions write enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--3. " SW_FLOW_CONTROL ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See." "No_transmit/No_receive,No_transmit/Rx_comp._XON2;XOFF2,No_transmit/Rx_comp._XON1;XOFF1,No_transmit/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON2;XOFF2/No_receive,Tx_XON2;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON2;XOFF2/Rx_comp._XON1;XOFF1,Tx_XON2;XOFF2/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XOFF1/No_receive,Tx_XON1;XOFF1/Rx_comp._XON2;XOFF2,Tx_XON1;XOFF1/Rx_comp._XON1;XOFF1,Tx_XON1;XOFF1/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/No_receive,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON1;XOFF1,Tx/Rx_comp._XON1;XON2:XOFF1;XOFF2" wgroup.long 0x8++0x3 line.long 0x00 "UART_FCR,FIFO control register" bitfld.long 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If UART_SCR[7] = 0 and UART_TLR[7:4] != 0000, RX_FIFO_TRIG is not co.." "8,16,56,60" bitfld.long 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If UART_SCR[6] = 0 and UART_TLR[3:0] != 0000, TX_FIFO_T.." "8,16,32,56" bitfld.long 0x00 3. " DMA_MODE ,This register is considered ifUART_SCR[0] = 0. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TX_FIFO_CLEAR ,- . - ." "No_effect,Clear" bitfld.long 0x00 1. " RX_FIFO_CLEAR ,- . - ." "No_effect,Clear" bitfld.long 0x00 0. " FIFO_EN ,- . - ." "Disabled,Enabled" rgroup.long 0x8++0x3 line.long 0x00 "UART_IIR,Interrupt identification register." bitfld.long 0x00 6.--7. " FCR_MIRROR ,Mirror the contents ofUART_FCR[0] on both bits." "0,1,2,3" bitfld.long 0x00 1.--5. " IT_TYPE ,Read 0x0: Modem interrupt. Priority = 4 - . - . - . - . - . - ." "0,THR,RHR,Receiver_line_status_error,4,5,Rx_time-out,7,XOFF/special_character,9,10,11,12,13,14,15,CTS/RTS/DSR_change,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " IT_PENDING ,Read 0x0: An interrupt is pending. - ." "0,Not_pending" group.long 0xC++0x3 line.long 0x00 "UART_LCR,Line control register" bitfld.long 0x00 7. " DIV_EN ,- . - ." "Disabled,Enabled" bitfld.long 0x00 6. " BREAK_EN ,Break control bit - . - ." "Normal,Forced_low" bitfld.long 0x00 5. " PARITY_TYPE2 ,Selects the forced parity format (ifUART_LCR[3] = 1). If UART_LCR[5] = 1 and UART_LCR[4] = 0, the parity bit is forced to 1 in the transmitted and received data. If UART_LCR[5] = 1 and UART_LCR.." "No_parity,Odd_parity" textline " " bitfld.long 0x00 4. " PARITY_TYPE1 ,- . - ." "0,1" bitfld.long 0x00 3. " PARITY_EN ,0x0: No parity - ." "0,1" bitfld.long 0x00 2. " NB_STOP ,Specifies the number of stop-bits - . - ." "1,1.5" textline " " bitfld.long 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received - . - . - . - ." "5,6,7,8" group.long 0x10++0x3 line.long 0x00 "UART_MCR,Modem control register" bitfld.long 0x00 6. " TCR_TLR ,0x0: No action - ." "0,Enabled" bitfld.long 0x00 5. " XON_EN ,0x0: Disable XON any function. - ." "0,Enabled" bitfld.long 0x00 4. " LOOPBACK_EN ,0x0: Normal operating mode - ." "0,Enabled" textline " " bitfld.long 0x00 3. " CD_STS_CH ,0x0: In loopback, forces DCD* input high and IRQ outputs to inactive state - ." "0,Low" bitfld.long 0x00 2. " RI_STS_CH ,0x0: In loopback, forces RI* input high - ." "0,Low" bitfld.long 0x00 1. " RTS ,In loopback, controls theUART_MSR[4] bit. If auto-RTS is enabled, the RTS* output is controlled by hardware flow control. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DTR ,0x0: Force DTR* output to inactive (high). - ." "0,Enabled" group.long 0x10++0x3 line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address" hexmask.long.byte 0x00 0.--7. 1. " XON_WORD1 ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x00 "UART_LSR,Line status register" bitfld.long 0x00 7. " RX_FIFO_STS ,Read 0x0: Normal operation - ." "0,Error" bitfld.long 0x00 6. " TX_SR_E ,Read 0x0: Transmitter hold (TX FIFO) and shift registers are not empty. - ." "0,Empty" bitfld.long 0x00 5. " TX_FIFO_E ,Read 0x0: Transmit hold register (TX FIFO) is not empty. - ." "0,Empty" textline " " bitfld.long 0x00 4. " RX_BI ,Read 0x0: No break condition - ." "0,Detected" bitfld.long 0x00 3. " RX_FE ,Read 0x0: No framing error in data RX FIFO - ." "0,Error" bitfld.long 0x00 2. " RX_PE ,Read 0x0: No parity error in data from RX FIFO - ." "0,Error" textline " " bitfld.long 0x00 1. " RX_OE ,Read 0x0: No overrun error - ." "0,Error" bitfld.long 0x00 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO - ." "0,One_data" group.long 0x14++0x3 line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.byte 0x00 0.--7. 1. " XON_WORD2 ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x00 "UART_MSR,Modem status register. UART mode only." bitfld.long 0x00 7. " NCD_STS ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent toUART_MCR[3]." "0,1" bitfld.long 0x00 6. " NRI_STS ,This bit is the complement of the RI* input. In loopback mode, it is equivalent toUART_MCR[2]." "0,1" bitfld.long 0x00 5. " NDSR_STS ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent toUART_MCR[0]." "0,1" textline " " bitfld.long 0x00 4. " NCTS_STS ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent toUART_MCR[1]." "0,1" bitfld.long 0x00 3. " DCD_STS ,Indicates that DCD* input (orUART_MCR[3] in loopback) changed. Cleared on a read." "0,1" bitfld.long 0x00 2. " RI_STS ,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high. Cleared on a read." "0,1" textline " " bitfld.long 0x00 1. " DSR_STS ,- ." "0,1" bitfld.long 0x00 0. " CTS_STS ,- ." "0,1" group.long 0x18++0x3 line.long 0x00 "UART_TCR,Transmission control register" bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_START ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.long 0x00 0.--3. " RX_FIFO_TRIG_HALT ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.long 0x18++0x3 line.long 0x00 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD1 ,Stores the 8-bit XOFF1 character used in UART modes" group.long 0x1C++0x3 line.long 0x00 "UART_SPR,Scratchpad register" hexmask.long.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" group.long 0x1C++0x3 line.long 0x00 "UART_TLR,Trigger level register" bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD2 ,Stores the 8-bit XOFF2 character used in UART modes." group.long 0x20++0x3 line.long 0x00 "UART_MDR1,Mode definition register 1" bitfld.long 0x00 7. " FRAME_END_MODE ,IrDA mode only - . - ." "Frame-length,EOT" bitfld.long 0x00 6. " SIP_MODE ,MIR/FIR modes only - . - ." "Manual_SIP,Automatic_SIP" bitfld.long 0x00 5. " SCT ,Store and control the transmission. - . - ." "THR,ACREG[2]" textline " " bitfld.long 0x00 4. " SET_TXIR ,Used to configure the infrared transceiver - . - ." "TXIR_low,IRTX_high" bitfld.long 0x00 3. " IR_SLEEP ,0x0: IrDA/CIR sleep mode disabled - ." "0,Enabled" bitfld.long 0x00 0.--2. " MODE_SELECT ,0x0: UART 16x mode - . - . - . - . - . - . - ." "0,Reserved,UART_16x_auto-baud,UART_13x,Reserved,Reserved,Reserved,Disabled" group.long 0x24++0x3 line.long 0x00 "UART_MDR2,Mode definition register 2" bitfld.long 0x00 7. " SET_TXIR_ALT ,Provide alternate function for MDR1[4] (SET_TXIR). - . - ." "Normal,Alternate" bitfld.long 0x00 6. " IRRXINVERT ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes. - . - ." "Inversion_is_performed.,1" bitfld.long 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit: - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 3. " UART_PULSE ,UART mode only. Allows pulse shaping in UART mode. - . - ." "Normal_UART_mode,1" bitfld.long 0x00 1.--2. " STS_FIFO_TRIG ,IR-IrDA mode only. Frame status FIFO threshold select: - . - . - . - ." "1_entry,4_entries,7_entries,8_entries" bitfld.long 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt. When theUART_IIR[5] interrupt occurs, the meaning of the interrupt is: - . - ." "0,1" rgroup.long 0x28++0x3 line.long 0x00 "UART_SFLSR,Status FIFO line status register" bitfld.long 0x00 4. " OE_ERROR ,Read 0x1: Overrun error in RX FIFO when frame at top of RX FIFO was received Top of RX FIFO = Next frame to be read from RX FIFO" "No_error,Error" bitfld.long 0x00 3. " FRAME_TOO_LONG_ERROR ,Read 0x1: Frame-length too long error in frame at top of RX FIFO" "No_error,Error" bitfld.long 0x00 2. " ABORT_DETECT ,Read 0x1: Abort pattern detected in frame at top of RX FIFO" "No_error,Error" textline " " bitfld.long 0x00 1. " CRC_ERROR ,Read 0x1: CRC error in frame at top of RX FIFO" "No_error,Error" wgroup.long 0x28++0x3 line.long 0x00 "UART_TXFLL,Transmit frame length register low" hexmask.long.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x00 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exi.." hexmask.long.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.long 0x2C++0x3 line.long 0x00 "UART_TXFLH,Transmit frame length register high" bitfld.long 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long 0x30++0x3 line.long 0x00 "UART_RXFLL,Received frame length register low" hexmask.long.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x00 "UART_SFREGL,Status FIFO register low" hexmask.long.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.long 0x34++0x3 line.long 0x00 "UART_RXFLH,Received frame length register high" bitfld.long 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x34++0x3 line.long 0x00 "UART_SFREGH,Status FIFO register high" bitfld.long 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "UART_BLR,BOF control register" bitfld.long 0x00 7. " STS_FIFO_RESET ,Status FIFO reset. This bit is self-clearing." "No_reset,Reset" bitfld.long 0x00 6. " XBOF_TYPE ,SIR xBOF select - . - ." "0xFF,0xC0" rgroup.long 0x38++0x3 line.long 0x00 "UART_UASR,UART autobauding status register" bitfld.long 0x00 6.--7. " PARITY_TYPE ,Read 0x0: No parity identified - . - . - ." "0,Parity_space,Even,Odd" bitfld.long 0x00 5. " BIT_BY_CHAR ,Read 0x0: 7-bit character identified - ." "0,8" bitfld.long 0x00 0.--4. " SPEED ,Used to report the speed identified - . - . - . - . - . - . - . - . - . - . - ." "No_speed,115_200,57_600,38_400,28_800,19_200,14_400,9_600,4_800,2_400,1_200,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3C++0x3 line.long 0x00 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." bitfld.long 0x00 7. " PULSE_TYPE ,SIR pulse width select - . - ." "3/16_of_baud-rate,1.6_us" bitfld.long 0x00 6. " SD_MOD ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. - . - ." "High,Low" bitfld.long 0x00 5. " DIS_IR_RX ,0x0: Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation) - ." "0,Yes" textline " " bitfld.long 0x00 4. " DIS_TX_UNDERRUN ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4] = 1, garbage data is sent over TX line. - . - ." "No,Yes" bitfld.long 0x00 3. " SEND_SIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end .." "No_action,Sent" bitfld.long 0x00 2. " SCTX_EN ,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit, the TX state-machine starts frame transmission. This bit is self-clearing." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ABORT_EN ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and MDR1[5] = 1, UART IrDA starts a new t.." "Disabled,Enabled" bitfld.long 0x00 0. " EOT_EN ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes t.." "Disabled,Enabled" group.long 0x40++0x3 line.long 0x00 "UART_SCR,Supplementary control register" bitfld.long 0x00 7. " RX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger RX level - ." "0,Enabled" bitfld.long 0x00 6. " TX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger TX level - ." "0,Enabled" bitfld.long 0x00 5. " DSR_IT ,0x0: Disables DSR* interrupt - ." "0,Enabled" textline " " bitfld.long 0x00 4. " RX_CTS_DSR_WAKE_UP_ENABLE ,0x0: Disables the wake-up interrupt and clears SSR[1] - ." "0,Enabled" bitfld.long 0x00 3. " TX_EMPTY_CTL_IT ,0x0: Normal mode for THR interrupt (see UART mode interrupts table) - ." "0,Interrupt" bitfld.long 0x00 1.--2. " DMA_MODE_2 ,Used to specify the DMA mode valid if theUART_SCR[0] bit = 1 - . - . - . - ." "No_DMA,UART_nDMA_REQ[0/1]_in_TX/RX;,UART_nDMA_REQ[0]_in_RX,UART_nDMA_REQ[0]_in_TX" textline " " bitfld.long 0x00 0. " DMA_MODE_CTL ,0x0: The DMA_MODE is set withUART_FCR[3]. - ." "0,UART_SCR[2:1]" group.long 0x44++0x3 line.long 0x00 "UART_SSR,Supplementary status register" bitfld.long 0x00 2. " DMA_COUNTER_RST ,0x0: The DMA counter will not be reset if the corresponding FIFO is reset (through FCR[1] or FCR[2]). - ." "0,Reset" bitfld.long 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Read 0x0: No falling edge event on RX, CTS*, and DSR* - ." "0,Occurred" bitfld.long 0x00 0. " TX_FIFO_FULL ,Read 0x0: TX FIFO is not full. - ." "0,Full" group.long 0x48++0x3 line.long 0x00 "UART_EBLR,BOF length register" hexmask.long.byte 0x00 0.--7. 1. " EBLR ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x00 "UART_MVR,Module version register" hexmask.long 0x00 0.--31. 1. " REV ,Revision number" group.long 0x54++0x3 line.long 0x00 "UART_SYSC,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,Power management req/ack control ref: OCP Design Guidelines Version 1.1 - . - . - . - ." "Force_idle,No-idle,Smart_idle,?..." bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0. - . - ." "No_reset,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy - . - ." "Running,Gated" rgroup.long 0x58++0x3 line.long 0x00 "UART_SYSS,System status register" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "Not_completed,Completed" group.long 0x5C++0x3 line.long 0x00 "UART_WER,Wake-up enable register" bitfld.long 0x00 7. " TX_WAKEUP_EN ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 6. " EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 5. " EVENT_5_RHR_INTERRUPT ,0x0: Event is not allowed to wake up the system. - ." "0,1" textline " " bitfld.long 0x00 4. " EVENT_4_RX_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 3. " EVENT_3_DCD_CD_ACTIVITY ,0x0: Event is not allowed to wake up the system - ." "0,1" bitfld.long 0x00 2. " EVENT_2_RI_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" textline " " bitfld.long 0x00 1. " EVENT_1_DSR_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 0. " EVENT_0_CTS_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" group.long 0x60++0x3 line.long 0x00 "UART_CFPS,Carrier frequency prescaler" hexmask.long.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple). Examples for CFPS values: - Target Freq (kHz) CFPS (decimal) Actual Freq (kHz) . - . - 30 133 30.08 . - . - 32.75 122 32.79 . - . - 36 111 36.04 . - . - 36.7 109 36.69 . - .." rgroup.long 0x64++0x3 line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Shows the number of received bytes in the RX FIFO" rgroup.long 0x68++0x3 line.long 0x00 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0x3 line.long 0x00 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x00 1. " EN_TXFIFO_EMPTY ,Enables TX FIFO empty corresponding interrupt - . - ." "Enabled,Disabled" bitfld.long 0x00 0. " EN_RXFIFO_EMPTY ,Enables RX FIFO empty corresponding interrupt - . - ." "Enabled,Disabled" group.long 0x70++0x3 line.long 0x00 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x00 1. " TXFIFO_EMPTY_STS ,Used to generate interrupt if the TX_FIFO is empty (software flow control) - . - ." "No_interrupt,Interrupt" bitfld.long 0x00 0. " RXFIFO_EMPTY_STS ,Used to generate interrupt if the RX_FIFO is empty (software flow control) - . - ." "No_interrupt,Interrupt" group.long 0x74++0x3 line.long 0x00 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if nondefault frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal to or higher then 6." group.long 0x80++0x3 line.long 0x00 "UART_MDR3,Mode definition register 3" bitfld.long 0x00 2. " SET_DMA_TX_THRESHOLD ,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register." "0,1" bitfld.long 0x00 1. " NONDEFAULT_FREQ ,Used to enable the NONDEFAULT fclk frequencies. - . - ." "0,1" bitfld.long 0x00 0. " DISABLE_CIR_RX_DEMOD ,Used to enable CIR RX demodulation. - . - ." "0,1" group.long 0x84++0x3 line.long 0x00 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register." bitfld.long 0x00 0.--5. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "UART2" base ad:0x4806C000 width 23. group.long 0x0++0x3 line.long 0x00 "UART_DLL,This register, with, stores the 14-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.byte 0x00 0.--7. 1. " CLOCK_LSB ,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved t.." hexmask.long.byte 0x00 0.--7. 1. " RHR ,Receive holding register" wgroup.long 0x0++0x3 line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The THR is a 64-byte FIFO. The local host (LH) writes data to the THR. The data is placed in the transmit shift register where it is shift.." hexmask.long.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.long 0x4++0x3 line.long 0x00 "UART_DLH,This register, with, stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." bitfld.long 0x00 0.--5. " CLOCK_MSB ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4++0x3 line.long 0x00 "UART_IER,Interrupt enable register" bitfld.long 0x00 7. " CTS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 6. " RTS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 5. " XOFF_IT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SLEEP_MODE ,- . - ." "Disabled,Enabled" bitfld.long 0x00 3. " MODEM_STS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 2. " LINE_STS_IT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " THR_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 0. " RHR_IT ,- . - ." "Disabled,Enabled" group.long 0x8++0x3 line.long 0x00 "UART_EFR,Enhanced feature register" bitfld.long 0x00 7. " AUTO_CTS_EN ,Auto-CTS enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " AUTO_RTS_EN ,Auto-RTS enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " SPECIAL_CHAR_DETECT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " ENHANCED_EN ,Enhanced functions write enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--3. " SW_FLOW_CONTROL ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See." "No_transmit/No_receive,No_transmit/Rx_comp._XON2;XOFF2,No_transmit/Rx_comp._XON1;XOFF1,No_transmit/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON2;XOFF2/No_receive,Tx_XON2;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON2;XOFF2/Rx_comp._XON1;XOFF1,Tx_XON2;XOFF2/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XOFF1/No_receive,Tx_XON1;XOFF1/Rx_comp._XON2;XOFF2,Tx_XON1;XOFF1/Rx_comp._XON1;XOFF1,Tx_XON1;XOFF1/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/No_receive,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON1;XOFF1,Tx/Rx_comp._XON1;XON2:XOFF1;XOFF2" wgroup.long 0x8++0x3 line.long 0x00 "UART_FCR,FIFO control register" bitfld.long 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If UART_SCR[7] = 0 and UART_TLR[7:4] != 0000, RX_FIFO_TRIG is not co.." "8,16,56,60" bitfld.long 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If UART_SCR[6] = 0 and UART_TLR[3:0] != 0000, TX_FIFO_T.." "8,16,32,56" bitfld.long 0x00 3. " DMA_MODE ,This register is considered ifUART_SCR[0] = 0. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TX_FIFO_CLEAR ,- . - ." "No_effect,Clear" bitfld.long 0x00 1. " RX_FIFO_CLEAR ,- . - ." "No_effect,Clear" bitfld.long 0x00 0. " FIFO_EN ,- . - ." "Disabled,Enabled" rgroup.long 0x8++0x3 line.long 0x00 "UART_IIR,Interrupt identification register." bitfld.long 0x00 6.--7. " FCR_MIRROR ,Mirror the contents ofUART_FCR[0] on both bits." "0,1,2,3" bitfld.long 0x00 1.--5. " IT_TYPE ,Read 0x0: Modem interrupt. Priority = 4 - . - . - . - . - . - ." "0,THR,RHR,Receiver_line_status_error,4,5,Rx_time-out,7,XOFF/special_character,9,10,11,12,13,14,15,CTS/RTS/DSR_change,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " IT_PENDING ,Read 0x0: An interrupt is pending. - ." "0,Not_pending" group.long 0xC++0x3 line.long 0x00 "UART_LCR,Line control register" bitfld.long 0x00 7. " DIV_EN ,- . - ." "Disabled,Enabled" bitfld.long 0x00 6. " BREAK_EN ,Break control bit - . - ." "Normal,Forced_low" bitfld.long 0x00 5. " PARITY_TYPE2 ,Selects the forced parity format (ifUART_LCR[3] = 1). If UART_LCR[5] = 1 and UART_LCR[4] = 0, the parity bit is forced to 1 in the transmitted and received data. If UART_LCR[5] = 1 and UART_LCR.." "No_parity,Odd_parity" textline " " bitfld.long 0x00 4. " PARITY_TYPE1 ,- . - ." "0,1" bitfld.long 0x00 3. " PARITY_EN ,0x0: No parity - ." "0,1" bitfld.long 0x00 2. " NB_STOP ,Specifies the number of stop-bits - . - ." "1,1.5" textline " " bitfld.long 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received - . - . - . - ." "5,6,7,8" group.long 0x10++0x3 line.long 0x00 "UART_MCR,Modem control register" bitfld.long 0x00 6. " TCR_TLR ,0x0: No action - ." "0,Enabled" bitfld.long 0x00 5. " XON_EN ,0x0: Disable XON any function. - ." "0,Enabled" bitfld.long 0x00 4. " LOOPBACK_EN ,0x0: Normal operating mode - ." "0,Enabled" textline " " bitfld.long 0x00 3. " CD_STS_CH ,0x0: In loopback, forces DCD* input high and IRQ outputs to inactive state - ." "0,Low" bitfld.long 0x00 2. " RI_STS_CH ,0x0: In loopback, forces RI* input high - ." "0,Low" bitfld.long 0x00 1. " RTS ,In loopback, controls theUART_MSR[4] bit. If auto-RTS is enabled, the RTS* output is controlled by hardware flow control. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DTR ,0x0: Force DTR* output to inactive (high). - ." "0,Enabled" group.long 0x10++0x3 line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address" hexmask.long.byte 0x00 0.--7. 1. " XON_WORD1 ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x00 "UART_LSR,Line status register" bitfld.long 0x00 7. " RX_FIFO_STS ,Read 0x0: Normal operation - ." "0,Error" bitfld.long 0x00 6. " TX_SR_E ,Read 0x0: Transmitter hold (TX FIFO) and shift registers are not empty. - ." "0,Empty" bitfld.long 0x00 5. " TX_FIFO_E ,Read 0x0: Transmit hold register (TX FIFO) is not empty. - ." "0,Empty" textline " " bitfld.long 0x00 4. " RX_BI ,Read 0x0: No break condition - ." "0,Detected" bitfld.long 0x00 3. " RX_FE ,Read 0x0: No framing error in data RX FIFO - ." "0,Error" bitfld.long 0x00 2. " RX_PE ,Read 0x0: No parity error in data from RX FIFO - ." "0,Error" textline " " bitfld.long 0x00 1. " RX_OE ,Read 0x0: No overrun error - ." "0,Error" bitfld.long 0x00 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO - ." "0,One_data" group.long 0x14++0x3 line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.byte 0x00 0.--7. 1. " XON_WORD2 ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x00 "UART_MSR,Modem status register. UART mode only." bitfld.long 0x00 7. " NCD_STS ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent toUART_MCR[3]." "0,1" bitfld.long 0x00 6. " NRI_STS ,This bit is the complement of the RI* input. In loopback mode, it is equivalent toUART_MCR[2]." "0,1" bitfld.long 0x00 5. " NDSR_STS ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent toUART_MCR[0]." "0,1" textline " " bitfld.long 0x00 4. " NCTS_STS ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent toUART_MCR[1]." "0,1" bitfld.long 0x00 3. " DCD_STS ,Indicates that DCD* input (orUART_MCR[3] in loopback) changed. Cleared on a read." "0,1" bitfld.long 0x00 2. " RI_STS ,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high. Cleared on a read." "0,1" textline " " bitfld.long 0x00 1. " DSR_STS ,- ." "0,1" bitfld.long 0x00 0. " CTS_STS ,- ." "0,1" group.long 0x18++0x3 line.long 0x00 "UART_TCR,Transmission control register" bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_START ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.long 0x00 0.--3. " RX_FIFO_TRIG_HALT ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.long 0x18++0x3 line.long 0x00 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD1 ,Stores the 8-bit XOFF1 character used in UART modes" group.long 0x1C++0x3 line.long 0x00 "UART_SPR,Scratchpad register" hexmask.long.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" group.long 0x1C++0x3 line.long 0x00 "UART_TLR,Trigger level register" bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD2 ,Stores the 8-bit XOFF2 character used in UART modes." group.long 0x20++0x3 line.long 0x00 "UART_MDR1,Mode definition register 1" bitfld.long 0x00 7. " FRAME_END_MODE ,IrDA mode only - . - ." "Frame-length,EOT" bitfld.long 0x00 6. " SIP_MODE ,MIR/FIR modes only - . - ." "Manual_SIP,Automatic_SIP" bitfld.long 0x00 5. " SCT ,Store and control the transmission. - . - ." "THR,ACREG[2]" textline " " bitfld.long 0x00 4. " SET_TXIR ,Used to configure the infrared transceiver - . - ." "TXIR_low,IRTX_high" bitfld.long 0x00 3. " IR_SLEEP ,0x0: IrDA/CIR sleep mode disabled - ." "0,Enabled" bitfld.long 0x00 0.--2. " MODE_SELECT ,0x0: UART 16x mode - . - . - . - . - . - . - ." "0,Reserved,UART_16x_auto-baud,UART_13x,Reserved,Reserved,Reserved,Disabled" group.long 0x24++0x3 line.long 0x00 "UART_MDR2,Mode definition register 2" bitfld.long 0x00 7. " SET_TXIR_ALT ,Provide alternate function for MDR1[4] (SET_TXIR). - . - ." "Normal,Alternate" bitfld.long 0x00 6. " IRRXINVERT ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes. - . - ." "Inversion_is_performed.,1" bitfld.long 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit: - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 3. " UART_PULSE ,UART mode only. Allows pulse shaping in UART mode. - . - ." "Normal_UART_mode,1" bitfld.long 0x00 1.--2. " STS_FIFO_TRIG ,IR-IrDA mode only. Frame status FIFO threshold select: - . - . - . - ." "1_entry,4_entries,7_entries,8_entries" bitfld.long 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt. When theUART_IIR[5] interrupt occurs, the meaning of the interrupt is: - . - ." "0,1" rgroup.long 0x28++0x3 line.long 0x00 "UART_SFLSR,Status FIFO line status register" bitfld.long 0x00 4. " OE_ERROR ,Read 0x1: Overrun error in RX FIFO when frame at top of RX FIFO was received Top of RX FIFO = Next frame to be read from RX FIFO" "No_error,Error" bitfld.long 0x00 3. " FRAME_TOO_LONG_ERROR ,Read 0x1: Frame-length too long error in frame at top of RX FIFO" "No_error,Error" bitfld.long 0x00 2. " ABORT_DETECT ,Read 0x1: Abort pattern detected in frame at top of RX FIFO" "No_error,Error" textline " " bitfld.long 0x00 1. " CRC_ERROR ,Read 0x1: CRC error in frame at top of RX FIFO" "No_error,Error" wgroup.long 0x28++0x3 line.long 0x00 "UART_TXFLL,Transmit frame length register low" hexmask.long.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x00 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exi.." hexmask.long.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.long 0x2C++0x3 line.long 0x00 "UART_TXFLH,Transmit frame length register high" bitfld.long 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long 0x30++0x3 line.long 0x00 "UART_RXFLL,Received frame length register low" hexmask.long.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x00 "UART_SFREGL,Status FIFO register low" hexmask.long.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.long 0x34++0x3 line.long 0x00 "UART_RXFLH,Received frame length register high" bitfld.long 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x34++0x3 line.long 0x00 "UART_SFREGH,Status FIFO register high" bitfld.long 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "UART_BLR,BOF control register" bitfld.long 0x00 7. " STS_FIFO_RESET ,Status FIFO reset. This bit is self-clearing." "No_reset,Reset" bitfld.long 0x00 6. " XBOF_TYPE ,SIR xBOF select - . - ." "0xFF,0xC0" rgroup.long 0x38++0x3 line.long 0x00 "UART_UASR,UART autobauding status register" bitfld.long 0x00 6.--7. " PARITY_TYPE ,Read 0x0: No parity identified - . - . - ." "0,Parity_space,Even,Odd" bitfld.long 0x00 5. " BIT_BY_CHAR ,Read 0x0: 7-bit character identified - ." "0,8" bitfld.long 0x00 0.--4. " SPEED ,Used to report the speed identified - . - . - . - . - . - . - . - . - . - . - ." "No_speed,115_200,57_600,38_400,28_800,19_200,14_400,9_600,4_800,2_400,1_200,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3C++0x3 line.long 0x00 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." bitfld.long 0x00 7. " PULSE_TYPE ,SIR pulse width select - . - ." "3/16_of_baud-rate,1.6_us" bitfld.long 0x00 6. " SD_MOD ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. - . - ." "High,Low" bitfld.long 0x00 5. " DIS_IR_RX ,0x0: Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation) - ." "0,Yes" textline " " bitfld.long 0x00 4. " DIS_TX_UNDERRUN ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4] = 1, garbage data is sent over TX line. - . - ." "No,Yes" bitfld.long 0x00 3. " SEND_SIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end .." "No_action,Sent" bitfld.long 0x00 2. " SCTX_EN ,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit, the TX state-machine starts frame transmission. This bit is self-clearing." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ABORT_EN ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and MDR1[5] = 1, UART IrDA starts a new t.." "Disabled,Enabled" bitfld.long 0x00 0. " EOT_EN ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes t.." "Disabled,Enabled" group.long 0x40++0x3 line.long 0x00 "UART_SCR,Supplementary control register" bitfld.long 0x00 7. " RX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger RX level - ." "0,Enabled" bitfld.long 0x00 6. " TX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger TX level - ." "0,Enabled" bitfld.long 0x00 5. " DSR_IT ,0x0: Disables DSR* interrupt - ." "0,Enabled" textline " " bitfld.long 0x00 4. " RX_CTS_DSR_WAKE_UP_ENABLE ,0x0: Disables the wake-up interrupt and clears SSR[1] - ." "0,Enabled" bitfld.long 0x00 3. " TX_EMPTY_CTL_IT ,0x0: Normal mode for THR interrupt (see UART mode interrupts table) - ." "0,Interrupt" bitfld.long 0x00 1.--2. " DMA_MODE_2 ,Used to specify the DMA mode valid if theUART_SCR[0] bit = 1 - . - . - . - ." "No_DMA,UART_nDMA_REQ[0/1]_in_TX/RX;,UART_nDMA_REQ[0]_in_RX,UART_nDMA_REQ[0]_in_TX" textline " " bitfld.long 0x00 0. " DMA_MODE_CTL ,0x0: The DMA_MODE is set withUART_FCR[3]. - ." "0,UART_SCR[2:1]" group.long 0x44++0x3 line.long 0x00 "UART_SSR,Supplementary status register" bitfld.long 0x00 2. " DMA_COUNTER_RST ,0x0: The DMA counter will not be reset if the corresponding FIFO is reset (through FCR[1] or FCR[2]). - ." "0,Reset" bitfld.long 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Read 0x0: No falling edge event on RX, CTS*, and DSR* - ." "0,Occurred" bitfld.long 0x00 0. " TX_FIFO_FULL ,Read 0x0: TX FIFO is not full. - ." "0,Full" group.long 0x48++0x3 line.long 0x00 "UART_EBLR,BOF length register" hexmask.long.byte 0x00 0.--7. 1. " EBLR ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x00 "UART_MVR,Module version register" hexmask.long 0x00 0.--31. 1. " REV ,Revision number" group.long 0x54++0x3 line.long 0x00 "UART_SYSC,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,Power management req/ack control ref: OCP Design Guidelines Version 1.1 - . - . - . - ." "Force_idle,No-idle,Smart_idle,?..." bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0. - . - ." "No_reset,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy - . - ." "Running,Gated" rgroup.long 0x58++0x3 line.long 0x00 "UART_SYSS,System status register" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "Not_completed,Completed" group.long 0x5C++0x3 line.long 0x00 "UART_WER,Wake-up enable register" bitfld.long 0x00 7. " TX_WAKEUP_EN ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 6. " EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 5. " EVENT_5_RHR_INTERRUPT ,0x0: Event is not allowed to wake up the system. - ." "0,1" textline " " bitfld.long 0x00 4. " EVENT_4_RX_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 3. " EVENT_3_DCD_CD_ACTIVITY ,0x0: Event is not allowed to wake up the system - ." "0,1" bitfld.long 0x00 2. " EVENT_2_RI_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" textline " " bitfld.long 0x00 1. " EVENT_1_DSR_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 0. " EVENT_0_CTS_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" group.long 0x60++0x3 line.long 0x00 "UART_CFPS,Carrier frequency prescaler" hexmask.long.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple). Examples for CFPS values: - Target Freq (kHz) CFPS (decimal) Actual Freq (kHz) . - . - 30 133 30.08 . - . - 32.75 122 32.79 . - . - 36 111 36.04 . - . - 36.7 109 36.69 . - .." rgroup.long 0x64++0x3 line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Shows the number of received bytes in the RX FIFO" rgroup.long 0x68++0x3 line.long 0x00 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0x3 line.long 0x00 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x00 1. " EN_TXFIFO_EMPTY ,Enables TX FIFO empty corresponding interrupt - . - ." "Enabled,Disabled" bitfld.long 0x00 0. " EN_RXFIFO_EMPTY ,Enables RX FIFO empty corresponding interrupt - . - ." "Enabled,Disabled" group.long 0x70++0x3 line.long 0x00 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x00 1. " TXFIFO_EMPTY_STS ,Used to generate interrupt if the TX_FIFO is empty (software flow control) - . - ." "No_interrupt,Interrupt" bitfld.long 0x00 0. " RXFIFO_EMPTY_STS ,Used to generate interrupt if the RX_FIFO is empty (software flow control) - . - ." "No_interrupt,Interrupt" group.long 0x74++0x3 line.long 0x00 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if nondefault frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal to or higher then 6." group.long 0x80++0x3 line.long 0x00 "UART_MDR3,Mode definition register 3" bitfld.long 0x00 2. " SET_DMA_TX_THRESHOLD ,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register." "0,1" bitfld.long 0x00 1. " NONDEFAULT_FREQ ,Used to enable the NONDEFAULT fclk frequencies. - . - ." "0,1" bitfld.long 0x00 0. " DISABLE_CIR_RX_DEMOD ,Used to enable CIR RX demodulation. - . - ." "0,1" group.long 0x84++0x3 line.long 0x00 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register." bitfld.long 0x00 0.--5. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "UART4" base ad:0x4806E000 width 23. group.long 0x0++0x3 line.long 0x00 "UART_DLL,This register, with, stores the 14-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.byte 0x00 0.--7. 1. " CLOCK_LSB ,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved t.." hexmask.long.byte 0x00 0.--7. 1. " RHR ,Receive holding register" wgroup.long 0x0++0x3 line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The THR is a 64-byte FIFO. The local host (LH) writes data to the THR. The data is placed in the transmit shift register where it is shift.." hexmask.long.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.long 0x4++0x3 line.long 0x00 "UART_DLH,This register, with, stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." bitfld.long 0x00 0.--5. " CLOCK_MSB ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4++0x3 line.long 0x00 "UART_IER,Interrupt enable register" bitfld.long 0x00 7. " CTS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 6. " RTS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 5. " XOFF_IT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SLEEP_MODE ,- . - ." "Disabled,Enabled" bitfld.long 0x00 3. " MODEM_STS_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 2. " LINE_STS_IT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " THR_IT ,- . - ." "Disabled,Enabled" bitfld.long 0x00 0. " RHR_IT ,- . - ." "Disabled,Enabled" group.long 0x8++0x3 line.long 0x00 "UART_EFR,Enhanced feature register" bitfld.long 0x00 7. " AUTO_CTS_EN ,Auto-CTS enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 6. " AUTO_RTS_EN ,Auto-RTS enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 5. " SPECIAL_CHAR_DETECT ,- . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " ENHANCED_EN ,Enhanced functions write enable bit - . - ." "Disabled,Enabled" bitfld.long 0x00 0.--3. " SW_FLOW_CONTROL ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See." "No_transmit/No_receive,No_transmit/Rx_comp._XON2;XOFF2,No_transmit/Rx_comp._XON1;XOFF1,No_transmit/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON2;XOFF2/No_receive,Tx_XON2;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON2;XOFF2/Rx_comp._XON1;XOFF1,Tx_XON2;XOFF2/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XOFF1/No_receive,Tx_XON1;XOFF1/Rx_comp._XON2;XOFF2,Tx_XON1;XOFF1/Rx_comp._XON1;XOFF1,Tx_XON1;XOFF1/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/No_receive,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON1;XOFF1,Tx/Rx_comp._XON1;XON2:XOFF1;XOFF2" wgroup.long 0x8++0x3 line.long 0x00 "UART_FCR,FIFO control register" bitfld.long 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If UART_SCR[7] = 0 and UART_TLR[7:4] != 0000, RX_FIFO_TRIG is not co.." "8,16,56,60" bitfld.long 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If UART_SCR[6] = 0 and UART_TLR[3:0] != 0000, TX_FIFO_T.." "8,16,32,56" bitfld.long 0x00 3. " DMA_MODE ,This register is considered ifUART_SCR[0] = 0. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TX_FIFO_CLEAR ,- . - ." "No_effect,Clear" bitfld.long 0x00 1. " RX_FIFO_CLEAR ,- . - ." "No_effect,Clear" bitfld.long 0x00 0. " FIFO_EN ,- . - ." "Disabled,Enabled" rgroup.long 0x8++0x3 line.long 0x00 "UART_IIR,Interrupt identification register." bitfld.long 0x00 6.--7. " FCR_MIRROR ,Mirror the contents ofUART_FCR[0] on both bits." "0,1,2,3" bitfld.long 0x00 1.--5. " IT_TYPE ,Read 0x0: Modem interrupt. Priority = 4 - . - . - . - . - . - ." "0,THR,RHR,Receiver_line_status_error,4,5,Rx_time-out,7,XOFF/special_character,9,10,11,12,13,14,15,CTS/RTS/DSR_change,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " IT_PENDING ,Read 0x0: An interrupt is pending. - ." "0,Not_pending" group.long 0xC++0x3 line.long 0x00 "UART_LCR,Line control register" bitfld.long 0x00 7. " DIV_EN ,- . - ." "Disabled,Enabled" bitfld.long 0x00 6. " BREAK_EN ,Break control bit - . - ." "Normal,Forced_low" bitfld.long 0x00 5. " PARITY_TYPE2 ,Selects the forced parity format (ifUART_LCR[3] = 1). If UART_LCR[5] = 1 and UART_LCR[4] = 0, the parity bit is forced to 1 in the transmitted and received data. If UART_LCR[5] = 1 and UART_LCR.." "No_parity,Odd_parity" textline " " bitfld.long 0x00 4. " PARITY_TYPE1 ,- . - ." "0,1" bitfld.long 0x00 3. " PARITY_EN ,0x0: No parity - ." "0,1" bitfld.long 0x00 2. " NB_STOP ,Specifies the number of stop-bits - . - ." "1,1.5" textline " " bitfld.long 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received - . - . - . - ." "5,6,7,8" group.long 0x10++0x3 line.long 0x00 "UART_MCR,Modem control register" bitfld.long 0x00 6. " TCR_TLR ,0x0: No action - ." "0,Enabled" bitfld.long 0x00 5. " XON_EN ,0x0: Disable XON any function. - ." "0,Enabled" bitfld.long 0x00 4. " LOOPBACK_EN ,0x0: Normal operating mode - ." "0,Enabled" textline " " bitfld.long 0x00 3. " CD_STS_CH ,0x0: In loopback, forces DCD* input high and IRQ outputs to inactive state - ." "0,Low" bitfld.long 0x00 2. " RI_STS_CH ,0x0: In loopback, forces RI* input high - ." "0,Low" bitfld.long 0x00 1. " RTS ,In loopback, controls theUART_MSR[4] bit. If auto-RTS is enabled, the RTS* output is controlled by hardware flow control. - . - ." "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DTR ,0x0: Force DTR* output to inactive (high). - ." "0,Enabled" group.long 0x10++0x3 line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address" hexmask.long.byte 0x00 0.--7. 1. " XON_WORD1 ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x00 "UART_LSR,Line status register" bitfld.long 0x00 7. " RX_FIFO_STS ,Read 0x0: Normal operation - ." "0,Error" bitfld.long 0x00 6. " TX_SR_E ,Read 0x0: Transmitter hold (TX FIFO) and shift registers are not empty. - ." "0,Empty" bitfld.long 0x00 5. " TX_FIFO_E ,Read 0x0: Transmit hold register (TX FIFO) is not empty. - ." "0,Empty" textline " " bitfld.long 0x00 4. " RX_BI ,Read 0x0: No break condition - ." "0,Detected" bitfld.long 0x00 3. " RX_FE ,Read 0x0: No framing error in data RX FIFO - ." "0,Error" bitfld.long 0x00 2. " RX_PE ,Read 0x0: No parity error in data from RX FIFO - ." "0,Error" textline " " bitfld.long 0x00 1. " RX_OE ,Read 0x0: No overrun error - ." "0,Error" bitfld.long 0x00 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO - ." "0,One_data" group.long 0x14++0x3 line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.byte 0x00 0.--7. 1. " XON_WORD2 ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x00 "UART_MSR,Modem status register. UART mode only." bitfld.long 0x00 7. " NCD_STS ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent toUART_MCR[3]." "0,1" bitfld.long 0x00 6. " NRI_STS ,This bit is the complement of the RI* input. In loopback mode, it is equivalent toUART_MCR[2]." "0,1" bitfld.long 0x00 5. " NDSR_STS ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent toUART_MCR[0]." "0,1" textline " " bitfld.long 0x00 4. " NCTS_STS ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent toUART_MCR[1]." "0,1" bitfld.long 0x00 3. " DCD_STS ,Indicates that DCD* input (orUART_MCR[3] in loopback) changed. Cleared on a read." "0,1" bitfld.long 0x00 2. " RI_STS ,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high. Cleared on a read." "0,1" textline " " bitfld.long 0x00 1. " DSR_STS ,- ." "0,1" bitfld.long 0x00 0. " CTS_STS ,- ." "0,1" group.long 0x18++0x3 line.long 0x00 "UART_TCR,Transmission control register" bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_START ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.long 0x00 0.--3. " RX_FIFO_TRIG_HALT ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.long 0x18++0x3 line.long 0x00 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD1 ,Stores the 8-bit XOFF1 character used in UART modes" group.long 0x1C++0x3 line.long 0x00 "UART_SPR,Scratchpad register" hexmask.long.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" group.long 0x1C++0x3 line.long 0x00 "UART_TLR,Trigger level register" bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD2 ,Stores the 8-bit XOFF2 character used in UART modes." group.long 0x20++0x3 line.long 0x00 "UART_MDR1,Mode definition register 1" bitfld.long 0x00 7. " FRAME_END_MODE ,IrDA mode only - . - ." "Frame-length,EOT" bitfld.long 0x00 6. " SIP_MODE ,MIR/FIR modes only - . - ." "Manual_SIP,Automatic_SIP" bitfld.long 0x00 5. " SCT ,Store and control the transmission. - . - ." "THR,ACREG[2]" textline " " bitfld.long 0x00 4. " SET_TXIR ,Used to configure the infrared transceiver - . - ." "TXIR_low,IRTX_high" bitfld.long 0x00 3. " IR_SLEEP ,0x0: IrDA/CIR sleep mode disabled - ." "0,Enabled" bitfld.long 0x00 0.--2. " MODE_SELECT ,0x0: UART 16x mode - . - . - . - . - . - . - ." "0,Reserved,UART_16x_auto-baud,UART_13x,Reserved,Reserved,Reserved,Disabled" group.long 0x24++0x3 line.long 0x00 "UART_MDR2,Mode definition register 2" bitfld.long 0x00 7. " SET_TXIR_ALT ,Provide alternate function for MDR1[4] (SET_TXIR). - . - ." "Normal,Alternate" bitfld.long 0x00 6. " IRRXINVERT ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes. - . - ." "Inversion_is_performed.,1" bitfld.long 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit: - . - . - . - ." "0,1,2,3" textline " " bitfld.long 0x00 3. " UART_PULSE ,UART mode only. Allows pulse shaping in UART mode. - . - ." "Normal_UART_mode,1" bitfld.long 0x00 1.--2. " STS_FIFO_TRIG ,IR-IrDA mode only. Frame status FIFO threshold select: - . - . - . - ." "1_entry,4_entries,7_entries,8_entries" bitfld.long 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt. When theUART_IIR[5] interrupt occurs, the meaning of the interrupt is: - . - ." "0,1" rgroup.long 0x28++0x3 line.long 0x00 "UART_SFLSR,Status FIFO line status register" bitfld.long 0x00 4. " OE_ERROR ,Read 0x1: Overrun error in RX FIFO when frame at top of RX FIFO was received Top of RX FIFO = Next frame to be read from RX FIFO" "No_error,Error" bitfld.long 0x00 3. " FRAME_TOO_LONG_ERROR ,Read 0x1: Frame-length too long error in frame at top of RX FIFO" "No_error,Error" bitfld.long 0x00 2. " ABORT_DETECT ,Read 0x1: Abort pattern detected in frame at top of RX FIFO" "No_error,Error" textline " " bitfld.long 0x00 1. " CRC_ERROR ,Read 0x1: CRC error in frame at top of RX FIFO" "No_error,Error" wgroup.long 0x28++0x3 line.long 0x00 "UART_TXFLL,Transmit frame length register low" hexmask.long.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x00 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exi.." hexmask.long.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.long 0x2C++0x3 line.long 0x00 "UART_TXFLH,Transmit frame length register high" bitfld.long 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long 0x30++0x3 line.long 0x00 "UART_RXFLL,Received frame length register low" hexmask.long.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x00 "UART_SFREGL,Status FIFO register low" hexmask.long.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.long 0x34++0x3 line.long 0x00 "UART_RXFLH,Received frame length register high" bitfld.long 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x34++0x3 line.long 0x00 "UART_SFREGH,Status FIFO register high" bitfld.long 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "UART_BLR,BOF control register" bitfld.long 0x00 7. " STS_FIFO_RESET ,Status FIFO reset. This bit is self-clearing." "No_reset,Reset" bitfld.long 0x00 6. " XBOF_TYPE ,SIR xBOF select - . - ." "0xFF,0xC0" rgroup.long 0x38++0x3 line.long 0x00 "UART_UASR,UART autobauding status register" bitfld.long 0x00 6.--7. " PARITY_TYPE ,Read 0x0: No parity identified - . - . - ." "0,Parity_space,Even,Odd" bitfld.long 0x00 5. " BIT_BY_CHAR ,Read 0x0: 7-bit character identified - ." "0,8" bitfld.long 0x00 0.--4. " SPEED ,Used to report the speed identified - . - . - . - . - . - . - . - . - . - . - ." "No_speed,115_200,57_600,38_400,28_800,19_200,14_400,9_600,4_800,2_400,1_200,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3C++0x3 line.long 0x00 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." bitfld.long 0x00 7. " PULSE_TYPE ,SIR pulse width select - . - ." "3/16_of_baud-rate,1.6_us" bitfld.long 0x00 6. " SD_MOD ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. - . - ." "High,Low" bitfld.long 0x00 5. " DIS_IR_RX ,0x0: Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation) - ." "0,Yes" textline " " bitfld.long 0x00 4. " DIS_TX_UNDERRUN ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4] = 1, garbage data is sent over TX line. - . - ." "No,Yes" bitfld.long 0x00 3. " SEND_SIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end .." "No_action,Sent" bitfld.long 0x00 2. " SCTX_EN ,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit, the TX state-machine starts frame transmission. This bit is self-clearing." "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ABORT_EN ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and MDR1[5] = 1, UART IrDA starts a new t.." "Disabled,Enabled" bitfld.long 0x00 0. " EOT_EN ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes t.." "Disabled,Enabled" group.long 0x40++0x3 line.long 0x00 "UART_SCR,Supplementary control register" bitfld.long 0x00 7. " RX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger RX level - ." "0,Enabled" bitfld.long 0x00 6. " TX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger TX level - ." "0,Enabled" bitfld.long 0x00 5. " DSR_IT ,0x0: Disables DSR* interrupt - ." "0,Enabled" textline " " bitfld.long 0x00 4. " RX_CTS_DSR_WAKE_UP_ENABLE ,0x0: Disables the wake-up interrupt and clears SSR[1] - ." "0,Enabled" bitfld.long 0x00 3. " TX_EMPTY_CTL_IT ,0x0: Normal mode for THR interrupt (see UART mode interrupts table) - ." "0,Interrupt" bitfld.long 0x00 1.--2. " DMA_MODE_2 ,Used to specify the DMA mode valid if theUART_SCR[0] bit = 1 - . - . - . - ." "No_DMA,UART_nDMA_REQ[0/1]_in_TX/RX;,UART_nDMA_REQ[0]_in_RX,UART_nDMA_REQ[0]_in_TX" textline " " bitfld.long 0x00 0. " DMA_MODE_CTL ,0x0: The DMA_MODE is set withUART_FCR[3]. - ." "0,UART_SCR[2:1]" group.long 0x44++0x3 line.long 0x00 "UART_SSR,Supplementary status register" bitfld.long 0x00 2. " DMA_COUNTER_RST ,0x0: The DMA counter will not be reset if the corresponding FIFO is reset (through FCR[1] or FCR[2]). - ." "0,Reset" bitfld.long 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Read 0x0: No falling edge event on RX, CTS*, and DSR* - ." "0,Occurred" bitfld.long 0x00 0. " TX_FIFO_FULL ,Read 0x0: TX FIFO is not full. - ." "0,Full" group.long 0x48++0x3 line.long 0x00 "UART_EBLR,BOF length register" hexmask.long.byte 0x00 0.--7. 1. " EBLR ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x00 "UART_MVR,Module version register" hexmask.long 0x00 0.--31. 1. " REV ,Revision number" group.long 0x54++0x3 line.long 0x00 "UART_SYSC,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,Power management req/ack control ref: OCP Design Guidelines Version 1.1 - . - . - . - ." "Force_idle,No-idle,Smart_idle,?..." bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0. - . - ." "No_reset,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy - . - ." "Running,Gated" rgroup.long 0x58++0x3 line.long 0x00 "UART_SYSS,System status register" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "Not_completed,Completed" group.long 0x5C++0x3 line.long 0x00 "UART_WER,Wake-up enable register" bitfld.long 0x00 7. " TX_WAKEUP_EN ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 6. " EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 5. " EVENT_5_RHR_INTERRUPT ,0x0: Event is not allowed to wake up the system. - ." "0,1" textline " " bitfld.long 0x00 4. " EVENT_4_RX_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 3. " EVENT_3_DCD_CD_ACTIVITY ,0x0: Event is not allowed to wake up the system - ." "0,1" bitfld.long 0x00 2. " EVENT_2_RI_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" textline " " bitfld.long 0x00 1. " EVENT_1_DSR_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" bitfld.long 0x00 0. " EVENT_0_CTS_ACTIVITY ,0x0: Event is not allowed to wake up the system. - ." "0,1" group.long 0x60++0x3 line.long 0x00 "UART_CFPS,Carrier frequency prescaler" hexmask.long.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple). Examples for CFPS values: - Target Freq (kHz) CFPS (decimal) Actual Freq (kHz) . - . - 30 133 30.08 . - . - 32.75 122 32.79 . - . - 36 111 36.04 . - . - 36.7 109 36.69 . - .." rgroup.long 0x64++0x3 line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Shows the number of received bytes in the RX FIFO" rgroup.long 0x68++0x3 line.long 0x00 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0x3 line.long 0x00 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x00 1. " EN_TXFIFO_EMPTY ,Enables TX FIFO empty corresponding interrupt - . - ." "Enabled,Disabled" bitfld.long 0x00 0. " EN_RXFIFO_EMPTY ,Enables RX FIFO empty corresponding interrupt - . - ." "Enabled,Disabled" group.long 0x70++0x3 line.long 0x00 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x00 1. " TXFIFO_EMPTY_STS ,Used to generate interrupt if the TX_FIFO is empty (software flow control) - . - ." "No_interrupt,Interrupt" bitfld.long 0x00 0. " RXFIFO_EMPTY_STS ,Used to generate interrupt if the RX_FIFO is empty (software flow control) - . - ." "No_interrupt,Interrupt" group.long 0x74++0x3 line.long 0x00 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if nondefault frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal to or higher then 6." group.long 0x80++0x3 line.long 0x00 "UART_MDR3,Mode definition register 3" bitfld.long 0x00 2. " SET_DMA_TX_THRESHOLD ,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register." "0,1" bitfld.long 0x00 1. " NONDEFAULT_FREQ ,Used to enable the NONDEFAULT fclk frequencies. - . - ." "0,1" bitfld.long 0x00 0. " DISABLE_CIR_RX_DEMOD ,Used to enable CIR RX demodulation. - . - ." "0,1" group.long 0x84++0x3 line.long 0x00 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register." bitfld.long 0x00 0.--5. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree.end tree.end tree.open "Multichannel_Serial_Port_Interface" tree "MCSPI1" base ad:0x48098000 tree "Channel_0" width 17. group.long 0x12C++0x3 line.long 0x00 "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock d.." "0,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set. - . - ." "0,1" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set. - . - ." "0,1" textline " " bitfld.long 0x00 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock. - . - . - . - ." "0.5_clock_cycle,1.5_clock_cycles,2.5_clock_cycles,3.5_clock_cycles" bitfld.long 0x00 24. " SBPOL ,Start-bit polarity - . - ." "0,1" bitfld.long 0x00 23. " SBE ,Start-bit enable for SPI transfer - . - ." "0,1" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only). - . - ." "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode - . - ." "0,1" textline " " bitfld.long 0x00 18. " IS ,Input Select - . - ." "0,1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1]) - . - ." "0,1" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0]) - . - ." "0,1" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the .." "0,1" bitfld.long 0x00 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter registe.." "0,1" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes - . - . - . - ." "Transmit-and-receive_mode,Receive-only_mode,Transmit-only_mode,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " EPOL ,SPIEN polarity - . - ." "0,1" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data.." "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity - . - ." "0,1" bitfld.long 0x00 0. " PHA ,SPICLK phase - . - ." "0,1" group.long 0x134++0x3 line.long 0x00 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel 0." hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio. .." bitfld.long 0x00 0. " EN ,Channel enable - . - ." "0,1" rgroup.long 0x130++0x3 line.long 0x00 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x00 6. " RXFFF ,Channel 'i' FIFO receive buffer full status - . - ." "0,1" bitfld.long 0x00 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status - . - ." "0,1" bitfld.long 0x00 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status - . - ." "0,1" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status - . - ." "0,1" bitfld.long 0x00 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. - . - ." "0,1" bitfld.long 0x00 1. " TXS ,Channel 'i' transmitter register status - . - ." "Register_is_full.,Register_is_empty." textline " " bitfld.long 0x00 0. " RXS ,Channel 'i' receiver register status - . - ." "Register_is_empty.,Register_is_full." rgroup.long 0x13C++0x3 line.long 0x00 "MCSPI_RXx_0,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " RDATA ,Channel 0 received data" group.long 0x138++0x3 line.long 0x00 "MCSPI_TXx_0,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " TDATA ,Channel 0 data to transmit" tree.end tree "Channel_1" width 17. group.long 0x140++0x3 line.long 0x00 "MCSPI_CHxCONF_1,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock d.." "0,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set. - . - ." "0,1" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set. - . - ." "0,1" textline " " bitfld.long 0x00 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock. - . - . - . - ." "0.5_clock_cycle,1.5_clock_cycles,2.5_clock_cycles,3.5_clock_cycles" bitfld.long 0x00 24. " SBPOL ,Start-bit polarity - . - ." "0,1" bitfld.long 0x00 23. " SBE ,Start-bit enable for SPI transfer - . - ." "0,1" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only). - . - ." "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode - . - ." "0,1" textline " " bitfld.long 0x00 18. " IS ,Input Select - . - ." "0,1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1]) - . - ." "0,1" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0]) - . - ." "0,1" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the .." "0,1" bitfld.long 0x00 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter registe.." "0,1" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes - . - . - . - ." "Transmit-and-receive_mode,Receive-only_mode,Transmit-only_mode,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " EPOL ,SPIEN polarity - . - ." "0,1" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data.." "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity - . - ." "0,1" bitfld.long 0x00 0. " PHA ,SPICLK phase - . - ." "0,1" group.long 0x148++0x3 line.long 0x00 "MCSPI_CHxCTRL_1,This register is dedicated to enable channel 0." hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio. .." bitfld.long 0x00 0. " EN ,Channel enable - . - ." "0,1" rgroup.long 0x144++0x3 line.long 0x00 "MCSPI_CHxSTAT_1,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x00 6. " RXFFF ,Channel 'i' FIFO receive buffer full status - . - ." "0,1" bitfld.long 0x00 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status - . - ." "0,1" bitfld.long 0x00 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status - . - ." "0,1" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status - . - ." "0,1" bitfld.long 0x00 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. - . - ." "0,1" bitfld.long 0x00 1. " TXS ,Channel 'i' transmitter register status - . - ." "Register_is_full.,Register_is_empty." textline " " bitfld.long 0x00 0. " RXS ,Channel 'i' receiver register status - . - ." "Register_is_empty.,Register_is_full." rgroup.long 0x150++0x3 line.long 0x00 "MCSPI_RXx_1,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " RDATA ,Channel 0 received data" group.long 0x14C++0x3 line.long 0x00 "MCSPI_TXx_1,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " TDATA ,Channel 0 data to transmit" tree.end tree "Channel_2" width 17. group.long 0x154++0x3 line.long 0x00 "MCSPI_CHxCONF_2,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock d.." "0,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set. - . - ." "0,1" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set. - . - ." "0,1" textline " " bitfld.long 0x00 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock. - . - . - . - ." "0.5_clock_cycle,1.5_clock_cycles,2.5_clock_cycles,3.5_clock_cycles" bitfld.long 0x00 24. " SBPOL ,Start-bit polarity - . - ." "0,1" bitfld.long 0x00 23. " SBE ,Start-bit enable for SPI transfer - . - ." "0,1" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only). - . - ." "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode - . - ." "0,1" textline " " bitfld.long 0x00 18. " IS ,Input Select - . - ." "0,1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1]) - . - ." "0,1" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0]) - . - ." "0,1" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the .." "0,1" bitfld.long 0x00 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter registe.." "0,1" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes - . - . - . - ." "Transmit-and-receive_mode,Receive-only_mode,Transmit-only_mode,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " EPOL ,SPIEN polarity - . - ." "0,1" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data.." "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity - . - ." "0,1" bitfld.long 0x00 0. " PHA ,SPICLK phase - . - ." "0,1" group.long 0x15C++0x3 line.long 0x00 "MCSPI_CHxCTRL_2,This register is dedicated to enable channel 0." hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio. .." bitfld.long 0x00 0. " EN ,Channel enable - . - ." "0,1" rgroup.long 0x158++0x3 line.long 0x00 "MCSPI_CHxSTAT_2,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x00 6. " RXFFF ,Channel 'i' FIFO receive buffer full status - . - ." "0,1" bitfld.long 0x00 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status - . - ." "0,1" bitfld.long 0x00 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status - . - ." "0,1" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status - . - ." "0,1" bitfld.long 0x00 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. - . - ." "0,1" bitfld.long 0x00 1. " TXS ,Channel 'i' transmitter register status - . - ." "Register_is_full.,Register_is_empty." textline " " bitfld.long 0x00 0. " RXS ,Channel 'i' receiver register status - . - ." "Register_is_empty.,Register_is_full." rgroup.long 0x164++0x3 line.long 0x00 "MCSPI_RXx_2,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " RDATA ,Channel 0 received data" group.long 0x160++0x3 line.long 0x00 "MCSPI_TXx_2,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " TDATA ,Channel 0 data to transmit" tree.end tree "Channel_3" width 17. group.long 0x168++0x3 line.long 0x00 "MCSPI_CHxCONF_3,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock d.." "0,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set. - . - ." "0,1" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set. - . - ." "0,1" textline " " bitfld.long 0x00 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock. - . - . - . - ." "0.5_clock_cycle,1.5_clock_cycles,2.5_clock_cycles,3.5_clock_cycles" bitfld.long 0x00 24. " SBPOL ,Start-bit polarity - . - ." "0,1" bitfld.long 0x00 23. " SBE ,Start-bit enable for SPI transfer - . - ." "0,1" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only). - . - ." "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode - . - ." "0,1" textline " " bitfld.long 0x00 18. " IS ,Input Select - . - ." "0,1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1]) - . - ." "0,1" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0]) - . - ." "0,1" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the .." "0,1" bitfld.long 0x00 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter registe.." "0,1" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes - . - . - . - ." "Transmit-and-receive_mode,Receive-only_mode,Transmit-only_mode,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " EPOL ,SPIEN polarity - . - ." "0,1" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data.." "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity - . - ." "0,1" bitfld.long 0x00 0. " PHA ,SPICLK phase - . - ." "0,1" group.long 0x170++0x3 line.long 0x00 "MCSPI_CHxCTRL_3,This register is dedicated to enable channel 0." hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio. .." bitfld.long 0x00 0. " EN ,Channel enable - . - ." "0,1" rgroup.long 0x16C++0x3 line.long 0x00 "MCSPI_CHxSTAT_3,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x00 6. " RXFFF ,Channel 'i' FIFO receive buffer full status - . - ." "0,1" bitfld.long 0x00 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status - . - ." "0,1" bitfld.long 0x00 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status - . - ." "0,1" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status - . - ." "0,1" bitfld.long 0x00 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. - . - ." "0,1" bitfld.long 0x00 1. " TXS ,Channel 'i' transmitter register status - . - ." "Register_is_full.,Register_is_empty." textline " " bitfld.long 0x00 0. " RXS ,Channel 'i' receiver register status - . - ." "Register_is_empty.,Register_is_full." rgroup.long 0x178++0x3 line.long 0x00 "MCSPI_RXx_3,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " RDATA ,Channel 0 received data" group.long 0x174++0x3 line.long 0x00 "MCSPI_TXx_3,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " TDATA ,Channel 0 data to transmit" tree.end textline "" width 20. rgroup.long 0x0++0x3 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x00 7.--31. 1. " RSVD ,Reserved These bits are initialized to 0, and writes to them are ignored." bitfld.long 0x00 6. " RETMODE ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET. 0x0: Retention mode disabled 0x1: Retention mode enabled" "0,1" bitfld.long 0x00 1.--5. " FFNBYTE ,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter, only MSB bits from 8 down to 4 are taken into account. - . - . - . - . - ." "0,FF16bytes,FF32bytes,3,FF64bytes,5,6,7,FF128bytes,9,10,11,12,13,14,15,FF256bytes,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0. " USEFIFO ,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management. - . - ." "NoFIFO,FIFOEn" group.long 0x10++0x3 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. " RSVD ," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. - . - ." "EmuEn,EmuDis" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing" rgroup.long 0x100++0x3 line.long 0x00 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x110++0x3 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period - . - . - . - ." "None,OCP,FUNC,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management - . - . - . - ." "Force,No,Smart,Rsvd" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control - . - ." "NoWakeUp,On" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset. During reads it always returns 0. - . - ." "Off,On" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock-gating strategy - . - ." "Off,On" rgroup.long 0x114++0x3 line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "InProgress,Completed" group.long 0x118++0x3 line.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt." eventfld.long 0x00 17. " EOW ,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]. - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 16. " WKS ,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 14. " RX3_FULL ,Receiver register is full or almost full. Only when Channel 3 is enabled - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been .." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register is empty or almost empty. Note: Enabling the channel automatically rises this event. - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only). Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" group.long 0x11C++0x3 line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis." bitfld.long 0x00 17. " EOW_ENABLE ,End of Word count Interrupt Enable. - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 16. " WKE ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 14. " RX3_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 12. " TX3_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 10. " RX2_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 8. " TX2_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 6. " RX1_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 4. " TX1_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 3. " RX0_OVERFLOW_ENABLE ,Receiver register Overflow Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 2. " RX0_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 0. " TX0_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" group.long 0x120++0x3 line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis." bitfld.long 0x00 0. " WKEN ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - . - ." "NoWakeUp,WakeUp" group.long 0x124++0x3 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode." bitfld.long 0x00 11. " SSB ,Set status bit - . - ." "Off,SetThemAll" bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line. - . - ." "Out,In" bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]. - . - ." "Out,In" textline " " bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]. - . - ." "Out,In" bitfld.long 0x00 7. " WAKD ,SWAKEUP output (signal data value of internal signal to system). The signal is driven high or low according to the value written into this register bit. - . - ." "DrivenLow,DrivenHigh" bitfld.long 0x00 6. " SPICLK ,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the CLKSPI line (high or low), and a write into this bit has no effect. If MCSPI_SYST[SPIENDIR] = 0 (out.." "0,1" textline " " bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction), the SPIDAT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR1] = 1 (input mode direc.." "0,1" bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction), the SPIDAT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR.." "0,1" bitfld.long 0x00 3. " SPIEN_3 ,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[3] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (i.." "0,1" textline " " bitfld.long 0x00 2. " SPIEN_2 ,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[2] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction).." "0,1" bitfld.long 0x00 1. " SPIEN_1 ,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = .." "0,1" bitfld.long 0x00 0. " SPIEN_0 ,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (i.." "0,1" group.long 0x128++0x3 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." bitfld.long 0x00 8. " FDAA ,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has.." "NoShadowReg,ShadowRegen" bitfld.long 0x00 7. " MOA ,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO. It allows the system to perform multiple SPI word access for a single 32-bit OCP word access. This is possible for WL .." "NoMultiAccess,MultiAcces" bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode. The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register fi.." "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7" textline " " bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode - . - ." "Off,On" bitfld.long 0x00 2. " MS ,Master/slave - . - ." "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection: This register is used to configure the SPI pin mode, in master or slave mode. If asserted the controller only use SIMO, SOMI, and SPICLK clock pin for SPI transfers. - . - ." "4PinMode,3PinMode" textline " " bitfld.long 0x00 0. " SINGLE ,Single channel/Multi Channel (master mode only) - . - ." "Multi,Single" group.long 0x17C++0x3 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x00 16.--31. 1. " WCNT ,SPI word counter. This register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this register returns the current SPI word .." hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a recei.." hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer almost empty. This register holds the programmable almost empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a tr.." tree.end tree "MCSPI2" base ad:0x4809A000 tree "Channel_0" width 17. group.long 0x12C++0x3 line.long 0x00 "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock d.." "0,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set. - . - ." "0,1" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set. - . - ." "0,1" textline " " bitfld.long 0x00 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock. - . - . - . - ." "0.5_clock_cycle,1.5_clock_cycles,2.5_clock_cycles,3.5_clock_cycles" bitfld.long 0x00 24. " SBPOL ,Start-bit polarity - . - ." "0,1" bitfld.long 0x00 23. " SBE ,Start-bit enable for SPI transfer - . - ." "0,1" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only). - . - ." "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode - . - ." "0,1" textline " " bitfld.long 0x00 18. " IS ,Input Select - . - ." "0,1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1]) - . - ." "0,1" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0]) - . - ." "0,1" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the .." "0,1" bitfld.long 0x00 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter registe.." "0,1" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes - . - . - . - ." "Transmit-and-receive_mode,Receive-only_mode,Transmit-only_mode,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " EPOL ,SPIEN polarity - . - ." "0,1" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data.." "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity - . - ." "0,1" bitfld.long 0x00 0. " PHA ,SPICLK phase - . - ." "0,1" group.long 0x134++0x3 line.long 0x00 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel 0." hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio. .." bitfld.long 0x00 0. " EN ,Channel enable - . - ." "0,1" rgroup.long 0x130++0x3 line.long 0x00 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x00 6. " RXFFF ,Channel 'i' FIFO receive buffer full status - . - ." "0,1" bitfld.long 0x00 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status - . - ." "0,1" bitfld.long 0x00 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status - . - ." "0,1" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status - . - ." "0,1" bitfld.long 0x00 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. - . - ." "0,1" bitfld.long 0x00 1. " TXS ,Channel 'i' transmitter register status - . - ." "Register_is_full.,Register_is_empty." textline " " bitfld.long 0x00 0. " RXS ,Channel 'i' receiver register status - . - ." "Register_is_empty.,Register_is_full." rgroup.long 0x13C++0x3 line.long 0x00 "MCSPI_RXx_0,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " RDATA ,Channel 0 received data" group.long 0x138++0x3 line.long 0x00 "MCSPI_TXx_0,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " TDATA ,Channel 0 data to transmit" tree.end tree "Channel_1" width 17. group.long 0x140++0x3 line.long 0x00 "MCSPI_CHxCONF_1,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock d.." "0,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set. - . - ." "0,1" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set. - . - ." "0,1" textline " " bitfld.long 0x00 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock. - . - . - . - ." "0.5_clock_cycle,1.5_clock_cycles,2.5_clock_cycles,3.5_clock_cycles" bitfld.long 0x00 24. " SBPOL ,Start-bit polarity - . - ." "0,1" bitfld.long 0x00 23. " SBE ,Start-bit enable for SPI transfer - . - ." "0,1" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only). - . - ." "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode - . - ." "0,1" textline " " bitfld.long 0x00 18. " IS ,Input Select - . - ." "0,1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1]) - . - ." "0,1" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0]) - . - ." "0,1" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the .." "0,1" bitfld.long 0x00 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter registe.." "0,1" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes - . - . - . - ." "Transmit-and-receive_mode,Receive-only_mode,Transmit-only_mode,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " EPOL ,SPIEN polarity - . - ." "0,1" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data.." "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity - . - ." "0,1" bitfld.long 0x00 0. " PHA ,SPICLK phase - . - ." "0,1" group.long 0x148++0x3 line.long 0x00 "MCSPI_CHxCTRL_1,This register is dedicated to enable channel 0." hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio. .." bitfld.long 0x00 0. " EN ,Channel enable - . - ." "0,1" rgroup.long 0x144++0x3 line.long 0x00 "MCSPI_CHxSTAT_1,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x00 6. " RXFFF ,Channel 'i' FIFO receive buffer full status - . - ." "0,1" bitfld.long 0x00 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status - . - ." "0,1" bitfld.long 0x00 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status - . - ." "0,1" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status - . - ." "0,1" bitfld.long 0x00 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. - . - ." "0,1" bitfld.long 0x00 1. " TXS ,Channel 'i' transmitter register status - . - ." "Register_is_full.,Register_is_empty." textline " " bitfld.long 0x00 0. " RXS ,Channel 'i' receiver register status - . - ." "Register_is_empty.,Register_is_full." rgroup.long 0x150++0x3 line.long 0x00 "MCSPI_RXx_1,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " RDATA ,Channel 0 received data" group.long 0x14C++0x3 line.long 0x00 "MCSPI_TXx_1,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " TDATA ,Channel 0 data to transmit" tree.end textline "" width 20. rgroup.long 0x0++0x3 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x00 7.--31. 1. " RSVD ,Reserved These bits are initialized to 0, and writes to them are ignored." bitfld.long 0x00 6. " RETMODE ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET. 0x0: Retention mode disabled 0x1: Retention mode enabled" "0,1" bitfld.long 0x00 1.--5. " FFNBYTE ,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter, only MSB bits from 8 down to 4 are taken into account. - . - . - . - . - ." "0,FF16bytes,FF32bytes,3,FF64bytes,5,6,7,FF128bytes,9,10,11,12,13,14,15,FF256bytes,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0. " USEFIFO ,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management. - . - ." "NoFIFO,FIFOEn" group.long 0x10++0x3 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. " RSVD ," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. - . - ." "EmuEn,EmuDis" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing" rgroup.long 0x100++0x3 line.long 0x00 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x110++0x3 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period - . - . - . - ." "None,OCP,FUNC,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management - . - . - . - ." "Force,No,Smart,Rsvd" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control - . - ." "NoWakeUp,On" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset. During reads it always returns 0. - . - ." "Off,On" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock-gating strategy - . - ." "Off,On" rgroup.long 0x114++0x3 line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "InProgress,Completed" group.long 0x118++0x3 line.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt." eventfld.long 0x00 17. " EOW ,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]. - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 16. " WKS ,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 14. " RX3_FULL ,Receiver register is full or almost full. Only when Channel 3 is enabled - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been .." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register is empty or almost empty. Note: Enabling the channel automatically rises this event. - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only). Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" group.long 0x11C++0x3 line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis." bitfld.long 0x00 17. " EOW_ENABLE ,End of Word count Interrupt Enable. - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 16. " WKE ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 14. " RX3_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 12. " TX3_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 10. " RX2_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 8. " TX2_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 6. " RX1_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 4. " TX1_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 3. " RX0_OVERFLOW_ENABLE ,Receiver register Overflow Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 2. " RX0_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 0. " TX0_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" group.long 0x120++0x3 line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis." bitfld.long 0x00 0. " WKEN ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - . - ." "NoWakeUp,WakeUp" group.long 0x124++0x3 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode." bitfld.long 0x00 11. " SSB ,Set status bit - . - ." "Off,SetThemAll" bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line. - . - ." "Out,In" bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]. - . - ." "Out,In" textline " " bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]. - . - ." "Out,In" bitfld.long 0x00 7. " WAKD ,SWAKEUP output (signal data value of internal signal to system). The signal is driven high or low according to the value written into this register bit. - . - ." "DrivenLow,DrivenHigh" bitfld.long 0x00 6. " SPICLK ,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the CLKSPI line (high or low), and a write into this bit has no effect. If MCSPI_SYST[SPIENDIR] = 0 (out.." "0,1" textline " " bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction), the SPIDAT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR1] = 1 (input mode direc.." "0,1" bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction), the SPIDAT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR.." "0,1" bitfld.long 0x00 3. " SPIEN_3 ,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[3] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (i.." "0,1" textline " " bitfld.long 0x00 2. " SPIEN_2 ,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[2] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction).." "0,1" bitfld.long 0x00 1. " SPIEN_1 ,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = .." "0,1" bitfld.long 0x00 0. " SPIEN_0 ,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (i.." "0,1" group.long 0x128++0x3 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." bitfld.long 0x00 8. " FDAA ,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has.." "NoShadowReg,ShadowRegen" bitfld.long 0x00 7. " MOA ,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO. It allows the system to perform multiple SPI word access for a single 32-bit OCP word access. This is possible for WL .." "NoMultiAccess,MultiAcces" bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode. The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register fi.." "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7" textline " " bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode - . - ." "Off,On" bitfld.long 0x00 2. " MS ,Master/slave - . - ." "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection: This register is used to configure the SPI pin mode, in master or slave mode. If asserted the controller only use SIMO, SOMI, and SPICLK clock pin for SPI transfers. - . - ." "4PinMode,3PinMode" textline " " bitfld.long 0x00 0. " SINGLE ,Single channel/Multi Channel (master mode only) - . - ." "Multi,Single" group.long 0x17C++0x3 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x00 16.--31. 1. " WCNT ,SPI word counter. This register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this register returns the current SPI word .." hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a recei.." hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer almost empty. This register holds the programmable almost empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a tr.." tree.end tree.open "MCSPI3" tree "MCSPI3" base ad:0x480B8000 width 20. rgroup.long 0x0++0x3 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x00 7.--31. 1. " RSVD ,Reserved These bits are initialized to 0, and writes to them are ignored." bitfld.long 0x00 6. " RETMODE ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET. 0x0: Retention mode disabled 0x1: Retention mode enabled" "0,1" bitfld.long 0x00 1.--5. " FFNBYTE ,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter, only MSB bits from 8 down to 4 are taken into account. - . - . - . - . - ." "0,FF16bytes,FF32bytes,3,FF64bytes,5,6,7,FF128bytes,9,10,11,12,13,14,15,FF256bytes,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0. " USEFIFO ,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management. - . - ." "NoFIFO,FIFOEn" group.long 0x10++0x3 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. " RSVD ," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. - . - ." "EmuEn,EmuDis" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing" rgroup.long 0x100++0x3 line.long 0x00 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x110++0x3 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period - . - . - . - ." "None,OCP,FUNC,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management - . - . - . - ." "Force,No,Smart,Rsvd" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control - . - ." "NoWakeUp,On" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset. During reads it always returns 0. - . - ." "Off,On" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock-gating strategy - . - ." "Off,On" rgroup.long 0x114++0x3 line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "InProgress,Completed" group.long 0x118++0x3 line.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt." eventfld.long 0x00 17. " EOW ,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]. - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 16. " WKS ,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 14. " RX3_FULL ,Receiver register is full or almost full. Only when Channel 3 is enabled - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been .." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register is empty or almost empty. Note: Enabling the channel automatically rises this event. - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only). Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" group.long 0x11C++0x3 line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis." bitfld.long 0x00 17. " EOW_ENABLE ,End of Word count Interrupt Enable. - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 16. " WKE ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 14. " RX3_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 12. " TX3_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 10. " RX2_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 8. " TX2_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 6. " RX1_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 4. " TX1_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 3. " RX0_OVERFLOW_ENABLE ,Receiver register Overflow Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 2. " RX0_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 0. " TX0_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" group.long 0x120++0x3 line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis." bitfld.long 0x00 0. " WKEN ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - . - ." "NoWakeUp,WakeUp" group.long 0x124++0x3 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode." bitfld.long 0x00 11. " SSB ,Set status bit - . - ." "Off,SetThemAll" bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line. - . - ." "Out,In" bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]. - . - ." "Out,In" textline " " bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]. - . - ." "Out,In" bitfld.long 0x00 7. " WAKD ,SWAKEUP output (signal data value of internal signal to system). The signal is driven high or low according to the value written into this register bit. - . - ." "DrivenLow,DrivenHigh" bitfld.long 0x00 6. " SPICLK ,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the CLKSPI line (high or low), and a write into this bit has no effect. If MCSPI_SYST[SPIENDIR] = 0 (out.." "0,1" textline " " bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction), the SPIDAT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR1] = 1 (input mode direc.." "0,1" bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction), the SPIDAT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR.." "0,1" bitfld.long 0x00 3. " SPIEN_3 ,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[3] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (i.." "0,1" textline " " bitfld.long 0x00 2. " SPIEN_2 ,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[2] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction).." "0,1" bitfld.long 0x00 1. " SPIEN_1 ,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = .." "0,1" bitfld.long 0x00 0. " SPIEN_0 ,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (i.." "0,1" group.long 0x128++0x3 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." bitfld.long 0x00 8. " FDAA ,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has.." "NoShadowReg,ShadowRegen" bitfld.long 0x00 7. " MOA ,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO. It allows the system to perform multiple SPI word access for a single 32-bit OCP word access. This is possible for WL .." "NoMultiAccess,MultiAcces" bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode. The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register fi.." "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7" textline " " bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode - . - ." "Off,On" bitfld.long 0x00 2. " MS ,Master/slave - . - ." "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection: This register is used to configure the SPI pin mode, in master or slave mode. If asserted the controller only use SIMO, SOMI, and SPICLK clock pin for SPI transfers. - . - ." "4PinMode,3PinMode" textline " " bitfld.long 0x00 0. " SINGLE ,Single channel/Multi Channel (master mode only) - . - ." "Multi,Single" group.long 0x12C++0x3 line.long 0x00 "MCSPI_CHxCONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of .." "0,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set. - . - ." "0,1" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set. - . - ." "0,1" textline " " bitfld.long 0x00 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock. - . - . - . - ." "0.5_clock_cycle,1.5_clock_cycles,2.5_clock_cycles,3.5_clock_cycles" bitfld.long 0x00 24. " SBPOL ,Start-bit polarity - . - ." "0,1" bitfld.long 0x00 23. " SBE ,Start-bit enable for SPI transfer - . - ." "0,1" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only). - . - ." "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode - . - ." "0,1" textline " " bitfld.long 0x00 18. " IS ,Input Select - . - ." "0,1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1]) - . - ." "0,1" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0]) - . - ." "0,1" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive regi.." "0,1" bitfld.long 0x00 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of th.." "0,1" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes - . - . - . - ." "Transmit-and-receive_mode,Receive-only_mode,Transmit-only_mode,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " EPOL ,SPIEN polarity - . - ." "0,1" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK availa.." "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity - . - ." "0,1" bitfld.long 0x00 0. " PHA ,SPICLK phase - . - ." "0,1" rgroup.long 0x130++0x3 line.long 0x00 "MCSPI_CHxSTAT,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x00 6. " RXFFF ,Channel 'i' FIFO receive buffer full status - . - ." "0,1" bitfld.long 0x00 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status - . - ." "0,1" bitfld.long 0x00 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status - . - ." "0,1" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status - . - ." "0,1" bitfld.long 0x00 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for d.." "0,1" bitfld.long 0x00 1. " TXS ,Channel 'i' transmitter register status - . - ." "Register_is_full.,Register_is_empty." textline " " bitfld.long 0x00 0. " RXS ,Channel 'i' receiver register status - . - ." "Register_is_empty.,Register_is_full." group.long 0x134++0x3 line.long 0x00 "MCSPI_CHxCTRL,This register is dedicated to enable channel 0." hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock div.." bitfld.long 0x00 0. " EN ,Channel enable - . - ." "0,1" group.long 0x138++0x3 line.long 0x00 "MCSPI_TXx,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " TDATA ,Channel 0 data to transmit" rgroup.long 0x13C++0x3 line.long 0x00 "MCSPI_RXx,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " RDATA ,Channel 0 received data" group.long 0x17C++0x3 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x00 16.--31. 1. " WCNT ,SPI word counter. This register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this register returns the current SPI word .." hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a recei.." hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer almost empty. This register holds the programmable almost empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a tr.." tree.end tree "MCSPI4" base ad:0x480BA000 width 20. rgroup.long 0x0++0x3 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x00 7.--31. 1. " RSVD ,Reserved These bits are initialized to 0, and writes to them are ignored." bitfld.long 0x00 6. " RETMODE ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET. 0x0: Retention mode disabled 0x1: Retention mode enabled" "0,1" bitfld.long 0x00 1.--5. " FFNBYTE ,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter, only MSB bits from 8 down to 4 are taken into account. - . - . - . - . - ." "0,FF16bytes,FF32bytes,3,FF64bytes,5,6,7,FF128bytes,9,10,11,12,13,14,15,FF256bytes,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0. " USEFIFO ,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management. - . - ." "NoFIFO,FIFOEn" group.long 0x10++0x3 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. " RSVD ," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. - . - ." "EmuEn,EmuDis" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing" rgroup.long 0x100++0x3 line.long 0x00 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x110++0x3 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period - . - . - . - ." "None,OCP,FUNC,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management - . - . - . - ." "Force,No,Smart,Rsvd" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control - . - ." "NoWakeUp,On" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset. During reads it always returns 0. - . - ." "Off,On" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock-gating strategy - . - ." "Off,On" rgroup.long 0x114++0x3 line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "InProgress,Completed" group.long 0x118++0x3 line.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt." eventfld.long 0x00 17. " EOW ,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]. - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 16. " WKS ,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 14. " RX3_FULL ,Receiver register is full or almost full. Only when Channel 3 is enabled - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been .." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register is empty or almost empty. Note: Enabling the channel automatically rises this event. - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty. Channel 2 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty. Channel 1 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only). Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" textline " " eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty. Channel 0 - . - . - . - ." "NoEvnt_r_/_NoEffect_w,Evnt_r_/_ClearSrc_w" group.long 0x11C++0x3 line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis." bitfld.long 0x00 17. " EOW_ENABLE ,End of Word count Interrupt Enable. - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 16. " WKE ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 14. " RX3_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 12. " TX3_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 3 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 10. " RX2_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 8. " TX2_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 2 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 6. " RX1_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 4. " TX1_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 1 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 3. " RX0_OVERFLOW_ENABLE ,Receiver register Overflow Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" textline " " bitfld.long 0x00 2. " RX0_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" bitfld.long 0x00 0. " TX0_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 0 - . - ." "IrqDisabled,IrqEnabled" group.long 0x120++0x3 line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis." bitfld.long 0x00 0. " WKEN ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - . - ." "NoWakeUp,WakeUp" group.long 0x124++0x3 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode." bitfld.long 0x00 11. " SSB ,Set status bit - . - ." "Off,SetThemAll" bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line. - . - ." "Out,In" bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]. - . - ." "Out,In" textline " " bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]. - . - ." "Out,In" bitfld.long 0x00 7. " WAKD ,SWAKEUP output (signal data value of internal signal to system). The signal is driven high or low according to the value written into this register bit. - . - ." "DrivenLow,DrivenHigh" bitfld.long 0x00 6. " SPICLK ,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the CLKSPI line (high or low), and a write into this bit has no effect. If MCSPI_SYST[SPIENDIR] = 0 (out.." "0,1" textline " " bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction), the SPIDAT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR1] = 1 (input mode direc.." "0,1" bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction), the SPIDAT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR.." "0,1" bitfld.long 0x00 3. " SPIEN_3 ,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[3] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (i.." "0,1" textline " " bitfld.long 0x00 2. " SPIEN_2 ,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[2] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction).." "0,1" bitfld.long 0x00 1. " SPIEN_1 ,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = .." "0,1" bitfld.long 0x00 0. " SPIEN_0 ,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (i.." "0,1" group.long 0x128++0x3 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." bitfld.long 0x00 8. " FDAA ,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has.." "NoShadowReg,ShadowRegen" bitfld.long 0x00 7. " MOA ,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO. It allows the system to perform multiple SPI word access for a single 32-bit OCP word access. This is possible for WL .." "NoMultiAccess,MultiAcces" bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode. The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register fi.." "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7" textline " " bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode - . - ." "Off,On" bitfld.long 0x00 2. " MS ,Master/slave - . - ." "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection: This register is used to configure the SPI pin mode, in master or slave mode. If asserted the controller only use SIMO, SOMI, and SPICLK clock pin for SPI transfers. - . - ." "4PinMode,3PinMode" textline " " bitfld.long 0x00 0. " SINGLE ,Single channel/Multi Channel (master mode only) - . - ." "Multi,Single" group.long 0x12C++0x3 line.long 0x00 "MCSPI_CHxCONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of .." "0,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set. - . - ." "0,1" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set. - . - ." "0,1" textline " " bitfld.long 0x00 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock. - . - . - . - ." "0.5_clock_cycle,1.5_clock_cycles,2.5_clock_cycles,3.5_clock_cycles" bitfld.long 0x00 24. " SBPOL ,Start-bit polarity - . - ." "0,1" bitfld.long 0x00 23. " SBE ,Start-bit enable for SPI transfer - . - ." "0,1" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only). - . - ." "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode - . - ." "0,1" textline " " bitfld.long 0x00 18. " IS ,Input Select - . - ." "0,1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1]) - . - ." "0,1" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0]) - . - ." "0,1" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive regi.." "0,1" bitfld.long 0x00 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of th.." "0,1" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes - . - . - . - ." "Transmit-and-receive_mode,Receive-only_mode,Transmit-only_mode,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "Reserved,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " EPOL ,SPIEN polarity - . - ." "0,1" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK availa.." "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity - . - ." "0,1" bitfld.long 0x00 0. " PHA ,SPICLK phase - . - ." "0,1" rgroup.long 0x130++0x3 line.long 0x00 "MCSPI_CHxSTAT,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x00 6. " RXFFF ,Channel 'i' FIFO receive buffer full status - . - ." "0,1" bitfld.long 0x00 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status - . - ." "0,1" bitfld.long 0x00 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status - . - ." "0,1" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status - . - ." "0,1" bitfld.long 0x00 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for d.." "0,1" bitfld.long 0x00 1. " TXS ,Channel 'i' transmitter register status - . - ." "Register_is_full.,Register_is_empty." textline " " bitfld.long 0x00 0. " RXS ,Channel 'i' receiver register status - . - ." "Register_is_empty.,Register_is_full." group.long 0x134++0x3 line.long 0x00 "MCSPI_CHxCTRL,This register is dedicated to enable channel 0." hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock div.." bitfld.long 0x00 0. " EN ,Channel enable - . - ." "0,1" group.long 0x138++0x3 line.long 0x00 "MCSPI_TXx,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " TDATA ,Channel 0 data to transmit" rgroup.long 0x13C++0x3 line.long 0x00 "MCSPI_RXx,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x00 0.--31. 1. " RDATA ,Channel 0 received data" group.long 0x17C++0x3 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x00 16.--31. 1. " WCNT ,SPI word counter. This register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this register returns the current SPI word .." hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a recei.." hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer almost empty. This register holds the programmable almost empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a tr.." tree.end tree.end tree.end tree.open "Multichannel_Buffered_Serial_Port_McBSP" tree.open "MCBSP1_DSP" tree "MCBSP1_Cortex_A9" base ad:0x40122000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "MCBSPLP_DRR_REG,McBSPLP data receive register" hexmask.long 0x00 0.--31. 1. " DRR ,Data receive register" wgroup.long 0x8++0x3 line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP data transmit register" hexmask.long 0x00 0.--31. 1. " DXR ,Data transmit register" group.long 0x10++0x3 line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP serial port control register 2" bitfld.long 0x00 9. " FREE ,Free Running Mode (When this bit is set, the module ignores the Msuspend input) - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " SOFT ,Soft Bit - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " FRST ,Frame-Sync Generator Reset - . - ." "Reset,Generated" textline " " bitfld.long 0x00 6. " GRST ,Sample-Rate Generator Reset - . - ." "Reset,PullOut" bitfld.long 0x00 4.--5. " XINTM ,Transmit Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedXSYNCERR" bitfld.long 0x00 3. " XSYNCERR ,Transmit Synchronization Error (writing 0 to this bit clear the legacy transmit interrupt if asserted due to XSYNCERR condition) - . - ." "No,Detected" textline " " bitfld.long 0x00 2. " XEMPTY ,Transmit Shift Register XSR Empty - . - ." "Empty,NotEmpty" bitfld.long 0x00 1. " XRDY ,Transmitter ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " XRST ,Transmitter reset. This resets and enables the transmitter. - . - ." "Disabled,Enabled" group.long 0x14++0x3 line.long 0x00 "MCBSPLP_SPCR1_REG,McBSPLP serial port control register 1" bitfld.long 0x00 15. " ALB ,Analog Loopback Mode - . - ." "Disabled,Enabled" bitfld.long 0x00 13.--14. " RJUST ,Receive Sign-Extension and Justification Mode - . - . - . - ." "RJ,RJsigned,LJ,?..." bitfld.long 0x00 7. " DXENA ,DX Enabler - . - ." "Off,On" textline " " bitfld.long 0x00 4.--5. " RINTM ,Receive Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedRSYNCCERR" bitfld.long 0x00 3. " RSYNCERR ,Receive Synchronization Error (writing 0 to this bit clear the legacy receive interrupt if asserted due to RSYNCERR condition) - . - ." "No,Detected" bitfld.long 0x00 2. " RFULL ,Receive Shift Register (RSR]) Full - . - ." "NotOverrun,NotRead" textline " " bitfld.long 0x00 1. " RRDY ,Receiver Ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " RRST ,Receiver reset. This resets and enables the receiver. - . - ." "Disabled,Enabled" group.long 0x18++0x3 line.long 0x00 "MCBSPLP_RCR2_REG,McBSPLP receive control register 2" bitfld.long 0x00 15. " RPHASE ,Receive Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN2 ,Receive Frame Length 2 Single-phase frame selected: RFRLEN2=don't care Dual-phase frame selected: RFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " RWDLEN2 ,Receive Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " RREVERSE ,Receive reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " RDATDLY ,Receive Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x1C++0x3 line.long 0x00 "MCBSPLP_RCR1_REG,McBSPLP receive control register 1" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN1 ,Receive Frame Length 1 Single-phase frame selected: RFRLEN1=000 0000 - 1 word per frame RFRLEN1=000 0001 - 2 words per frame RFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: RFRLEN1=000 0000 - 1 word per phase (other va.." bitfld.long 0x00 5.--7. " RWDLEN1 ,Receive Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x20++0x3 line.long 0x00 "MCBSPLP_XCR2_REG,McBSPLP transmit control register 2" bitfld.long 0x00 15. " XPHASE ,Transmit Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN2 ,Transmit Frame Length 2 Single-phase frame selected: XFRLEN2=don't care Dual-phase frame selected: XFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " XWDLEN2 ,Transmit Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " XREVERSE ,Transmit reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " XDATDLY ,Transmit Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x24++0x3 line.long 0x00 "MCBSPLP_XCR1_REG,McBSPLP transmit control register 1" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN1 ,Transmit Frame Length 1 Single-phase frame selected: XFRLEN1=000 0000 - 1 word per frame XFRLEN1=000 0001 - 2 words per frame XFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: XFRLEN1=000 0000 - 1 word per phase (other v.." bitfld.long 0x00 5.--7. " XWDLEN1 ,Transmit Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x28++0x3 line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP sample rate generator register 2" bitfld.long 0x00 15. " GSYNC ,- . - ." "FreeRunning,Running" bitfld.long 0x00 14. " CLKSP ,CLKS Polarity Clock Edge Select Only used when the external clock CLKS drives the SRG clock (CLKSM=0). - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 13. " CLKSM ,McBSPLP Sample Rate Generator Clock Mode - . - ." "0x0,0x1" textline " " bitfld.long 0x00 12. " FSGM ,Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 in the PCR. - . - ." "TransmitAndIgnore,Transmit" hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame Period. This field plus 1 determines when the next frame-sync signal becomes active. Range: 1 to 4096 CLKG periods" group.long 0x2C++0x3 line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP sample rate generator register 1" hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame Width. This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period. Range: 1 to 256 CLKG periods." hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample Rate Generator Clock Divider This value is used as the divide-down number to generate the required SRG clock frequency. Default value is 1." group.long 0x30++0x3 line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP multi channel register 2" bitfld.long 0x00 9. " XMCME ,- . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " XPBBLK ,Transmit Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " XPABLK ,Transmit Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0.--1. " XMCM ,Transmit Multichannel Selection Enable - . - . - . - ." "Enabled,Disabled,EnabledMasked,DisabledMasked" group.long 0x34++0x3 line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP multi channel register 1" bitfld.long 0x00 9. " RMCME ,(legacy) - . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " RPBBLK ,Receive Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " RPABLK ,Receive Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0. " RMCM ,Receive Multichannel Selection Enable - . - ." "Enabled,Disabled" group.long 0x38++0x3 line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP receive channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " RCERA ,Receive Channel Enable RCERA n=0 Disables reception of n-th channel in an even-numbered block in partition A RCERA n=1 Enables reception of n-th channel in an even-numbered block in partition A" group.long 0x3C++0x3 line.long 0x00 "MCBSPLP_RCERB_REG,McBSPLP receive channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " RCERB ,Receive Channel Enable RCERB n=0 Disables reception of n-th channel in a even-numbered block in partition B RCERB n=1 Enables reception of n-th channel in a even-numbered block in partition B" group.long 0x40++0x3 line.long 0x00 "MCBSPLP_XCERA_REG,McBSPLP transmit channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " XCERA ,Transmit Channel Enable XCERA n=0 Disables transmission of n-th channel in an event-numbered block in partition A XCERA n=1 Enables transmission of n-th channel in an event-numbered block in partition A" group.long 0x44++0x3 line.long 0x00 "MCBSPLP_XCERB_REG,McBSPLP transmit channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " XCERB ,Transmit Channel Enable XCERB n=0 Disables transmission of n-th channel in an even-numbered block in partition B XCERB n=1 Enables transmission of n-th channel in an even-numbered block in partition B" group.long 0x48++0x3 line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP pin control register" bitfld.long 0x00 14. " IDLE_EN ,Idle enable. This bit allows stopping all the clocks in the MCBSPLP. (legacy) - . - ." "Running,ShutOff" bitfld.long 0x00 13. " XIOEN ,Transmit General Purpose I/O Mode only when XRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" bitfld.long 0x00 12. " RIOEN ,Receive General Purpose I/O Mode when RRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" textline " " bitfld.long 0x00 11. " FSXM ,Transmit Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 10. " FSRM ,Receive Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 9. " CLKXM ,Transmitter Clock Mode - . - ." "External,Internal" textline " " bitfld.long 0x00 8. " CLKRM ,Receiver Clock Mode - . - ." "External,Internal" bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG is: CLKG frequency = (Input clock frequency) / (CLKGDV + 1) SCLKME is used in conjunction with the CLKSM bit to select the input clock: - . - ." "0x0,0x1" bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input. (legacy) - . - ." "Low,High" textline " " bitfld.long 0x00 5. " DX_STAT ,DX pin status. Reflects value driven on to DX pin when selected as a general purpose output. (legacy) - . - ." "Low,High" bitfld.long 0x00 4. " DR_STAT ,DR pin status. Reflects value on DR pin when selected as a general purpose input. (legacy) - . - ." "Low,High" bitfld.long 0x00 3. " FSXP ,Transmit Frame-Synchronization Polarity - . - ." "High,Low" textline " " bitfld.long 0x00 2. " FSRP ,Receive Frame-Synchronization Polarity - . - ." "High,Low" bitfld.long 0x00 1. " CLKXP ,Transmit Clock Polarity - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 0. " CLKRP ,Receive Clock Polarity - . - ." "FallingEdge,RisingEdge" group.long 0x4C++0x3 line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP receive channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " RCERC ,Receive Channel Enable RCERC n=0 Disables reception of n-th channel in an even-numbered block in partition C RCERC n=1 Enables reception of n-th channel in an even-numbered block in partition C" group.long 0x50++0x3 line.long 0x00 "MCBSPLP_RCERD_REG,McBSPLP receive channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " RCERD ,Receive Channel Enable RCERD n=0 Disables reception of n-th channel in an even-numbered block in partition D RCERD n=1 Enables reception of n-th channel in an even-numbered block in partition D" group.long 0x54++0x3 line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP transmit channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " XCERC ,Transmit Channel Enable XCERC n=0 Disables transmission of n-th channel in an event-numbered block in partition C XCERC n=1 Enables transmission of n-th channel in an event-numbered block in partition C" group.long 0x58++0x3 line.long 0x00 "MCBSPLP_XCERD_REG,McBSPLP transmit channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " XCERD ,Transmit Channel Enable XCERD n=0 Disables transmission of n-th channel in an even-numbered block in partition D XCERD n=1 Enables transmission of n-th channel in an even-numbered block in partition D" group.long 0x5C++0x3 line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP receive channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " RCERE ,Receive Channel Enable RCERE n=0 Disables reception of n-th channel in an even-numbered block in partition E RCERE n=1 Enables reception of n-th channel in an even-numbered block in partition E" group.long 0x60++0x3 line.long 0x00 "MCBSPLP_RCERF_REG,McBSPLP receive channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " RCERF ,Receive Channel Enable RCERF n=0 Disables reception of n-th channel in an even-numbered block in partition F RCERF n=1 Enables reception of n-th channel in an even-numbered block in partition F" group.long 0x64++0x3 line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP transmit channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " XCERE ,Transmit Channel Enable XCERE n=0 Disables transmission of n-th channel in an event-numbered block in partition E XCERE n=1 Enables transmission of n-th channel in an event-numbered block in partition E" group.long 0x68++0x3 line.long 0x00 "MCBSPLP_XCERF_REG,McBSPLP transmit channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " XCERF ,Transmit Channel Enable XCERF n=0 Disables transmission of n-th channel in an even-numbered block in partition F XCERF n=1 Enables transmission of n-th channel in an even-numbered block in partition F" group.long 0x6C++0x3 line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP receive channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " RCERG ,Receive Channel Enable RCERG n=0 Disables reception of n-th channel in an even-numbered block in partition G RCERG n=1 Enables reception of n-th channel in an even-numbered block in partition G" group.long 0x70++0x3 line.long 0x00 "MCBSPLP_RCERH_REG,McBSPLP receive channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " RCERH ,Receive Channel Enable RCERH n=0 Disables reception of n-th channel in an even-numbered block in partition H RCERH n=1 Enables reception of n-th channel in an even-numbered block in partition H" group.long 0x74++0x3 line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP transmit channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " XCERG ,Transmit Channel Enable XCERG n=0 Disables transmission of n-th channel in an event-numbered block in partition G XCERG n=1 Enables transmission of n-th channel in an event-numbered block in partition G" group.long 0x78++0x3 line.long 0x00 "MCBSPLP_XCERH_REG,McBSPLP transmit channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " XCERH ,Transmit Channel Enable XCERH n=0 Disables transmission of n-th channel in an even-numbered block in partition H XCERH n=1 Enables transmission of n-th channel in an even-numbered block in partition H" rgroup.long 0x7C++0x3 line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision number register" hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number" group.long 0x80++0x3 line.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP receive interrupt clear" hexmask.long 0x00 0.--31. 1. " RINTCLR ,Read from this register will clear the IRQ generated by receive end-of-frame indication or MCBSPLP.FSR detection. Write to this register has no effect. (legacy)" group.long 0x84++0x3 line.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP transmit interrupt clear (legacy)" hexmask.long 0x00 0.--31. 1. " XINTCLR ,Read from this register will clear the IRQ generated by transmit end-of-frame indication or MCBSPLP.FSX detection. Write to this register has no effect." group.long 0x88++0x3 line.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP receive overflow interrupt clear" hexmask.long 0x00 0.--31. 1. " ROVFLCLR ,Read from this register will clear the IRQ generated by the receive overflow condition. Write to this register has no effect." group.long 0x8C++0x3 line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,- . - . - . - ." "CLKACT0,CLKACT1,CLKACT2,CLKACT3" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, req/ack control: - . - . - . - ." "SIDLEMODE0,SIDLEMODE1,SIDLEMODE2,SIDLEMODE3" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control: - . - ." "ENWK0,ENWK1" textline " " bitfld.long 0x00 1. " SOFTRESET ,McBSPLP global software reset - . - ." "NORESET,SOFTRESET" group.long 0x90++0x3 line.long 0x00 "MCBSPLP_THRSH2_REG,McBSPLP transmit buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of free locations inside transmit buffer are above or equal to the XTHRESHOLD value + 1. Also, this value .." group.long 0x94++0x3 line.long 0x00 "MCBSPLP_THRSH1_REG,McBSPLP receive buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of occupied locations inside receive buffer are above or equal to the RTHRESHOLD value + 1. Also, this valu.." group.long 0xA0++0x3 line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOF ,Transmit Buffer Empty at end of frame (XEMPTYEOF is set to 1 when a complete frame was transmitted and the transmit buffer is empty). - . - ." "XEMPTYEOF0,XEMPTYEOF1" bitfld.long 0x00 12. " XOVFLSTAT ,Transmit Buffer Overflow (XOVFLSTAT bit is set to 1 when transmit buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "XOVFLSTAT0,XOVFLSTAT1" bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit Buffer Underflow (XUNDFLSTAT bit is set to 1 when the transmit data buffer is empty new data is required to be transmitted). Writing 1 to this bit clears the bit. - . - ." "XUNDFLSTAT0,XUNDFLSTAT1" textline " " bitfld.long 0x00 10. " XRDY ,Transmit Buffer Threshold Reached (XRDY bit is set to 1 when the transmit buffer free locations are equal or above the THRSH2_REG value). Writing 1 to this bit clears the bit. - . - ." "XRDY0,XRDY1" bitfld.long 0x00 9. " XEOF ,Transmit End Of Frame (XEOF is set to 1 when a complete frame was transmitted). Writing 1 to this bit clears the bit. - . - ." "XEOF0,XEOF1" bitfld.long 0x00 8. " XFSX ,Transmit Frame Synchronization (XFSX bit is set to 1 when a new transmit frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "XFSX0,XFSX1" textline " " bitfld.long 0x00 7. " XSYNCERR ,Transmit Frame Synchronization Error (XSYNCERR is set to 1 when a transmit frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "XSYNCERR0,XSYNCERR1" bitfld.long 0x00 5. " ROVFLSTAT ,Receive Buffer Overflow (ROVFLSTAT bit is set to 1 when receive buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "ROVFLSTAT0,ROVFLSTAT1" bitfld.long 0x00 4. " RUNDFLSTAT ,Receive Buffer Underflow (RUNDFLSTAT bit is set to 1 when read operation is performed to the receive data register while receive buffer is empty; data read while underflow condition is undefined). Writing 1 to this bit clears the.." "RUNDFLSTAT0,RUNDFLSTAT1" textline " " bitfld.long 0x00 3. " RRDY ,Receive Buffer Threshold Reached (RRDY bit is set to 1 when the receive buffer occupied locations are equal or above the THRSH1_REG value). Writing 1 to this bit clears the bit. - . - ." "RRDY0,RRDY1" bitfld.long 0x00 2. " REOF ,Receive End Of Frame (REOF is set to 1 when a complete frame was received). Writing 1 to this bit clears the bit. - . - ." "REOF0,REOF1" bitfld.long 0x00 1. " RFSR ,Receive Frame Synchronization (RFSR bit is set to 1 when a new receive frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "RFSR0,RFSR1" textline " " bitfld.long 0x00 0. " RSYNCERR ,Receive Frame Synchronization Error (RSYNCERR is set to 1 when a receive frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "RSYNCERR0,RSYNCERR1" group.long 0xA4++0x3 line.long 0x00 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 12. " XOVFLEN ,Transmit Buffer Overflow enable bit. - . - ." "XOVFLEN0,XOVFLEN1" bitfld.long 0x00 11. " XUNDFLEN ,Transmit Buffer Underflow enable bit. - . - ." "XUNDFLEN0,XUNDFLEN1" textline " " bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame enable bit. - . - ." "XEOFEN0,XEOFEN1" bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization enable bit. - . - ." "XFSXEN0,XFSXEN1" textline " " bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 5. " ROVFLEN ,Receive Buffer Overflow enable bit. - . - ." "ROVFLEN0,ROVFLEN1" bitfld.long 0x00 4. " RUNDFLEN ,Receive Buffer Underflow enable bit. - . - ." "RUNDFLEN0,RUNDFLEN1" textline " " bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold enable bit. - . - ." "RRDYEN0,RRDYEN1" bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization enable bit. RW - . - ." "RFSREN0,RFSREN1" textline " " bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xA8++0x3 line.long 0x00 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable register" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit Buffer Empty at End Of Frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached WK enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame WK enable bit. - . - ." "XEOFEN0,XEOFEN1" textline " " bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization WK enable bit. - . - ." "XFSXEN0,XFSXEN1" bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error WK enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold wakeup enable bit. - . - ." "RRDYEN0,RRDYEN1" textline " " bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame WK enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization WK enable bit. - . - ." "RFSREN0,RFSREN1" bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error WK enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xAC++0x3 line.long 0x00 "MCBSPLP_XCCR_REG,McBSPLP transmit configuration control register" bitfld.long 0x00 15. " EXTCLKGATE ,External clock gating enable (CLKX and FSX master only). When this bit is set and the transmit clock and FSX are set as output, the CLKX is enabled when FSX is active plus 3 clock cycles after (clock is provided for FWID + 4 clock cycle.." "EXTCLKGATE0,EXTCLKGATE1" bitfld.long 0x00 14. " PPCONNECT ,Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output - . - ." "PPCONNECT0,PPCONNECT1" bitfld.long 0x00 12.--13. " DXENDLY ,When DXENA bit in SPCR1 is set to 1 this field selects the added delay as follow: - . - . - . - ." "DXENDLY0,DXENDLY1,DXENDLY2,DXENDLY3" textline " " bitfld.long 0x00 11. " XFULL_CYCLE ,Transmit full-cycle mode select. - . - ." "XFULL_CYCLE0,XFULL_CYCLE1" bitfld.long 0x00 5. " DLB ,Digital Loop-Back - . - ." "NODLB,DLB" bitfld.long 0x00 3. " XDMAEN ,Transmit DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during transmit reset. - . - ." "XDMAEN0,XDMAEN1" textline " " bitfld.long 0x00 0. " XDISABLE ,Transmit Disable bit. When this bit is set the transmit process will stop at the next frame boundary. - . - ." "XDSB0,XDSB1" group.long 0xB0++0x3 line.long 0x00 "MCBSPLP_RCCR_REG,McBSPLP receive configuration control register" bitfld.long 0x00 11. " RFULL_CYCLE ,Receive full-cycle mode select. - . - ." "RFULL_CYCLE0,RFULL_CYCLE1" bitfld.long 0x00 3. " RDMAEN ,Receive DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during receive reset. - . - ." "RDMAEN0,RDMAEN1" bitfld.long 0x00 0. " RDISABLE ,Receive Disable bit. When this bit is set the receive process will stop at the next frame boundary. - . - ." "RDSB0,RDSB1" rgroup.long 0xB4++0x3 line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP transmit buffer status" hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit Buffer Status (indicates the number of free locations inside transmit buffer). The XBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the number of free locations which are seen .." rgroup.long 0xB8++0x3 line.long 0x00 "MCBSPLP_RBUFFSTAT_REG,McBSPLP receive buffer status" hexmask.long.byte 0x00 0.--7. 1. " RBUFFSTAT ,Receive Buffer Status (indicates the number of occupied locations inside receive buffer). The RBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the real number of the occupied locations .." tree.end tree "MCBSP2_Cortex_A9" base ad:0x40124000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "MCBSPLP_DRR_REG,McBSPLP data receive register" hexmask.long 0x00 0.--31. 1. " DRR ,Data receive register" wgroup.long 0x8++0x3 line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP data transmit register" hexmask.long 0x00 0.--31. 1. " DXR ,Data transmit register" group.long 0x10++0x3 line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP serial port control register 2" bitfld.long 0x00 9. " FREE ,Free Running Mode (When this bit is set, the module ignores the Msuspend input) - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " SOFT ,Soft Bit - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " FRST ,Frame-Sync Generator Reset - . - ." "Reset,Generated" textline " " bitfld.long 0x00 6. " GRST ,Sample-Rate Generator Reset - . - ." "Reset,PullOut" bitfld.long 0x00 4.--5. " XINTM ,Transmit Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedXSYNCERR" bitfld.long 0x00 3. " XSYNCERR ,Transmit Synchronization Error (writing 0 to this bit clear the legacy transmit interrupt if asserted due to XSYNCERR condition) - . - ." "No,Detected" textline " " bitfld.long 0x00 2. " XEMPTY ,Transmit Shift Register XSR Empty - . - ." "Empty,NotEmpty" bitfld.long 0x00 1. " XRDY ,Transmitter ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " XRST ,Transmitter reset. This resets and enables the transmitter. - . - ." "Disabled,Enabled" group.long 0x14++0x3 line.long 0x00 "MCBSPLP_SPCR1_REG,McBSPLP serial port control register 1" bitfld.long 0x00 15. " ALB ,Analog Loopback Mode - . - ." "Disabled,Enabled" bitfld.long 0x00 13.--14. " RJUST ,Receive Sign-Extension and Justification Mode - . - . - . - ." "RJ,RJsigned,LJ,?..." bitfld.long 0x00 7. " DXENA ,DX Enabler - . - ." "Off,On" textline " " bitfld.long 0x00 4.--5. " RINTM ,Receive Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedRSYNCCERR" bitfld.long 0x00 3. " RSYNCERR ,Receive Synchronization Error (writing 0 to this bit clear the legacy receive interrupt if asserted due to RSYNCERR condition) - . - ." "No,Detected" bitfld.long 0x00 2. " RFULL ,Receive Shift Register (RSR]) Full - . - ." "NotOverrun,NotRead" textline " " bitfld.long 0x00 1. " RRDY ,Receiver Ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " RRST ,Receiver reset. This resets and enables the receiver. - . - ." "Disabled,Enabled" group.long 0x18++0x3 line.long 0x00 "MCBSPLP_RCR2_REG,McBSPLP receive control register 2" bitfld.long 0x00 15. " RPHASE ,Receive Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN2 ,Receive Frame Length 2 Single-phase frame selected: RFRLEN2=don't care Dual-phase frame selected: RFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " RWDLEN2 ,Receive Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " RREVERSE ,Receive reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " RDATDLY ,Receive Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x1C++0x3 line.long 0x00 "MCBSPLP_RCR1_REG,McBSPLP receive control register 1" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN1 ,Receive Frame Length 1 Single-phase frame selected: RFRLEN1=000 0000 - 1 word per frame RFRLEN1=000 0001 - 2 words per frame RFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: RFRLEN1=000 0000 - 1 word per phase (other va.." bitfld.long 0x00 5.--7. " RWDLEN1 ,Receive Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x20++0x3 line.long 0x00 "MCBSPLP_XCR2_REG,McBSPLP transmit control register 2" bitfld.long 0x00 15. " XPHASE ,Transmit Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN2 ,Transmit Frame Length 2 Single-phase frame selected: XFRLEN2=don't care Dual-phase frame selected: XFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " XWDLEN2 ,Transmit Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " XREVERSE ,Transmit reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " XDATDLY ,Transmit Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x24++0x3 line.long 0x00 "MCBSPLP_XCR1_REG,McBSPLP transmit control register 1" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN1 ,Transmit Frame Length 1 Single-phase frame selected: XFRLEN1=000 0000 - 1 word per frame XFRLEN1=000 0001 - 2 words per frame XFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: XFRLEN1=000 0000 - 1 word per phase (other v.." bitfld.long 0x00 5.--7. " XWDLEN1 ,Transmit Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x28++0x3 line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP sample rate generator register 2" bitfld.long 0x00 15. " GSYNC ,- . - ." "FreeRunning,Running" bitfld.long 0x00 14. " CLKSP ,CLKS Polarity Clock Edge Select Only used when the external clock CLKS drives the SRG clock (CLKSM=0). - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 13. " CLKSM ,McBSPLP Sample Rate Generator Clock Mode - . - ." "0x0,0x1" textline " " bitfld.long 0x00 12. " FSGM ,Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 in the PCR. - . - ." "TransmitAndIgnore,Transmit" hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame Period. This field plus 1 determines when the next frame-sync signal becomes active. Range: 1 to 4096 CLKG periods" group.long 0x2C++0x3 line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP sample rate generator register 1" hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame Width. This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period. Range: 1 to 256 CLKG periods." hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample Rate Generator Clock Divider This value is used as the divide-down number to generate the required SRG clock frequency. Default value is 1." group.long 0x30++0x3 line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP multi channel register 2" bitfld.long 0x00 9. " XMCME ,- . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " XPBBLK ,Transmit Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " XPABLK ,Transmit Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0.--1. " XMCM ,Transmit Multichannel Selection Enable - . - . - . - ." "Enabled,Disabled,EnabledMasked,DisabledMasked" group.long 0x34++0x3 line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP multi channel register 1" bitfld.long 0x00 9. " RMCME ,(legacy) - . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " RPBBLK ,Receive Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " RPABLK ,Receive Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0. " RMCM ,Receive Multichannel Selection Enable - . - ." "Enabled,Disabled" group.long 0x38++0x3 line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP receive channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " RCERA ,Receive Channel Enable RCERA n=0 Disables reception of n-th channel in an even-numbered block in partition A RCERA n=1 Enables reception of n-th channel in an even-numbered block in partition A" group.long 0x3C++0x3 line.long 0x00 "MCBSPLP_RCERB_REG,McBSPLP receive channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " RCERB ,Receive Channel Enable RCERB n=0 Disables reception of n-th channel in a even-numbered block in partition B RCERB n=1 Enables reception of n-th channel in a even-numbered block in partition B" group.long 0x40++0x3 line.long 0x00 "MCBSPLP_XCERA_REG,McBSPLP transmit channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " XCERA ,Transmit Channel Enable XCERA n=0 Disables transmission of n-th channel in an event-numbered block in partition A XCERA n=1 Enables transmission of n-th channel in an event-numbered block in partition A" group.long 0x44++0x3 line.long 0x00 "MCBSPLP_XCERB_REG,McBSPLP transmit channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " XCERB ,Transmit Channel Enable XCERB n=0 Disables transmission of n-th channel in an even-numbered block in partition B XCERB n=1 Enables transmission of n-th channel in an even-numbered block in partition B" group.long 0x48++0x3 line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP pin control register" bitfld.long 0x00 14. " IDLE_EN ,Idle enable. This bit allows stopping all the clocks in the MCBSPLP. (legacy) - . - ." "Running,ShutOff" bitfld.long 0x00 13. " XIOEN ,Transmit General Purpose I/O Mode only when XRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" bitfld.long 0x00 12. " RIOEN ,Receive General Purpose I/O Mode when RRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" textline " " bitfld.long 0x00 11. " FSXM ,Transmit Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 10. " FSRM ,Receive Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 9. " CLKXM ,Transmitter Clock Mode - . - ." "External,Internal" textline " " bitfld.long 0x00 8. " CLKRM ,Receiver Clock Mode - . - ." "External,Internal" bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG is: CLKG frequency = (Input clock frequency) / (CLKGDV + 1) SCLKME is used in conjunction with the CLKSM bit to select the input clock: - . - ." "0x0,0x1" bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input. (legacy) - . - ." "Low,High" textline " " bitfld.long 0x00 5. " DX_STAT ,DX pin status. Reflects value driven on to DX pin when selected as a general purpose output. (legacy) - . - ." "Low,High" bitfld.long 0x00 4. " DR_STAT ,DR pin status. Reflects value on DR pin when selected as a general purpose input. (legacy) - . - ." "Low,High" bitfld.long 0x00 3. " FSXP ,Transmit Frame-Synchronization Polarity - . - ." "High,Low" textline " " bitfld.long 0x00 2. " FSRP ,Receive Frame-Synchronization Polarity - . - ." "High,Low" bitfld.long 0x00 1. " CLKXP ,Transmit Clock Polarity - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 0. " CLKRP ,Receive Clock Polarity - . - ." "FallingEdge,RisingEdge" group.long 0x4C++0x3 line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP receive channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " RCERC ,Receive Channel Enable RCERC n=0 Disables reception of n-th channel in an even-numbered block in partition C RCERC n=1 Enables reception of n-th channel in an even-numbered block in partition C" group.long 0x50++0x3 line.long 0x00 "MCBSPLP_RCERD_REG,McBSPLP receive channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " RCERD ,Receive Channel Enable RCERD n=0 Disables reception of n-th channel in an even-numbered block in partition D RCERD n=1 Enables reception of n-th channel in an even-numbered block in partition D" group.long 0x54++0x3 line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP transmit channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " XCERC ,Transmit Channel Enable XCERC n=0 Disables transmission of n-th channel in an event-numbered block in partition C XCERC n=1 Enables transmission of n-th channel in an event-numbered block in partition C" group.long 0x58++0x3 line.long 0x00 "MCBSPLP_XCERD_REG,McBSPLP transmit channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " XCERD ,Transmit Channel Enable XCERD n=0 Disables transmission of n-th channel in an even-numbered block in partition D XCERD n=1 Enables transmission of n-th channel in an even-numbered block in partition D" group.long 0x5C++0x3 line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP receive channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " RCERE ,Receive Channel Enable RCERE n=0 Disables reception of n-th channel in an even-numbered block in partition E RCERE n=1 Enables reception of n-th channel in an even-numbered block in partition E" group.long 0x60++0x3 line.long 0x00 "MCBSPLP_RCERF_REG,McBSPLP receive channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " RCERF ,Receive Channel Enable RCERF n=0 Disables reception of n-th channel in an even-numbered block in partition F RCERF n=1 Enables reception of n-th channel in an even-numbered block in partition F" group.long 0x64++0x3 line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP transmit channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " XCERE ,Transmit Channel Enable XCERE n=0 Disables transmission of n-th channel in an event-numbered block in partition E XCERE n=1 Enables transmission of n-th channel in an event-numbered block in partition E" group.long 0x68++0x3 line.long 0x00 "MCBSPLP_XCERF_REG,McBSPLP transmit channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " XCERF ,Transmit Channel Enable XCERF n=0 Disables transmission of n-th channel in an even-numbered block in partition F XCERF n=1 Enables transmission of n-th channel in an even-numbered block in partition F" group.long 0x6C++0x3 line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP receive channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " RCERG ,Receive Channel Enable RCERG n=0 Disables reception of n-th channel in an even-numbered block in partition G RCERG n=1 Enables reception of n-th channel in an even-numbered block in partition G" group.long 0x70++0x3 line.long 0x00 "MCBSPLP_RCERH_REG,McBSPLP receive channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " RCERH ,Receive Channel Enable RCERH n=0 Disables reception of n-th channel in an even-numbered block in partition H RCERH n=1 Enables reception of n-th channel in an even-numbered block in partition H" group.long 0x74++0x3 line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP transmit channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " XCERG ,Transmit Channel Enable XCERG n=0 Disables transmission of n-th channel in an event-numbered block in partition G XCERG n=1 Enables transmission of n-th channel in an event-numbered block in partition G" group.long 0x78++0x3 line.long 0x00 "MCBSPLP_XCERH_REG,McBSPLP transmit channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " XCERH ,Transmit Channel Enable XCERH n=0 Disables transmission of n-th channel in an even-numbered block in partition H XCERH n=1 Enables transmission of n-th channel in an even-numbered block in partition H" rgroup.long 0x7C++0x3 line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision number register" hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number" group.long 0x80++0x3 line.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP receive interrupt clear" hexmask.long 0x00 0.--31. 1. " RINTCLR ,Read from this register will clear the IRQ generated by receive end-of-frame indication or MCBSPLP.FSR detection. Write to this register has no effect. (legacy)" group.long 0x84++0x3 line.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP transmit interrupt clear (legacy)" hexmask.long 0x00 0.--31. 1. " XINTCLR ,Read from this register will clear the IRQ generated by transmit end-of-frame indication or MCBSPLP.FSX detection. Write to this register has no effect." group.long 0x88++0x3 line.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP receive overflow interrupt clear" hexmask.long 0x00 0.--31. 1. " ROVFLCLR ,Read from this register will clear the IRQ generated by the receive overflow condition. Write to this register has no effect." group.long 0x8C++0x3 line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,- . - . - . - ." "CLKACT0,CLKACT1,CLKACT2,CLKACT3" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, req/ack control: - . - . - . - ." "SIDLEMODE0,SIDLEMODE1,SIDLEMODE2,SIDLEMODE3" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control: - . - ." "ENWK0,ENWK1" textline " " bitfld.long 0x00 1. " SOFTRESET ,McBSPLP global software reset - . - ." "NORESET,SOFTRESET" group.long 0x90++0x3 line.long 0x00 "MCBSPLP_THRSH2_REG,McBSPLP transmit buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of free locations inside transmit buffer are above or equal to the XTHRESHOLD value + 1. Also, this value .." group.long 0x94++0x3 line.long 0x00 "MCBSPLP_THRSH1_REG,McBSPLP receive buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of occupied locations inside receive buffer are above or equal to the RTHRESHOLD value + 1. Also, this valu.." group.long 0xA0++0x3 line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOF ,Transmit Buffer Empty at end of frame (XEMPTYEOF is set to 1 when a complete frame was transmitted and the transmit buffer is empty). - . - ." "XEMPTYEOF0,XEMPTYEOF1" bitfld.long 0x00 12. " XOVFLSTAT ,Transmit Buffer Overflow (XOVFLSTAT bit is set to 1 when transmit buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "XOVFLSTAT0,XOVFLSTAT1" bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit Buffer Underflow (XUNDFLSTAT bit is set to 1 when the transmit data buffer is empty new data is required to be transmitted). Writing 1 to this bit clears the bit. - . - ." "XUNDFLSTAT0,XUNDFLSTAT1" textline " " bitfld.long 0x00 10. " XRDY ,Transmit Buffer Threshold Reached (XRDY bit is set to 1 when the transmit buffer free locations are equal or above the THRSH2_REG value). Writing 1 to this bit clears the bit. - . - ." "XRDY0,XRDY1" bitfld.long 0x00 9. " XEOF ,Transmit End Of Frame (XEOF is set to 1 when a complete frame was transmitted). Writing 1 to this bit clears the bit. - . - ." "XEOF0,XEOF1" bitfld.long 0x00 8. " XFSX ,Transmit Frame Synchronization (XFSX bit is set to 1 when a new transmit frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "XFSX0,XFSX1" textline " " bitfld.long 0x00 7. " XSYNCERR ,Transmit Frame Synchronization Error (XSYNCERR is set to 1 when a transmit frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "XSYNCERR0,XSYNCERR1" bitfld.long 0x00 5. " ROVFLSTAT ,Receive Buffer Overflow (ROVFLSTAT bit is set to 1 when receive buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "ROVFLSTAT0,ROVFLSTAT1" bitfld.long 0x00 4. " RUNDFLSTAT ,Receive Buffer Underflow (RUNDFLSTAT bit is set to 1 when read operation is performed to the receive data register while receive buffer is empty; data read while underflow condition is undefined). Writing 1 to this bit clears the.." "RUNDFLSTAT0,RUNDFLSTAT1" textline " " bitfld.long 0x00 3. " RRDY ,Receive Buffer Threshold Reached (RRDY bit is set to 1 when the receive buffer occupied locations are equal or above the THRSH1_REG value). Writing 1 to this bit clears the bit. - . - ." "RRDY0,RRDY1" bitfld.long 0x00 2. " REOF ,Receive End Of Frame (REOF is set to 1 when a complete frame was received). Writing 1 to this bit clears the bit. - . - ." "REOF0,REOF1" bitfld.long 0x00 1. " RFSR ,Receive Frame Synchronization (RFSR bit is set to 1 when a new receive frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "RFSR0,RFSR1" textline " " bitfld.long 0x00 0. " RSYNCERR ,Receive Frame Synchronization Error (RSYNCERR is set to 1 when a receive frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "RSYNCERR0,RSYNCERR1" group.long 0xA4++0x3 line.long 0x00 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 12. " XOVFLEN ,Transmit Buffer Overflow enable bit. - . - ." "XOVFLEN0,XOVFLEN1" bitfld.long 0x00 11. " XUNDFLEN ,Transmit Buffer Underflow enable bit. - . - ." "XUNDFLEN0,XUNDFLEN1" textline " " bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame enable bit. - . - ." "XEOFEN0,XEOFEN1" bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization enable bit. - . - ." "XFSXEN0,XFSXEN1" textline " " bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 5. " ROVFLEN ,Receive Buffer Overflow enable bit. - . - ." "ROVFLEN0,ROVFLEN1" bitfld.long 0x00 4. " RUNDFLEN ,Receive Buffer Underflow enable bit. - . - ." "RUNDFLEN0,RUNDFLEN1" textline " " bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold enable bit. - . - ." "RRDYEN0,RRDYEN1" bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization enable bit. RW - . - ." "RFSREN0,RFSREN1" textline " " bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xA8++0x3 line.long 0x00 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable register" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit Buffer Empty at End Of Frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached WK enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame WK enable bit. - . - ." "XEOFEN0,XEOFEN1" textline " " bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization WK enable bit. - . - ." "XFSXEN0,XFSXEN1" bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error WK enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold wakeup enable bit. - . - ." "RRDYEN0,RRDYEN1" textline " " bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame WK enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization WK enable bit. - . - ." "RFSREN0,RFSREN1" bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error WK enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xAC++0x3 line.long 0x00 "MCBSPLP_XCCR_REG,McBSPLP transmit configuration control register" bitfld.long 0x00 15. " EXTCLKGATE ,External clock gating enable (CLKX and FSX master only). When this bit is set and the transmit clock and FSX are set as output, the CLKX is enabled when FSX is active plus 3 clock cycles after (clock is provided for FWID + 4 clock cycle.." "EXTCLKGATE0,EXTCLKGATE1" bitfld.long 0x00 14. " PPCONNECT ,Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output - . - ." "PPCONNECT0,PPCONNECT1" bitfld.long 0x00 12.--13. " DXENDLY ,When DXENA bit in SPCR1 is set to 1 this field selects the added delay as follow: - . - . - . - ." "DXENDLY0,DXENDLY1,DXENDLY2,DXENDLY3" textline " " bitfld.long 0x00 11. " XFULL_CYCLE ,Transmit full-cycle mode select. - . - ." "XFULL_CYCLE0,XFULL_CYCLE1" bitfld.long 0x00 5. " DLB ,Digital Loop-Back - . - ." "NODLB,DLB" bitfld.long 0x00 3. " XDMAEN ,Transmit DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during transmit reset. - . - ." "XDMAEN0,XDMAEN1" textline " " bitfld.long 0x00 0. " XDISABLE ,Transmit Disable bit. When this bit is set the transmit process will stop at the next frame boundary. - . - ." "XDSB0,XDSB1" group.long 0xB0++0x3 line.long 0x00 "MCBSPLP_RCCR_REG,McBSPLP receive configuration control register" bitfld.long 0x00 11. " RFULL_CYCLE ,Receive full-cycle mode select. - . - ." "RFULL_CYCLE0,RFULL_CYCLE1" bitfld.long 0x00 3. " RDMAEN ,Receive DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during receive reset. - . - ." "RDMAEN0,RDMAEN1" bitfld.long 0x00 0. " RDISABLE ,Receive Disable bit. When this bit is set the receive process will stop at the next frame boundary. - . - ." "RDSB0,RDSB1" rgroup.long 0xB4++0x3 line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP transmit buffer status" hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit Buffer Status (indicates the number of free locations inside transmit buffer). The XBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the number of free locations which are seen .." rgroup.long 0xB8++0x3 line.long 0x00 "MCBSPLP_RBUFFSTAT_REG,McBSPLP receive buffer status" hexmask.long.byte 0x00 0.--7. 1. " RBUFFSTAT ,Receive Buffer Status (indicates the number of occupied locations inside receive buffer). The RBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the real number of the occupied locations .." tree.end tree "MCBSP3_Cortex_A9" base ad:0x40126000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "MCBSPLP_DRR_REG,McBSPLP data receive register" hexmask.long 0x00 0.--31. 1. " DRR ,Data receive register" wgroup.long 0x8++0x3 line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP data transmit register" hexmask.long 0x00 0.--31. 1. " DXR ,Data transmit register" group.long 0x10++0x3 line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP serial port control register 2" bitfld.long 0x00 9. " FREE ,Free Running Mode (When this bit is set, the module ignores the Msuspend input) - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " SOFT ,Soft Bit - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " FRST ,Frame-Sync Generator Reset - . - ." "Reset,Generated" textline " " bitfld.long 0x00 6. " GRST ,Sample-Rate Generator Reset - . - ." "Reset,PullOut" bitfld.long 0x00 4.--5. " XINTM ,Transmit Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedXSYNCERR" bitfld.long 0x00 3. " XSYNCERR ,Transmit Synchronization Error (writing 0 to this bit clear the legacy transmit interrupt if asserted due to XSYNCERR condition) - . - ." "No,Detected" textline " " bitfld.long 0x00 2. " XEMPTY ,Transmit Shift Register XSR Empty - . - ." "Empty,NotEmpty" bitfld.long 0x00 1. " XRDY ,Transmitter ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " XRST ,Transmitter reset. This resets and enables the transmitter. - . - ." "Disabled,Enabled" group.long 0x14++0x3 line.long 0x00 "MCBSPLP_SPCR1_REG,McBSPLP serial port control register 1" bitfld.long 0x00 15. " ALB ,Analog Loopback Mode - . - ." "Disabled,Enabled" bitfld.long 0x00 13.--14. " RJUST ,Receive Sign-Extension and Justification Mode - . - . - . - ." "RJ,RJsigned,LJ,?..." bitfld.long 0x00 7. " DXENA ,DX Enabler - . - ." "Off,On" textline " " bitfld.long 0x00 4.--5. " RINTM ,Receive Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedRSYNCCERR" bitfld.long 0x00 3. " RSYNCERR ,Receive Synchronization Error (writing 0 to this bit clear the legacy receive interrupt if asserted due to RSYNCERR condition) - . - ." "No,Detected" bitfld.long 0x00 2. " RFULL ,Receive Shift Register (RSR]) Full - . - ." "NotOverrun,NotRead" textline " " bitfld.long 0x00 1. " RRDY ,Receiver Ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " RRST ,Receiver reset. This resets and enables the receiver. - . - ." "Disabled,Enabled" group.long 0x18++0x3 line.long 0x00 "MCBSPLP_RCR2_REG,McBSPLP receive control register 2" bitfld.long 0x00 15. " RPHASE ,Receive Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN2 ,Receive Frame Length 2 Single-phase frame selected: RFRLEN2=don't care Dual-phase frame selected: RFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " RWDLEN2 ,Receive Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " RREVERSE ,Receive reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " RDATDLY ,Receive Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x1C++0x3 line.long 0x00 "MCBSPLP_RCR1_REG,McBSPLP receive control register 1" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN1 ,Receive Frame Length 1 Single-phase frame selected: RFRLEN1=000 0000 - 1 word per frame RFRLEN1=000 0001 - 2 words per frame RFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: RFRLEN1=000 0000 - 1 word per phase (other va.." bitfld.long 0x00 5.--7. " RWDLEN1 ,Receive Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x20++0x3 line.long 0x00 "MCBSPLP_XCR2_REG,McBSPLP transmit control register 2" bitfld.long 0x00 15. " XPHASE ,Transmit Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN2 ,Transmit Frame Length 2 Single-phase frame selected: XFRLEN2=don't care Dual-phase frame selected: XFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " XWDLEN2 ,Transmit Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " XREVERSE ,Transmit reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " XDATDLY ,Transmit Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x24++0x3 line.long 0x00 "MCBSPLP_XCR1_REG,McBSPLP transmit control register 1" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN1 ,Transmit Frame Length 1 Single-phase frame selected: XFRLEN1=000 0000 - 1 word per frame XFRLEN1=000 0001 - 2 words per frame XFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: XFRLEN1=000 0000 - 1 word per phase (other v.." bitfld.long 0x00 5.--7. " XWDLEN1 ,Transmit Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x28++0x3 line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP sample rate generator register 2" bitfld.long 0x00 15. " GSYNC ,- . - ." "FreeRunning,Running" bitfld.long 0x00 14. " CLKSP ,CLKS Polarity Clock Edge Select Only used when the external clock CLKS drives the SRG clock (CLKSM=0). - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 13. " CLKSM ,McBSPLP Sample Rate Generator Clock Mode - . - ." "0x0,0x1" textline " " bitfld.long 0x00 12. " FSGM ,Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 in the PCR. - . - ." "TransmitAndIgnore,Transmit" hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame Period. This field plus 1 determines when the next frame-sync signal becomes active. Range: 1 to 4096 CLKG periods" group.long 0x2C++0x3 line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP sample rate generator register 1" hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame Width. This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period. Range: 1 to 256 CLKG periods." hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample Rate Generator Clock Divider This value is used as the divide-down number to generate the required SRG clock frequency. Default value is 1." group.long 0x30++0x3 line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP multi channel register 2" bitfld.long 0x00 9. " XMCME ,- . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " XPBBLK ,Transmit Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " XPABLK ,Transmit Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0.--1. " XMCM ,Transmit Multichannel Selection Enable - . - . - . - ." "Enabled,Disabled,EnabledMasked,DisabledMasked" group.long 0x34++0x3 line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP multi channel register 1" bitfld.long 0x00 9. " RMCME ,(legacy) - . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " RPBBLK ,Receive Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " RPABLK ,Receive Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0. " RMCM ,Receive Multichannel Selection Enable - . - ." "Enabled,Disabled" group.long 0x38++0x3 line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP receive channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " RCERA ,Receive Channel Enable RCERA n=0 Disables reception of n-th channel in an even-numbered block in partition A RCERA n=1 Enables reception of n-th channel in an even-numbered block in partition A" group.long 0x3C++0x3 line.long 0x00 "MCBSPLP_RCERB_REG,McBSPLP receive channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " RCERB ,Receive Channel Enable RCERB n=0 Disables reception of n-th channel in a even-numbered block in partition B RCERB n=1 Enables reception of n-th channel in a even-numbered block in partition B" group.long 0x40++0x3 line.long 0x00 "MCBSPLP_XCERA_REG,McBSPLP transmit channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " XCERA ,Transmit Channel Enable XCERA n=0 Disables transmission of n-th channel in an event-numbered block in partition A XCERA n=1 Enables transmission of n-th channel in an event-numbered block in partition A" group.long 0x44++0x3 line.long 0x00 "MCBSPLP_XCERB_REG,McBSPLP transmit channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " XCERB ,Transmit Channel Enable XCERB n=0 Disables transmission of n-th channel in an even-numbered block in partition B XCERB n=1 Enables transmission of n-th channel in an even-numbered block in partition B" group.long 0x48++0x3 line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP pin control register" bitfld.long 0x00 14. " IDLE_EN ,Idle enable. This bit allows stopping all the clocks in the MCBSPLP. (legacy) - . - ." "Running,ShutOff" bitfld.long 0x00 13. " XIOEN ,Transmit General Purpose I/O Mode only when XRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" bitfld.long 0x00 12. " RIOEN ,Receive General Purpose I/O Mode when RRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" textline " " bitfld.long 0x00 11. " FSXM ,Transmit Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 10. " FSRM ,Receive Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 9. " CLKXM ,Transmitter Clock Mode - . - ." "External,Internal" textline " " bitfld.long 0x00 8. " CLKRM ,Receiver Clock Mode - . - ." "External,Internal" bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG is: CLKG frequency = (Input clock frequency) / (CLKGDV + 1) SCLKME is used in conjunction with the CLKSM bit to select the input clock: - . - ." "0x0,0x1" bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input. (legacy) - . - ." "Low,High" textline " " bitfld.long 0x00 5. " DX_STAT ,DX pin status. Reflects value driven on to DX pin when selected as a general purpose output. (legacy) - . - ." "Low,High" bitfld.long 0x00 4. " DR_STAT ,DR pin status. Reflects value on DR pin when selected as a general purpose input. (legacy) - . - ." "Low,High" bitfld.long 0x00 3. " FSXP ,Transmit Frame-Synchronization Polarity - . - ." "High,Low" textline " " bitfld.long 0x00 2. " FSRP ,Receive Frame-Synchronization Polarity - . - ." "High,Low" bitfld.long 0x00 1. " CLKXP ,Transmit Clock Polarity - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 0. " CLKRP ,Receive Clock Polarity - . - ." "FallingEdge,RisingEdge" group.long 0x4C++0x3 line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP receive channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " RCERC ,Receive Channel Enable RCERC n=0 Disables reception of n-th channel in an even-numbered block in partition C RCERC n=1 Enables reception of n-th channel in an even-numbered block in partition C" group.long 0x50++0x3 line.long 0x00 "MCBSPLP_RCERD_REG,McBSPLP receive channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " RCERD ,Receive Channel Enable RCERD n=0 Disables reception of n-th channel in an even-numbered block in partition D RCERD n=1 Enables reception of n-th channel in an even-numbered block in partition D" group.long 0x54++0x3 line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP transmit channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " XCERC ,Transmit Channel Enable XCERC n=0 Disables transmission of n-th channel in an event-numbered block in partition C XCERC n=1 Enables transmission of n-th channel in an event-numbered block in partition C" group.long 0x58++0x3 line.long 0x00 "MCBSPLP_XCERD_REG,McBSPLP transmit channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " XCERD ,Transmit Channel Enable XCERD n=0 Disables transmission of n-th channel in an even-numbered block in partition D XCERD n=1 Enables transmission of n-th channel in an even-numbered block in partition D" group.long 0x5C++0x3 line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP receive channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " RCERE ,Receive Channel Enable RCERE n=0 Disables reception of n-th channel in an even-numbered block in partition E RCERE n=1 Enables reception of n-th channel in an even-numbered block in partition E" group.long 0x60++0x3 line.long 0x00 "MCBSPLP_RCERF_REG,McBSPLP receive channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " RCERF ,Receive Channel Enable RCERF n=0 Disables reception of n-th channel in an even-numbered block in partition F RCERF n=1 Enables reception of n-th channel in an even-numbered block in partition F" group.long 0x64++0x3 line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP transmit channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " XCERE ,Transmit Channel Enable XCERE n=0 Disables transmission of n-th channel in an event-numbered block in partition E XCERE n=1 Enables transmission of n-th channel in an event-numbered block in partition E" group.long 0x68++0x3 line.long 0x00 "MCBSPLP_XCERF_REG,McBSPLP transmit channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " XCERF ,Transmit Channel Enable XCERF n=0 Disables transmission of n-th channel in an even-numbered block in partition F XCERF n=1 Enables transmission of n-th channel in an even-numbered block in partition F" group.long 0x6C++0x3 line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP receive channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " RCERG ,Receive Channel Enable RCERG n=0 Disables reception of n-th channel in an even-numbered block in partition G RCERG n=1 Enables reception of n-th channel in an even-numbered block in partition G" group.long 0x70++0x3 line.long 0x00 "MCBSPLP_RCERH_REG,McBSPLP receive channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " RCERH ,Receive Channel Enable RCERH n=0 Disables reception of n-th channel in an even-numbered block in partition H RCERH n=1 Enables reception of n-th channel in an even-numbered block in partition H" group.long 0x74++0x3 line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP transmit channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " XCERG ,Transmit Channel Enable XCERG n=0 Disables transmission of n-th channel in an event-numbered block in partition G XCERG n=1 Enables transmission of n-th channel in an event-numbered block in partition G" group.long 0x78++0x3 line.long 0x00 "MCBSPLP_XCERH_REG,McBSPLP transmit channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " XCERH ,Transmit Channel Enable XCERH n=0 Disables transmission of n-th channel in an even-numbered block in partition H XCERH n=1 Enables transmission of n-th channel in an even-numbered block in partition H" rgroup.long 0x7C++0x3 line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision number register" hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number" group.long 0x80++0x3 line.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP receive interrupt clear" hexmask.long 0x00 0.--31. 1. " RINTCLR ,Read from this register will clear the IRQ generated by receive end-of-frame indication or MCBSPLP.FSR detection. Write to this register has no effect. (legacy)" group.long 0x84++0x3 line.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP transmit interrupt clear (legacy)" hexmask.long 0x00 0.--31. 1. " XINTCLR ,Read from this register will clear the IRQ generated by transmit end-of-frame indication or MCBSPLP.FSX detection. Write to this register has no effect." group.long 0x88++0x3 line.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP receive overflow interrupt clear" hexmask.long 0x00 0.--31. 1. " ROVFLCLR ,Read from this register will clear the IRQ generated by the receive overflow condition. Write to this register has no effect." group.long 0x8C++0x3 line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,- . - . - . - ." "CLKACT0,CLKACT1,CLKACT2,CLKACT3" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, req/ack control: - . - . - . - ." "SIDLEMODE0,SIDLEMODE1,SIDLEMODE2,SIDLEMODE3" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control: - . - ." "ENWK0,ENWK1" textline " " bitfld.long 0x00 1. " SOFTRESET ,McBSPLP global software reset - . - ." "NORESET,SOFTRESET" group.long 0x90++0x3 line.long 0x00 "MCBSPLP_THRSH2_REG,McBSPLP transmit buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of free locations inside transmit buffer are above or equal to the XTHRESHOLD value + 1. Also, this value .." group.long 0x94++0x3 line.long 0x00 "MCBSPLP_THRSH1_REG,McBSPLP receive buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of occupied locations inside receive buffer are above or equal to the RTHRESHOLD value + 1. Also, this valu.." group.long 0xA0++0x3 line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOF ,Transmit Buffer Empty at end of frame (XEMPTYEOF is set to 1 when a complete frame was transmitted and the transmit buffer is empty). - . - ." "XEMPTYEOF0,XEMPTYEOF1" bitfld.long 0x00 12. " XOVFLSTAT ,Transmit Buffer Overflow (XOVFLSTAT bit is set to 1 when transmit buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "XOVFLSTAT0,XOVFLSTAT1" bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit Buffer Underflow (XUNDFLSTAT bit is set to 1 when the transmit data buffer is empty new data is required to be transmitted). Writing 1 to this bit clears the bit. - . - ." "XUNDFLSTAT0,XUNDFLSTAT1" textline " " bitfld.long 0x00 10. " XRDY ,Transmit Buffer Threshold Reached (XRDY bit is set to 1 when the transmit buffer free locations are equal or above the THRSH2_REG value). Writing 1 to this bit clears the bit. - . - ." "XRDY0,XRDY1" bitfld.long 0x00 9. " XEOF ,Transmit End Of Frame (XEOF is set to 1 when a complete frame was transmitted). Writing 1 to this bit clears the bit. - . - ." "XEOF0,XEOF1" bitfld.long 0x00 8. " XFSX ,Transmit Frame Synchronization (XFSX bit is set to 1 when a new transmit frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "XFSX0,XFSX1" textline " " bitfld.long 0x00 7. " XSYNCERR ,Transmit Frame Synchronization Error (XSYNCERR is set to 1 when a transmit frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "XSYNCERR0,XSYNCERR1" bitfld.long 0x00 5. " ROVFLSTAT ,Receive Buffer Overflow (ROVFLSTAT bit is set to 1 when receive buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "ROVFLSTAT0,ROVFLSTAT1" bitfld.long 0x00 4. " RUNDFLSTAT ,Receive Buffer Underflow (RUNDFLSTAT bit is set to 1 when read operation is performed to the receive data register while receive buffer is empty; data read while underflow condition is undefined). Writing 1 to this bit clears the.." "RUNDFLSTAT0,RUNDFLSTAT1" textline " " bitfld.long 0x00 3. " RRDY ,Receive Buffer Threshold Reached (RRDY bit is set to 1 when the receive buffer occupied locations are equal or above the THRSH1_REG value). Writing 1 to this bit clears the bit. - . - ." "RRDY0,RRDY1" bitfld.long 0x00 2. " REOF ,Receive End Of Frame (REOF is set to 1 when a complete frame was received). Writing 1 to this bit clears the bit. - . - ." "REOF0,REOF1" bitfld.long 0x00 1. " RFSR ,Receive Frame Synchronization (RFSR bit is set to 1 when a new receive frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "RFSR0,RFSR1" textline " " bitfld.long 0x00 0. " RSYNCERR ,Receive Frame Synchronization Error (RSYNCERR is set to 1 when a receive frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "RSYNCERR0,RSYNCERR1" group.long 0xA4++0x3 line.long 0x00 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 12. " XOVFLEN ,Transmit Buffer Overflow enable bit. - . - ." "XOVFLEN0,XOVFLEN1" bitfld.long 0x00 11. " XUNDFLEN ,Transmit Buffer Underflow enable bit. - . - ." "XUNDFLEN0,XUNDFLEN1" textline " " bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame enable bit. - . - ." "XEOFEN0,XEOFEN1" bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization enable bit. - . - ." "XFSXEN0,XFSXEN1" textline " " bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 5. " ROVFLEN ,Receive Buffer Overflow enable bit. - . - ." "ROVFLEN0,ROVFLEN1" bitfld.long 0x00 4. " RUNDFLEN ,Receive Buffer Underflow enable bit. - . - ." "RUNDFLEN0,RUNDFLEN1" textline " " bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold enable bit. - . - ." "RRDYEN0,RRDYEN1" bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization enable bit. RW - . - ." "RFSREN0,RFSREN1" textline " " bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xA8++0x3 line.long 0x00 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable register" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit Buffer Empty at End Of Frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached WK enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame WK enable bit. - . - ." "XEOFEN0,XEOFEN1" textline " " bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization WK enable bit. - . - ." "XFSXEN0,XFSXEN1" bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error WK enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold wakeup enable bit. - . - ." "RRDYEN0,RRDYEN1" textline " " bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame WK enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization WK enable bit. - . - ." "RFSREN0,RFSREN1" bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error WK enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xAC++0x3 line.long 0x00 "MCBSPLP_XCCR_REG,McBSPLP transmit configuration control register" bitfld.long 0x00 15. " EXTCLKGATE ,External clock gating enable (CLKX and FSX master only). When this bit is set and the transmit clock and FSX are set as output, the CLKX is enabled when FSX is active plus 3 clock cycles after (clock is provided for FWID + 4 clock cycle.." "EXTCLKGATE0,EXTCLKGATE1" bitfld.long 0x00 14. " PPCONNECT ,Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output - . - ." "PPCONNECT0,PPCONNECT1" bitfld.long 0x00 12.--13. " DXENDLY ,When DXENA bit in SPCR1 is set to 1 this field selects the added delay as follow: - . - . - . - ." "DXENDLY0,DXENDLY1,DXENDLY2,DXENDLY3" textline " " bitfld.long 0x00 11. " XFULL_CYCLE ,Transmit full-cycle mode select. - . - ." "XFULL_CYCLE0,XFULL_CYCLE1" bitfld.long 0x00 5. " DLB ,Digital Loop-Back - . - ." "NODLB,DLB" bitfld.long 0x00 3. " XDMAEN ,Transmit DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during transmit reset. - . - ." "XDMAEN0,XDMAEN1" textline " " bitfld.long 0x00 0. " XDISABLE ,Transmit Disable bit. When this bit is set the transmit process will stop at the next frame boundary. - . - ." "XDSB0,XDSB1" group.long 0xB0++0x3 line.long 0x00 "MCBSPLP_RCCR_REG,McBSPLP receive configuration control register" bitfld.long 0x00 11. " RFULL_CYCLE ,Receive full-cycle mode select. - . - ." "RFULL_CYCLE0,RFULL_CYCLE1" bitfld.long 0x00 3. " RDMAEN ,Receive DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during receive reset. - . - ." "RDMAEN0,RDMAEN1" bitfld.long 0x00 0. " RDISABLE ,Receive Disable bit. When this bit is set the receive process will stop at the next frame boundary. - . - ." "RDSB0,RDSB1" rgroup.long 0xB4++0x3 line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP transmit buffer status" hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit Buffer Status (indicates the number of free locations inside transmit buffer). The XBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the number of free locations which are seen .." rgroup.long 0xB8++0x3 line.long 0x00 "MCBSPLP_RBUFFSTAT_REG,McBSPLP receive buffer status" hexmask.long.byte 0x00 0.--7. 1. " RBUFFSTAT ,Receive Buffer Status (indicates the number of occupied locations inside receive buffer). The RBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the real number of the occupied locations .." tree.end tree "MCBSP4_L4_PERInterconnect" base ad:0x48096000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "MCBSPLP_DRR_REG,McBSPLP data receive register" hexmask.long 0x00 0.--31. 1. " DRR ,Data receive register" wgroup.long 0x8++0x3 line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP data transmit register" hexmask.long 0x00 0.--31. 1. " DXR ,Data transmit register" group.long 0x10++0x3 line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP serial port control register 2" bitfld.long 0x00 9. " FREE ,Free Running Mode (When this bit is set, the module ignores the Msuspend input) - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " SOFT ,Soft Bit - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " FRST ,Frame-Sync Generator Reset - . - ." "Reset,Generated" textline " " bitfld.long 0x00 6. " GRST ,Sample-Rate Generator Reset - . - ." "Reset,PullOut" bitfld.long 0x00 4.--5. " XINTM ,Transmit Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedXSYNCERR" bitfld.long 0x00 3. " XSYNCERR ,Transmit Synchronization Error (writing 0 to this bit clear the legacy transmit interrupt if asserted due to XSYNCERR condition) - . - ." "No,Detected" textline " " bitfld.long 0x00 2. " XEMPTY ,Transmit Shift Register XSR Empty - . - ." "Empty,NotEmpty" bitfld.long 0x00 1. " XRDY ,Transmitter ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " XRST ,Transmitter reset. This resets and enables the transmitter. - . - ." "Disabled,Enabled" group.long 0x14++0x3 line.long 0x00 "MCBSPLP_SPCR1_REG,McBSPLP serial port control register 1" bitfld.long 0x00 15. " ALB ,Analog Loopback Mode - . - ." "Disabled,Enabled" bitfld.long 0x00 13.--14. " RJUST ,Receive Sign-Extension and Justification Mode - . - . - . - ." "RJ,RJsigned,LJ,?..." bitfld.long 0x00 7. " DXENA ,DX Enabler - . - ." "Off,On" textline " " bitfld.long 0x00 4.--5. " RINTM ,Receive Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedRSYNCCERR" bitfld.long 0x00 3. " RSYNCERR ,Receive Synchronization Error (writing 0 to this bit clear the legacy receive interrupt if asserted due to RSYNCERR condition) - . - ." "No,Detected" bitfld.long 0x00 2. " RFULL ,Receive Shift Register (RSR]) Full - . - ." "NotOverrun,NotRead" textline " " bitfld.long 0x00 1. " RRDY ,Receiver Ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " RRST ,Receiver reset. This resets and enables the receiver. - . - ." "Disabled,Enabled" group.long 0x18++0x3 line.long 0x00 "MCBSPLP_RCR2_REG,McBSPLP receive control register 2" bitfld.long 0x00 15. " RPHASE ,Receive Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN2 ,Receive Frame Length 2 Single-phase frame selected: RFRLEN2=don't care Dual-phase frame selected: RFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " RWDLEN2 ,Receive Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " RREVERSE ,Receive reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " RDATDLY ,Receive Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x1C++0x3 line.long 0x00 "MCBSPLP_RCR1_REG,McBSPLP receive control register 1" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN1 ,Receive Frame Length 1 Single-phase frame selected: RFRLEN1=000 0000 - 1 word per frame RFRLEN1=000 0001 - 2 words per frame RFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: RFRLEN1=000 0000 - 1 word per phase (other va.." bitfld.long 0x00 5.--7. " RWDLEN1 ,Receive Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x20++0x3 line.long 0x00 "MCBSPLP_XCR2_REG,McBSPLP transmit control register 2" bitfld.long 0x00 15. " XPHASE ,Transmit Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN2 ,Transmit Frame Length 2 Single-phase frame selected: XFRLEN2=don't care Dual-phase frame selected: XFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " XWDLEN2 ,Transmit Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " XREVERSE ,Transmit reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " XDATDLY ,Transmit Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x24++0x3 line.long 0x00 "MCBSPLP_XCR1_REG,McBSPLP transmit control register 1" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN1 ,Transmit Frame Length 1 Single-phase frame selected: XFRLEN1=000 0000 - 1 word per frame XFRLEN1=000 0001 - 2 words per frame XFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: XFRLEN1=000 0000 - 1 word per phase (other v.." bitfld.long 0x00 5.--7. " XWDLEN1 ,Transmit Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x28++0x3 line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP sample rate generator register 2" bitfld.long 0x00 15. " GSYNC ,- . - ." "FreeRunning,Running" bitfld.long 0x00 14. " CLKSP ,CLKS Polarity Clock Edge Select Only used when the external clock CLKS drives the SRG clock (CLKSM=0). - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 13. " CLKSM ,McBSPLP Sample Rate Generator Clock Mode - . - ." "0x0,0x1" textline " " bitfld.long 0x00 12. " FSGM ,Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 in the PCR. - . - ." "TransmitAndIgnore,Transmit" hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame Period. This field plus 1 determines when the next frame-sync signal becomes active. Range: 1 to 4096 CLKG periods" group.long 0x2C++0x3 line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP sample rate generator register 1" hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame Width. This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period. Range: 1 to 256 CLKG periods." hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample Rate Generator Clock Divider This value is used as the divide-down number to generate the required SRG clock frequency. Default value is 1." group.long 0x30++0x3 line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP multi channel register 2" bitfld.long 0x00 9. " XMCME ,- . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " XPBBLK ,Transmit Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " XPABLK ,Transmit Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0.--1. " XMCM ,Transmit Multichannel Selection Enable - . - . - . - ." "Enabled,Disabled,EnabledMasked,DisabledMasked" group.long 0x34++0x3 line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP multi channel register 1" bitfld.long 0x00 9. " RMCME ,(legacy) - . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " RPBBLK ,Receive Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " RPABLK ,Receive Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0. " RMCM ,Receive Multichannel Selection Enable - . - ." "Enabled,Disabled" group.long 0x38++0x3 line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP receive channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " RCERA ,Receive Channel Enable RCERA n=0 Disables reception of n-th channel in an even-numbered block in partition A RCERA n=1 Enables reception of n-th channel in an even-numbered block in partition A" group.long 0x3C++0x3 line.long 0x00 "MCBSPLP_RCERB_REG,McBSPLP receive channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " RCERB ,Receive Channel Enable RCERB n=0 Disables reception of n-th channel in a even-numbered block in partition B RCERB n=1 Enables reception of n-th channel in a even-numbered block in partition B" group.long 0x40++0x3 line.long 0x00 "MCBSPLP_XCERA_REG,McBSPLP transmit channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " XCERA ,Transmit Channel Enable XCERA n=0 Disables transmission of n-th channel in an event-numbered block in partition A XCERA n=1 Enables transmission of n-th channel in an event-numbered block in partition A" group.long 0x44++0x3 line.long 0x00 "MCBSPLP_XCERB_REG,McBSPLP transmit channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " XCERB ,Transmit Channel Enable XCERB n=0 Disables transmission of n-th channel in an even-numbered block in partition B XCERB n=1 Enables transmission of n-th channel in an even-numbered block in partition B" group.long 0x48++0x3 line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP pin control register" bitfld.long 0x00 14. " IDLE_EN ,Idle enable. This bit allows stopping all the clocks in the MCBSPLP. (legacy) - . - ." "Running,ShutOff" bitfld.long 0x00 13. " XIOEN ,Transmit General Purpose I/O Mode only when XRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" bitfld.long 0x00 12. " RIOEN ,Receive General Purpose I/O Mode when RRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" textline " " bitfld.long 0x00 11. " FSXM ,Transmit Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 10. " FSRM ,Receive Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 9. " CLKXM ,Transmitter Clock Mode - . - ." "External,Internal" textline " " bitfld.long 0x00 8. " CLKRM ,Receiver Clock Mode - . - ." "External,Internal" bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG is: CLKG frequency = (Input clock frequency) / (CLKGDV + 1) SCLKME is used in conjunction with the CLKSM bit to select the input clock: - . - ." "0x0,0x1" bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input. (legacy) - . - ." "Low,High" textline " " bitfld.long 0x00 5. " DX_STAT ,DX pin status. Reflects value driven on to DX pin when selected as a general purpose output. (legacy) - . - ." "Low,High" bitfld.long 0x00 4. " DR_STAT ,DR pin status. Reflects value on DR pin when selected as a general purpose input. (legacy) - . - ." "Low,High" bitfld.long 0x00 3. " FSXP ,Transmit Frame-Synchronization Polarity - . - ." "High,Low" textline " " bitfld.long 0x00 2. " FSRP ,Receive Frame-Synchronization Polarity - . - ." "High,Low" bitfld.long 0x00 1. " CLKXP ,Transmit Clock Polarity - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 0. " CLKRP ,Receive Clock Polarity - . - ." "FallingEdge,RisingEdge" group.long 0x4C++0x3 line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP receive channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " RCERC ,Receive Channel Enable RCERC n=0 Disables reception of n-th channel in an even-numbered block in partition C RCERC n=1 Enables reception of n-th channel in an even-numbered block in partition C" group.long 0x50++0x3 line.long 0x00 "MCBSPLP_RCERD_REG,McBSPLP receive channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " RCERD ,Receive Channel Enable RCERD n=0 Disables reception of n-th channel in an even-numbered block in partition D RCERD n=1 Enables reception of n-th channel in an even-numbered block in partition D" group.long 0x54++0x3 line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP transmit channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " XCERC ,Transmit Channel Enable XCERC n=0 Disables transmission of n-th channel in an event-numbered block in partition C XCERC n=1 Enables transmission of n-th channel in an event-numbered block in partition C" group.long 0x58++0x3 line.long 0x00 "MCBSPLP_XCERD_REG,McBSPLP transmit channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " XCERD ,Transmit Channel Enable XCERD n=0 Disables transmission of n-th channel in an even-numbered block in partition D XCERD n=1 Enables transmission of n-th channel in an even-numbered block in partition D" group.long 0x5C++0x3 line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP receive channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " RCERE ,Receive Channel Enable RCERE n=0 Disables reception of n-th channel in an even-numbered block in partition E RCERE n=1 Enables reception of n-th channel in an even-numbered block in partition E" group.long 0x60++0x3 line.long 0x00 "MCBSPLP_RCERF_REG,McBSPLP receive channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " RCERF ,Receive Channel Enable RCERF n=0 Disables reception of n-th channel in an even-numbered block in partition F RCERF n=1 Enables reception of n-th channel in an even-numbered block in partition F" group.long 0x64++0x3 line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP transmit channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " XCERE ,Transmit Channel Enable XCERE n=0 Disables transmission of n-th channel in an event-numbered block in partition E XCERE n=1 Enables transmission of n-th channel in an event-numbered block in partition E" group.long 0x68++0x3 line.long 0x00 "MCBSPLP_XCERF_REG,McBSPLP transmit channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " XCERF ,Transmit Channel Enable XCERF n=0 Disables transmission of n-th channel in an even-numbered block in partition F XCERF n=1 Enables transmission of n-th channel in an even-numbered block in partition F" group.long 0x6C++0x3 line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP receive channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " RCERG ,Receive Channel Enable RCERG n=0 Disables reception of n-th channel in an even-numbered block in partition G RCERG n=1 Enables reception of n-th channel in an even-numbered block in partition G" group.long 0x70++0x3 line.long 0x00 "MCBSPLP_RCERH_REG,McBSPLP receive channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " RCERH ,Receive Channel Enable RCERH n=0 Disables reception of n-th channel in an even-numbered block in partition H RCERH n=1 Enables reception of n-th channel in an even-numbered block in partition H" group.long 0x74++0x3 line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP transmit channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " XCERG ,Transmit Channel Enable XCERG n=0 Disables transmission of n-th channel in an event-numbered block in partition G XCERG n=1 Enables transmission of n-th channel in an event-numbered block in partition G" group.long 0x78++0x3 line.long 0x00 "MCBSPLP_XCERH_REG,McBSPLP transmit channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " XCERH ,Transmit Channel Enable XCERH n=0 Disables transmission of n-th channel in an even-numbered block in partition H XCERH n=1 Enables transmission of n-th channel in an even-numbered block in partition H" rgroup.long 0x7C++0x3 line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision number register" hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number" group.long 0x80++0x3 line.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP receive interrupt clear" hexmask.long 0x00 0.--31. 1. " RINTCLR ,Read from this register will clear the IRQ generated by receive end-of-frame indication or MCBSPLP.FSR detection. Write to this register has no effect. (legacy)" group.long 0x84++0x3 line.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP transmit interrupt clear (legacy)" hexmask.long 0x00 0.--31. 1. " XINTCLR ,Read from this register will clear the IRQ generated by transmit end-of-frame indication or MCBSPLP.FSX detection. Write to this register has no effect." group.long 0x88++0x3 line.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP receive overflow interrupt clear" hexmask.long 0x00 0.--31. 1. " ROVFLCLR ,Read from this register will clear the IRQ generated by the receive overflow condition. Write to this register has no effect." group.long 0x8C++0x3 line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,- . - . - . - ." "CLKACT0,CLKACT1,CLKACT2,CLKACT3" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, req/ack control: - . - . - . - ." "SIDLEMODE0,SIDLEMODE1,SIDLEMODE2,SIDLEMODE3" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control: - . - ." "ENWK0,ENWK1" textline " " bitfld.long 0x00 1. " SOFTRESET ,McBSPLP global software reset - . - ." "NORESET,SOFTRESET" group.long 0x90++0x3 line.long 0x00 "MCBSPLP_THRSH2_REG,McBSPLP transmit buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of free locations inside transmit buffer are above or equal to the XTHRESHOLD value + 1. Also, this value .." group.long 0x94++0x3 line.long 0x00 "MCBSPLP_THRSH1_REG,McBSPLP receive buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of occupied locations inside receive buffer are above or equal to the RTHRESHOLD value + 1. Also, this valu.." group.long 0xA0++0x3 line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOF ,Transmit Buffer Empty at end of frame (XEMPTYEOF is set to 1 when a complete frame was transmitted and the transmit buffer is empty). - . - ." "XEMPTYEOF0,XEMPTYEOF1" bitfld.long 0x00 12. " XOVFLSTAT ,Transmit Buffer Overflow (XOVFLSTAT bit is set to 1 when transmit buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "XOVFLSTAT0,XOVFLSTAT1" bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit Buffer Underflow (XUNDFLSTAT bit is set to 1 when the transmit data buffer is empty new data is required to be transmitted). Writing 1 to this bit clears the bit. - . - ." "XUNDFLSTAT0,XUNDFLSTAT1" textline " " bitfld.long 0x00 10. " XRDY ,Transmit Buffer Threshold Reached (XRDY bit is set to 1 when the transmit buffer free locations are equal or above the THRSH2_REG value). Writing 1 to this bit clears the bit. - . - ." "XRDY0,XRDY1" bitfld.long 0x00 9. " XEOF ,Transmit End Of Frame (XEOF is set to 1 when a complete frame was transmitted). Writing 1 to this bit clears the bit. - . - ." "XEOF0,XEOF1" bitfld.long 0x00 8. " XFSX ,Transmit Frame Synchronization (XFSX bit is set to 1 when a new transmit frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "XFSX0,XFSX1" textline " " bitfld.long 0x00 7. " XSYNCERR ,Transmit Frame Synchronization Error (XSYNCERR is set to 1 when a transmit frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "XSYNCERR0,XSYNCERR1" bitfld.long 0x00 5. " ROVFLSTAT ,Receive Buffer Overflow (ROVFLSTAT bit is set to 1 when receive buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "ROVFLSTAT0,ROVFLSTAT1" bitfld.long 0x00 4. " RUNDFLSTAT ,Receive Buffer Underflow (RUNDFLSTAT bit is set to 1 when read operation is performed to the receive data register while receive buffer is empty; data read while underflow condition is undefined). Writing 1 to this bit clears the.." "RUNDFLSTAT0,RUNDFLSTAT1" textline " " bitfld.long 0x00 3. " RRDY ,Receive Buffer Threshold Reached (RRDY bit is set to 1 when the receive buffer occupied locations are equal or above the THRSH1_REG value). Writing 1 to this bit clears the bit. - . - ." "RRDY0,RRDY1" bitfld.long 0x00 2. " REOF ,Receive End Of Frame (REOF is set to 1 when a complete frame was received). Writing 1 to this bit clears the bit. - . - ." "REOF0,REOF1" bitfld.long 0x00 1. " RFSR ,Receive Frame Synchronization (RFSR bit is set to 1 when a new receive frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "RFSR0,RFSR1" textline " " bitfld.long 0x00 0. " RSYNCERR ,Receive Frame Synchronization Error (RSYNCERR is set to 1 when a receive frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "RSYNCERR0,RSYNCERR1" group.long 0xA4++0x3 line.long 0x00 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 12. " XOVFLEN ,Transmit Buffer Overflow enable bit. - . - ." "XOVFLEN0,XOVFLEN1" bitfld.long 0x00 11. " XUNDFLEN ,Transmit Buffer Underflow enable bit. - . - ." "XUNDFLEN0,XUNDFLEN1" textline " " bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame enable bit. - . - ." "XEOFEN0,XEOFEN1" bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization enable bit. - . - ." "XFSXEN0,XFSXEN1" textline " " bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 5. " ROVFLEN ,Receive Buffer Overflow enable bit. - . - ." "ROVFLEN0,ROVFLEN1" bitfld.long 0x00 4. " RUNDFLEN ,Receive Buffer Underflow enable bit. - . - ." "RUNDFLEN0,RUNDFLEN1" textline " " bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold enable bit. - . - ." "RRDYEN0,RRDYEN1" bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization enable bit. RW - . - ." "RFSREN0,RFSREN1" textline " " bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xA8++0x3 line.long 0x00 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable register" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit Buffer Empty at End Of Frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached WK enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame WK enable bit. - . - ." "XEOFEN0,XEOFEN1" textline " " bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization WK enable bit. - . - ." "XFSXEN0,XFSXEN1" bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error WK enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold wakeup enable bit. - . - ." "RRDYEN0,RRDYEN1" textline " " bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame WK enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization WK enable bit. - . - ." "RFSREN0,RFSREN1" bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error WK enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xAC++0x3 line.long 0x00 "MCBSPLP_XCCR_REG,McBSPLP transmit configuration control register" bitfld.long 0x00 15. " EXTCLKGATE ,External clock gating enable (CLKX and FSX master only). When this bit is set and the transmit clock and FSX are set as output, the CLKX is enabled when FSX is active plus 3 clock cycles after (clock is provided for FWID + 4 clock cycle.." "EXTCLKGATE0,EXTCLKGATE1" bitfld.long 0x00 14. " PPCONNECT ,Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output - . - ." "PPCONNECT0,PPCONNECT1" bitfld.long 0x00 12.--13. " DXENDLY ,When DXENA bit in SPCR1 is set to 1 this field selects the added delay as follow: - . - . - . - ." "DXENDLY0,DXENDLY1,DXENDLY2,DXENDLY3" textline " " bitfld.long 0x00 11. " XFULL_CYCLE ,Transmit full-cycle mode select. - . - ." "XFULL_CYCLE0,XFULL_CYCLE1" bitfld.long 0x00 5. " DLB ,Digital Loop-Back - . - ." "NODLB,DLB" bitfld.long 0x00 3. " XDMAEN ,Transmit DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during transmit reset. - . - ." "XDMAEN0,XDMAEN1" textline " " bitfld.long 0x00 0. " XDISABLE ,Transmit Disable bit. When this bit is set the transmit process will stop at the next frame boundary. - . - ." "XDSB0,XDSB1" group.long 0xB0++0x3 line.long 0x00 "MCBSPLP_RCCR_REG,McBSPLP receive configuration control register" bitfld.long 0x00 11. " RFULL_CYCLE ,Receive full-cycle mode select. - . - ." "RFULL_CYCLE0,RFULL_CYCLE1" bitfld.long 0x00 3. " RDMAEN ,Receive DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during receive reset. - . - ." "RDMAEN0,RDMAEN1" bitfld.long 0x00 0. " RDISABLE ,Receive Disable bit. When this bit is set the receive process will stop at the next frame boundary. - . - ." "RDSB0,RDSB1" rgroup.long 0xB4++0x3 line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP transmit buffer status" hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit Buffer Status (indicates the number of free locations inside transmit buffer). The XBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the number of free locations which are seen .." rgroup.long 0xB8++0x3 line.long 0x00 "MCBSPLP_RBUFFSTAT_REG,McBSPLP receive buffer status" hexmask.long.byte 0x00 0.--7. 1. " RBUFFSTAT ,Receive Buffer Status (indicates the number of occupied locations inside receive buffer). The RBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the real number of the occupied locations .." tree.end tree "MCBSP1_L3Interconnect" base ad:0x49022000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "MCBSPLP_DRR_REG,McBSPLP data receive register" hexmask.long 0x00 0.--31. 1. " DRR ,Data receive register" wgroup.long 0x8++0x3 line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP data transmit register" hexmask.long 0x00 0.--31. 1. " DXR ,Data transmit register" group.long 0x10++0x3 line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP serial port control register 2" bitfld.long 0x00 9. " FREE ,Free Running Mode (When this bit is set, the module ignores the Msuspend input) - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " SOFT ,Soft Bit - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " FRST ,Frame-Sync Generator Reset - . - ." "Reset,Generated" textline " " bitfld.long 0x00 6. " GRST ,Sample-Rate Generator Reset - . - ." "Reset,PullOut" bitfld.long 0x00 4.--5. " XINTM ,Transmit Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedXSYNCERR" bitfld.long 0x00 3. " XSYNCERR ,Transmit Synchronization Error (writing 0 to this bit clear the legacy transmit interrupt if asserted due to XSYNCERR condition) - . - ." "No,Detected" textline " " bitfld.long 0x00 2. " XEMPTY ,Transmit Shift Register XSR Empty - . - ." "Empty,NotEmpty" bitfld.long 0x00 1. " XRDY ,Transmitter ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " XRST ,Transmitter reset. This resets and enables the transmitter. - . - ." "Disabled,Enabled" group.long 0x14++0x3 line.long 0x00 "MCBSPLP_SPCR1_REG,McBSPLP serial port control register 1" bitfld.long 0x00 15. " ALB ,Analog Loopback Mode - . - ." "Disabled,Enabled" bitfld.long 0x00 13.--14. " RJUST ,Receive Sign-Extension and Justification Mode - . - . - . - ." "RJ,RJsigned,LJ,?..." bitfld.long 0x00 7. " DXENA ,DX Enabler - . - ." "Off,On" textline " " bitfld.long 0x00 4.--5. " RINTM ,Receive Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedRSYNCCERR" bitfld.long 0x00 3. " RSYNCERR ,Receive Synchronization Error (writing 0 to this bit clear the legacy receive interrupt if asserted due to RSYNCERR condition) - . - ." "No,Detected" bitfld.long 0x00 2. " RFULL ,Receive Shift Register (RSR]) Full - . - ." "NotOverrun,NotRead" textline " " bitfld.long 0x00 1. " RRDY ,Receiver Ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " RRST ,Receiver reset. This resets and enables the receiver. - . - ." "Disabled,Enabled" group.long 0x18++0x3 line.long 0x00 "MCBSPLP_RCR2_REG,McBSPLP receive control register 2" bitfld.long 0x00 15. " RPHASE ,Receive Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN2 ,Receive Frame Length 2 Single-phase frame selected: RFRLEN2=don't care Dual-phase frame selected: RFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " RWDLEN2 ,Receive Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " RREVERSE ,Receive reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " RDATDLY ,Receive Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x1C++0x3 line.long 0x00 "MCBSPLP_RCR1_REG,McBSPLP receive control register 1" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN1 ,Receive Frame Length 1 Single-phase frame selected: RFRLEN1=000 0000 - 1 word per frame RFRLEN1=000 0001 - 2 words per frame RFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: RFRLEN1=000 0000 - 1 word per phase (other va.." bitfld.long 0x00 5.--7. " RWDLEN1 ,Receive Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x20++0x3 line.long 0x00 "MCBSPLP_XCR2_REG,McBSPLP transmit control register 2" bitfld.long 0x00 15. " XPHASE ,Transmit Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN2 ,Transmit Frame Length 2 Single-phase frame selected: XFRLEN2=don't care Dual-phase frame selected: XFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " XWDLEN2 ,Transmit Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " XREVERSE ,Transmit reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " XDATDLY ,Transmit Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x24++0x3 line.long 0x00 "MCBSPLP_XCR1_REG,McBSPLP transmit control register 1" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN1 ,Transmit Frame Length 1 Single-phase frame selected: XFRLEN1=000 0000 - 1 word per frame XFRLEN1=000 0001 - 2 words per frame XFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: XFRLEN1=000 0000 - 1 word per phase (other v.." bitfld.long 0x00 5.--7. " XWDLEN1 ,Transmit Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x28++0x3 line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP sample rate generator register 2" bitfld.long 0x00 15. " GSYNC ,- . - ." "FreeRunning,Running" bitfld.long 0x00 14. " CLKSP ,CLKS Polarity Clock Edge Select Only used when the external clock CLKS drives the SRG clock (CLKSM=0). - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 13. " CLKSM ,McBSPLP Sample Rate Generator Clock Mode - . - ." "0x0,0x1" textline " " bitfld.long 0x00 12. " FSGM ,Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 in the PCR. - . - ." "TransmitAndIgnore,Transmit" hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame Period. This field plus 1 determines when the next frame-sync signal becomes active. Range: 1 to 4096 CLKG periods" group.long 0x2C++0x3 line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP sample rate generator register 1" hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame Width. This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period. Range: 1 to 256 CLKG periods." hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample Rate Generator Clock Divider This value is used as the divide-down number to generate the required SRG clock frequency. Default value is 1." group.long 0x30++0x3 line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP multi channel register 2" bitfld.long 0x00 9. " XMCME ,- . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " XPBBLK ,Transmit Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " XPABLK ,Transmit Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0.--1. " XMCM ,Transmit Multichannel Selection Enable - . - . - . - ." "Enabled,Disabled,EnabledMasked,DisabledMasked" group.long 0x34++0x3 line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP multi channel register 1" bitfld.long 0x00 9. " RMCME ,(legacy) - . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " RPBBLK ,Receive Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " RPABLK ,Receive Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0. " RMCM ,Receive Multichannel Selection Enable - . - ." "Enabled,Disabled" group.long 0x38++0x3 line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP receive channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " RCERA ,Receive Channel Enable RCERA n=0 Disables reception of n-th channel in an even-numbered block in partition A RCERA n=1 Enables reception of n-th channel in an even-numbered block in partition A" group.long 0x3C++0x3 line.long 0x00 "MCBSPLP_RCERB_REG,McBSPLP receive channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " RCERB ,Receive Channel Enable RCERB n=0 Disables reception of n-th channel in a even-numbered block in partition B RCERB n=1 Enables reception of n-th channel in a even-numbered block in partition B" group.long 0x40++0x3 line.long 0x00 "MCBSPLP_XCERA_REG,McBSPLP transmit channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " XCERA ,Transmit Channel Enable XCERA n=0 Disables transmission of n-th channel in an event-numbered block in partition A XCERA n=1 Enables transmission of n-th channel in an event-numbered block in partition A" group.long 0x44++0x3 line.long 0x00 "MCBSPLP_XCERB_REG,McBSPLP transmit channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " XCERB ,Transmit Channel Enable XCERB n=0 Disables transmission of n-th channel in an even-numbered block in partition B XCERB n=1 Enables transmission of n-th channel in an even-numbered block in partition B" group.long 0x48++0x3 line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP pin control register" bitfld.long 0x00 14. " IDLE_EN ,Idle enable. This bit allows stopping all the clocks in the MCBSPLP. (legacy) - . - ." "Running,ShutOff" bitfld.long 0x00 13. " XIOEN ,Transmit General Purpose I/O Mode only when XRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" bitfld.long 0x00 12. " RIOEN ,Receive General Purpose I/O Mode when RRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" textline " " bitfld.long 0x00 11. " FSXM ,Transmit Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 10. " FSRM ,Receive Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 9. " CLKXM ,Transmitter Clock Mode - . - ." "External,Internal" textline " " bitfld.long 0x00 8. " CLKRM ,Receiver Clock Mode - . - ." "External,Internal" bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG is: CLKG frequency = (Input clock frequency) / (CLKGDV + 1) SCLKME is used in conjunction with the CLKSM bit to select the input clock: - . - ." "0x0,0x1" bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input. (legacy) - . - ." "Low,High" textline " " bitfld.long 0x00 5. " DX_STAT ,DX pin status. Reflects value driven on to DX pin when selected as a general purpose output. (legacy) - . - ." "Low,High" bitfld.long 0x00 4. " DR_STAT ,DR pin status. Reflects value on DR pin when selected as a general purpose input. (legacy) - . - ." "Low,High" bitfld.long 0x00 3. " FSXP ,Transmit Frame-Synchronization Polarity - . - ." "High,Low" textline " " bitfld.long 0x00 2. " FSRP ,Receive Frame-Synchronization Polarity - . - ." "High,Low" bitfld.long 0x00 1. " CLKXP ,Transmit Clock Polarity - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 0. " CLKRP ,Receive Clock Polarity - . - ." "FallingEdge,RisingEdge" group.long 0x4C++0x3 line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP receive channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " RCERC ,Receive Channel Enable RCERC n=0 Disables reception of n-th channel in an even-numbered block in partition C RCERC n=1 Enables reception of n-th channel in an even-numbered block in partition C" group.long 0x50++0x3 line.long 0x00 "MCBSPLP_RCERD_REG,McBSPLP receive channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " RCERD ,Receive Channel Enable RCERD n=0 Disables reception of n-th channel in an even-numbered block in partition D RCERD n=1 Enables reception of n-th channel in an even-numbered block in partition D" group.long 0x54++0x3 line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP transmit channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " XCERC ,Transmit Channel Enable XCERC n=0 Disables transmission of n-th channel in an event-numbered block in partition C XCERC n=1 Enables transmission of n-th channel in an event-numbered block in partition C" group.long 0x58++0x3 line.long 0x00 "MCBSPLP_XCERD_REG,McBSPLP transmit channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " XCERD ,Transmit Channel Enable XCERD n=0 Disables transmission of n-th channel in an even-numbered block in partition D XCERD n=1 Enables transmission of n-th channel in an even-numbered block in partition D" group.long 0x5C++0x3 line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP receive channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " RCERE ,Receive Channel Enable RCERE n=0 Disables reception of n-th channel in an even-numbered block in partition E RCERE n=1 Enables reception of n-th channel in an even-numbered block in partition E" group.long 0x60++0x3 line.long 0x00 "MCBSPLP_RCERF_REG,McBSPLP receive channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " RCERF ,Receive Channel Enable RCERF n=0 Disables reception of n-th channel in an even-numbered block in partition F RCERF n=1 Enables reception of n-th channel in an even-numbered block in partition F" group.long 0x64++0x3 line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP transmit channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " XCERE ,Transmit Channel Enable XCERE n=0 Disables transmission of n-th channel in an event-numbered block in partition E XCERE n=1 Enables transmission of n-th channel in an event-numbered block in partition E" group.long 0x68++0x3 line.long 0x00 "MCBSPLP_XCERF_REG,McBSPLP transmit channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " XCERF ,Transmit Channel Enable XCERF n=0 Disables transmission of n-th channel in an even-numbered block in partition F XCERF n=1 Enables transmission of n-th channel in an even-numbered block in partition F" group.long 0x6C++0x3 line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP receive channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " RCERG ,Receive Channel Enable RCERG n=0 Disables reception of n-th channel in an even-numbered block in partition G RCERG n=1 Enables reception of n-th channel in an even-numbered block in partition G" group.long 0x70++0x3 line.long 0x00 "MCBSPLP_RCERH_REG,McBSPLP receive channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " RCERH ,Receive Channel Enable RCERH n=0 Disables reception of n-th channel in an even-numbered block in partition H RCERH n=1 Enables reception of n-th channel in an even-numbered block in partition H" group.long 0x74++0x3 line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP transmit channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " XCERG ,Transmit Channel Enable XCERG n=0 Disables transmission of n-th channel in an event-numbered block in partition G XCERG n=1 Enables transmission of n-th channel in an event-numbered block in partition G" group.long 0x78++0x3 line.long 0x00 "MCBSPLP_XCERH_REG,McBSPLP transmit channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " XCERH ,Transmit Channel Enable XCERH n=0 Disables transmission of n-th channel in an even-numbered block in partition H XCERH n=1 Enables transmission of n-th channel in an even-numbered block in partition H" rgroup.long 0x7C++0x3 line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision number register" hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number" group.long 0x80++0x3 line.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP receive interrupt clear" hexmask.long 0x00 0.--31. 1. " RINTCLR ,Read from this register will clear the IRQ generated by receive end-of-frame indication or MCBSPLP.FSR detection. Write to this register has no effect. (legacy)" group.long 0x84++0x3 line.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP transmit interrupt clear (legacy)" hexmask.long 0x00 0.--31. 1. " XINTCLR ,Read from this register will clear the IRQ generated by transmit end-of-frame indication or MCBSPLP.FSX detection. Write to this register has no effect." group.long 0x88++0x3 line.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP receive overflow interrupt clear" hexmask.long 0x00 0.--31. 1. " ROVFLCLR ,Read from this register will clear the IRQ generated by the receive overflow condition. Write to this register has no effect." group.long 0x8C++0x3 line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,- . - . - . - ." "CLKACT0,CLKACT1,CLKACT2,CLKACT3" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, req/ack control: - . - . - . - ." "SIDLEMODE0,SIDLEMODE1,SIDLEMODE2,SIDLEMODE3" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control: - . - ." "ENWK0,ENWK1" textline " " bitfld.long 0x00 1. " SOFTRESET ,McBSPLP global software reset - . - ." "NORESET,SOFTRESET" group.long 0x90++0x3 line.long 0x00 "MCBSPLP_THRSH2_REG,McBSPLP transmit buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of free locations inside transmit buffer are above or equal to the XTHRESHOLD value + 1. Also, this value .." group.long 0x94++0x3 line.long 0x00 "MCBSPLP_THRSH1_REG,McBSPLP receive buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of occupied locations inside receive buffer are above or equal to the RTHRESHOLD value + 1. Also, this valu.." group.long 0xA0++0x3 line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOF ,Transmit Buffer Empty at end of frame (XEMPTYEOF is set to 1 when a complete frame was transmitted and the transmit buffer is empty). - . - ." "XEMPTYEOF0,XEMPTYEOF1" bitfld.long 0x00 12. " XOVFLSTAT ,Transmit Buffer Overflow (XOVFLSTAT bit is set to 1 when transmit buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "XOVFLSTAT0,XOVFLSTAT1" bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit Buffer Underflow (XUNDFLSTAT bit is set to 1 when the transmit data buffer is empty new data is required to be transmitted). Writing 1 to this bit clears the bit. - . - ." "XUNDFLSTAT0,XUNDFLSTAT1" textline " " bitfld.long 0x00 10. " XRDY ,Transmit Buffer Threshold Reached (XRDY bit is set to 1 when the transmit buffer free locations are equal or above the THRSH2_REG value). Writing 1 to this bit clears the bit. - . - ." "XRDY0,XRDY1" bitfld.long 0x00 9. " XEOF ,Transmit End Of Frame (XEOF is set to 1 when a complete frame was transmitted). Writing 1 to this bit clears the bit. - . - ." "XEOF0,XEOF1" bitfld.long 0x00 8. " XFSX ,Transmit Frame Synchronization (XFSX bit is set to 1 when a new transmit frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "XFSX0,XFSX1" textline " " bitfld.long 0x00 7. " XSYNCERR ,Transmit Frame Synchronization Error (XSYNCERR is set to 1 when a transmit frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "XSYNCERR0,XSYNCERR1" bitfld.long 0x00 5. " ROVFLSTAT ,Receive Buffer Overflow (ROVFLSTAT bit is set to 1 when receive buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "ROVFLSTAT0,ROVFLSTAT1" bitfld.long 0x00 4. " RUNDFLSTAT ,Receive Buffer Underflow (RUNDFLSTAT bit is set to 1 when read operation is performed to the receive data register while receive buffer is empty; data read while underflow condition is undefined). Writing 1 to this bit clears the.." "RUNDFLSTAT0,RUNDFLSTAT1" textline " " bitfld.long 0x00 3. " RRDY ,Receive Buffer Threshold Reached (RRDY bit is set to 1 when the receive buffer occupied locations are equal or above the THRSH1_REG value). Writing 1 to this bit clears the bit. - . - ." "RRDY0,RRDY1" bitfld.long 0x00 2. " REOF ,Receive End Of Frame (REOF is set to 1 when a complete frame was received). Writing 1 to this bit clears the bit. - . - ." "REOF0,REOF1" bitfld.long 0x00 1. " RFSR ,Receive Frame Synchronization (RFSR bit is set to 1 when a new receive frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "RFSR0,RFSR1" textline " " bitfld.long 0x00 0. " RSYNCERR ,Receive Frame Synchronization Error (RSYNCERR is set to 1 when a receive frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "RSYNCERR0,RSYNCERR1" group.long 0xA4++0x3 line.long 0x00 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 12. " XOVFLEN ,Transmit Buffer Overflow enable bit. - . - ." "XOVFLEN0,XOVFLEN1" bitfld.long 0x00 11. " XUNDFLEN ,Transmit Buffer Underflow enable bit. - . - ." "XUNDFLEN0,XUNDFLEN1" textline " " bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame enable bit. - . - ." "XEOFEN0,XEOFEN1" bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization enable bit. - . - ." "XFSXEN0,XFSXEN1" textline " " bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 5. " ROVFLEN ,Receive Buffer Overflow enable bit. - . - ." "ROVFLEN0,ROVFLEN1" bitfld.long 0x00 4. " RUNDFLEN ,Receive Buffer Underflow enable bit. - . - ." "RUNDFLEN0,RUNDFLEN1" textline " " bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold enable bit. - . - ." "RRDYEN0,RRDYEN1" bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization enable bit. RW - . - ." "RFSREN0,RFSREN1" textline " " bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xA8++0x3 line.long 0x00 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable register" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit Buffer Empty at End Of Frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached WK enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame WK enable bit. - . - ." "XEOFEN0,XEOFEN1" textline " " bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization WK enable bit. - . - ." "XFSXEN0,XFSXEN1" bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error WK enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold wakeup enable bit. - . - ." "RRDYEN0,RRDYEN1" textline " " bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame WK enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization WK enable bit. - . - ." "RFSREN0,RFSREN1" bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error WK enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xAC++0x3 line.long 0x00 "MCBSPLP_XCCR_REG,McBSPLP transmit configuration control register" bitfld.long 0x00 15. " EXTCLKGATE ,External clock gating enable (CLKX and FSX master only). When this bit is set and the transmit clock and FSX are set as output, the CLKX is enabled when FSX is active plus 3 clock cycles after (clock is provided for FWID + 4 clock cycle.." "EXTCLKGATE0,EXTCLKGATE1" bitfld.long 0x00 14. " PPCONNECT ,Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output - . - ." "PPCONNECT0,PPCONNECT1" bitfld.long 0x00 12.--13. " DXENDLY ,When DXENA bit in SPCR1 is set to 1 this field selects the added delay as follow: - . - . - . - ." "DXENDLY0,DXENDLY1,DXENDLY2,DXENDLY3" textline " " bitfld.long 0x00 11. " XFULL_CYCLE ,Transmit full-cycle mode select. - . - ." "XFULL_CYCLE0,XFULL_CYCLE1" bitfld.long 0x00 5. " DLB ,Digital Loop-Back - . - ." "NODLB,DLB" bitfld.long 0x00 3. " XDMAEN ,Transmit DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during transmit reset. - . - ." "XDMAEN0,XDMAEN1" textline " " bitfld.long 0x00 0. " XDISABLE ,Transmit Disable bit. When this bit is set the transmit process will stop at the next frame boundary. - . - ." "XDSB0,XDSB1" group.long 0xB0++0x3 line.long 0x00 "MCBSPLP_RCCR_REG,McBSPLP receive configuration control register" bitfld.long 0x00 11. " RFULL_CYCLE ,Receive full-cycle mode select. - . - ." "RFULL_CYCLE0,RFULL_CYCLE1" bitfld.long 0x00 3. " RDMAEN ,Receive DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during receive reset. - . - ." "RDMAEN0,RDMAEN1" bitfld.long 0x00 0. " RDISABLE ,Receive Disable bit. When this bit is set the receive process will stop at the next frame boundary. - . - ." "RDSB0,RDSB1" rgroup.long 0xB4++0x3 line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP transmit buffer status" hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit Buffer Status (indicates the number of free locations inside transmit buffer). The XBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the number of free locations which are seen .." rgroup.long 0xB8++0x3 line.long 0x00 "MCBSPLP_RBUFFSTAT_REG,McBSPLP receive buffer status" hexmask.long.byte 0x00 0.--7. 1. " RBUFFSTAT ,Receive Buffer Status (indicates the number of occupied locations inside receive buffer). The RBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the real number of the occupied locations .." tree.end tree "MCBSP2_L3Interconnect" base ad:0x49024000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "MCBSPLP_DRR_REG,McBSPLP data receive register" hexmask.long 0x00 0.--31. 1. " DRR ,Data receive register" wgroup.long 0x8++0x3 line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP data transmit register" hexmask.long 0x00 0.--31. 1. " DXR ,Data transmit register" group.long 0x10++0x3 line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP serial port control register 2" bitfld.long 0x00 9. " FREE ,Free Running Mode (When this bit is set, the module ignores the Msuspend input) - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " SOFT ,Soft Bit - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " FRST ,Frame-Sync Generator Reset - . - ." "Reset,Generated" textline " " bitfld.long 0x00 6. " GRST ,Sample-Rate Generator Reset - . - ." "Reset,PullOut" bitfld.long 0x00 4.--5. " XINTM ,Transmit Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedXSYNCERR" bitfld.long 0x00 3. " XSYNCERR ,Transmit Synchronization Error (writing 0 to this bit clear the legacy transmit interrupt if asserted due to XSYNCERR condition) - . - ." "No,Detected" textline " " bitfld.long 0x00 2. " XEMPTY ,Transmit Shift Register XSR Empty - . - ." "Empty,NotEmpty" bitfld.long 0x00 1. " XRDY ,Transmitter ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " XRST ,Transmitter reset. This resets and enables the transmitter. - . - ." "Disabled,Enabled" group.long 0x14++0x3 line.long 0x00 "MCBSPLP_SPCR1_REG,McBSPLP serial port control register 1" bitfld.long 0x00 15. " ALB ,Analog Loopback Mode - . - ." "Disabled,Enabled" bitfld.long 0x00 13.--14. " RJUST ,Receive Sign-Extension and Justification Mode - . - . - . - ." "RJ,RJsigned,LJ,?..." bitfld.long 0x00 7. " DXENA ,DX Enabler - . - ." "Off,On" textline " " bitfld.long 0x00 4.--5. " RINTM ,Receive Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedRSYNCCERR" bitfld.long 0x00 3. " RSYNCERR ,Receive Synchronization Error (writing 0 to this bit clear the legacy receive interrupt if asserted due to RSYNCERR condition) - . - ." "No,Detected" bitfld.long 0x00 2. " RFULL ,Receive Shift Register (RSR]) Full - . - ." "NotOverrun,NotRead" textline " " bitfld.long 0x00 1. " RRDY ,Receiver Ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " RRST ,Receiver reset. This resets and enables the receiver. - . - ." "Disabled,Enabled" group.long 0x18++0x3 line.long 0x00 "MCBSPLP_RCR2_REG,McBSPLP receive control register 2" bitfld.long 0x00 15. " RPHASE ,Receive Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN2 ,Receive Frame Length 2 Single-phase frame selected: RFRLEN2=don't care Dual-phase frame selected: RFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " RWDLEN2 ,Receive Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " RREVERSE ,Receive reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " RDATDLY ,Receive Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x1C++0x3 line.long 0x00 "MCBSPLP_RCR1_REG,McBSPLP receive control register 1" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN1 ,Receive Frame Length 1 Single-phase frame selected: RFRLEN1=000 0000 - 1 word per frame RFRLEN1=000 0001 - 2 words per frame RFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: RFRLEN1=000 0000 - 1 word per phase (other va.." bitfld.long 0x00 5.--7. " RWDLEN1 ,Receive Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x20++0x3 line.long 0x00 "MCBSPLP_XCR2_REG,McBSPLP transmit control register 2" bitfld.long 0x00 15. " XPHASE ,Transmit Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN2 ,Transmit Frame Length 2 Single-phase frame selected: XFRLEN2=don't care Dual-phase frame selected: XFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " XWDLEN2 ,Transmit Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " XREVERSE ,Transmit reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " XDATDLY ,Transmit Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x24++0x3 line.long 0x00 "MCBSPLP_XCR1_REG,McBSPLP transmit control register 1" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN1 ,Transmit Frame Length 1 Single-phase frame selected: XFRLEN1=000 0000 - 1 word per frame XFRLEN1=000 0001 - 2 words per frame XFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: XFRLEN1=000 0000 - 1 word per phase (other v.." bitfld.long 0x00 5.--7. " XWDLEN1 ,Transmit Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x28++0x3 line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP sample rate generator register 2" bitfld.long 0x00 15. " GSYNC ,- . - ." "FreeRunning,Running" bitfld.long 0x00 14. " CLKSP ,CLKS Polarity Clock Edge Select Only used when the external clock CLKS drives the SRG clock (CLKSM=0). - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 13. " CLKSM ,McBSPLP Sample Rate Generator Clock Mode - . - ." "0x0,0x1" textline " " bitfld.long 0x00 12. " FSGM ,Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 in the PCR. - . - ." "TransmitAndIgnore,Transmit" hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame Period. This field plus 1 determines when the next frame-sync signal becomes active. Range: 1 to 4096 CLKG periods" group.long 0x2C++0x3 line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP sample rate generator register 1" hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame Width. This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period. Range: 1 to 256 CLKG periods." hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample Rate Generator Clock Divider This value is used as the divide-down number to generate the required SRG clock frequency. Default value is 1." group.long 0x30++0x3 line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP multi channel register 2" bitfld.long 0x00 9. " XMCME ,- . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " XPBBLK ,Transmit Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " XPABLK ,Transmit Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0.--1. " XMCM ,Transmit Multichannel Selection Enable - . - . - . - ." "Enabled,Disabled,EnabledMasked,DisabledMasked" group.long 0x34++0x3 line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP multi channel register 1" bitfld.long 0x00 9. " RMCME ,(legacy) - . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " RPBBLK ,Receive Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " RPABLK ,Receive Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0. " RMCM ,Receive Multichannel Selection Enable - . - ." "Enabled,Disabled" group.long 0x38++0x3 line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP receive channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " RCERA ,Receive Channel Enable RCERA n=0 Disables reception of n-th channel in an even-numbered block in partition A RCERA n=1 Enables reception of n-th channel in an even-numbered block in partition A" group.long 0x3C++0x3 line.long 0x00 "MCBSPLP_RCERB_REG,McBSPLP receive channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " RCERB ,Receive Channel Enable RCERB n=0 Disables reception of n-th channel in a even-numbered block in partition B RCERB n=1 Enables reception of n-th channel in a even-numbered block in partition B" group.long 0x40++0x3 line.long 0x00 "MCBSPLP_XCERA_REG,McBSPLP transmit channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " XCERA ,Transmit Channel Enable XCERA n=0 Disables transmission of n-th channel in an event-numbered block in partition A XCERA n=1 Enables transmission of n-th channel in an event-numbered block in partition A" group.long 0x44++0x3 line.long 0x00 "MCBSPLP_XCERB_REG,McBSPLP transmit channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " XCERB ,Transmit Channel Enable XCERB n=0 Disables transmission of n-th channel in an even-numbered block in partition B XCERB n=1 Enables transmission of n-th channel in an even-numbered block in partition B" group.long 0x48++0x3 line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP pin control register" bitfld.long 0x00 14. " IDLE_EN ,Idle enable. This bit allows stopping all the clocks in the MCBSPLP. (legacy) - . - ." "Running,ShutOff" bitfld.long 0x00 13. " XIOEN ,Transmit General Purpose I/O Mode only when XRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" bitfld.long 0x00 12. " RIOEN ,Receive General Purpose I/O Mode when RRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" textline " " bitfld.long 0x00 11. " FSXM ,Transmit Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 10. " FSRM ,Receive Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 9. " CLKXM ,Transmitter Clock Mode - . - ." "External,Internal" textline " " bitfld.long 0x00 8. " CLKRM ,Receiver Clock Mode - . - ." "External,Internal" bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG is: CLKG frequency = (Input clock frequency) / (CLKGDV + 1) SCLKME is used in conjunction with the CLKSM bit to select the input clock: - . - ." "0x0,0x1" bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input. (legacy) - . - ." "Low,High" textline " " bitfld.long 0x00 5. " DX_STAT ,DX pin status. Reflects value driven on to DX pin when selected as a general purpose output. (legacy) - . - ." "Low,High" bitfld.long 0x00 4. " DR_STAT ,DR pin status. Reflects value on DR pin when selected as a general purpose input. (legacy) - . - ." "Low,High" bitfld.long 0x00 3. " FSXP ,Transmit Frame-Synchronization Polarity - . - ." "High,Low" textline " " bitfld.long 0x00 2. " FSRP ,Receive Frame-Synchronization Polarity - . - ." "High,Low" bitfld.long 0x00 1. " CLKXP ,Transmit Clock Polarity - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 0. " CLKRP ,Receive Clock Polarity - . - ." "FallingEdge,RisingEdge" group.long 0x4C++0x3 line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP receive channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " RCERC ,Receive Channel Enable RCERC n=0 Disables reception of n-th channel in an even-numbered block in partition C RCERC n=1 Enables reception of n-th channel in an even-numbered block in partition C" group.long 0x50++0x3 line.long 0x00 "MCBSPLP_RCERD_REG,McBSPLP receive channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " RCERD ,Receive Channel Enable RCERD n=0 Disables reception of n-th channel in an even-numbered block in partition D RCERD n=1 Enables reception of n-th channel in an even-numbered block in partition D" group.long 0x54++0x3 line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP transmit channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " XCERC ,Transmit Channel Enable XCERC n=0 Disables transmission of n-th channel in an event-numbered block in partition C XCERC n=1 Enables transmission of n-th channel in an event-numbered block in partition C" group.long 0x58++0x3 line.long 0x00 "MCBSPLP_XCERD_REG,McBSPLP transmit channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " XCERD ,Transmit Channel Enable XCERD n=0 Disables transmission of n-th channel in an even-numbered block in partition D XCERD n=1 Enables transmission of n-th channel in an even-numbered block in partition D" group.long 0x5C++0x3 line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP receive channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " RCERE ,Receive Channel Enable RCERE n=0 Disables reception of n-th channel in an even-numbered block in partition E RCERE n=1 Enables reception of n-th channel in an even-numbered block in partition E" group.long 0x60++0x3 line.long 0x00 "MCBSPLP_RCERF_REG,McBSPLP receive channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " RCERF ,Receive Channel Enable RCERF n=0 Disables reception of n-th channel in an even-numbered block in partition F RCERF n=1 Enables reception of n-th channel in an even-numbered block in partition F" group.long 0x64++0x3 line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP transmit channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " XCERE ,Transmit Channel Enable XCERE n=0 Disables transmission of n-th channel in an event-numbered block in partition E XCERE n=1 Enables transmission of n-th channel in an event-numbered block in partition E" group.long 0x68++0x3 line.long 0x00 "MCBSPLP_XCERF_REG,McBSPLP transmit channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " XCERF ,Transmit Channel Enable XCERF n=0 Disables transmission of n-th channel in an even-numbered block in partition F XCERF n=1 Enables transmission of n-th channel in an even-numbered block in partition F" group.long 0x6C++0x3 line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP receive channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " RCERG ,Receive Channel Enable RCERG n=0 Disables reception of n-th channel in an even-numbered block in partition G RCERG n=1 Enables reception of n-th channel in an even-numbered block in partition G" group.long 0x70++0x3 line.long 0x00 "MCBSPLP_RCERH_REG,McBSPLP receive channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " RCERH ,Receive Channel Enable RCERH n=0 Disables reception of n-th channel in an even-numbered block in partition H RCERH n=1 Enables reception of n-th channel in an even-numbered block in partition H" group.long 0x74++0x3 line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP transmit channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " XCERG ,Transmit Channel Enable XCERG n=0 Disables transmission of n-th channel in an event-numbered block in partition G XCERG n=1 Enables transmission of n-th channel in an event-numbered block in partition G" group.long 0x78++0x3 line.long 0x00 "MCBSPLP_XCERH_REG,McBSPLP transmit channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " XCERH ,Transmit Channel Enable XCERH n=0 Disables transmission of n-th channel in an even-numbered block in partition H XCERH n=1 Enables transmission of n-th channel in an even-numbered block in partition H" rgroup.long 0x7C++0x3 line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision number register" hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number" group.long 0x80++0x3 line.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP receive interrupt clear" hexmask.long 0x00 0.--31. 1. " RINTCLR ,Read from this register will clear the IRQ generated by receive end-of-frame indication or MCBSPLP.FSR detection. Write to this register has no effect. (legacy)" group.long 0x84++0x3 line.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP transmit interrupt clear (legacy)" hexmask.long 0x00 0.--31. 1. " XINTCLR ,Read from this register will clear the IRQ generated by transmit end-of-frame indication or MCBSPLP.FSX detection. Write to this register has no effect." group.long 0x88++0x3 line.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP receive overflow interrupt clear" hexmask.long 0x00 0.--31. 1. " ROVFLCLR ,Read from this register will clear the IRQ generated by the receive overflow condition. Write to this register has no effect." group.long 0x8C++0x3 line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,- . - . - . - ." "CLKACT0,CLKACT1,CLKACT2,CLKACT3" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, req/ack control: - . - . - . - ." "SIDLEMODE0,SIDLEMODE1,SIDLEMODE2,SIDLEMODE3" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control: - . - ." "ENWK0,ENWK1" textline " " bitfld.long 0x00 1. " SOFTRESET ,McBSPLP global software reset - . - ." "NORESET,SOFTRESET" group.long 0x90++0x3 line.long 0x00 "MCBSPLP_THRSH2_REG,McBSPLP transmit buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of free locations inside transmit buffer are above or equal to the XTHRESHOLD value + 1. Also, this value .." group.long 0x94++0x3 line.long 0x00 "MCBSPLP_THRSH1_REG,McBSPLP receive buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of occupied locations inside receive buffer are above or equal to the RTHRESHOLD value + 1. Also, this valu.." group.long 0xA0++0x3 line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOF ,Transmit Buffer Empty at end of frame (XEMPTYEOF is set to 1 when a complete frame was transmitted and the transmit buffer is empty). - . - ." "XEMPTYEOF0,XEMPTYEOF1" bitfld.long 0x00 12. " XOVFLSTAT ,Transmit Buffer Overflow (XOVFLSTAT bit is set to 1 when transmit buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "XOVFLSTAT0,XOVFLSTAT1" bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit Buffer Underflow (XUNDFLSTAT bit is set to 1 when the transmit data buffer is empty new data is required to be transmitted). Writing 1 to this bit clears the bit. - . - ." "XUNDFLSTAT0,XUNDFLSTAT1" textline " " bitfld.long 0x00 10. " XRDY ,Transmit Buffer Threshold Reached (XRDY bit is set to 1 when the transmit buffer free locations are equal or above the THRSH2_REG value). Writing 1 to this bit clears the bit. - . - ." "XRDY0,XRDY1" bitfld.long 0x00 9. " XEOF ,Transmit End Of Frame (XEOF is set to 1 when a complete frame was transmitted). Writing 1 to this bit clears the bit. - . - ." "XEOF0,XEOF1" bitfld.long 0x00 8. " XFSX ,Transmit Frame Synchronization (XFSX bit is set to 1 when a new transmit frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "XFSX0,XFSX1" textline " " bitfld.long 0x00 7. " XSYNCERR ,Transmit Frame Synchronization Error (XSYNCERR is set to 1 when a transmit frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "XSYNCERR0,XSYNCERR1" bitfld.long 0x00 5. " ROVFLSTAT ,Receive Buffer Overflow (ROVFLSTAT bit is set to 1 when receive buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "ROVFLSTAT0,ROVFLSTAT1" bitfld.long 0x00 4. " RUNDFLSTAT ,Receive Buffer Underflow (RUNDFLSTAT bit is set to 1 when read operation is performed to the receive data register while receive buffer is empty; data read while underflow condition is undefined). Writing 1 to this bit clears the.." "RUNDFLSTAT0,RUNDFLSTAT1" textline " " bitfld.long 0x00 3. " RRDY ,Receive Buffer Threshold Reached (RRDY bit is set to 1 when the receive buffer occupied locations are equal or above the THRSH1_REG value). Writing 1 to this bit clears the bit. - . - ." "RRDY0,RRDY1" bitfld.long 0x00 2. " REOF ,Receive End Of Frame (REOF is set to 1 when a complete frame was received). Writing 1 to this bit clears the bit. - . - ." "REOF0,REOF1" bitfld.long 0x00 1. " RFSR ,Receive Frame Synchronization (RFSR bit is set to 1 when a new receive frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "RFSR0,RFSR1" textline " " bitfld.long 0x00 0. " RSYNCERR ,Receive Frame Synchronization Error (RSYNCERR is set to 1 when a receive frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "RSYNCERR0,RSYNCERR1" group.long 0xA4++0x3 line.long 0x00 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 12. " XOVFLEN ,Transmit Buffer Overflow enable bit. - . - ." "XOVFLEN0,XOVFLEN1" bitfld.long 0x00 11. " XUNDFLEN ,Transmit Buffer Underflow enable bit. - . - ." "XUNDFLEN0,XUNDFLEN1" textline " " bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame enable bit. - . - ." "XEOFEN0,XEOFEN1" bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization enable bit. - . - ." "XFSXEN0,XFSXEN1" textline " " bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 5. " ROVFLEN ,Receive Buffer Overflow enable bit. - . - ." "ROVFLEN0,ROVFLEN1" bitfld.long 0x00 4. " RUNDFLEN ,Receive Buffer Underflow enable bit. - . - ." "RUNDFLEN0,RUNDFLEN1" textline " " bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold enable bit. - . - ." "RRDYEN0,RRDYEN1" bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization enable bit. RW - . - ." "RFSREN0,RFSREN1" textline " " bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xA8++0x3 line.long 0x00 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable register" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit Buffer Empty at End Of Frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached WK enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame WK enable bit. - . - ." "XEOFEN0,XEOFEN1" textline " " bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization WK enable bit. - . - ." "XFSXEN0,XFSXEN1" bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error WK enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold wakeup enable bit. - . - ." "RRDYEN0,RRDYEN1" textline " " bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame WK enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization WK enable bit. - . - ." "RFSREN0,RFSREN1" bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error WK enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xAC++0x3 line.long 0x00 "MCBSPLP_XCCR_REG,McBSPLP transmit configuration control register" bitfld.long 0x00 15. " EXTCLKGATE ,External clock gating enable (CLKX and FSX master only). When this bit is set and the transmit clock and FSX are set as output, the CLKX is enabled when FSX is active plus 3 clock cycles after (clock is provided for FWID + 4 clock cycle.." "EXTCLKGATE0,EXTCLKGATE1" bitfld.long 0x00 14. " PPCONNECT ,Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output - . - ." "PPCONNECT0,PPCONNECT1" bitfld.long 0x00 12.--13. " DXENDLY ,When DXENA bit in SPCR1 is set to 1 this field selects the added delay as follow: - . - . - . - ." "DXENDLY0,DXENDLY1,DXENDLY2,DXENDLY3" textline " " bitfld.long 0x00 11. " XFULL_CYCLE ,Transmit full-cycle mode select. - . - ." "XFULL_CYCLE0,XFULL_CYCLE1" bitfld.long 0x00 5. " DLB ,Digital Loop-Back - . - ." "NODLB,DLB" bitfld.long 0x00 3. " XDMAEN ,Transmit DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during transmit reset. - . - ." "XDMAEN0,XDMAEN1" textline " " bitfld.long 0x00 0. " XDISABLE ,Transmit Disable bit. When this bit is set the transmit process will stop at the next frame boundary. - . - ." "XDSB0,XDSB1" group.long 0xB0++0x3 line.long 0x00 "MCBSPLP_RCCR_REG,McBSPLP receive configuration control register" bitfld.long 0x00 11. " RFULL_CYCLE ,Receive full-cycle mode select. - . - ." "RFULL_CYCLE0,RFULL_CYCLE1" bitfld.long 0x00 3. " RDMAEN ,Receive DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during receive reset. - . - ." "RDMAEN0,RDMAEN1" bitfld.long 0x00 0. " RDISABLE ,Receive Disable bit. When this bit is set the receive process will stop at the next frame boundary. - . - ." "RDSB0,RDSB1" rgroup.long 0xB4++0x3 line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP transmit buffer status" hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit Buffer Status (indicates the number of free locations inside transmit buffer). The XBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the number of free locations which are seen .." rgroup.long 0xB8++0x3 line.long 0x00 "MCBSPLP_RBUFFSTAT_REG,McBSPLP receive buffer status" hexmask.long.byte 0x00 0.--7. 1. " RBUFFSTAT ,Receive Buffer Status (indicates the number of occupied locations inside receive buffer). The RBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the real number of the occupied locations .." tree.end tree "MCBSP3_L3Interconnect" base ad:0x49026000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "MCBSPLP_DRR_REG,McBSPLP data receive register" hexmask.long 0x00 0.--31. 1. " DRR ,Data receive register" wgroup.long 0x8++0x3 line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP data transmit register" hexmask.long 0x00 0.--31. 1. " DXR ,Data transmit register" group.long 0x10++0x3 line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP serial port control register 2" bitfld.long 0x00 9. " FREE ,Free Running Mode (When this bit is set, the module ignores the Msuspend input) - . - ." "Disabled,Enabled" bitfld.long 0x00 8. " SOFT ,Soft Bit - . - ." "Disabled,Enabled" bitfld.long 0x00 7. " FRST ,Frame-Sync Generator Reset - . - ." "Reset,Generated" textline " " bitfld.long 0x00 6. " GRST ,Sample-Rate Generator Reset - . - ." "Reset,PullOut" bitfld.long 0x00 4.--5. " XINTM ,Transmit Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedXSYNCERR" bitfld.long 0x00 3. " XSYNCERR ,Transmit Synchronization Error (writing 0 to this bit clear the legacy transmit interrupt if asserted due to XSYNCERR condition) - . - ." "No,Detected" textline " " bitfld.long 0x00 2. " XEMPTY ,Transmit Shift Register XSR Empty - . - ." "Empty,NotEmpty" bitfld.long 0x00 1. " XRDY ,Transmitter ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " XRST ,Transmitter reset. This resets and enables the transmitter. - . - ." "Disabled,Enabled" group.long 0x14++0x3 line.long 0x00 "MCBSPLP_SPCR1_REG,McBSPLP serial port control register 1" bitfld.long 0x00 15. " ALB ,Analog Loopback Mode - . - ." "Disabled,Enabled" bitfld.long 0x00 13.--14. " RJUST ,Receive Sign-Extension and Justification Mode - . - . - . - ." "RJ,RJsigned,LJ,?..." bitfld.long 0x00 7. " DXENA ,DX Enabler - . - ." "Off,On" textline " " bitfld.long 0x00 4.--5. " RINTM ,Receive Interrupt Mode (legacy) - . - . - . - ." "Driven,GeneratedEndOfBlock,GeneratedNewFrame,GeneratedRSYNCCERR" bitfld.long 0x00 3. " RSYNCERR ,Receive Synchronization Error (writing 0 to this bit clear the legacy receive interrupt if asserted due to RSYNCERR condition) - . - ." "No,Detected" bitfld.long 0x00 2. " RFULL ,Receive Shift Register (RSR]) Full - . - ." "NotOverrun,NotRead" textline " " bitfld.long 0x00 1. " RRDY ,Receiver Ready - . - ." "NotReady,Ready" bitfld.long 0x00 0. " RRST ,Receiver reset. This resets and enables the receiver. - . - ." "Disabled,Enabled" group.long 0x18++0x3 line.long 0x00 "MCBSPLP_RCR2_REG,McBSPLP receive control register 2" bitfld.long 0x00 15. " RPHASE ,Receive Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN2 ,Receive Frame Length 2 Single-phase frame selected: RFRLEN2=don't care Dual-phase frame selected: RFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " RWDLEN2 ,Receive Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " RREVERSE ,Receive reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " RDATDLY ,Receive Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x1C++0x3 line.long 0x00 "MCBSPLP_RCR1_REG,McBSPLP receive control register 1" hexmask.long.byte 0x00 8.--14. 1. " RFRLEN1 ,Receive Frame Length 1 Single-phase frame selected: RFRLEN1=000 0000 - 1 word per frame RFRLEN1=000 0001 - 2 words per frame RFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: RFRLEN1=000 0000 - 1 word per phase (other va.." bitfld.long 0x00 5.--7. " RWDLEN1 ,Receive Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x20++0x3 line.long 0x00 "MCBSPLP_XCR2_REG,McBSPLP transmit control register 2" bitfld.long 0x00 15. " XPHASE ,Transmit Phases - . - ." "Single,Dual" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN2 ,Transmit Frame Length 2 Single-phase frame selected: XFRLEN2=don't care Dual-phase frame selected: XFRLEN2=000 0000 - 1 word per second phase (other values are reserved)" bitfld.long 0x00 5.--7. " XWDLEN2 ,Transmit Word Length 2 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" textline " " bitfld.long 0x00 3.--4. " XREVERSE ,Transmit reverse mode. - . - . - . - ." "NoCompandingMSB,NoCompandingLSB,CompandU,CompandA" bitfld.long 0x00 0.--1. " XDATDLY ,Transmit Data Delay - . - . - . - ." "0bit,1bit,2bits,?..." group.long 0x24++0x3 line.long 0x00 "MCBSPLP_XCR1_REG,McBSPLP transmit control register 1" hexmask.long.byte 0x00 8.--14. 1. " XFRLEN1 ,Transmit Frame Length 1 Single-phase frame selected: XFRLEN1=000 0000 - 1 word per frame XFRLEN1=000 0001 - 2 words per frame XFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: XFRLEN1=000 0000 - 1 word per phase (other v.." bitfld.long 0x00 5.--7. " XWDLEN1 ,Transmit Word Length 1 - . - . - . - . - . - . - . - ." "8bits,12bits,16bits,20bits,24bits,32bits,Reserved0x6,Reserved0x7" group.long 0x28++0x3 line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP sample rate generator register 2" bitfld.long 0x00 15. " GSYNC ,- . - ." "FreeRunning,Running" bitfld.long 0x00 14. " CLKSP ,CLKS Polarity Clock Edge Select Only used when the external clock CLKS drives the SRG clock (CLKSM=0). - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 13. " CLKSM ,McBSPLP Sample Rate Generator Clock Mode - . - ." "0x0,0x1" textline " " bitfld.long 0x00 12. " FSGM ,Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 in the PCR. - . - ." "TransmitAndIgnore,Transmit" hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame Period. This field plus 1 determines when the next frame-sync signal becomes active. Range: 1 to 4096 CLKG periods" group.long 0x2C++0x3 line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP sample rate generator register 1" hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame Width. This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period. Range: 1 to 256 CLKG periods." hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample Rate Generator Clock Divider This value is used as the divide-down number to generate the required SRG clock frequency. Default value is 1." group.long 0x30++0x3 line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP multi channel register 2" bitfld.long 0x00 9. " XMCME ,- . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " XPBBLK ,Transmit Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " XPABLK ,Transmit Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0.--1. " XMCM ,Transmit Multichannel Selection Enable - . - . - . - ." "Enabled,Disabled,EnabledMasked,DisabledMasked" group.long 0x34++0x3 line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP multi channel register 1" bitfld.long 0x00 9. " RMCME ,(legacy) - . - ." "2partitions,8partitions" bitfld.long 0x00 7.--8. " RPBBLK ,Receive Partition B Block (legacy) - . - . - . - ." "Block1,Block3,Block5,Block7" bitfld.long 0x00 5.--6. " RPABLK ,Receive Partition A Block (legacy) - . - . - . - ." "Block0,Block2,Block4,Block6" textline " " bitfld.long 0x00 0. " RMCM ,Receive Multichannel Selection Enable - . - ." "Enabled,Disabled" group.long 0x38++0x3 line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP receive channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " RCERA ,Receive Channel Enable RCERA n=0 Disables reception of n-th channel in an even-numbered block in partition A RCERA n=1 Enables reception of n-th channel in an even-numbered block in partition A" group.long 0x3C++0x3 line.long 0x00 "MCBSPLP_RCERB_REG,McBSPLP receive channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " RCERB ,Receive Channel Enable RCERB n=0 Disables reception of n-th channel in a even-numbered block in partition B RCERB n=1 Enables reception of n-th channel in a even-numbered block in partition B" group.long 0x40++0x3 line.long 0x00 "MCBSPLP_XCERA_REG,McBSPLP transmit channel enable register partition A" hexmask.long.word 0x00 0.--15. 1. " XCERA ,Transmit Channel Enable XCERA n=0 Disables transmission of n-th channel in an event-numbered block in partition A XCERA n=1 Enables transmission of n-th channel in an event-numbered block in partition A" group.long 0x44++0x3 line.long 0x00 "MCBSPLP_XCERB_REG,McBSPLP transmit channel enable register partition B" hexmask.long.word 0x00 0.--15. 1. " XCERB ,Transmit Channel Enable XCERB n=0 Disables transmission of n-th channel in an even-numbered block in partition B XCERB n=1 Enables transmission of n-th channel in an even-numbered block in partition B" group.long 0x48++0x3 line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP pin control register" bitfld.long 0x00 14. " IDLE_EN ,Idle enable. This bit allows stopping all the clocks in the MCBSPLP. (legacy) - . - ." "Running,ShutOff" bitfld.long 0x00 13. " XIOEN ,Transmit General Purpose I/O Mode only when XRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" bitfld.long 0x00 12. " RIOEN ,Receive General Purpose I/O Mode when RRST=0 in SPCR[1,2] (legacy) - . - ." "Serial,GP" textline " " bitfld.long 0x00 11. " FSXM ,Transmit Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 10. " FSRM ,Receive Frame-Synchronization Mode - . - ." "External,Sampled" bitfld.long 0x00 9. " CLKXM ,Transmitter Clock Mode - . - ." "External,Internal" textline " " bitfld.long 0x00 8. " CLKRM ,Receiver Clock Mode - . - ." "External,Internal" bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG is: CLKG frequency = (Input clock frequency) / (CLKGDV + 1) SCLKME is used in conjunction with the CLKSM bit to select the input clock: - . - ." "0x0,0x1" bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input. (legacy) - . - ." "Low,High" textline " " bitfld.long 0x00 5. " DX_STAT ,DX pin status. Reflects value driven on to DX pin when selected as a general purpose output. (legacy) - . - ." "Low,High" bitfld.long 0x00 4. " DR_STAT ,DR pin status. Reflects value on DR pin when selected as a general purpose input. (legacy) - . - ." "Low,High" bitfld.long 0x00 3. " FSXP ,Transmit Frame-Synchronization Polarity - . - ." "High,Low" textline " " bitfld.long 0x00 2. " FSRP ,Receive Frame-Synchronization Polarity - . - ." "High,Low" bitfld.long 0x00 1. " CLKXP ,Transmit Clock Polarity - . - ." "RisingEdge,FallingEdge" bitfld.long 0x00 0. " CLKRP ,Receive Clock Polarity - . - ." "FallingEdge,RisingEdge" group.long 0x4C++0x3 line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP receive channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " RCERC ,Receive Channel Enable RCERC n=0 Disables reception of n-th channel in an even-numbered block in partition C RCERC n=1 Enables reception of n-th channel in an even-numbered block in partition C" group.long 0x50++0x3 line.long 0x00 "MCBSPLP_RCERD_REG,McBSPLP receive channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " RCERD ,Receive Channel Enable RCERD n=0 Disables reception of n-th channel in an even-numbered block in partition D RCERD n=1 Enables reception of n-th channel in an even-numbered block in partition D" group.long 0x54++0x3 line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP transmit channel enable register partition C" hexmask.long.word 0x00 0.--15. 1. " XCERC ,Transmit Channel Enable XCERC n=0 Disables transmission of n-th channel in an event-numbered block in partition C XCERC n=1 Enables transmission of n-th channel in an event-numbered block in partition C" group.long 0x58++0x3 line.long 0x00 "MCBSPLP_XCERD_REG,McBSPLP transmit channel enable register partition D" hexmask.long.word 0x00 0.--15. 1. " XCERD ,Transmit Channel Enable XCERD n=0 Disables transmission of n-th channel in an even-numbered block in partition D XCERD n=1 Enables transmission of n-th channel in an even-numbered block in partition D" group.long 0x5C++0x3 line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP receive channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " RCERE ,Receive Channel Enable RCERE n=0 Disables reception of n-th channel in an even-numbered block in partition E RCERE n=1 Enables reception of n-th channel in an even-numbered block in partition E" group.long 0x60++0x3 line.long 0x00 "MCBSPLP_RCERF_REG,McBSPLP receive channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " RCERF ,Receive Channel Enable RCERF n=0 Disables reception of n-th channel in an even-numbered block in partition F RCERF n=1 Enables reception of n-th channel in an even-numbered block in partition F" group.long 0x64++0x3 line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP transmit channel enable register partition E" hexmask.long.word 0x00 0.--15. 1. " XCERE ,Transmit Channel Enable XCERE n=0 Disables transmission of n-th channel in an event-numbered block in partition E XCERE n=1 Enables transmission of n-th channel in an event-numbered block in partition E" group.long 0x68++0x3 line.long 0x00 "MCBSPLP_XCERF_REG,McBSPLP transmit channel enable register partition F" hexmask.long.word 0x00 0.--15. 1. " XCERF ,Transmit Channel Enable XCERF n=0 Disables transmission of n-th channel in an even-numbered block in partition F XCERF n=1 Enables transmission of n-th channel in an even-numbered block in partition F" group.long 0x6C++0x3 line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP receive channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " RCERG ,Receive Channel Enable RCERG n=0 Disables reception of n-th channel in an even-numbered block in partition G RCERG n=1 Enables reception of n-th channel in an even-numbered block in partition G" group.long 0x70++0x3 line.long 0x00 "MCBSPLP_RCERH_REG,McBSPLP receive channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " RCERH ,Receive Channel Enable RCERH n=0 Disables reception of n-th channel in an even-numbered block in partition H RCERH n=1 Enables reception of n-th channel in an even-numbered block in partition H" group.long 0x74++0x3 line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP transmit channel enable register partition G" hexmask.long.word 0x00 0.--15. 1. " XCERG ,Transmit Channel Enable XCERG n=0 Disables transmission of n-th channel in an event-numbered block in partition G XCERG n=1 Enables transmission of n-th channel in an event-numbered block in partition G" group.long 0x78++0x3 line.long 0x00 "MCBSPLP_XCERH_REG,McBSPLP transmit channel enable register partition H" hexmask.long.word 0x00 0.--15. 1. " XCERH ,Transmit Channel Enable XCERH n=0 Disables transmission of n-th channel in an even-numbered block in partition H XCERH n=1 Enables transmission of n-th channel in an even-numbered block in partition H" rgroup.long 0x7C++0x3 line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision number register" hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number" group.long 0x80++0x3 line.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP receive interrupt clear" hexmask.long 0x00 0.--31. 1. " RINTCLR ,Read from this register will clear the IRQ generated by receive end-of-frame indication or MCBSPLP.FSR detection. Write to this register has no effect. (legacy)" group.long 0x84++0x3 line.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP transmit interrupt clear (legacy)" hexmask.long 0x00 0.--31. 1. " XINTCLR ,Read from this register will clear the IRQ generated by transmit end-of-frame indication or MCBSPLP.FSX detection. Write to this register has no effect." group.long 0x88++0x3 line.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP receive overflow interrupt clear" hexmask.long 0x00 0.--31. 1. " ROVFLCLR ,Read from this register will clear the IRQ generated by the receive overflow condition. Write to this register has no effect." group.long 0x8C++0x3 line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,- . - . - . - ." "CLKACT0,CLKACT1,CLKACT2,CLKACT3" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, req/ack control: - . - . - . - ." "SIDLEMODE0,SIDLEMODE1,SIDLEMODE2,SIDLEMODE3" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control: - . - ." "ENWK0,ENWK1" textline " " bitfld.long 0x00 1. " SOFTRESET ,McBSPLP global software reset - . - ." "NORESET,SOFTRESET" group.long 0x90++0x3 line.long 0x00 "MCBSPLP_THRSH2_REG,McBSPLP transmit buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of free locations inside transmit buffer are above or equal to the XTHRESHOLD value + 1. Also, this value .." group.long 0x94++0x3 line.long 0x00 "MCBSPLP_THRSH1_REG,McBSPLP receive buffer threshold (DMA or IRQ trigger)" hexmask.long.byte 0x00 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of occupied locations inside receive buffer are above or equal to the RTHRESHOLD value + 1. Also, this valu.." group.long 0xA0++0x3 line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOF ,Transmit Buffer Empty at end of frame (XEMPTYEOF is set to 1 when a complete frame was transmitted and the transmit buffer is empty). - . - ." "XEMPTYEOF0,XEMPTYEOF1" bitfld.long 0x00 12. " XOVFLSTAT ,Transmit Buffer Overflow (XOVFLSTAT bit is set to 1 when transmit buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "XOVFLSTAT0,XOVFLSTAT1" bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit Buffer Underflow (XUNDFLSTAT bit is set to 1 when the transmit data buffer is empty new data is required to be transmitted). Writing 1 to this bit clears the bit. - . - ." "XUNDFLSTAT0,XUNDFLSTAT1" textline " " bitfld.long 0x00 10. " XRDY ,Transmit Buffer Threshold Reached (XRDY bit is set to 1 when the transmit buffer free locations are equal or above the THRSH2_REG value). Writing 1 to this bit clears the bit. - . - ." "XRDY0,XRDY1" bitfld.long 0x00 9. " XEOF ,Transmit End Of Frame (XEOF is set to 1 when a complete frame was transmitted). Writing 1 to this bit clears the bit. - . - ." "XEOF0,XEOF1" bitfld.long 0x00 8. " XFSX ,Transmit Frame Synchronization (XFSX bit is set to 1 when a new transmit frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "XFSX0,XFSX1" textline " " bitfld.long 0x00 7. " XSYNCERR ,Transmit Frame Synchronization Error (XSYNCERR is set to 1 when a transmit frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "XSYNCERR0,XSYNCERR1" bitfld.long 0x00 5. " ROVFLSTAT ,Receive Buffer Overflow (ROVFLSTAT bit is set to 1 when receive buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit. - . - ." "ROVFLSTAT0,ROVFLSTAT1" bitfld.long 0x00 4. " RUNDFLSTAT ,Receive Buffer Underflow (RUNDFLSTAT bit is set to 1 when read operation is performed to the receive data register while receive buffer is empty; data read while underflow condition is undefined). Writing 1 to this bit clears the.." "RUNDFLSTAT0,RUNDFLSTAT1" textline " " bitfld.long 0x00 3. " RRDY ,Receive Buffer Threshold Reached (RRDY bit is set to 1 when the receive buffer occupied locations are equal or above the THRSH1_REG value). Writing 1 to this bit clears the bit. - . - ." "RRDY0,RRDY1" bitfld.long 0x00 2. " REOF ,Receive End Of Frame (REOF is set to 1 when a complete frame was received). Writing 1 to this bit clears the bit. - . - ." "REOF0,REOF1" bitfld.long 0x00 1. " RFSR ,Receive Frame Synchronization (RFSR bit is set to 1 when a new receive frame synchronization is asserted). Writing 1 to this bit clears the bit. - . - ." "RFSR0,RFSR1" textline " " bitfld.long 0x00 0. " RSYNCERR ,Receive Frame Synchronization Error (RSYNCERR is set to 1 when a receive frame-sync error is detected). Writing 1 to this bit clears the bit. - . - ." "RSYNCERR0,RSYNCERR1" group.long 0xA4++0x3 line.long 0x00 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable register (interconnect compliant IRQ line)" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 12. " XOVFLEN ,Transmit Buffer Overflow enable bit. - . - ." "XOVFLEN0,XOVFLEN1" bitfld.long 0x00 11. " XUNDFLEN ,Transmit Buffer Underflow enable bit. - . - ." "XUNDFLEN0,XUNDFLEN1" textline " " bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame enable bit. - . - ." "XEOFEN0,XEOFEN1" bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization enable bit. - . - ." "XFSXEN0,XFSXEN1" textline " " bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 5. " ROVFLEN ,Receive Buffer Overflow enable bit. - . - ." "ROVFLEN0,ROVFLEN1" bitfld.long 0x00 4. " RUNDFLEN ,Receive Buffer Underflow enable bit. - . - ." "RUNDFLEN0,RUNDFLEN1" textline " " bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold enable bit. - . - ." "RRDYEN0,RRDYEN1" bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization enable bit. RW - . - ." "RFSREN0,RFSREN1" textline " " bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xA8++0x3 line.long 0x00 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable register" bitfld.long 0x00 14. " XEMPTYEOFEN ,Transmit Buffer Empty at End Of Frame enable bit. - . - ." "XEMPTYEOFEN0,XEMPTYEOFEN1" bitfld.long 0x00 10. " XRDYEN ,Transmit Buffer Threshold Reached WK enable bit. - . - ." "XRDYEN0,XRDYEN1" bitfld.long 0x00 9. " XEOFEN ,Transmit End Of Frame WK enable bit. - . - ." "XEOFEN0,XEOFEN1" textline " " bitfld.long 0x00 8. " XFSXEN ,Transmit Frame Synchronization WK enable bit. - . - ." "XFSXEN0,XFSXEN1" bitfld.long 0x00 7. " XSYNCERREN ,Transmit Frame Synchronization Error WK enable bit. - . - ." "XSYNCERREN0,XSYNCERREN1" bitfld.long 0x00 3. " RRDYEN ,Receive Buffer Threshold wakeup enable bit. - . - ." "RRDYEN0,RRDYEN1" textline " " bitfld.long 0x00 2. " REOFEN ,Receive End Of Frame WK enable bit. - . - ." "REOFEN0,REOFEN1" bitfld.long 0x00 1. " RFSREN ,Receive Frame Synchronization WK enable bit. - . - ." "RFSREN0,RFSREN1" bitfld.long 0x00 0. " RSYNCERREN ,Receive Frame Synchronization Error WK enable bit. - . - ." "RSYNCERREN0,RSYNCERREN1" group.long 0xAC++0x3 line.long 0x00 "MCBSPLP_XCCR_REG,McBSPLP transmit configuration control register" bitfld.long 0x00 15. " EXTCLKGATE ,External clock gating enable (CLKX and FSX master only). When this bit is set and the transmit clock and FSX are set as output, the CLKX is enabled when FSX is active plus 3 clock cycles after (clock is provided for FWID + 4 clock cycle.." "EXTCLKGATE0,EXTCLKGATE1" bitfld.long 0x00 14. " PPCONNECT ,Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output - . - ." "PPCONNECT0,PPCONNECT1" bitfld.long 0x00 12.--13. " DXENDLY ,When DXENA bit in SPCR1 is set to 1 this field selects the added delay as follow: - . - . - . - ." "DXENDLY0,DXENDLY1,DXENDLY2,DXENDLY3" textline " " bitfld.long 0x00 11. " XFULL_CYCLE ,Transmit full-cycle mode select. - . - ." "XFULL_CYCLE0,XFULL_CYCLE1" bitfld.long 0x00 5. " DLB ,Digital Loop-Back - . - ." "NODLB,DLB" bitfld.long 0x00 3. " XDMAEN ,Transmit DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during transmit reset. - . - ." "XDMAEN0,XDMAEN1" textline " " bitfld.long 0x00 0. " XDISABLE ,Transmit Disable bit. When this bit is set the transmit process will stop at the next frame boundary. - . - ." "XDSB0,XDSB1" group.long 0xB0++0x3 line.long 0x00 "MCBSPLP_RCCR_REG,McBSPLP receive configuration control register" bitfld.long 0x00 11. " RFULL_CYCLE ,Receive full-cycle mode select. - . - ." "RFULL_CYCLE0,RFULL_CYCLE1" bitfld.long 0x00 3. " RDMAEN ,Receive DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during receive reset. - . - ." "RDMAEN0,RDMAEN1" bitfld.long 0x00 0. " RDISABLE ,Receive Disable bit. When this bit is set the receive process will stop at the next frame boundary. - . - ." "RDSB0,RDSB1" rgroup.long 0xB4++0x3 line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP transmit buffer status" hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit Buffer Status (indicates the number of free locations inside transmit buffer). The XBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the number of free locations which are seen .." rgroup.long 0xB8++0x3 line.long 0x00 "MCBSPLP_RBUFFSTAT_REG,McBSPLP receive buffer status" hexmask.long.byte 0x00 0.--7. 1. " RBUFFSTAT ,Receive Buffer Status (indicates the number of occupied locations inside receive buffer). The RBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the real number of the occupied locations .." tree.end tree.end tree.end tree.open "Multichannel_PDM_Controller" tree.open "McPDM_DSP" tree "McPDM_Cortex_A9" base ad:0x40132000 width 21. rgroup.long 0x0++0x3 line.long 0x00 "MCPDM_REVISION,IP revision identifier (X.Y.R) used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "MCPDM_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the idle mode. - . - . - . - ." "FORCE_Idle,NO_idle,SMART_idle,SMART_Idle_Wakeup" bitfld.long 0x00 1. " FREEMU ,Sensitivity to emulation (debug) suspend input signal. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " SOFTRESET ,McPDM software Reset. - . - . - . - ." "NORMAL_/_NO_ACTION,RESET_/_RST_ON_GOING" group.long 0x24++0x3 line.long 0x00 "MCPDM_IRQSTATUS_RAW,Interrupt request raw status register (for debug purpose)." bitfld.long 0x00 11. " UP_IRQ_FULL ,FIFO-uplink-full signal appears when a write access is performed and the FIFO uplink is already full. - . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 10. " UP_IRQ_ALST_FULL ,FIFO uplink almost-full signal appears when the FIFO uplink contains (FIFO uplink size ? 1) elements. - . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 9. " UP_IRQ_EMPTY ,FIFO uplink empty signal appears when a read access is done and FIFO uplink already empty. - . - . - . - ." "none_/_noaction,pending_/_set" textline " " bitfld.long 0x00 8. " UP_IRQ ,FIFO uplink interrupt appears when the number of data present in the FIFO uplink has reached the value of the FIFO uplink threshold. - . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 3. " DN_IRQ_FULL ,FIFO downlink full signal appears when the FIFO uplink is full and another a write access is performed. - . - . - . - ." "0,1" bitfld.long 0x00 2. " DN_IRQ_ALST_EMPTY ,FIFO downlink almost empty signal appears when the FIFO downlink contains only one element. - . - . - . - ." "none_/_noaction,pending_/_set" textline " " bitfld.long 0x00 1. " DN_IRQ_EMPTY ,FIFO-downlink-empty signal appears when read access is performed and FIFO downlink is already empty. - . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 0. " DN_IRQ ,FIFO downlink status is set when the number of data is below the FIFO downlink threshold value. - . - . - . - ." "none_/_noaction,pending_/_set" group.long 0x28++0x3 line.long 0x00 "MCPDM_IRQSTATUS,Interrupt request status register." bitfld.long 0x00 11. " UP_IRQ_FULL ,FIFO-uplink-full signal appears when a write access is performed and the FIFO uplink is already full. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 10. " UP_IRQ_ALST_FULL ,FIFO uplink almost-full signal appears when the FIFO uplink contains (FIFO uplink size ? 1) elements. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 9. " UP_IRQ_EMPTY ,FIFO uplink empty signal appears when a read access is done and FIFO uplink already empty. - . - . - . - ." "none_/_noaction,pending_/_clear" textline " " bitfld.long 0x00 8. " UP_IRQ ,FIFO uplink interrupt appears when the number of data present in the FIFO uplink has reached the value of the FIFO uplink threshold. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 3. " DN_IRQ_FULL ,FIFO downlink full signal appears when the FIFO uplink is full and another a write access is performed. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 2. " DN_IRQ_ALST_EMPTY ,FIFO downlink almost empty signal appears when the FIFO downlink contains only one element. - . - . - . - ." "none_/_noaction,pending_/_clear" textline " " bitfld.long 0x00 1. " DN_IRQ_EMPTY ,FIFO-downlink-empty signal appears when read access is performed and FIFO downlink is already empty. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 0. " DN_IRQ ,FIFO downlink status is set when the number of data is below the FIFO downlink threshold value. - . - . - . - ." "none_/_noaction,pending_/_clear" group.long 0x2C++0x3 line.long 0x00 "MCPDM_IRQENABLE_SET,Interrupt request enable set register." bitfld.long 0x00 11. " UP_IRQ_FULL_MASK ,FIFO-uplink-full event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 10. " UP_IRQ_ALST_FULL_MASK ,FIFO-uplink-almost-full event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 9. " UP_IRQ_EMPTY_MASK ,FIFO-uplink-empty event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" textline " " bitfld.long 0x00 8. " UP_IRQ_MASK ,FIFO-uplink-read-request event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 3. " DN_IRQ_FULL_MASK ,FIFO-downlink-full event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 2. " DN_IRQ_ALST_EMPTY_MASK ,FIFO downlink almost-empty event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" textline " " bitfld.long 0x00 1. " DN_IRQ_EMPTY_MASK ,FIFO-downlink-empty event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 0. " DN_IRQ_MASK ,FIFO downlink write-request event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" group.long 0x30++0x3 line.long 0x00 "MCPDM_IRQENABLE_CLR,Interrupt request enable clear register." bitfld.long 0x00 11. " UP_IRQ_FULL_MASK ,FIFO-uplink-full event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 10. " UP_IRQ_ALST_FULL_MASK ,FIFO-uplink-almost-full event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 9. " UP_IRQ_EMPTY_MASK ,FIFO-uplink-empty event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" textline " " bitfld.long 0x00 8. " UP_IRQ_MASK ,FIFO-uplink-read-request event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 3. " DN_IRQ_FULL_MASK ,FIFO-downlink-full event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 2. " DN_IRQ_ALST_EMPTY_MASK ,FIFO downlink almost-empty event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" textline " " bitfld.long 0x00 1. " DN_IRQ_EMPTY_MASK ,FIFO-downlink-empty event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 0. " DN_IRQ_MASK ,FIFO downlink write-request event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" group.long 0x34++0x3 line.long 0x00 "MCPDM_IRQWAKEEN,Interrupt request wake-up enable register." bitfld.long 0x00 1. " IRQ_WAKEUP_UP_EN ,Enabling/disabling bit for wake-up request generation upon a FIFO-uplink-read-request event. - . - ." "0,1" bitfld.long 0x00 0. " IRQ_WAKEUP_DN_EN ,Enabling/disabling bit for wake-up by FIFO downlink write-request event. - . - ." "0,1" group.long 0x38++0x3 line.long 0x00 "MCPDM_DMAENABLE_SET,DMA request enable set register." bitfld.long 0x00 1. " DMA_UP_ENABLE ,Uplink path DMA request generation enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 0. " DMA_DN_ENABLE ,Downlink path DMA request generation enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" group.long 0x3C++0x3 line.long 0x00 "MCPDM_DMAENABLE_CLR,DMA request enable clear register." bitfld.long 0x00 1. " DMA_UP_ENABLE ,Uplink path DMA request generation disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 0. " DMA_DN_ENABLE ,Downlink path DMA request generation disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" group.long 0x40++0x3 line.long 0x00 "MCPDM_DMAWAKEEN,DMA request wake-up enable register." bitfld.long 0x00 1. " DMA_WAKEUP_UP_EN ,Enabling/disabling bit for wake-up request generation upon an uplink path DMA request. - . - ." "0,1" bitfld.long 0x00 0. " DMA_WAKEUP_DN_EN ,Enabling/disabling bit for wake-up request generation upon a downlink path DMA request. - . - ." "0,1" group.long 0x44++0x3 line.long 0x00 "MCPDM_CTRL,MCPDM control register." bitfld.long 0x00 14. " WD_EN ,This bit is used to enable or disable the pulse-density modulator watchdog logic.0x0: Disabled (default after reset)0x1: Enabled" "0,1" bitfld.long 0x00 13. " DIV_SEL ,Multiply by 2 the FS of the uplink path0x0: FS = 88.2 kHz, or 96 kHz0x1: FS = 176.4 kHz, or 192 kHz" "0,1" bitfld.long 0x00 12. " SW_DN_RST ,Software reset of the downlink path. - . - ." "0,1" textline " " bitfld.long 0x00 11. " SW_UP_RST ,Software reset of the uplink path. - . - ." "0,1" bitfld.long 0x00 10. " STATUS_INT ,Status channel enabling/disabling bit. - . - ." "0,1" bitfld.long 0x00 9. " CMD_INT ,Command channel enabling/disabling bit. - . - ." "0,1" textline " " bitfld.long 0x00 8. " PDMOUTFORMAT ,Audio format selection: - . - ." "0,1" bitfld.long 0x00 7. " PDM_DN5_EN ,Audio downlink channel 5 enabling/disabling bit" "0,1" bitfld.long 0x00 6. " PDM_DN4_EN ,Audio downlink channel 4 enabling/disabling bit" "0,1" textline " " bitfld.long 0x00 5. " PDM_DN3_EN ,Audio downlink channel 3 enabling/disabling bit" "0,1" bitfld.long 0x00 4. " PDM_DN2_EN ,Audio downlink channel 2 enabling/disabling bit" "0,1" bitfld.long 0x00 3. " PDM_DN1_EN ,Audio downlink channel 1 enabling/disabling bit" "0,1" textline " " bitfld.long 0x00 2. " PDM_UP3_EN ,Audio uplink channel 3 enabling/disabling bit" "0,1" bitfld.long 0x00 1. " PDM_UP2_EN ,Audio uplink channel 2 enabling/disabling bit" "0,1" bitfld.long 0x00 0. " PDM_UP1_EN ,Audio uplink channel 1 enabling/disabling bit" "0,1" group.long 0x48++0x3 line.long 0x00 "MCPDM_DN_DATA,Downlink path data register." hexmask.long 0x00 0.--31. 1. " DN_DATA ,Downlink path data value" rgroup.long 0x4C++0x3 line.long 0x00 "MCPDM_UP_DATA,Uplink path data register." hexmask.long 0x00 0.--31. 1. " UP_DATA ,Uplink path data value" group.long 0x50++0x3 line.long 0x00 "MCPDM_FIFO_CTRL_DN,FIFO downlink control register." bitfld.long 0x00 0.--3. " DN_TRESH ,FIFO downlink threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x3 line.long 0x00 "MCPDM_FIFO_CTRL_UP,FIFO uplink control register." bitfld.long 0x00 0.--3. " UP_TRESH ,FIFO uplink threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x58++0x3 line.long 0x00 "MCPDM_DN_OFFSET," bitfld.long 0x00 9.--13. " DN_OFST_RX2 ,Offset value for the audio downlink channel 2" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8. " DN_OFST_RX2_EN ,Offset cancellation feature enabling/disabling bit for the audio downlink channel 2. - . - ." "0,1" bitfld.long 0x00 1.--5. " DN_OFST_RX1 ,Offset value for the audio downlink channel 1" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" textline " " bitfld.long 0x00 0. " DN_OFST_RX1_EN ,Offset cancellation feature enabling/disabling bit for the audio downlink channel 1. - . - ." "0,1" tree.end tree "McPDM_L3Interconnect" base ad:0x49032000 width 21. rgroup.long 0x0++0x3 line.long 0x00 "MCPDM_REVISION,IP revision identifier (X.Y.R) used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "MCPDM_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the idle mode. - . - . - . - ." "FORCE_Idle,NO_idle,SMART_idle,SMART_Idle_Wakeup" bitfld.long 0x00 1. " FREEMU ,Sensitivity to emulation (debug) suspend input signal. - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " SOFTRESET ,McPDM software Reset. - . - . - . - ." "NORMAL_/_NO_ACTION,RESET_/_RST_ON_GOING" group.long 0x24++0x3 line.long 0x00 "MCPDM_IRQSTATUS_RAW,Interrupt request raw status register (for debug purpose)." bitfld.long 0x00 11. " UP_IRQ_FULL ,FIFO-uplink-full signal appears when a write access is performed and the FIFO uplink is already full. - . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 10. " UP_IRQ_ALST_FULL ,FIFO uplink almost-full signal appears when the FIFO uplink contains (FIFO uplink size ? 1) elements. - . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 9. " UP_IRQ_EMPTY ,FIFO uplink empty signal appears when a read access is done and FIFO uplink already empty. - . - . - . - ." "none_/_noaction,pending_/_set" textline " " bitfld.long 0x00 8. " UP_IRQ ,FIFO uplink interrupt appears when the number of data present in the FIFO uplink has reached the value of the FIFO uplink threshold. - . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 3. " DN_IRQ_FULL ,FIFO downlink full signal appears when the FIFO uplink is full and another a write access is performed. - . - . - . - ." "0,1" bitfld.long 0x00 2. " DN_IRQ_ALST_EMPTY ,FIFO downlink almost empty signal appears when the FIFO downlink contains only one element. - . - . - . - ." "none_/_noaction,pending_/_set" textline " " bitfld.long 0x00 1. " DN_IRQ_EMPTY ,FIFO-downlink-empty signal appears when read access is performed and FIFO downlink is already empty. - . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 0. " DN_IRQ ,FIFO downlink status is set when the number of data is below the FIFO downlink threshold value. - . - . - . - ." "none_/_noaction,pending_/_set" group.long 0x28++0x3 line.long 0x00 "MCPDM_IRQSTATUS,Interrupt request status register." bitfld.long 0x00 11. " UP_IRQ_FULL ,FIFO-uplink-full signal appears when a write access is performed and the FIFO uplink is already full. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 10. " UP_IRQ_ALST_FULL ,FIFO uplink almost-full signal appears when the FIFO uplink contains (FIFO uplink size ? 1) elements. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 9. " UP_IRQ_EMPTY ,FIFO uplink empty signal appears when a read access is done and FIFO uplink already empty. - . - . - . - ." "none_/_noaction,pending_/_clear" textline " " bitfld.long 0x00 8. " UP_IRQ ,FIFO uplink interrupt appears when the number of data present in the FIFO uplink has reached the value of the FIFO uplink threshold. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 3. " DN_IRQ_FULL ,FIFO downlink full signal appears when the FIFO uplink is full and another a write access is performed. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 2. " DN_IRQ_ALST_EMPTY ,FIFO downlink almost empty signal appears when the FIFO downlink contains only one element. - . - . - . - ." "none_/_noaction,pending_/_clear" textline " " bitfld.long 0x00 1. " DN_IRQ_EMPTY ,FIFO-downlink-empty signal appears when read access is performed and FIFO downlink is already empty. - . - . - . - ." "none_/_noaction,pending_/_clear" bitfld.long 0x00 0. " DN_IRQ ,FIFO downlink status is set when the number of data is below the FIFO downlink threshold value. - . - . - . - ." "none_/_noaction,pending_/_clear" group.long 0x2C++0x3 line.long 0x00 "MCPDM_IRQENABLE_SET,Interrupt request enable set register." bitfld.long 0x00 11. " UP_IRQ_FULL_MASK ,FIFO-uplink-full event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 10. " UP_IRQ_ALST_FULL_MASK ,FIFO-uplink-almost-full event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 9. " UP_IRQ_EMPTY_MASK ,FIFO-uplink-empty event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" textline " " bitfld.long 0x00 8. " UP_IRQ_MASK ,FIFO-uplink-read-request event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 3. " DN_IRQ_FULL_MASK ,FIFO-downlink-full event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 2. " DN_IRQ_ALST_EMPTY_MASK ,FIFO downlink almost-empty event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" textline " " bitfld.long 0x00 1. " DN_IRQ_EMPTY_MASK ,FIFO-downlink-empty event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 0. " DN_IRQ_MASK ,FIFO downlink write-request event interrupt enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" group.long 0x30++0x3 line.long 0x00 "MCPDM_IRQENABLE_CLR,Interrupt request enable clear register." bitfld.long 0x00 11. " UP_IRQ_FULL_MASK ,FIFO-uplink-full event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 10. " UP_IRQ_ALST_FULL_MASK ,FIFO-uplink-almost-full event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 9. " UP_IRQ_EMPTY_MASK ,FIFO-uplink-empty event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" textline " " bitfld.long 0x00 8. " UP_IRQ_MASK ,FIFO-uplink-read-request event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 3. " DN_IRQ_FULL_MASK ,FIFO-downlink-full event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 2. " DN_IRQ_ALST_EMPTY_MASK ,FIFO downlink almost-empty event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" textline " " bitfld.long 0x00 1. " DN_IRQ_EMPTY_MASK ,FIFO-downlink-empty event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 0. " DN_IRQ_MASK ,FIFO downlink write-request event interrupt disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" group.long 0x34++0x3 line.long 0x00 "MCPDM_IRQWAKEEN,Interrupt request wake-up enable register." bitfld.long 0x00 1. " IRQ_WAKEUP_UP_EN ,Enabling/disabling bit for wake-up request generation upon a FIFO-uplink-read-request event. - . - ." "0,1" bitfld.long 0x00 0. " IRQ_WAKEUP_DN_EN ,Enabling/disabling bit for wake-up by FIFO downlink write-request event. - . - ." "0,1" group.long 0x38++0x3 line.long 0x00 "MCPDM_DMAENABLE_SET,DMA request enable set register." bitfld.long 0x00 1. " DMA_UP_ENABLE ,Uplink path DMA request generation enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 0. " DMA_DN_ENABLE ,Downlink path DMA request generation enabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_enable" group.long 0x3C++0x3 line.long 0x00 "MCPDM_DMAENABLE_CLR,DMA request enable clear register." bitfld.long 0x00 1. " DMA_UP_ENABLE ,Uplink path DMA request generation disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" bitfld.long 0x00 0. " DMA_DN_ENABLE ,Downlink path DMA request generation disabling bit. - . - . - . - ." "disabled_/_noaction,enabled_/_disable" group.long 0x40++0x3 line.long 0x00 "MCPDM_DMAWAKEEN,DMA request wake-up enable register." bitfld.long 0x00 1. " DMA_WAKEUP_UP_EN ,Enabling/disabling bit for wake-up request generation upon an uplink path DMA request. - . - ." "0,1" bitfld.long 0x00 0. " DMA_WAKEUP_DN_EN ,Enabling/disabling bit for wake-up request generation upon a downlink path DMA request. - . - ." "0,1" group.long 0x44++0x3 line.long 0x00 "MCPDM_CTRL,MCPDM control register." bitfld.long 0x00 14. " WD_EN ,This bit is used to enable or disable the pulse-density modulator watchdog logic.0x0: Disabled (default after reset)0x1: Enabled" "0,1" bitfld.long 0x00 13. " DIV_SEL ,Multiply by 2 the FS of the uplink path0x0: FS = 88.2 kHz, or 96 kHz0x1: FS = 176.4 kHz, or 192 kHz" "0,1" bitfld.long 0x00 12. " SW_DN_RST ,Software reset of the downlink path. - . - ." "0,1" textline " " bitfld.long 0x00 11. " SW_UP_RST ,Software reset of the uplink path. - . - ." "0,1" bitfld.long 0x00 10. " STATUS_INT ,Status channel enabling/disabling bit. - . - ." "0,1" bitfld.long 0x00 9. " CMD_INT ,Command channel enabling/disabling bit. - . - ." "0,1" textline " " bitfld.long 0x00 8. " PDMOUTFORMAT ,Audio format selection: - . - ." "0,1" bitfld.long 0x00 7. " PDM_DN5_EN ,Audio downlink channel 5 enabling/disabling bit" "0,1" bitfld.long 0x00 6. " PDM_DN4_EN ,Audio downlink channel 4 enabling/disabling bit" "0,1" textline " " bitfld.long 0x00 5. " PDM_DN3_EN ,Audio downlink channel 3 enabling/disabling bit" "0,1" bitfld.long 0x00 4. " PDM_DN2_EN ,Audio downlink channel 2 enabling/disabling bit" "0,1" bitfld.long 0x00 3. " PDM_DN1_EN ,Audio downlink channel 1 enabling/disabling bit" "0,1" textline " " bitfld.long 0x00 2. " PDM_UP3_EN ,Audio uplink channel 3 enabling/disabling bit" "0,1" bitfld.long 0x00 1. " PDM_UP2_EN ,Audio uplink channel 2 enabling/disabling bit" "0,1" bitfld.long 0x00 0. " PDM_UP1_EN ,Audio uplink channel 1 enabling/disabling bit" "0,1" group.long 0x48++0x3 line.long 0x00 "MCPDM_DN_DATA,Downlink path data register." hexmask.long 0x00 0.--31. 1. " DN_DATA ,Downlink path data value" rgroup.long 0x4C++0x3 line.long 0x00 "MCPDM_UP_DATA,Uplink path data register." hexmask.long 0x00 0.--31. 1. " UP_DATA ,Uplink path data value" group.long 0x50++0x3 line.long 0x00 "MCPDM_FIFO_CTRL_DN,FIFO downlink control register." bitfld.long 0x00 0.--3. " DN_TRESH ,FIFO downlink threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x3 line.long 0x00 "MCPDM_FIFO_CTRL_UP,FIFO uplink control register." bitfld.long 0x00 0.--3. " UP_TRESH ,FIFO uplink threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x58++0x3 line.long 0x00 "MCPDM_DN_OFFSET," bitfld.long 0x00 9.--13. " DN_OFST_RX2 ,Offset value for the audio downlink channel 2" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" bitfld.long 0x00 8. " DN_OFST_RX2_EN ,Offset cancellation feature enabling/disabling bit for the audio downlink channel 2. - . - ." "0,1" bitfld.long 0x00 1.--5. " DN_OFST_RX1 ,Offset value for the audio downlink channel 1" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" textline " " bitfld.long 0x00 0. " DN_OFST_RX1_EN ,Offset cancellation feature enabling/disabling bit for the audio downlink channel 1. - . - ." "0,1" tree.end tree.end tree.end tree.open "Digital_Microphone_Module" tree.open "DMIC_DSP" tree "DMIC_Cortex_A9" base ad:0x4012E000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "DMIC_REVISION,IP Revision Identifier (X.Y.R) used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "DMIC_SYSCONFIG,This register allows controlling various parameters of the DMIC interface." bitfld.long 0x00 2.--3. " SIDLEMODE ,Configuration of the local target state management (idlereq/idleack control) - . - . - . - ." "FORCE_Idle,NO_idle,SMART_idle,?..." bitfld.long 0x00 1. " FREEMU ,Sensitivity to emulation (debug) suspend input signal - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " SOFTRESET ,Module software reset. The bit is automatically reset by the hardware. It has same effect as the main hardware reset. - . - . - . - ." "NORMAL_/_NO_ACTION,RESET_/_RST_ON_GOING" group.long 0x24++0x3 line.long 0x00 "DMIC_IRQSTATUS_RAW,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 3. " DMIC_IRQ_EMPTY ,- . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 2. " DMIC_IRQ_ALST_FULL ,- . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 1. " DMIC_IRQ_FULL ,- . - . - . - ." "none_/_noaction,pending_/_set" textline " " bitfld.long 0x00 0. " DMIC_IRQ ,- . - . - . - ." "none_/_noaction,pending_/_set" group.long 0x28++0x3 line.long 0x00 "DMIC_IRQSTATUS,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets clea.." bitfld.long 0x00 3. " DMIC_IRQ_EMPTY ,- . - . - . - ." "none_/_noaction,pending_/_clear" eventfld.long 0x00 2. " DMIC_IRQ_ALST_FULL ,This interrupt status is set when only one FIFO space is still available. - . - . - . - ." "none_/_noaction,pending_/_clear" eventfld.long 0x00 1. " DMIC_IRQ_FULL ,This interrupt status is set when FIFO is full and a new write access has been performed by filter. - . - . - . - ." "none_/_noaction,pending_/_clear" textline " " eventfld.long 0x00 0. " DMIC_IRQ ,This interrupt status is set when FIFO threshold value defined inDMIC_FIFO_CTRL is reached. - . - . - . - ." "none_/_noaction,pending_/_clear" group.long 0x2C++0x3 line.long 0x00 "DMIC_IRQENABLE_SET,Component (that is, main) interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." bitfld.long 0x00 3. " DMIC_IRQ_EMPTY_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 2. " DMIC_IRQ_ALST_FULL_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 1. " DMIC_IRQ_FULL_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_enable" textline " " bitfld.long 0x00 0. " DMIC_IRQ_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_enable" group.long 0x30++0x3 line.long 0x00 "DMIC_IRQENABLE_CLR,Component (that is, main) interrupt request enable Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." eventfld.long 0x00 3. " DMIC_IRQ_EMPTY_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_disable" eventfld.long 0x00 2. " DMIC_IRQ_ALST_FULL_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_disable" eventfld.long 0x00 1. " DMIC_IRQ_FULL_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_disable" textline " " eventfld.long 0x00 0. " DMIC_IRQ_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_disable" group.long 0x34++0x3 line.long 0x00 "DMIC_IRQWAKEEN,This register allows to enable the wake-up capability on interrupt event." bitfld.long 0x00 0. " IRQ_WAKEUP_EN ,Write 1 to allow wake-up by IRQ source (register threshold value reached)." "0,1" group.long 0x38++0x3 line.long 0x00 "DMIC_DMAENABLE_SET,Component DMA enable (1 bit per DMA-capable channel)/Write 1 to set (enable DMA). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." bitfld.long 0x00 0. " DMA_ENABLE ,Write 1 to set (enable DMA request) - . - . - . - ." "disabled_/_noaction,enabled_/_enable" group.long 0x3C++0x3 line.long 0x00 "DMIC_DMAENABLE_CLR,Component DMA enable (1 bit per DMA-capable channel)/Write 1 to clear (disable DMA). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." eventfld.long 0x00 0. " DMA_ENABLE ,Write 1 to clear (disable DMA request) - . - . - . - ." "disabled_/_noaction,enabled_/_disable" group.long 0x40++0x3 line.long 0x00 "DMIC_DMAWAKEEN,This register allows to enable the wake-up capability on DMA request event." bitfld.long 0x00 0. " DMA_WAKEUP_EN ,Write 1 to allow wakeup by DMA source (register threshold value reached)." "0,1" group.long 0x44++0x3 line.long 0x00 "DMIC_CTRL,This register configures the various parameters of the DMIC module." bitfld.long 0x00 10. " SW_DMIC_RST ,Software reset of the DMIC path. When 1, the DMIC path is reset. Clearing the reset is done by writing 0 to the register." "0,1" bitfld.long 0x00 7.--9. " DMIC_CLK_DIV ,Select the DMIC output clock frequency. See for details." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. " DMIC_POLAR3 ,- . - ." "low_level,high_level" textline " " bitfld.long 0x00 5. " DMIC_POLAR2 ,- . - ." "low_level,high_level" bitfld.long 0x00 4. " DMIC_POLAR1 ,- . - ." "low_level,high_level" bitfld.long 0x00 3. " DMICOUTFORMAT ,When 0, the data going out from the FIFO are left shifted from 8 bits. When 1, the data going are signed extended on 32 bits" "0,1" textline " " bitfld.long 0x00 2. " DMIC_UP3_EN ,When 1, uplink path 3 is powered up." "0,1" bitfld.long 0x00 1. " DMIC_UP2_EN ,When 1, uplink path 2 is powered up." "0,1" bitfld.long 0x00 0. " DMIC_UP1_EN ,When 1, uplink path 1 is powered up." "0,1" rgroup.long 0x48++0x3 line.long 0x00 "DMIC_DATA_REG,DMIC FIFO data" hexmask.long 0x00 0.--31. 1. " DMIC_DATA ,DMIC FIFO data" group.long 0x4C++0x3 line.long 0x00 "DMIC_FIFO_CTRL,This register sets the FIFO threshold for the data-ready event." bitfld.long 0x00 0.--3. " DMIC_TRESH ,Uplink FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "DMIC_FIFO_DMIC1R_DATA,Data of the first FIFO DMIC right channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC1R_DAT ,Data of the right FIFO DMIC path 1" rgroup.long 0x54++0x3 line.long 0x00 "DMIC_FIFO_DMIC1L_DATA,Data of the first FIFO DMIC left channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC1R_DAT ,Data of the left FIFO DMIC path 1" rgroup.long 0x58++0x3 line.long 0x00 "DMIC_FIFO_DMIC2R_DATA,Data of the second FIFO DMIC right channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC2R_DAT ,Data of the right FIFO DMIC path 2" rgroup.long 0x5C++0x3 line.long 0x00 "DMIC_FIFO_DMIC2L_DATA,Data of the second FIFO DMIC left channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC2L_DAT ,Data of the left FIFO DMIC path 2" rgroup.long 0x60++0x3 line.long 0x00 "DMIC_FIFO_DMIC3R_DATA,Data of the third FIFO DMIC right channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC3R_DAT ,Data of the right FIFO DMIC path 3" rgroup.long 0x64++0x3 line.long 0x00 "DMIC_FIFO_DMIC3L_DATA,Data of the third FIFO DMIC left channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC3R_DAT ,Data of the left FIFO DMIC path 3" tree.end tree "DMIC_L3Interconnect" base ad:0x4902E000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "DMIC_REVISION,IP Revision Identifier (X.Y.R) used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "DMIC_SYSCONFIG,This register allows controlling various parameters of the DMIC interface." bitfld.long 0x00 2.--3. " SIDLEMODE ,Configuration of the local target state management (idlereq/idleack control) - . - . - . - ." "FORCE_Idle,NO_idle,SMART_idle,?..." bitfld.long 0x00 1. " FREEMU ,Sensitivity to emulation (debug) suspend input signal - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " SOFTRESET ,Module software reset. The bit is automatically reset by the hardware. It has same effect as the main hardware reset. - . - . - . - ." "NORMAL_/_NO_ACTION,RESET_/_RST_ON_GOING" group.long 0x24++0x3 line.long 0x00 "DMIC_IRQSTATUS_RAW,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 3. " DMIC_IRQ_EMPTY ,- . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 2. " DMIC_IRQ_ALST_FULL ,- . - . - . - ." "none_/_noaction,pending_/_set" bitfld.long 0x00 1. " DMIC_IRQ_FULL ,- . - . - . - ." "none_/_noaction,pending_/_set" textline " " bitfld.long 0x00 0. " DMIC_IRQ ,- . - . - . - ." "none_/_noaction,pending_/_set" group.long 0x28++0x3 line.long 0x00 "DMIC_IRQSTATUS,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets clea.." bitfld.long 0x00 3. " DMIC_IRQ_EMPTY ,- . - . - . - ." "none_/_noaction,pending_/_clear" eventfld.long 0x00 2. " DMIC_IRQ_ALST_FULL ,This interrupt status is set when only one FIFO space is still available. - . - . - . - ." "none_/_noaction,pending_/_clear" eventfld.long 0x00 1. " DMIC_IRQ_FULL ,This interrupt status is set when FIFO is full and a new write access has been performed by filter. - . - . - . - ." "none_/_noaction,pending_/_clear" textline " " eventfld.long 0x00 0. " DMIC_IRQ ,This interrupt status is set when FIFO threshold value defined inDMIC_FIFO_CTRL is reached. - . - . - . - ." "none_/_noaction,pending_/_clear" group.long 0x2C++0x3 line.long 0x00 "DMIC_IRQENABLE_SET,Component (that is, main) interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." bitfld.long 0x00 3. " DMIC_IRQ_EMPTY_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 2. " DMIC_IRQ_ALST_FULL_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_enable" bitfld.long 0x00 1. " DMIC_IRQ_FULL_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_enable" textline " " bitfld.long 0x00 0. " DMIC_IRQ_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_enable" group.long 0x30++0x3 line.long 0x00 "DMIC_IRQENABLE_CLR,Component (that is, main) interrupt request enable Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." eventfld.long 0x00 3. " DMIC_IRQ_EMPTY_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_disable" eventfld.long 0x00 2. " DMIC_IRQ_ALST_FULL_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_disable" eventfld.long 0x00 1. " DMIC_IRQ_FULL_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_disable" textline " " eventfld.long 0x00 0. " DMIC_IRQ_MASK ,- . - . - . - ." "disabled_/_noaction,enabled_/_disable" group.long 0x34++0x3 line.long 0x00 "DMIC_IRQWAKEEN,This register allows to enable the wake-up capability on interrupt event." bitfld.long 0x00 0. " IRQ_WAKEUP_EN ,Write 1 to allow wake-up by IRQ source (register threshold value reached)." "0,1" group.long 0x38++0x3 line.long 0x00 "DMIC_DMAENABLE_SET,Component DMA enable (1 bit per DMA-capable channel)/Write 1 to set (enable DMA). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." bitfld.long 0x00 0. " DMA_ENABLE ,Write 1 to set (enable DMA request) - . - . - . - ." "disabled_/_noaction,enabled_/_enable" group.long 0x3C++0x3 line.long 0x00 "DMIC_DMAENABLE_CLR,Component DMA enable (1 bit per DMA-capable channel)/Write 1 to clear (disable DMA). Readout equal to corresponding _SET register. _SET register is cleared when writing 1 to _CLR register." eventfld.long 0x00 0. " DMA_ENABLE ,Write 1 to clear (disable DMA request) - . - . - . - ." "disabled_/_noaction,enabled_/_disable" group.long 0x40++0x3 line.long 0x00 "DMIC_DMAWAKEEN,This register allows to enable the wake-up capability on DMA request event." bitfld.long 0x00 0. " DMA_WAKEUP_EN ,Write 1 to allow wakeup by DMA source (register threshold value reached)." "0,1" group.long 0x44++0x3 line.long 0x00 "DMIC_CTRL,This register configures the various parameters of the DMIC module." bitfld.long 0x00 10. " SW_DMIC_RST ,Software reset of the DMIC path. When 1, the DMIC path is reset. Clearing the reset is done by writing 0 to the register." "0,1" bitfld.long 0x00 7.--9. " DMIC_CLK_DIV ,Select the DMIC output clock frequency. See for details." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. " DMIC_POLAR3 ,- . - ." "low_level,high_level" textline " " bitfld.long 0x00 5. " DMIC_POLAR2 ,- . - ." "low_level,high_level" bitfld.long 0x00 4. " DMIC_POLAR1 ,- . - ." "low_level,high_level" bitfld.long 0x00 3. " DMICOUTFORMAT ,When 0, the data going out from the FIFO are left shifted from 8 bits. When 1, the data going are signed extended on 32 bits" "0,1" textline " " bitfld.long 0x00 2. " DMIC_UP3_EN ,When 1, uplink path 3 is powered up." "0,1" bitfld.long 0x00 1. " DMIC_UP2_EN ,When 1, uplink path 2 is powered up." "0,1" bitfld.long 0x00 0. " DMIC_UP1_EN ,When 1, uplink path 1 is powered up." "0,1" rgroup.long 0x48++0x3 line.long 0x00 "DMIC_DATA_REG,DMIC FIFO data" hexmask.long 0x00 0.--31. 1. " DMIC_DATA ,DMIC FIFO data" group.long 0x4C++0x3 line.long 0x00 "DMIC_FIFO_CTRL,This register sets the FIFO threshold for the data-ready event." bitfld.long 0x00 0.--3. " DMIC_TRESH ,Uplink FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x50++0x3 line.long 0x00 "DMIC_FIFO_DMIC1R_DATA,Data of the first FIFO DMIC right channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC1R_DAT ,Data of the right FIFO DMIC path 1" rgroup.long 0x54++0x3 line.long 0x00 "DMIC_FIFO_DMIC1L_DATA,Data of the first FIFO DMIC left channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC1R_DAT ,Data of the left FIFO DMIC path 1" rgroup.long 0x58++0x3 line.long 0x00 "DMIC_FIFO_DMIC2R_DATA,Data of the second FIFO DMIC right channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC2R_DAT ,Data of the right FIFO DMIC path 2" rgroup.long 0x5C++0x3 line.long 0x00 "DMIC_FIFO_DMIC2L_DATA,Data of the second FIFO DMIC left channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC2L_DAT ,Data of the left FIFO DMIC path 2" rgroup.long 0x60++0x3 line.long 0x00 "DMIC_FIFO_DMIC3R_DATA,Data of the third FIFO DMIC right channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC3R_DAT ,Data of the right FIFO DMIC path 3" rgroup.long 0x64++0x3 line.long 0x00 "DMIC_FIFO_DMIC3L_DATA,Data of the third FIFO DMIC left channel" hexmask.long.tbyte 0x00 0.--23. 1. " FIFO_DMIC3R_DAT ,Data of the left FIFO DMIC path 3" tree.end tree.end tree.end tree.open "Multichannel_Audio_Serial_Port" tree.open "McASP_DSP" tree "McASP_Cortex_A9" base ad:0x40128000 tree "Channel_0" width 18. group.long 0x100++0x3 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x118++0x3 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x130++0x3 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x148++0x3 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_1" width 18. group.long 0x104++0x3 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x11C++0x3 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x134++0x3 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x14C++0x3 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_2" width 18. group.long 0x108++0x3 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x120++0x3 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x138++0x3 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x150++0x3 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_3" width 18. group.long 0x10C++0x3 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x124++0x3 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x13C++0x3 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x154++0x3 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_4" width 18. group.long 0x110++0x3 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x128++0x3 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x140++0x3 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x158++0x3 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_5" width 18. group.long 0x114++0x3 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x12C++0x3 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x144++0x3 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x15C++0x3 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end textline "" width 17. rgroup.long 0x0++0x3 line.long 0x00 "MCASP_PID,Peripheral identification register" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x4++0x3 line.long 0x00 "MCASP_SYSCONFIG,Power idle module configuration register." bitfld.long 0x00 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" group.long 0x10++0x3 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a McASP pin or a GPIO pin" bitfld.long 0x00 28. " AFSX ,Determines if abe_mcasp_afsx pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" bitfld.long 0x00 27. " AHCLKX ,Determines if abe_mcasp_ahclkx pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" bitfld.long 0x00 26. " ACLKX ,Determines if abe_mcasp_aclkx pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" textline " " bitfld.long 0x00 25. " AMUTE ,Determines if abe_mcasp_amute pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" bitfld.long 0x00 0. " AXR0 ,Determines if abe_mcasp_axr pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" group.long 0x14++0x3 line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the McASP pins as either an input or an output pin. For the module to operate properly, configure them as outputs." bitfld.long 0x00 28. " AFSX ,Determines if abe_mcasp_afsx pin functions as an input or output. - . - ." "INPUT,OUTPUT" bitfld.long 0x00 27. " AHCLKX ,Determines if abe_mcasp_ahclkx pin functions as an input or output. - . - ." "INPUT,OUTPUT" bitfld.long 0x00 26. " ACLKX ,Determines if abe_mcasp_aclkx pin functions as an input or output. - . - ." "INPUT,OUTPUT" textline " " bitfld.long 0x00 25. " AMUTE ,Determines if abe_mcasp_amute pin functions as an input or output. - . - ." "INPUT,OUTPUT" bitfld.long 0x00 0. " AXR0 ,Determines if abe_mcasp_axr pin functions as an input or output. - . - ." "INPUT,OUTPUT" group.long 0x18++0x3 line.long 0x00 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the McASP pin only if the correspondi.." bitfld.long 0x00 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1. - . - ." "DRV0,DRV1" bitfld.long 0x00 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1. - . - ." "DRV0,DRV1" bitfld.long 0x00 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1 - . - ." "DRV0,DRV1" textline " " bitfld.long 0x00 25. " AMUTE ,Determines drive on AMUTE output pin when the correspondingMCASP_PFUNC[25] and MCASP_PDIR[25] bits are set to 1. - . - ." "DRV0,DRV1" bitfld.long 0x00 0. " AXR0 ,Determines drive on abe_mcasp_axr output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1. - . - ." "DRV0,DRV1" rgroup.long 0x1C++0x3 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the McASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x00 28. " AFSX ,Logic level on abe_mcasp_afsx pin. - . - ." "LOW,HIGH" bitfld.long 0x00 27. " AHCLKX ,Logic level on abe_mcasp_ahclkx pin. - . - ." "LOW,HIGH" bitfld.long 0x00 26. " ACLKX ,Logic level on abe_mcasp_aclkx pin. - . - ." "LOW,HIGH" textline " " bitfld.long 0x00 25. " AMUTE ,Logic level on abe_mcasp_amute pin. - . - ." "LOW,HIGH" bitfld.long 0x00 0. " AXR0 ,Logic level on abe_mcasp_axr pin. - . - ." "LOW,HIGH" wgroup.long 0x1C++0x3 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x00 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" bitfld.long 0x00 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" bitfld.long 0x00 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" textline " " bitfld.long 0x00 25. " AMUTE ,Allows the corresponding AMUTE bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" bitfld.long 0x00 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" group.long 0x20++0x3 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x00 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" bitfld.long 0x00 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" bitfld.long 0x00 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" textline " " bitfld.long 0x00 25. " AMUTE ,Allows the corresponding AMUTE bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" bitfld.long 0x00 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" group.long 0x44++0x3 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit section. The bit fields in are synchronized and latched by the abe_mcasp_aclkx clock. Before programming , ensure that the serial clocks are running. If the corresp.." bitfld.long 0x00 12. " XFRST ,Transmit frame-sync generator reset enable bit - . - ." "RESET,ACTIVE" bitfld.long 0x00 11. " XSMRST ,Transmit state-machine reset enable bit - . abe_mcasp_axr pin state: If[0] = 0 and [0] = 1, the serializer drives the abe_mcasp_axr pin to the state specified for inactive time slot. - . - ." "RESET,ACTIVE" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the.." "CLEAR,ACTIVE" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit - . - ." "RESET,ACTIVE" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable bit - . - ." "RESET,ACTIVE" group.long 0x48++0x3 line.long 0x00 "MCASP_AMUTE,Mute control register - Controls the McASP mute output pin (abe_mcasp_amute)" bitfld.long 0x00 12. " XDMAERR ,Drives AMUTE active enable bit on transmit DMA error (XDMAERR). - . - ." "DISABLE,ENABLE" bitfld.long 0x00 10. " XCKFAIL ,XMT bad clock. Drives AMUTE active enable bit on transmit clock failure (XCKFAIL). - . - ." "DISABLE,ENABLE" bitfld.long 0x00 8. " XSYNCERR ,XMT unexpected FS. Drives AMUTE active enable bit on unexpected transmit frame-sync error (XSYNCERR). - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 6. " XUNDRN ,XMT underrun occurs. Drives AMUTE active enable bit on ransmit underrun error (XUNDRN). - . - ." "DISABLE,ENABLE" bitfld.long 0x00 4. " INSTAT ,Status of mute in pin, determines drive on abe_mcasp_axr pin when theMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1. - . - ." "ACTIVE,INACTIVE" bitfld.long 0x00 3. " INEN ,Drive abe_mcasp_amute active when abe_mcasp_amutein error is active. - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 2. " INPOL ,Audio mute in (abe_mcasp_amutein) polarity select bit - . - ." "ACTHIGH,ACTLOW" bitfld.long 0x00 0.--1. " MUTEN ,abe_mcasp_amute pin enable bit field (unless overridden by GPIO registers) - . - . - ." "DISABLE,ERRHIGH,ERRLOW,3" group.long 0x50++0x3 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the McASP" bitfld.long 0x00 3. " VB ,Valid bit for odd time slots (DIT right subframe). - . - ." "ZEROSTUFF,ONESTUFF" bitfld.long 0x00 2. " VA ,Valid bit for even time slots (DIT left subframe). - . - ." "ZEROSTUFF,ONESTUFF" bitfld.long 0x00 0. " DITEN ,DIT mode enable bit - . - ." "DISABLE,ENABLE" group.long 0xA4++0x3 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the McASP" hexmask.long 0x00 0.--31. 1. " XMASK[31:0] ,Transmit data mask enable bit - . - ." group.long 0xA8++0x3 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. " XDATDLY ,Transmit sync bit delay - . - . - ." "0BIT,1BIT,2BIT,3" bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order 0x0: Bitstream is LSB first. No bit reversal is performed in transmit format unit. 0x1: Reserved" "LSBFIRST,MSBFIRST" bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0. 0x0: Pad extra bits with 0. 0x1 to 0x3: Reserved" "ZERO,ONE,XPBIT,3" textline " " bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size0x0 to 0xE: Reserved. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,32BITS" bitfld.long 0x00 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF originate from the peripheral configuration port or the DMA port. - . - ." "VBUSP,VBUS" bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit - . - . - . - . - . - . - . - ." "NONE,4BITS,8BITS,12BITS,16BITS,20BITS,24BITS,28BITS" group.long 0xAC++0x3 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (abe_mcasp_afsx)." hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x180: 384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (abe_mcasp_afsx) during its active period. - . - ." "BIT,WORD" bitfld.long 0x00 1. " FSXM ,Transmit frame-sync generation select bit - . - ." "EXTERNAL,INTERNAL" textline " " bitfld.long 0x00 0. " FSXP ,Transmit frame-sync polarity select bit - . - ." "RISINGEDGE,FALLINGEDGE" group.long 0xB0++0x3 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (abe_mcasp_aclkx) and the transmit clock generator." bitfld.long 0x00 6. " ASYNC ,Transmit operation asynchronous enable bit - . - ." "SYNC,ASYNC" bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source bit - . - ." "EXTERNAL,INTERNAL" bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0xB4++0x3 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (abe_mcasp_ahclkx) and the transmit clock generator." bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source bit - . - ." "EXTERNAL,INTERNAL" hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to abe_mcasp_ahclkx. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" group.long 0xB8++0x3 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x00 0.--31. 1. " XTDMS[31:0] ,Transmitter mode during TDM time slot n - . - ." group.long 0xBC++0x3 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates XINT." bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable bit - . - ." "DISABLE,ENABLE" bitfld.long 0x00 5. " XDATA ,Transmit data-ready interrupt enable bit - . - ." "DISABLE,ENABLE" bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable bit - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable bit - . - ." "DISABLE,ENABLE" bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable bit - . - ." "DISABLE,ENABLE" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable bit - . - ." "DISABLE,ENABLE" group.long 0xC0++0x3 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set. This also causes the generation of a n.." bitfld.long 0x00 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred. - . - ." "NOERROR,ERROR" bitfld.long 0x00 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the data port of the McASPin a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit.." "NOTOCCUR,OCCUR" bitfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect. - . - ." "NOTOCCUR,OCCUR" textline " " bitfld.long 0x00 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect - . - ." "NOTOCCUR,OCCUR" bitfld.long 0x00 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writi.." "NOTOCCUR,OCCUR" bitfld.long 0x00 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd. - . - ." "ODDSLOT,EVENSLOT" textline " " bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit..." "NOTOCCUR,OCCUR" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing .." "NOTOCCUR,OCCUR" bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR, but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bi.." "NOTOCCUR,OCCUR" rgroup.long 0xC4++0x3 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." group.long 0xC8++0x3 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock (abe_mcasp_ahclkx) signals, and stores the count in XCNT until the .." hexmask.long.byte 0x00 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (abe_mcasp_ahclkx) signals have been received. If t.." hexmask.long.byte 0x00 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (abe_mcasp_ahclkx) signals have been received. If XCN.." textline " " bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value 0x0: McASP system clock divided by 1 0x1: McASP system clock divided by 2 0x2: McASP system clock divided by 4 0x3: McASP system clock divided by 8 0x4: McASP system clock divided by 16 0x5: McASP syst.." "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128,DIVBY256,9,10,11,12,13,14,15" group.long 0xCC++0x3 line.long 0x00 "MCASP_TXEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. " XDATDMA ,Transmit data DMA request enable bit. When writing to this field, always write the default value of 0. - . - ." "0,1" group.long 0x180++0x3 line.long 0x00 "MCASP_XRSRCTL0,Serializer control register" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit - . - ." "DATA,EMPTY" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit - . - ." "INACTIVE,XMT,2,3" group.long 0x200++0x3 line.long 0x00 "MCASP_TXBUF0,Transmit buffer - The transmit buffer for the serializer holds data from the transmit format unit." hexmask.long 0x00 0.--31. 1. " XBUF0 ,Transmit buffer" tree.end tree "McASP_L3Interconnect" base ad:0x49028000 tree "Channel_0" width 18. group.long 0x100++0x3 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x118++0x3 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x130++0x3 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x148++0x3 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_1" width 18. group.long 0x104++0x3 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x11C++0x3 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x134++0x3 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x14C++0x3 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_2" width 18. group.long 0x108++0x3 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x120++0x3 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x138++0x3 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x150++0x3 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_3" width 18. group.long 0x10C++0x3 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x124++0x3 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x13C++0x3 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x154++0x3 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_4" width 18. group.long 0x110++0x3 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x128++0x3 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x140++0x3 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x158++0x3 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end tree "Channel_5" width 18. group.long 0x114++0x3 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register .." hexmask.long 0x00 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.long 0x12C++0x3 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (I = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register.." hexmask.long 0x00 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.long 0x144++0x3 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same.." hexmask.long 0x00 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.long 0x15C++0x3 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (I = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data f.." hexmask.long 0x00 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" tree.end textline "" width 17. rgroup.long 0x0++0x3 line.long 0x00 "MCASP_PID,Peripheral identification register" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x4++0x3 line.long 0x00 "MCASP_SYSCONFIG,Power idle module configuration register." bitfld.long 0x00 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" group.long 0x10++0x3 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a McASP pin or a GPIO pin" bitfld.long 0x00 28. " AFSX ,Determines if abe_mcasp_afsx pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" bitfld.long 0x00 27. " AHCLKX ,Determines if abe_mcasp_ahclkx pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" bitfld.long 0x00 26. " ACLKX ,Determines if abe_mcasp_aclkx pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" textline " " bitfld.long 0x00 25. " AMUTE ,Determines if abe_mcasp_amute pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" bitfld.long 0x00 0. " AXR0 ,Determines if abe_mcasp_axr pin functions as McASP or GPIO. - . - ." "MCASP,GPIO" group.long 0x14++0x3 line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the McASP pins as either an input or an output pin. For the module to operate properly, configure them as outputs." bitfld.long 0x00 28. " AFSX ,Determines if abe_mcasp_afsx pin functions as an input or output. - . - ." "INPUT,OUTPUT" bitfld.long 0x00 27. " AHCLKX ,Determines if abe_mcasp_ahclkx pin functions as an input or output. - . - ." "INPUT,OUTPUT" bitfld.long 0x00 26. " ACLKX ,Determines if abe_mcasp_aclkx pin functions as an input or output. - . - ." "INPUT,OUTPUT" textline " " bitfld.long 0x00 25. " AMUTE ,Determines if abe_mcasp_amute pin functions as an input or output. - . - ." "INPUT,OUTPUT" bitfld.long 0x00 0. " AXR0 ,Determines if abe_mcasp_axr pin functions as an input or output. - . - ." "INPUT,OUTPUT" group.long 0x18++0x3 line.long 0x00 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the McASP pin only if the correspondi.." bitfld.long 0x00 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1. - . - ." "DRV0,DRV1" bitfld.long 0x00 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1. - . - ." "DRV0,DRV1" bitfld.long 0x00 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1 - . - ." "DRV0,DRV1" textline " " bitfld.long 0x00 25. " AMUTE ,Determines drive on AMUTE output pin when the correspondingMCASP_PFUNC[25] and MCASP_PDIR[25] bits are set to 1. - . - ." "DRV0,DRV1" bitfld.long 0x00 0. " AXR0 ,Determines drive on abe_mcasp_axr output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1. - . - ." "DRV0,DRV1" rgroup.long 0x1C++0x3 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the McASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x00 28. " AFSX ,Logic level on abe_mcasp_afsx pin. - . - ." "LOW,HIGH" bitfld.long 0x00 27. " AHCLKX ,Logic level on abe_mcasp_ahclkx pin. - . - ." "LOW,HIGH" bitfld.long 0x00 26. " ACLKX ,Logic level on abe_mcasp_aclkx pin. - . - ." "LOW,HIGH" textline " " bitfld.long 0x00 25. " AMUTE ,Logic level on abe_mcasp_amute pin. - . - ." "LOW,HIGH" bitfld.long 0x00 0. " AXR0 ,Logic level on abe_mcasp_axr pin. - . - ." "LOW,HIGH" wgroup.long 0x1C++0x3 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x00 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" bitfld.long 0x00 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" bitfld.long 0x00 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" textline " " bitfld.long 0x00 25. " AMUTE ,Allows the corresponding AMUTE bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" bitfld.long 0x00 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,SET" group.long 0x20++0x3 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x00 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" bitfld.long 0x00 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" bitfld.long 0x00 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" textline " " bitfld.long 0x00 25. " AMUTE ,Allows the corresponding AMUTE bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" bitfld.long 0x00 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. - . - ." "NOEFFECT,CLEAR" group.long 0x44++0x3 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit section. The bit fields in are synchronized and latched by the abe_mcasp_aclkx clock. Before programming , ensure that the serial clocks are running. If the corresp.." bitfld.long 0x00 12. " XFRST ,Transmit frame-sync generator reset enable bit - . - ." "RESET,ACTIVE" bitfld.long 0x00 11. " XSMRST ,Transmit state-machine reset enable bit - . abe_mcasp_axr pin state: If[0] = 0 and [0] = 1, the serializer drives the abe_mcasp_axr pin to the state specified for inactive time slot. - . - ." "RESET,ACTIVE" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the.." "CLEAR,ACTIVE" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit - . - ." "RESET,ACTIVE" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable bit - . - ." "RESET,ACTIVE" group.long 0x48++0x3 line.long 0x00 "MCASP_AMUTE,Mute control register - Controls the McASP mute output pin (abe_mcasp_amute)" bitfld.long 0x00 12. " XDMAERR ,Drives AMUTE active enable bit on transmit DMA error (XDMAERR). - . - ." "DISABLE,ENABLE" bitfld.long 0x00 10. " XCKFAIL ,XMT bad clock. Drives AMUTE active enable bit on transmit clock failure (XCKFAIL). - . - ." "DISABLE,ENABLE" bitfld.long 0x00 8. " XSYNCERR ,XMT unexpected FS. Drives AMUTE active enable bit on unexpected transmit frame-sync error (XSYNCERR). - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 6. " XUNDRN ,XMT underrun occurs. Drives AMUTE active enable bit on ransmit underrun error (XUNDRN). - . - ." "DISABLE,ENABLE" bitfld.long 0x00 4. " INSTAT ,Status of mute in pin, determines drive on abe_mcasp_axr pin when theMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1. - . - ." "ACTIVE,INACTIVE" bitfld.long 0x00 3. " INEN ,Drive abe_mcasp_amute active when abe_mcasp_amutein error is active. - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 2. " INPOL ,Audio mute in (abe_mcasp_amutein) polarity select bit - . - ." "ACTHIGH,ACTLOW" bitfld.long 0x00 0.--1. " MUTEN ,abe_mcasp_amute pin enable bit field (unless overridden by GPIO registers) - . - . - ." "DISABLE,ERRHIGH,ERRLOW,3" group.long 0x50++0x3 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the McASP" bitfld.long 0x00 3. " VB ,Valid bit for odd time slots (DIT right subframe). - . - ." "ZEROSTUFF,ONESTUFF" bitfld.long 0x00 2. " VA ,Valid bit for even time slots (DIT left subframe). - . - ." "ZEROSTUFF,ONESTUFF" bitfld.long 0x00 0. " DITEN ,DIT mode enable bit - . - ." "DISABLE,ENABLE" group.long 0xA4++0x3 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the McASP" hexmask.long 0x00 0.--31. 1. " XMASK[31:0] ,Transmit data mask enable bit - . - ." group.long 0xA8++0x3 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. " XDATDLY ,Transmit sync bit delay - . - . - ." "0BIT,1BIT,2BIT,3" bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order 0x0: Bitstream is LSB first. No bit reversal is performed in transmit format unit. 0x1: Reserved" "LSBFIRST,MSBFIRST" bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0. 0x0: Pad extra bits with 0. 0x1 to 0x3: Reserved" "ZERO,ONE,XPBIT,3" textline " " bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size0x0 to 0xE: Reserved. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,32BITS" bitfld.long 0x00 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF originate from the peripheral configuration port or the DMA port. - . - ." "VBUSP,VBUS" bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit - . - . - . - . - . - . - . - ." "NONE,4BITS,8BITS,12BITS,16BITS,20BITS,24BITS,28BITS" group.long 0xAC++0x3 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (abe_mcasp_afsx)." hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x180: 384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (abe_mcasp_afsx) during its active period. - . - ." "BIT,WORD" bitfld.long 0x00 1. " FSXM ,Transmit frame-sync generation select bit - . - ." "EXTERNAL,INTERNAL" textline " " bitfld.long 0x00 0. " FSXP ,Transmit frame-sync polarity select bit - . - ." "RISINGEDGE,FALLINGEDGE" group.long 0xB0++0x3 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (abe_mcasp_aclkx) and the transmit clock generator." bitfld.long 0x00 6. " ASYNC ,Transmit operation asynchronous enable bit - . - ." "SYNC,ASYNC" bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source bit - . - ." "EXTERNAL,INTERNAL" bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" group.long 0xB4++0x3 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (abe_mcasp_ahclkx) and the transmit clock generator." bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source bit - . - ." "EXTERNAL,INTERNAL" hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to abe_mcasp_ahclkx. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" group.long 0xB8++0x3 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x00 0.--31. 1. " XTDMS[31:0] ,Transmitter mode during TDM time slot n - . - ." group.long 0xBC++0x3 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates XINT." bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable bit - . - ." "DISABLE,ENABLE" bitfld.long 0x00 5. " XDATA ,Transmit data-ready interrupt enable bit - . - ." "DISABLE,ENABLE" bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable bit - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable bit - . - ." "DISABLE,ENABLE" bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable bit - . - ." "DISABLE,ENABLE" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit - . - ." "DISABLE,ENABLE" textline " " bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable bit - . - ." "DISABLE,ENABLE" group.long 0xC0++0x3 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set. This also causes the generation of a n.." bitfld.long 0x00 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred. - . - ." "NOERROR,ERROR" bitfld.long 0x00 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the data port of the McASPin a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit.." "NOTOCCUR,OCCUR" bitfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect. - . - ." "NOTOCCUR,OCCUR" textline " " bitfld.long 0x00 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect - . - ." "NOTOCCUR,OCCUR" bitfld.long 0x00 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writi.." "NOTOCCUR,OCCUR" bitfld.long 0x00 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd. - . - ." "ODDSLOT,EVENSLOT" textline " " bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit..." "NOTOCCUR,OCCUR" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing .." "NOTOCCUR,OCCUR" bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR, but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bi.." "NOTOCCUR,OCCUR" rgroup.long 0xC4++0x3 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." group.long 0xC8++0x3 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock (abe_mcasp_ahclkx) signals, and stores the count in XCNT until the .." hexmask.long.byte 0x00 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (abe_mcasp_ahclkx) signals have been received. If t.." hexmask.long.byte 0x00 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (abe_mcasp_ahclkx) signals have been received. If XCN.." textline " " bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value 0x0: McASP system clock divided by 1 0x1: McASP system clock divided by 2 0x2: McASP system clock divided by 4 0x3: McASP system clock divided by 8 0x4: McASP system clock divided by 16 0x5: McASP syst.." "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128,DIVBY256,9,10,11,12,13,14,15" group.long 0xCC++0x3 line.long 0x00 "MCASP_TXEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. " XDATDMA ,Transmit data DMA request enable bit. When writing to this field, always write the default value of 0. - . - ." "0,1" group.long 0x180++0x3 line.long 0x00 "MCASP_XRSRCTL0,Serializer control register" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit - . - ." "DATA,EMPTY" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit - . - ." "INACTIVE,XMT,2,3" group.long 0x200++0x3 line.long 0x00 "MCASP_TXBUF0,Transmit buffer - The transmit buffer for the serializer holds data from the transmit format unit." hexmask.long 0x00 0.--31. 1. " XBUF0 ,Transmit buffer" tree.end tree.end tree.end tree.open "Serial_Low_Power_Inter_Chip_Media_Bus_Controller" tree "SLIMBUS2_L3Interconnect" base ad:0x48076000 tree "Channel_0" width 29. group.long 0x294++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_0,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x298++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_0,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x29C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_0,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x284++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_0,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x288++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_0,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x28C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_0,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x280++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_0,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x290++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_0,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x214++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_0,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x218++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_0,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x21C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_0,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x204++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_0,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x208++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_0,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x20C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_0,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x200++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_0,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x210++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_0,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x108++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_0,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x104++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_0,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x100++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_0,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_1" width 29. group.long 0x2B4++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_1,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2B8++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_1,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x2BC++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_1,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x2A4++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_1,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x2A8++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_1,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x2AC++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_1,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x2A0++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_1,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2B0++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_1,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x234++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_1,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x238++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_1,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x23C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_1,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x224++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_1,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x228++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_1,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x22C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_1,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x220++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_1,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x230++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_1,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x118++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_1,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x114++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_1,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x110++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_1,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_2" width 29. group.long 0x2D4++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_2,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2D8++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_2,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x2DC++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_2,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x2C4++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_2,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x2C8++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_2,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x2CC++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_2,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x2C0++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_2,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2D0++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_2,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x254++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_2,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x258++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_2,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x25C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_2,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x244++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_2,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x248++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_2,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x24C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_2,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x240++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_2,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x250++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_2,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x128++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_2,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x124++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_2,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x120++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_2,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_3" width 29. group.long 0x2F4++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_3,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F8++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_3,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x2FC++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_3,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x2E4++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_3,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x2E8++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_3,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x2EC++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_3,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x2E0++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_3,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2F0++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_3,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x274++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_3,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x278++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_3,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x27C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_3,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x264++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_3,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x268++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_3,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x26C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_3,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x260++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_3,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x270++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_3,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x138++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_3,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x134++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_3,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x130++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_3,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_4" width 23. rgroup.long 0x148++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_4,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x144++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_4,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x140++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_4,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_5" width 23. rgroup.long 0x158++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_5,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x154++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_5,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x150++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_5,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_6" width 23. rgroup.long 0x168++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_6,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x164++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_6,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x160++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_6,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end textline "" width 28. rgroup.long 0x0++0x3 line.long 0x00 "SLIMBUS_CMP_REVISION,IP Revision Identifier Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,Revision Number" rgroup.long 0x4++0x3 line.long 0x00 "SLIMBUS_CMP_HWINFO,Those read-only, hardcoded fields display the values of the eponymous hardware configuration depending on module instantiation - SLIMBUS1 or SLIMBUS2." bitfld.long 0x00 28.--31. " DEV ,Device count: number of devices supported by the component, most notably through the automatically reception of the messages addressed to them. Sets the number of instances of the 'DEV_XYZ' registers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TDC ,Transmit Data agent Count: Number of transmit hardware data agents (FIFO and associated logic) Sets the number of instances of the 'DCT_XYZ' registers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RDC ,Receive Data agent Count: Number of receive hardware data agents (FIFO and associated logic) Sets the number of instances of the 'DCR_XYZ' registers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 12.--19. 1. " RRSZ ,Size of receive FIFO RAM, in 32-bit words. RX message FIFO and all RX data FIFOs map to that shared RAM." hexmask.long.byte 0x00 4.--11. 1. " TRSZ ,Size of transmit FIFO RAM, in 32-bit words. TX message FIFO and all TX data FIFOs map to that shared RAM." bitfld.long 0x00 0.--3. " PSZ ,Size of (both TX and RX) FIFO segment word pointers, in bits. Determines the maximum number of (variable-sized) segment words a data agent FIFO can contain. Sets the width of FIFO control and status fields: size,.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "SLIMBUS_CMP_SYSCONFIG,This register allows controlling various parameters of the interconnect interface" bitfld.long 0x00 8. " AUTOGATINGDISABLE ,Control of the internal clock autogating for safety / debug only. No impact on module functionality, only on dynamic power. - . - ." "0,1" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "No_action,Initiate_software_reset" group.long 0x24++0x3 line.long 0x00 "SLIMBUS_CMP_IRQSTATUS_RAW,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 19. " DCR_INFO_7 ,IRQ status for RX Data agent 7 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 18. " DCR_INFO_6 ,IRQ status for RX Data agent 6 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 17. " DCR_INFO_5 ,IRQ status for RX Data agent 5 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 16. " DCR_INFO_4 ,IRQ status for RX Data agent 4 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 15. " DCR_INFO_3 ,IRQ status for RX Data agent 3 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 14. " DCR_INFO_2 ,IRQ status for RX Data agent 2 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 13. " DCR_INFO_1 ,IRQ status for RX Data agent 1 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 12. " DCR_INFO_0 ,IRQ status for RX Data agent 0 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 11. " DCT_INFO_7 ,IRQ status for TX Data agent 7 - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 10. " DCT_INFO_6 ,IRQ status for TX Data agent 6 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 9. " DCT_INFO_5 ,IRQ status for TX Data agent 5 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 8. " DCT_INFO_4 ,IRQ status for TX Data agent 4 - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 7. " DCT_INFO_3 ,IRQ status for TX Data agent 3 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 6. " DCT_INFO_2 ,IRQ status for TX Data agent 2 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 5. " DCT_INFO_1 ,IRQ status for TX Data agent 1 - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 4. " DCT_INFO_0 ,IRQ status for TX Data agent 0 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 3. " SMR_INFO ,IRQ status for message receive - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 2. " SMT_INFO ,IRQ status for message transmit - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 1. " FR_INFO ,IRQ status for Framer device, when active - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 0. " FL_INFO ,IRQ status for Frame Layer - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x28++0x3 line.long 0x00 "SLIMBUS_CMP_IRQSTATUS,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Enabled status isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status get.." eventfld.long 0x00 19. " DCR_INFO_7 ,IRQ status for RX Data agent 7. If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 18. " DCR_INFO_6 ,IRQ status for RX Data agent 6. If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 17. " DCR_INFO_5 ,IRQ status for RX Data agent 5 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 16. " DCR_INFO_4 ,IRQ status for RX Data agent 4 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 15. " DCR_INFO_3 ,IRQ status for RX Data agent 3 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 14. " DCR_INFO_2 ,IRQ status for RX Data agent 2 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 13. " DCR_INFO_1 ,IRQ status for RX Data agent 1 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 12. " DCR_INFO_0 ,IRQ status for RX Data agent 0 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 11. " DCT_INFO_7 ,IRQ status for TX Data agent 7 - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 10. " DCT_INFO_6 ,IRQ status for TX Data agent 6 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 9. " DCT_INFO_5 ,IRQ status for TX Data agent 5 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 8. " DCT_INFO_4 ,IRQ status for TX Data agent 4 - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 7. " DCT_INFO_3 ,IRQ status for TX Data agent 3 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 6. " DCT_INFO_2 ,IRQ status for TX Data agent 2 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 5. " DCT_INFO_1 ,IRQ status for TX Data agent 1 - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 4. " DCT_INFO_0 ,IRQ status for TX Data agent 0 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 3. " SMR_INFO ,IRQ status for message receive - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " SMT_INFO ,IRQ status for message transmit - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 1. " FR_INFO ,IRQ status for Framer device, when active - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 0. " FL_INFO ,IRQ status for Frame Layer - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2C++0x3 line.long 0x00 "SLIMBUS_CMP_IRQENABLE_SET,Component (that is, main) interrupt request enable Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " DCR_INFO_7_EN ,IRQ enable for RX Data agent 7. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 18. " DCR_INFO_6_EN ,IRQ enable for RX Data agent 6. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 17. " DCR_INFO_5_EN ,IRQ enable for RX Data agent 5. If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 16. " DCR_INFO_4_EN ,IRQ enable for RX Data agent 4. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 15. " DCR_INFO_3_EN ,IRQ enable for RX Data agent 3. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " DCR_INFO_2_EN ,IRQ enable for RX Data agent 2. If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 13. " DCR_INFO_1_EN ,IRQ enable for RX Data agent 1. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 12. " DCR_INFO_0_EN ,IRQ enable for RX Data agent 0. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 11. " DCT_INFO_7_EN ,IRQ enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 10. " DCT_INFO_6_EN ,IRQ enable for TX Data agent 6 - . - . - . - ." "No_action,1" bitfld.long 0x00 9. " DCT_INFO_5_EN ,IRQ enable for TX Data agent 5 - . - . - . - ." "No_action,1" bitfld.long 0x00 8. " DCT_INFO_4_EN ,IRQ enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 7. " DCT_INFO_3_EN ,IRQ enable for TX Data agent 3 - . - . - . - ." "No_action,1" bitfld.long 0x00 6. " DCT_INFO_2_EN ,IRQ enable for TX Data agent 2 - . - . - . - ." "No_action,1" bitfld.long 0x00 5. " DCT_INFO_1_EN ,IRQ enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 4. " DCT_INFO_0_EN ,IRQ enable for TX Data agent 0 - . - . - . - ." "No_action,1" bitfld.long 0x00 3. " SMR_INFO_EN ,IRQ enable for message receive - . - . - . - ." "No_action,1" bitfld.long 0x00 2. " SMT_INFO_EN ,IRQ enable for message transmit - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 1. " FR_INFO_EN ,IRQ enable for Framer device, when active - . - . - . - ." "No_action,1" bitfld.long 0x00 0. " FL_INFO_EN ,IRQ enable for Frame Layer - . - . - . - ." "No_action,1" group.long 0x30++0x3 line.long 0x00 "SLIMBUS_CMP_IRQENABLE_CLR,Component (that is, main) interrupt request enable Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " DCR_INFO_7_EN ,IRQ enable for RX data agent 7. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 18. " DCR_INFO_6_EN ,IRQ enable for RX data agent 6. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 17. " DCR_INFO_5_EN ,IRQ enable for RX data agent 5. If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 16. " DCR_INFO_4_EN ,IRQ enable for RX data agent 4. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 15. " DCR_INFO_3_EN ,IRQ enable for RX data agent 3. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 14. " DCR_INFO_2_EN ,IRQ enable for RX data agent 2. If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 13. " DCR_INFO_1_EN ,IRQ enable for RX data agent 1. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 12. " DCR_INFO_0_EN ,IRQ enable for RX data agent 0. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 11. " DCT_INFO_7_EN ,IRQ enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 10. " DCT_INFO_6_EN ,IRQ enable for TX Data agent 6 - . - . - . - ." "No_action,1" eventfld.long 0x00 9. " DCT_INFO_5_EN ,IRQ enable for TX Data agent 5 - . - . - . - ." "No_action,1" eventfld.long 0x00 8. " DCT_INFO_4_EN ,IRQ enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 7. " DCT_INFO_3_EN ,IRQ enable for TX Data agent 3 - . - . - . - ." "No_action,1" eventfld.long 0x00 6. " DCT_INFO_2_EN ,IRQ enable for TX Data agent 2 - . - . - . - ." "No_action,1" eventfld.long 0x00 5. " DCT_INFO_1_EN ,IRQ enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 4. " DCT_INFO_0_EN ,IRQ enable for TX Data agent 0 - . - . - . - ." "No_action,1" eventfld.long 0x00 3. " SMR_INFO_EN ,IRQ enable for message receive - . - . - . - ." "No_action,1" eventfld.long 0x00 2. " SMT_INFO_EN ,IRQ enable for message transmit - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 1. " FR_INFO_EN ,IRQ enable for Framer device, when active - . - . - . - ." "No_action,1" eventfld.long 0x00 0. " FL_INFO_EN ,IRQ enable for Frame Layer - . - . - . - ." "No_action,1" group.long 0x34++0x3 line.long 0x00 "SLIMBUS_CMP_DMAENABLE_SET,Components DMA enable (1 bit per DMA-capable channel) Write 1 to set (enable DMA). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " DCR_DMA_7_EN ,DMA enable for RX Data agent 7 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 18. " DCR_DMA_6_EN ,DMA enable for RX Data agent 6 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 17. " DCR_DMA_5_EN ,DMA enable for RX Data agent 5 . If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 16. " DCR_DMA_4_EN ,DMA enable for RX Data agent 4 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 15. " DCR_DMA_3_EN ,DMA enable for RX Data agent 3 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " DCR_DMA_2_EN ,DMA enable for RX Data agent 2 . If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 13. " DCR_DMA_1_EN ,DMA enable for RX Data agent 1 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 12. " DCR_DMA_0_EN ,DMA enable for RX Data agent 0 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 11. " DCT_DMA_7_EN ,DMA enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 10. " DCT_DMA_6_EN ,DMA enable for TX Data agent 6 - . - . - . - ." "No_action,1" bitfld.long 0x00 9. " DCT_DMA_5_EN ,DMA enable for TX Data agent 5 - . - . - . - ." "No_action,1" bitfld.long 0x00 8. " DCT_DMA_4_EN ,DMA enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 7. " DCT_DMA_3_EN ,DMA enable for TX Data agent 3 - . - . - . - ." "No_action,1" bitfld.long 0x00 6. " DCT_DMA_2_EN ,DMA enable for TX Data agent 2 - . - . - . - ." "No_action,1" bitfld.long 0x00 5. " DCT_DMA_1_EN ,DMA enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 4. " DCT_DMA_0_EN ,DMA enable for TX Data agent 0 - . - . - . - ." "No_action,1" group.long 0x38++0x3 line.long 0x00 "SLIMBUS_CMP_DMAENABLE_CLR,Components DMA enable (1 bit per DMA-capable channel) Write 1 to clear (disable DMA). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " DCR_DMA_7_EN ,DMA enable for RX Data agent 7 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 18. " DCR_DMA_6_EN ,DMA enable for RX Data agent 6 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 17. " DCR_DMA_5_EN ,DMA enable for RX Data agent 5 . If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 16. " DCR_DMA_4_EN ,DMA enable for RX Data agent 4 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 15. " DCR_DMA_3_EN ,DMA enable for RX Data agent 3 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 14. " DCR_DMA_2_EN ,DMA enable for RX Data agent 2 . If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 13. " DCR_DMA_1_EN ,DMA enable for RX Data agent 1 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 12. " DCR_DMA_0_EN ,DMA enable for RX Data agent 0 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 11. " DCT_DMA_7_EN ,DMA enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 10. " DCT_DMA_6_EN ,DMA enable for TX Data agent 6 - . - . - . - ." "No_action,1" eventfld.long 0x00 9. " DCT_DMA_5_EN ,DMA enable for TX Data agent 5 - . - . - . - ." "No_action,1" eventfld.long 0x00 8. " DCT_DMA_4_EN ,DMA enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 7. " DCT_DMA_3_EN ,DMA enable for TX Data agent 3 - . - . - . - ." "No_action,1" eventfld.long 0x00 6. " DCT_DMA_2_EN ,DMA enable for TX Data agent 2 - . - . - . - ." "No_action,1" eventfld.long 0x00 5. " DCT_DMA_1_EN ,DMA enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 4. " DCT_DMA_0_EN ,DMA enable for TX Data agent 0 - . - . - . - ." "No_action,1" group.long 0x40++0x3 line.long 0x00 "SLIMBUS_CMP_IV,Component IV field, used as lower 8 bits of the devices' Enumeration Address (EA[47:0]). Identical for all devices of the component." hexmask.long.byte 0x00 0.--7. 1. " IV ,Device component's Instance Value (IV[7:0])" group.long 0x44++0x3 line.long 0x00 "SLIMBUS_CMP_MI_PC,Component MI and PC fields, used as upper 32 bits of the devices' Enumeration Address (EA[47:0]). Identical for all devices of the component." hexmask.long.word 0x00 16.--31. 1. " PC ,Device component's Product Code (PC[15:0])" hexmask.long.word 0x00 0.--15. 1. " MI ,Device component's Manufacturer Index (MI[15:0])" group.long 0x50++0x3 line.long 0x00 "SLIMBUS_SMT_INFO,IRQ status for Shared Message Transmit channel. Write 1 to a bit to clear it." eventfld.long 0x00 7. " ABORT ,TX message was aborted before completion because of message sync loss. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 5. " UDEF ,TX message was UDEF'ed: undefined response, protocol error. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 4. " NORE ,TX message was NORE'ed: no or all-zero message response - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 3. " NACK ,TX message was NACK'ed: at least one of the recipient devices requested message retransmission. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " PACK ,TX message was PACK'ed: all recipient devices accepted the message. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX message FIFO: Software tried to write more bytes than available in the FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " MC_TX_COL ,Transmit collision in Message Channel (MC) during message transmission. Interface device class-specific information element (IE) - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x54++0x3 line.long 0x00 "SLIMBUS_SMT_MESSAGE,Shared Message Transmit FIFO input" hexmask.long 0x00 0.--31. 1. " TX_MESSAGE ,TX message byte(s), depending on packing mode. Reads return 0. Enter the whole message except last byte (Message Integrity MI and Response MR), and with a don't care placeholder for Primary Integrity (PI)." group.long 0x58++0x3 line.long 0x00 "SLIMBUS_SMT_CONTROL,Control of Shared Message channel Transmission." bitfld.long 0x00 0. " MESSAGE_ENABLE ,Enable the transmission of the message(s) previously written into the TX Message FIFO, with unlimited arbitration auto-retries. Self-cleared after either a message not get PACK'ed or the FIFO is empty. - . - . - . - ." "No_effect,1" group.long 0x5C++0x3 line.long 0x00 "SLIMBUS_SMT_FIFO_SETUP,Shared Message Transmit channel configuration. To be kept static during operation. Note that message segment word size is 2 slots = 1 byte (= message size granularity) and that message FIFO base address is always 0x0." bitfld.long 0x00 7. " PACKING ,Packing enable control for TX message FIFO - . - ." "0,1" bitfld.long 0x00 5.--6. " SIZE_HI ,(Upper bits of the) capacity of shared TX message FIFO, in bytes, minus one. To be set for largest supported (transmitted) message(s). - . - . - . - ." "0,32_bytes_(recommended),2,3" bitfld.long 0x00 1.--4. " SIZE_LO ,(Lower bits of the) capacity of shared TX message FIFO, in bytes, minus one. Read-only, for reference only." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x60++0x3 line.long 0x00 "SLIMBUS_SMR_INFO,IRQ status for Shared Message Receive channel. Write 1 to a bit to clear it." eventfld.long 0x00 4. " OVERFLOW ,Overflow in RX message FIFO: received message is larger than the FIFO. - . - . - . - ." "no_action,clear_event" eventfld.long 0x00 3. " RECEIVED_RECONFIGURE ,RECONFIGURE_NOW message received, available in RX message FIFO - . - . - . - ." "no_action,clear_event" eventfld.long 0x00 2. " RECEIVED_MESSAGE ,Message available in the RX message FIFO. Clear bit to clear the FIFO and allow the reception of further messages (incoming messages will be NACK'ed until then). - . - . - . - ." "no_action,event_pending" textline " " eventfld.long 0x00 1. " UNDERFLOW ,Underflow in RX message FIFO: Software tried to read out more bytes than available. - . - . - . - ." "no_action,clear_event" eventfld.long 0x00 0. " MC_TX_COL ,Transmit collision in Message Channel (MC) during RX message during message reception. Interface device class-specific information element (IE) - . - . - . - ." "no_action,clear_event" rgroup.long 0x64++0x3 line.long 0x00 "SLIMBUS_SMR_MESSAGE,Shared Message Receive channel FIFO output." hexmask.long 0x00 0.--31. 1. " RX_MESSAGE ,RX message byte(s), depending on packing mode. Writes have no effect. Readout value from an empty FIFO is undefined, that is, there is no defined 'reset value'. Message is guaranteed to have destination address matching a local devi.." group.long 0x68++0x3 line.long 0x00 "SLIMBUS_SMR_CONTROL,Control of Shared Message channel Reception." bitfld.long 0x00 0. " MESSAGE_DISABLE ,Disables the reception of incoming messages (that is, broadcast or locally addressed) into the RX Message FIFO. Same effect for the same value than SMR_INFO[2] RECEIVED_MESSAGE, but this bit can be set to 1. - . - ." "0,1" group.long 0x6C++0x3 line.long 0x00 "SLIMBUS_SMR_FIFO_SETUP,Shared Message Receive channel setup. To be kept static during operation. Note that message segment word size is 2 slots = 1 byte (= message size granularity) and that message FIFO base address is always 0x0." bitfld.long 0x00 7. " PACKING ,Packing enable control for RX message FIFO - . - ." "0,1" bitfld.long 0x00 5.--6. " SIZE_HI ,(Upper bits of the) capacity of shared RX message FIFO, in bytes, minus one. To be set for largest supported (received) message. - . - . - . - ." "0,32_bytes_(recommended),2,3" bitfld.long 0x00 1.--4. " SIZE_LO ,(Lower bits of the) capacity of shared RX message FIFO, in bytes, minus one. Read-only, for reference only." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " FIFO_CLEAR ,Returns message FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x70++0x3 line.long 0x00 "SLIMBUS_FL_INFO,Frame Layer IRQ status. Write 1 to a bit to clear it. Note: FS loss implies SFS loss, and SFS loss implies MS loss, but only the 'strongest' loss event is logged for a given event." eventfld.long 0x00 6. " RECONFIGURED ,Reconfiguration boundary crossed - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 5. " SAW_BUS_RESET ,Bus reset sequence detected on the bus: no activity on DATA line (all-zero) for 2 to 4 frames. Clock receiver FSM has returned to Reset state. Should trigger a local component reset (software sequence). - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 3. " FOUND_MS ,Message sync was acquired: operational state reached - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 2. " LOST_MS ,Message Synchronization was lost Interface device class-specific information element (IE) Note: Not asserted in case of FS or SFS loss. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " LOST_SFS ,Super Frame Synchronization was lost Interface device class-specific information element (IE) Note: Not asserted in case of FS loss. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 0. " LOST_FS ,Frame Synchronization was lost Interface device class-specific information element (IE) - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x74++0x3 line.long 0x00 "SLIMBUS_FL_CONTROL,Frame Layer control. (Self-cleared bits)" bitfld.long 0x00 8. " VALIDATE_DCMAP ,Validates the mapping of data channels on devices: to be used after modifying the DC*_MAP* fields (DI and PN). - . - ." "No_action,1" bitfld.long 0x00 7. " CLEAR_RECONFIGURATION ,Clear all updates cumulated since the last reconfiguration, return reconfiguration fields to currently active value. Self-cleared immediately. - . - ." "No_action,Clear_reconfiguration" bitfld.long 0x00 6. " BUS_SHUTDOWN ,Sets both the clock source or the clock receiver FSMs back to 'Undefined' state at the next reconfiguration boundary. Executed (and bit self-cleared) on next reconfiguration (forced or not); also cleared by a 'clear_reconfiguration.." "0,1" textline " " bitfld.long 0x00 5. " KILL_FS ,Force immediate Frame Synchronization loss (implying as well message and superframe sync) When in 'Operational', 'SeekingMessageSync' or 'SeekingSuperFrameSync' states, component shall go to 'SeekingFrameSync' and start reaquiring f.." "No_action,1" bitfld.long 0x00 4. " KILL_SFS ,Force SuperFrame Synchronization loss at next reconfiguration boundary (implying as well message sync loss). When in 'Operational' or 'SeekingMessageSync' states, component shall go to 'SeekingSuperFrameSync' and start.." "No_action,1" bitfld.long 0x00 3. " KILL_MS ,Force an immediate Message Synchronization loss. When in 'Operational' state, component shall go to 'SeekingMessageSync' and start reaquiring message sync. No effect otherwise. For debug use. - . - . - ." "No_action,1" textline " " bitfld.long 0x00 2. " FORCE_RECONFIGURE ,Force a reconfiguration boundary at next superframe boundary, rather than wait for a RECONFIGURE_NOW() message. - . - . - . - ." "No_request_pending,1" bitfld.long 0x00 1. " COMPONENT_RESET ,Component reset request control: Transitions clock receiver FSM to state 'Reset' (from any other state). Immediate action. Set upon reception of the RESET_DEVICE() message by the interface device, which requires a component-lev.." "0,1" bitfld.long 0x00 0. " BOOT ,Boot the component when not in active framer mode (don't care when in active framer mode). Transitions clock receiver FSM from state 'Undefined' to 'Reset'. - . - ." "No_action,1" group.long 0x78++0x3 line.long 0x00 "SLIMBUS_FL_SM,Subframe mode (SM: defines control vs. data space partition) control and status Software must write in values : a) to use when booting in active framer mode. b) extracted from NEXT_SUBFRAME_MODE(SM), to use at following reconfiguration bo.." bitfld.long 0x00 0.--4. " SM ,Subframe Mode, which sets Control Space Width (CSW) and Subframe Length (SFL), both expressed in slots. Note that we always have CSW &lt;= SFL since the control is included in the subframe. - . - . - . - . - . - . - . - . - . - .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7C++0x3 line.long 0x00 "SLIMBUS_FL_CG,Clock Gear (CG) control and status Software must write in values : a) to use when booting in active framer mode. b) extracted from NEXT_CLOCK_GEAR(CG), to use at following reconfiguration boundary. Hardware-updated upon superframe sync ac.." bitfld.long 0x00 0.--3. " CG ,Clock Gear (CG) to be used after the next reconfiguration boundary. Root / SLIMbus frequency ratio is defined as 2 - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x3 line.long 0x00 "SLIMBUS_FL_RF,Root frequency (RF = SLIMbus clock frequency when in gear 10) control and status Software must write in values : a) to use when booting in active framer mode. b) extracted from NEXT_ROOT_FREQUENCY(RF), to use at following reconfiguration .." bitfld.long 0x00 0.--3. " RF ,Root frequency - . - . - . - . - . - . - . - . - . - ." "0,24.576_MHz,22.5792_MHz,15.36_MHz,16.8_MHz,19.2_MHz,24_MHz,25_MHz,26_MHz,27_MHz,10,11,12,13,14,15" group.long 0x90++0x3 line.long 0x00 "SLIMBUS_FR_INFO,Framer device status (when active). Write 1 to a bit to clear it." eventfld.long 0x00 5. " CLOCK_RESTART ,Clock restart request event detected (that is, asynchronous DATA line transition during clock pause) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 4. " FRAMER_UNACTIVATED ,Framer has left clock source operational state. Set on ACTIVE_FRAMER information element deassertion. (framer device class-specific IE) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 3. " FRAMER_ACTIVATED ,Framer has reached clock source operational state. Set on ACTIVE_FRAMER information element assertion. (framer device class-specific IE) - . - ." "no_event_pending,event_pending" textline " " eventfld.long 0x00 2. " GC_TX_COL ,Collision during guide byte transmit (Guide Channel) Framer device class-specific information element (IE) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 1. " FI_TX_COL ,Collision during Framing Information transmit (framing channel) Framer device class-specific information element (IE) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 0. " FS_TX_COL ,Collision during Frame Sync symbol transmit (framing channel) Framer device class-specific information element (IE) - . - ." "no_event_pending,event_pending" group.long 0x94++0x3 line.long 0x00 "SLIMBUS_FR_CLOCK_SOURCE,Root clock configuration for active framer mode, used at next reconfiguration boundary. Unused when not active framer." bitfld.long 0x00 4.--6. " CLKSEL ,SLIMbus clock selection - . - . - ." "FCLK1,FCLK2,FCLK3,3,4,5,6,7" bitfld.long 0x00 0.--3. " CLKDIV ,Root divider ratio, applied on clock input to obtain root clock, to be used at next reconfiguration boundary. Input/ root frequency ratio is defined as 2 With CG the SLIMbus clock gear, Input / SLIMbus frequency ra.." "0,1,2,3,4,5,Ratio_is_2,Ratio_is_4,Ratio_is_8,Ratio_is_16,Ratio_is_32,11,12,13,14,15" group.long 0x98++0x3 line.long 0x00 "SLIMBUS_FR_CONTROL,Framer Device control. Unused when not active framer. (Self-cleared bits)" bitfld.long 0x00 1. " BUS_RESET ,Bus reset request control, when framer is already active. Set upon reception of the NEXT_RESET_BUS() message. Transitions clock source FSM to state 'StartingClock' (from 'Operational'). - . - . - . - ." "0,1" bitfld.long 0x00 0. " BOOT ,Initiate an active framer (clock source) boot sequence for the component, that is, when component is default active framer. Transitions clock source FSM from state 'Undefined' to 'CheckingDataLine'. Transitions.." "0,1" group.long 0x9C++0x3 line.long 0x00 "SLIMBUS_FR_FRAMER_HANDOVER,Framer handover control (outgoing if currently active, incoming if currently inactive)" bitfld.long 0x00 12. " HANDOVER_ENABLE ,Enable framer handover, upon NEXT_ACTIVE_FRAMER(NCi,NCo) reception. Self-cleared upon handover, that is, at next reconfiguration boundary. - . - ." "No_framer_handover,1" hexmask.long.word 0x00 0.--11. 1. " NCO_NCI ,NCo[11:0] / NCi[11:0] for outgoing / incoming framer respectively, as extracted from NEXT_ACTIVE_FRAMER(NCi,NCo) Used on framer handover at next reconfiguration boundary." group.long 0xA0++0x3 line.long 0x00 "SLIMBUS_FR_CLOCK_PAUSE,Clock and pause restart control. Applied at following reconfiguration boundary, that is, where the clock is paused. Note that programming is indentical for an active framer (clock source) and a clock receiver." bitfld.long 0x00 3.--8. " RT_HI ,MSBs of 8-bit SLIMbus parameter. Constant. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--2. " RT ,Restart Time (RT) for recovery after clock pause, as extracted from NEXT_PAUSE_CLOCK(RT) LSBs of 8-bit SLIMbus parameter. Unused when not active framer. - . - . - ." "0,1,2,3" bitfld.long 0x00 0. " CLOCK_PAUSE ,Control clock pause / restart. Self-cleared upon restart. - . - ." "0,1" tree.end tree.open "SLIMBUS1_DSP" tree "SLIMBUS1_Cortex_A9" base ad:0x4012C000 tree "Channel_0" width 29. group.long 0x314++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_0,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x318++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_0,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x31C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_0,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x304++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_0,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x308++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_0,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x30C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_0,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x300++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_0,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x310++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_0,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x214++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_0,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x218++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_0,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x21C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_0,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x204++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_0,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x208++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_0,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x20C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_0,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x200++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_0,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x210++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_0,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x108++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_0,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x104++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_0,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x100++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_0,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_1" width 29. group.long 0x334++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_1,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x338++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_1,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x33C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_1,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x324++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_1,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x328++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_1,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x32C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_1,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x320++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_1,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x330++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_1,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x234++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_1,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x238++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_1,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x23C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_1,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x224++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_1,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x228++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_1,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x22C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_1,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x220++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_1,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x230++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_1,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x118++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_1,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x114++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_1,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x110++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_1,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_2" width 29. group.long 0x354++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_2,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x358++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_2,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x35C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_2,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x344++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_2,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x348++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_2,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x34C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_2,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x340++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_2,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x350++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_2,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x254++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_2,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x258++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_2,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x25C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_2,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x244++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_2,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x248++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_2,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x24C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_2,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x240++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_2,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x250++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_2,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x128++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_2,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x124++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_2,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x120++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_2,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_3" width 29. group.long 0x374++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_3,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x378++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_3,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x37C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_3,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x364++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_3,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x368++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_3,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x36C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_3,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x360++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_3,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x370++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_3,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x274++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_3,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x278++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_3,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x27C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_3,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x264++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_3,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x268++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_3,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x26C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_3,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x260++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_3,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x270++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_3,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x138++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_3,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x134++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_3,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x130++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_3,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_4" width 29. group.long 0x394++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_4,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x398++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_4,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x39C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_4,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x384++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_4,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x388++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_4,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x38C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_4,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x380++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_4,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x390++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_4,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x294++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_4,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x298++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_4,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x29C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_4,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x284++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_4,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x288++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_4,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x28C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_4,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x280++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_4,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x290++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_4,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x148++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_4,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x144++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_4,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x140++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_4,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_5" width 29. group.long 0x3B4++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_5,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3B8++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_5,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x3BC++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_5,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x3A4++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_5,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x3A8++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_5,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x3AC++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_5,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x3A0++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_5,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x3B0++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_5,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x2B4++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_5,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2B8++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_5,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x2BC++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_5,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x2A4++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_5,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x2A8++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_5,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x2AC++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_5,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x2A0++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_5,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2B0++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_5,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x158++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_5,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x154++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_5,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x150++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_5,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_6" width 29. group.long 0x3D4++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_6,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3D8++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_6,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x3DC++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_6,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x3C4++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_6,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x3C8++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_6,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x3CC++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_6,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x3C0++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_6,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x3D0++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_6,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x2D4++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_6,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2D8++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_6,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x2DC++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_6,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x2C4++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_6,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x2C8++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_6,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x2CC++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_6,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x2C0++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_6,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2D0++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_6,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x168++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_6,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x164++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_6,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x160++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_6,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_7" width 29. group.long 0x3F4++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_7,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3F8++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_7,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x3FC++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_7,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x3E4++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_7,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x3E8++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_7,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x3EC++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_7,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x3E0++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_7,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x3F0++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_7,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x2F4++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_7,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F8++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_7,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x2FC++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_7,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x2E4++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_7,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x2E8++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_7,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x2EC++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_7,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x2E0++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_7,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2F0++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_7,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." tree.end textline "" width 28. rgroup.long 0x0++0x3 line.long 0x00 "SLIMBUS_CMP_REVISION,IP Revision Identifier Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,Revision Number" rgroup.long 0x4++0x3 line.long 0x00 "SLIMBUS_CMP_HWINFO,Those read-only, hardcoded fields display the values of the eponymous hardware configuration depending on module instantiation - SLIMBUS1 or SLIMBUS2." bitfld.long 0x00 28.--31. " DEV ,Device count: number of devices supported by the component, most notably through the automatically reception of the messages addressed to them. Sets the number of instances of the 'DEV_XYZ' registers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TDC ,Transmit Data agent Count: Number of transmit hardware data agents (FIFO and associated logic) Sets the number of instances of the 'DCT_XYZ' registers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RDC ,Receive Data agent Count: Number of receive hardware data agents (FIFO and associated logic) Sets the number of instances of the 'DCR_XYZ' registers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 12.--19. 1. " RRSZ ,Size of receive FIFO RAM, in 32-bit words. RX message FIFO and all RX data FIFOs map to that shared RAM." hexmask.long.byte 0x00 4.--11. 1. " TRSZ ,Size of transmit FIFO RAM, in 32-bit words. TX message FIFO and all TX data FIFOs map to that shared RAM." bitfld.long 0x00 0.--3. " PSZ ,Size of (both TX and RX) FIFO segment word pointers, in bits. Determines the maximum number of (variable-sized) segment words a data agent FIFO can contain. Sets the width of FIFO control and status fields: size,.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "SLIMBUS_CMP_SYSCONFIG,This register allows controlling various parameters of the interconnect interface" bitfld.long 0x00 8. " AUTOGATINGDISABLE ,Control of the internal clock autogating for safety / debug only. No impact on module functionality, only on dynamic power. - . - ." "0,1" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "No_action,Initiate_software_reset" group.long 0x24++0x3 line.long 0x00 "SLIMBUS_CMP_IRQSTATUS_RAW,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 19. " DCR_INFO_7 ,IRQ status for RX Data agent 7 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 18. " DCR_INFO_6 ,IRQ status for RX Data agent 6 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 17. " DCR_INFO_5 ,IRQ status for RX Data agent 5 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 16. " DCR_INFO_4 ,IRQ status for RX Data agent 4 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 15. " DCR_INFO_3 ,IRQ status for RX Data agent 3 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 14. " DCR_INFO_2 ,IRQ status for RX Data agent 2 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 13. " DCR_INFO_1 ,IRQ status for RX Data agent 1 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 12. " DCR_INFO_0 ,IRQ status for RX Data agent 0 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 11. " DCT_INFO_7 ,IRQ status for TX Data agent 7 - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 10. " DCT_INFO_6 ,IRQ status for TX Data agent 6 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 9. " DCT_INFO_5 ,IRQ status for TX Data agent 5 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 8. " DCT_INFO_4 ,IRQ status for TX Data agent 4 - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 7. " DCT_INFO_3 ,IRQ status for TX Data agent 3 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 6. " DCT_INFO_2 ,IRQ status for TX Data agent 2 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 5. " DCT_INFO_1 ,IRQ status for TX Data agent 1 - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 4. " DCT_INFO_0 ,IRQ status for TX Data agent 0 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 3. " SMR_INFO ,IRQ status for message receive - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 2. " SMT_INFO ,IRQ status for message transmit - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 1. " FR_INFO ,IRQ status for Framer device, when active - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 0. " FL_INFO ,IRQ status for Frame Layer - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x28++0x3 line.long 0x00 "SLIMBUS_CMP_IRQSTATUS,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Enabled status isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status get.." eventfld.long 0x00 19. " DCR_INFO_7 ,IRQ status for RX Data agent 7. If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 18. " DCR_INFO_6 ,IRQ status for RX Data agent 6. If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 17. " DCR_INFO_5 ,IRQ status for RX Data agent 5 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 16. " DCR_INFO_4 ,IRQ status for RX Data agent 4 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 15. " DCR_INFO_3 ,IRQ status for RX Data agent 3 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 14. " DCR_INFO_2 ,IRQ status for RX Data agent 2 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 13. " DCR_INFO_1 ,IRQ status for RX Data agent 1 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 12. " DCR_INFO_0 ,IRQ status for RX Data agent 0 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 11. " DCT_INFO_7 ,IRQ status for TX Data agent 7 - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 10. " DCT_INFO_6 ,IRQ status for TX Data agent 6 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 9. " DCT_INFO_5 ,IRQ status for TX Data agent 5 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 8. " DCT_INFO_4 ,IRQ status for TX Data agent 4 - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 7. " DCT_INFO_3 ,IRQ status for TX Data agent 3 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 6. " DCT_INFO_2 ,IRQ status for TX Data agent 2 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 5. " DCT_INFO_1 ,IRQ status for TX Data agent 1 - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 4. " DCT_INFO_0 ,IRQ status for TX Data agent 0 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 3. " SMR_INFO ,IRQ status for message receive - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " SMT_INFO ,IRQ status for message transmit - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 1. " FR_INFO ,IRQ status for Framer device, when active - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 0. " FL_INFO ,IRQ status for Frame Layer - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2C++0x3 line.long 0x00 "SLIMBUS_CMP_IRQENABLE_SET,Component (that is, main) interrupt request enable Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " DCR_INFO_7_EN ,IRQ enable for RX Data agent 7. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 18. " DCR_INFO_6_EN ,IRQ enable for RX Data agent 6. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 17. " DCR_INFO_5_EN ,IRQ enable for RX Data agent 5. If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 16. " DCR_INFO_4_EN ,IRQ enable for RX Data agent 4. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 15. " DCR_INFO_3_EN ,IRQ enable for RX Data agent 3. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " DCR_INFO_2_EN ,IRQ enable for RX Data agent 2. If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 13. " DCR_INFO_1_EN ,IRQ enable for RX Data agent 1. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 12. " DCR_INFO_0_EN ,IRQ enable for RX Data agent 0. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 11. " DCT_INFO_7_EN ,IRQ enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 10. " DCT_INFO_6_EN ,IRQ enable for TX Data agent 6 - . - . - . - ." "No_action,1" bitfld.long 0x00 9. " DCT_INFO_5_EN ,IRQ enable for TX Data agent 5 - . - . - . - ." "No_action,1" bitfld.long 0x00 8. " DCT_INFO_4_EN ,IRQ enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 7. " DCT_INFO_3_EN ,IRQ enable for TX Data agent 3 - . - . - . - ." "No_action,1" bitfld.long 0x00 6. " DCT_INFO_2_EN ,IRQ enable for TX Data agent 2 - . - . - . - ." "No_action,1" bitfld.long 0x00 5. " DCT_INFO_1_EN ,IRQ enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 4. " DCT_INFO_0_EN ,IRQ enable for TX Data agent 0 - . - . - . - ." "No_action,1" bitfld.long 0x00 3. " SMR_INFO_EN ,IRQ enable for message receive - . - . - . - ." "No_action,1" bitfld.long 0x00 2. " SMT_INFO_EN ,IRQ enable for message transmit - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 1. " FR_INFO_EN ,IRQ enable for Framer device, when active - . - . - . - ." "No_action,1" bitfld.long 0x00 0. " FL_INFO_EN ,IRQ enable for Frame Layer - . - . - . - ." "No_action,1" group.long 0x30++0x3 line.long 0x00 "SLIMBUS_CMP_IRQENABLE_CLR,Component (that is, main) interrupt request enable Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " DCR_INFO_7_EN ,IRQ enable for RX data agent 7. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 18. " DCR_INFO_6_EN ,IRQ enable for RX data agent 6. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 17. " DCR_INFO_5_EN ,IRQ enable for RX data agent 5. If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 16. " DCR_INFO_4_EN ,IRQ enable for RX data agent 4. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 15. " DCR_INFO_3_EN ,IRQ enable for RX data agent 3. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 14. " DCR_INFO_2_EN ,IRQ enable for RX data agent 2. If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 13. " DCR_INFO_1_EN ,IRQ enable for RX data agent 1. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 12. " DCR_INFO_0_EN ,IRQ enable for RX data agent 0. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 11. " DCT_INFO_7_EN ,IRQ enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 10. " DCT_INFO_6_EN ,IRQ enable for TX Data agent 6 - . - . - . - ." "No_action,1" eventfld.long 0x00 9. " DCT_INFO_5_EN ,IRQ enable for TX Data agent 5 - . - . - . - ." "No_action,1" eventfld.long 0x00 8. " DCT_INFO_4_EN ,IRQ enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 7. " DCT_INFO_3_EN ,IRQ enable for TX Data agent 3 - . - . - . - ." "No_action,1" eventfld.long 0x00 6. " DCT_INFO_2_EN ,IRQ enable for TX Data agent 2 - . - . - . - ." "No_action,1" eventfld.long 0x00 5. " DCT_INFO_1_EN ,IRQ enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 4. " DCT_INFO_0_EN ,IRQ enable for TX Data agent 0 - . - . - . - ." "No_action,1" eventfld.long 0x00 3. " SMR_INFO_EN ,IRQ enable for message receive - . - . - . - ." "No_action,1" eventfld.long 0x00 2. " SMT_INFO_EN ,IRQ enable for message transmit - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 1. " FR_INFO_EN ,IRQ enable for Framer device, when active - . - . - . - ." "No_action,1" eventfld.long 0x00 0. " FL_INFO_EN ,IRQ enable for Frame Layer - . - . - . - ." "No_action,1" group.long 0x34++0x3 line.long 0x00 "SLIMBUS_CMP_DMAENABLE_SET,Components DMA enable (1 bit per DMA-capable channel) Write 1 to set (enable DMA). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " DCR_DMA_7_EN ,DMA enable for RX Data agent 7 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 18. " DCR_DMA_6_EN ,DMA enable for RX Data agent 6 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 17. " DCR_DMA_5_EN ,DMA enable for RX Data agent 5 . If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 16. " DCR_DMA_4_EN ,DMA enable for RX Data agent 4 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 15. " DCR_DMA_3_EN ,DMA enable for RX Data agent 3 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " DCR_DMA_2_EN ,DMA enable for RX Data agent 2 . If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 13. " DCR_DMA_1_EN ,DMA enable for RX Data agent 1 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 12. " DCR_DMA_0_EN ,DMA enable for RX Data agent 0 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 11. " DCT_DMA_7_EN ,DMA enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 10. " DCT_DMA_6_EN ,DMA enable for TX Data agent 6 - . - . - . - ." "No_action,1" bitfld.long 0x00 9. " DCT_DMA_5_EN ,DMA enable for TX Data agent 5 - . - . - . - ." "No_action,1" bitfld.long 0x00 8. " DCT_DMA_4_EN ,DMA enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 7. " DCT_DMA_3_EN ,DMA enable for TX Data agent 3 - . - . - . - ." "No_action,1" bitfld.long 0x00 6. " DCT_DMA_2_EN ,DMA enable for TX Data agent 2 - . - . - . - ." "No_action,1" bitfld.long 0x00 5. " DCT_DMA_1_EN ,DMA enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 4. " DCT_DMA_0_EN ,DMA enable for TX Data agent 0 - . - . - . - ." "No_action,1" group.long 0x38++0x3 line.long 0x00 "SLIMBUS_CMP_DMAENABLE_CLR,Components DMA enable (1 bit per DMA-capable channel) Write 1 to clear (disable DMA). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " DCR_DMA_7_EN ,DMA enable for RX Data agent 7 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 18. " DCR_DMA_6_EN ,DMA enable for RX Data agent 6 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 17. " DCR_DMA_5_EN ,DMA enable for RX Data agent 5 . If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 16. " DCR_DMA_4_EN ,DMA enable for RX Data agent 4 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 15. " DCR_DMA_3_EN ,DMA enable for RX Data agent 3 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 14. " DCR_DMA_2_EN ,DMA enable for RX Data agent 2 . If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 13. " DCR_DMA_1_EN ,DMA enable for RX Data agent 1 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 12. " DCR_DMA_0_EN ,DMA enable for RX Data agent 0 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 11. " DCT_DMA_7_EN ,DMA enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 10. " DCT_DMA_6_EN ,DMA enable for TX Data agent 6 - . - . - . - ." "No_action,1" eventfld.long 0x00 9. " DCT_DMA_5_EN ,DMA enable for TX Data agent 5 - . - . - . - ." "No_action,1" eventfld.long 0x00 8. " DCT_DMA_4_EN ,DMA enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 7. " DCT_DMA_3_EN ,DMA enable for TX Data agent 3 - . - . - . - ." "No_action,1" eventfld.long 0x00 6. " DCT_DMA_2_EN ,DMA enable for TX Data agent 2 - . - . - . - ." "No_action,1" eventfld.long 0x00 5. " DCT_DMA_1_EN ,DMA enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 4. " DCT_DMA_0_EN ,DMA enable for TX Data agent 0 - . - . - . - ." "No_action,1" group.long 0x40++0x3 line.long 0x00 "SLIMBUS_CMP_IV,Component IV field, used as lower 8 bits of the devices' Enumeration Address (EA[47:0]). Identical for all devices of the component." hexmask.long.byte 0x00 0.--7. 1. " IV ,Device component's Instance Value (IV[7:0])" group.long 0x44++0x3 line.long 0x00 "SLIMBUS_CMP_MI_PC,Component MI and PC fields, used as upper 32 bits of the devices' Enumeration Address (EA[47:0]). Identical for all devices of the component." hexmask.long.word 0x00 16.--31. 1. " PC ,Device component's Product Code (PC[15:0])" hexmask.long.word 0x00 0.--15. 1. " MI ,Device component's Manufacturer Index (MI[15:0])" group.long 0x50++0x3 line.long 0x00 "SLIMBUS_SMT_INFO,IRQ status for Shared Message Transmit channel. Write 1 to a bit to clear it." eventfld.long 0x00 7. " ABORT ,TX message was aborted before completion because of message sync loss. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 5. " UDEF ,TX message was UDEF'ed: undefined response, protocol error. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 4. " NORE ,TX message was NORE'ed: no or all-zero message response - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 3. " NACK ,TX message was NACK'ed: at least one of the recipient devices requested message retransmission. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " PACK ,TX message was PACK'ed: all recipient devices accepted the message. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX message FIFO: Software tried to write more bytes than available in the FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " MC_TX_COL ,Transmit collision in Message Channel (MC) during message transmission. Interface device class-specific information element (IE) - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x54++0x3 line.long 0x00 "SLIMBUS_SMT_MESSAGE,Shared Message Transmit FIFO input" hexmask.long 0x00 0.--31. 1. " TX_MESSAGE ,TX message byte(s), depending on packing mode. Reads return 0. Enter the whole message except last byte (Message Integrity MI and Response MR), and with a don't care placeholder for Primary Integrity (PI)." group.long 0x58++0x3 line.long 0x00 "SLIMBUS_SMT_CONTROL,Control of Shared Message channel Transmission." bitfld.long 0x00 0. " MESSAGE_ENABLE ,Enable the transmission of the message(s) previously written into the TX Message FIFO, with unlimited arbitration auto-retries. Self-cleared after either a message not get PACK'ed or the FIFO is empty. - . - . - . - ." "No_effect,1" group.long 0x5C++0x3 line.long 0x00 "SLIMBUS_SMT_FIFO_SETUP,Shared Message Transmit channel configuration. To be kept static during operation. Note that message segment word size is 2 slots = 1 byte (= message size granularity) and that message FIFO base address is always 0x0." bitfld.long 0x00 7. " PACKING ,Packing enable control for TX message FIFO - . - ." "0,1" bitfld.long 0x00 5.--6. " SIZE_HI ,(Upper bits of the) capacity of shared TX message FIFO, in bytes, minus one. To be set for largest supported (transmitted) message(s). - . - . - . - ." "0,32_bytes_(recommended),2,3" bitfld.long 0x00 1.--4. " SIZE_LO ,(Lower bits of the) capacity of shared TX message FIFO, in bytes, minus one. Read-only, for reference only." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x60++0x3 line.long 0x00 "SLIMBUS_SMR_INFO,IRQ status for Shared Message Receive channel. Write 1 to a bit to clear it." eventfld.long 0x00 4. " OVERFLOW ,Overflow in RX message FIFO: received message is larger than the FIFO. - . - . - . - ." "no_action,clear_event" eventfld.long 0x00 3. " RECEIVED_RECONFIGURE ,RECONFIGURE_NOW message received, available in RX message FIFO - . - . - . - ." "no_action,clear_event" eventfld.long 0x00 2. " RECEIVED_MESSAGE ,Message available in the RX message FIFO. Clear bit to clear the FIFO and allow the reception of further messages (incoming messages will be NACK'ed until then). - . - . - . - ." "no_action,event_pending" textline " " eventfld.long 0x00 1. " UNDERFLOW ,Underflow in RX message FIFO: Software tried to read out more bytes than available. - . - . - . - ." "no_action,clear_event" eventfld.long 0x00 0. " MC_TX_COL ,Transmit collision in Message Channel (MC) during RX message during message reception. Interface device class-specific information element (IE) - . - . - . - ." "no_action,clear_event" rgroup.long 0x64++0x3 line.long 0x00 "SLIMBUS_SMR_MESSAGE,Shared Message Receive channel FIFO output." hexmask.long 0x00 0.--31. 1. " RX_MESSAGE ,RX message byte(s), depending on packing mode. Writes have no effect. Readout value from an empty FIFO is undefined, that is, there is no defined 'reset value'. Message is guaranteed to have destination address matching a local devi.." group.long 0x68++0x3 line.long 0x00 "SLIMBUS_SMR_CONTROL,Control of Shared Message channel Reception." bitfld.long 0x00 0. " MESSAGE_DISABLE ,Disables the reception of incoming messages (that is, broadcast or locally addressed) into the RX Message FIFO. Same effect for the same value than SMR_INFO[2] RECEIVED_MESSAGE, but this bit can be set to 1. - . - ." "0,1" group.long 0x6C++0x3 line.long 0x00 "SLIMBUS_SMR_FIFO_SETUP,Shared Message Receive channel setup. To be kept static during operation. Note that message segment word size is 2 slots = 1 byte (= message size granularity) and that message FIFO base address is always 0x0." bitfld.long 0x00 7. " PACKING ,Packing enable control for RX message FIFO - . - ." "0,1" bitfld.long 0x00 5.--6. " SIZE_HI ,(Upper bits of the) capacity of shared RX message FIFO, in bytes, minus one. To be set for largest supported (received) message. - . - . - . - ." "0,32_bytes_(recommended),2,3" bitfld.long 0x00 1.--4. " SIZE_LO ,(Lower bits of the) capacity of shared RX message FIFO, in bytes, minus one. Read-only, for reference only." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " FIFO_CLEAR ,Returns message FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x70++0x3 line.long 0x00 "SLIMBUS_FL_INFO,Frame Layer IRQ status. Write 1 to a bit to clear it. Note: FS loss implies SFS loss, and SFS loss implies MS loss, but only the 'strongest' loss event is logged for a given event." eventfld.long 0x00 6. " RECONFIGURED ,Reconfiguration boundary crossed - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 5. " SAW_BUS_RESET ,Bus reset sequence detected on the bus: no activity on DATA line (all-zero) for 2 to 4 frames. Clock receiver FSM has returned to Reset state. Should trigger a local component reset (software sequence). - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 3. " FOUND_MS ,Message sync was acquired: operational state reached - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 2. " LOST_MS ,Message Synchronization was lost Interface device class-specific information element (IE) Note: Not asserted in case of FS or SFS loss. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " LOST_SFS ,Super Frame Synchronization was lost Interface device class-specific information element (IE) Note: Not asserted in case of FS loss. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 0. " LOST_FS ,Frame Synchronization was lost Interface device class-specific information element (IE) - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x74++0x3 line.long 0x00 "SLIMBUS_FL_CONTROL,Frame Layer control. (Self-cleared bits)" bitfld.long 0x00 8. " VALIDATE_DCMAP ,Validates the mapping of data channels on devices: to be used after modifying the DC*_MAP* fields (DI and PN). - . - ." "No_action,1" bitfld.long 0x00 7. " CLEAR_RECONFIGURATION ,Clear all updates cumulated since the last reconfiguration, return reconfiguration fields to currently active value. Self-cleared immediately. - . - ." "No_action,Clear_reconfiguration" bitfld.long 0x00 6. " BUS_SHUTDOWN ,Sets both the clock source or the clock receiver FSMs back to 'Undefined' state at the next reconfiguration boundary. Executed (and bit self-cleared) on next reconfiguration (forced or not); also cleared by a 'clear_reconfiguration.." "0,1" textline " " bitfld.long 0x00 5. " KILL_FS ,Force immediate Frame Synchronization loss (implying as well message and superframe sync) When in 'Operational', 'SeekingMessageSync' or 'SeekingSuperFrameSync' states, component shall go to 'SeekingFrameSync' and start reaquiring f.." "No_action,1" bitfld.long 0x00 4. " KILL_SFS ,Force SuperFrame Synchronization loss at next reconfiguration boundary (implying as well message sync loss). When in 'Operational' or 'SeekingMessageSync' states, component shall go to 'SeekingSuperFrameSync' and start.." "No_action,1" bitfld.long 0x00 3. " KILL_MS ,Force an immediate Message Synchronization loss. When in 'Operational' state, component shall go to 'SeekingMessageSync' and start reaquiring message sync. No effect otherwise. For debug use. - . - . - ." "No_action,1" textline " " bitfld.long 0x00 2. " FORCE_RECONFIGURE ,Force a reconfiguration boundary at next superframe boundary, rather than wait for a RECONFIGURE_NOW() message. - . - . - . - ." "No_request_pending,1" bitfld.long 0x00 1. " COMPONENT_RESET ,Component reset request control: Transitions clock receiver FSM to state 'Reset' (from any other state). Immediate action. Set upon reception of the RESET_DEVICE() message by the interface device, which requires a component-lev.." "0,1" bitfld.long 0x00 0. " BOOT ,Boot the component when not in active framer mode (don't care when in active framer mode). Transitions clock receiver FSM from state 'Undefined' to 'Reset'. - . - ." "No_action,1" group.long 0x78++0x3 line.long 0x00 "SLIMBUS_FL_SM,Subframe mode (SM: defines control vs. data space partition) control and status Software must write in values : a) to use when booting in active framer mode. b) extracted from NEXT_SUBFRAME_MODE(SM), to use at following reconfiguration bo.." bitfld.long 0x00 0.--4. " SM ,Subframe Mode, which sets Control Space Width (CSW) and Subframe Length (SFL), both expressed in slots. Note that we always have CSW &lt;= SFL since the control is included in the subframe. - . - . - . - . - . - . - . - . - . - .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7C++0x3 line.long 0x00 "SLIMBUS_FL_CG,Clock Gear (CG) control and status Software must write in values : a) to use when booting in active framer mode. b) extracted from NEXT_CLOCK_GEAR(CG), to use at following reconfiguration boundary. Hardware-updated upon superframe sync ac.." bitfld.long 0x00 0.--3. " CG ,Clock Gear (CG) to be used after the next reconfiguration boundary. Root / SLIMbus frequency ratio is defined as 2 - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x3 line.long 0x00 "SLIMBUS_FL_RF,Root frequency (RF = SLIMbus clock frequency when in gear 10) control and status Software must write in values : a) to use when booting in active framer mode. b) extracted from NEXT_ROOT_FREQUENCY(RF), to use at following reconfiguration .." bitfld.long 0x00 0.--3. " RF ,Root frequency - . - . - . - . - . - . - . - . - . - ." "0,24.576_MHz,22.5792_MHz,15.36_MHz,16.8_MHz,19.2_MHz,24_MHz,25_MHz,26_MHz,27_MHz,10,11,12,13,14,15" group.long 0x90++0x3 line.long 0x00 "SLIMBUS_FR_INFO,Framer device status (when active). Write 1 to a bit to clear it." eventfld.long 0x00 5. " CLOCK_RESTART ,Clock restart request event detected (that is, asynchronous DATA line transition during clock pause) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 4. " FRAMER_UNACTIVATED ,Framer has left clock source operational state. Set on ACTIVE_FRAMER information element deassertion. (framer device class-specific IE) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 3. " FRAMER_ACTIVATED ,Framer has reached clock source operational state. Set on ACTIVE_FRAMER information element assertion. (framer device class-specific IE) - . - ." "no_event_pending,event_pending" textline " " eventfld.long 0x00 2. " GC_TX_COL ,Collision during guide byte transmit (Guide Channel) Framer device class-specific information element (IE) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 1. " FI_TX_COL ,Collision during Framing Information transmit (framing channel) Framer device class-specific information element (IE) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 0. " FS_TX_COL ,Collision during Frame Sync symbol transmit (framing channel) Framer device class-specific information element (IE) - . - ." "no_event_pending,event_pending" group.long 0x94++0x3 line.long 0x00 "SLIMBUS_FR_CLOCK_SOURCE,Root clock configuration for active framer mode, used at next reconfiguration boundary. Unused when not active framer." bitfld.long 0x00 4.--6. " CLKSEL ,SLIMbus clock selection - . - . - ." "FCLK1,FCLK2,FCLK3,3,4,5,6,7" bitfld.long 0x00 0.--3. " CLKDIV ,Root divider ratio, applied on clock input to obtain root clock, to be used at next reconfiguration boundary. Input/ root frequency ratio is defined as 2 With CG the SLIMbus clock gear, Input / SLIMbus frequency ra.." "0,1,2,3,4,5,Ratio_is_2,Ratio_is_4,Ratio_is_8,Ratio_is_16,Ratio_is_32,11,12,13,14,15" group.long 0x98++0x3 line.long 0x00 "SLIMBUS_FR_CONTROL,Framer Device control. Unused when not active framer. (Self-cleared bits)" bitfld.long 0x00 1. " BUS_RESET ,Bus reset request control, when framer is already active. Set upon reception of the NEXT_RESET_BUS() message. Transitions clock source FSM to state 'StartingClock' (from 'Operational'). - . - . - . - ." "0,1" bitfld.long 0x00 0. " BOOT ,Initiate an active framer (clock source) boot sequence for the component, that is, when component is default active framer. Transitions clock source FSM from state 'Undefined' to 'CheckingDataLine'. Transitions.." "0,1" group.long 0x9C++0x3 line.long 0x00 "SLIMBUS_FR_FRAMER_HANDOVER,Framer handover control (outgoing if currently active, incoming if currently inactive)" bitfld.long 0x00 12. " HANDOVER_ENABLE ,Enable framer handover, upon NEXT_ACTIVE_FRAMER(NCi,NCo) reception. Self-cleared upon handover, that is, at next reconfiguration boundary. - . - ." "No_framer_handover,1" hexmask.long.word 0x00 0.--11. 1. " NCO_NCI ,NCo[11:0] / NCi[11:0] for outgoing / incoming framer respectively, as extracted from NEXT_ACTIVE_FRAMER(NCi,NCo) Used on framer handover at next reconfiguration boundary." group.long 0xA0++0x3 line.long 0x00 "SLIMBUS_FR_CLOCK_PAUSE,Clock and pause restart control. Applied at following reconfiguration boundary, that is, where the clock is paused. Note that programming is indentical for an active framer (clock source) and a clock receiver." bitfld.long 0x00 3.--8. " RT_HI ,MSBs of 8-bit SLIMbus parameter. Constant. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--2. " RT ,Restart Time (RT) for recovery after clock pause, as extracted from NEXT_PAUSE_CLOCK(RT) LSBs of 8-bit SLIMbus parameter. Unused when not active framer. - . - . - ." "0,1,2,3" bitfld.long 0x00 0. " CLOCK_PAUSE ,Control clock pause / restart. Self-cleared upon restart. - . - ." "0,1" tree.end tree "SLIMBUS1_L3Interconnect" base ad:0x4902C000 tree "Channel_0" width 29. group.long 0x314++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_0,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x318++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_0,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x31C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_0,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x304++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_0,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x308++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_0,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x30C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_0,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x300++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_0,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x310++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_0,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x214++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_0,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x218++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_0,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x21C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_0,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x204++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_0,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x208++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_0,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x20C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_0,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x200++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_0,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x210++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_0,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x108++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_0,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x104++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_0,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x100++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_0,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_1" width 29. group.long 0x334++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_1,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x338++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_1,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x33C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_1,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x324++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_1,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x328++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_1,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x32C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_1,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x320++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_1,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x330++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_1,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x234++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_1,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x238++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_1,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x23C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_1,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x224++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_1,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x228++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_1,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x22C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_1,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x220++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_1,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x230++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_1,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x118++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_1,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x114++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_1,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x110++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_1,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_2" width 29. group.long 0x354++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_2,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x358++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_2,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x35C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_2,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x344++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_2,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x348++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_2,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x34C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_2,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x340++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_2,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x350++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_2,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x254++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_2,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x258++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_2,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x25C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_2,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x244++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_2,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x248++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_2,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x24C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_2,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x240++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_2,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x250++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_2,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x128++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_2,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x124++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_2,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x120++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_2,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_3" width 29. group.long 0x374++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_3,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x378++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_3,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x37C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_3,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x364++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_3,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x368++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_3,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x36C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_3,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x360++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_3,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x370++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_3,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x274++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_3,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x278++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_3,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x27C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_3,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x264++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_3,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x268++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_3,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x26C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_3,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x260++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_3,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x270++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_3,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x138++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_3,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x134++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_3,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x130++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_3,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_4" width 29. group.long 0x394++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_4,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x398++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_4,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x39C++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_4,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x384++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_4,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x388++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_4,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x38C++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_4,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x380++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_4,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x390++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_4,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x294++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_4,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x298++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_4,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x29C++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_4,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x284++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_4,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x288++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_4,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x28C++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_4,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x280++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_4,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x290++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_4,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x148++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_4,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x144++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_4,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x140++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_4,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_5" width 29. group.long 0x3B4++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_5,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3B8++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_5,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x3BC++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_5,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x3A4++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_5,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x3A8++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_5,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x3AC++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_5,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x3A0++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_5,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x3B0++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_5,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x2B4++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_5,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2B8++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_5,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x2BC++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_5,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x2A4++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_5,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x2A8++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_5,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x2AC++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_5,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x2A0++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_5,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2B0++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_5,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x158++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_5,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x154++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_5,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x150++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_5,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_6" width 29. group.long 0x3D4++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_6,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3D8++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_6,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x3DC++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_6,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x3C4++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_6,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x3C8++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_6,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x3CC++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_6,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x3C0++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_6,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x3D0++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_6,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x2D4++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_6,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2D8++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_6,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x2DC++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_6,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x2C4++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_6,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x2C8++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_6,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x2CC++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_6,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x2C0++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_6,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2D0++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_6,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." rgroup.long 0x168++0x3 line.long 0x00 "SLIMBUS_DEV_EA_HI_i_6,Device's Enumeration Address (EA[47:0]), upper 16 bits. For reference." hexmask.long.word 0x00 0.--15. 1. " EA_MI ,Manufacturer Index (MI[15:0]), shared by all devices" rgroup.long 0x164++0x3 line.long 0x00 "SLIMBUS_DEV_EA_LO_i_6,Device's Enumeration Address (EA[47:0]), lower 32 bits. For reference." hexmask.long.word 0x00 16.--31. 1. " EA_PC ,Product Code (PC[15:0]), shared by all devices of the component" hexmask.long.byte 0x00 8.--15. 1. " EA_DI ,Device Index (DI[15:0]), hardcoded from 0 upwards (0x00,0x01,0x02, etc...) each device of the component. WARNING: value is incorrectly given as 0x00 for all indexes." hexmask.long.byte 0x00 0.--7. 1. " EA_IV ,Component's Instance Value (IV[7:0]), shared by all devices of the component" group.long 0x160++0x3 line.long 0x00 "SLIMBUS_DEV_LA_i_6,Device Logical Address control" bitfld.long 0x00 9. " EA_ENABLE ,Enables the reception of 'long-header' messages to the device's hardwired Enumeration Address (EA). Don't care if LA_ENABLE is 1. - . - ." "0,1" bitfld.long 0x00 8. " LA_ENABLE ,Enables the reception of 'short-header' messages to the device's Logical Address (LA). - . - ." "0,1" hexmask.long.byte 0x00 0.--7. 1. " LA ,Device Logical Address, assigned by manager device at enumeration (0x00 through 0xEF). The active manager device itself has address 0xFF by default. - ." tree.end tree "Channel_7" width 29. group.long 0x3F4++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG1_j_7,RX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_FORCE_VALUE ,Value to force the CTS TAG bit value when in asynchronous TP and secondary channel owner (that is, receiver) and CTS is forced (CTS_force_en=1) Don't care in all other cases. Warning: forcing CTS=1 can result i.." "0,1" bitfld.long 0x00 29. " CTS_FORCE_EN ,Forces the CTS TAG bit value when in an asynchronous TP and secondary owner (that is, receiver) of the channel. Don't care in other cases. - . - ." "0,1" textline " " bitfld.long 0x00 28. " DT_LPCM ,OSAM-to-unsigned decoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_decoding_enabled" bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Channel index 0 should have CL=0, since there is no 'previous' channel in that case. TP and segment interval (encod.." "0,1" textline " " bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . - . - . - . - . - ..." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs - . - ." "0,1" textline " " bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3F8++0x3 line.long 0x00 "SLIMBUS_DCR_CONFIG2_j_7,RX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution" rgroup.long 0x3FC++0x3 line.long 0x00 "SLIMBUS_DCR_DATA_j_7,RX data agent DATA FIFO output. Writes have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x3E4++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP1_j_7,RX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,RX data agent FIFO base address within shared RX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in read accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x3E8++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_SETUP2_j_7,RX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO output (read) RX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side RX data agent FIFO threshold. DMA read requests get (re-)asserted when RD_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side RX data agent FIFO threshold, used for SLIMbus reception. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x3EC++0x3 line.long 0x00 "SLIMBUS_DCR_FIFO_STATUS_j_7,RX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCR_DATA read accesses. In that mode, DMA request shall reassert when ACC_CNT = RD_LEVEL (that is, whole packet received). - . - . - . - ." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " RD_LEVEL ,Number of segment words stored in FIFO, that can be read out. - . - ." bitfld.long 0x00 1. " HILEVEL ,Indicator of read level (RD_LEVEL: number of readable segment words) with respect to (read) threshold (DMA_THRESHOLD). Activates DMA read requests when high. - . - ." "0,1" bitfld.long 0x00 0. " EMPTY ,FIFO empty indicator - . - ." "0,1" group.long 0x3E0++0x3 line.long 0x00 "SLIMBUS_DCR_INFO_j_7,RX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " HILEVEL ,Read level of RX data agent FIFO has gone above DMA threshold (that is, reads required to empty FIFO) - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in RX data agent FIFO - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in RX data agent FIFO Note: never asserted in pulled or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in RX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x3F0++0x3 line.long 0x00 "SLIMBUS_DCR_MAP_j_7,Associates a device and port to the RX data agent. Write to field FL_CONTROL[8] VALIDATE_DCMAP to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." group.long 0x2F4++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG1_j_7,TX data agent configuration, applied at the next reconfiguration boundary" bitfld.long 0x00 31. " ENABLE ,Data agent enabling control. Auto-cleared upon frame or superframe sync loss. - . - ." "0,1" bitfld.long 0x00 30. " CTS_LAST_VALUE ,Last received value of the CTS TAG bit. Only updated for asynchronous TP, when primary owner (that is, transmitter) of the channel. - . - ." "0,1" bitfld.long 0x00 28. " DT_LPCM ,Unsigned-to-OSAM encoding enable for Data Type (DT) = LPCM audio (0x1) - . - ." "0,DT=0x1:_encoding_enabled" textline " " bitfld.long 0x00 16.--19. " AF ,Auxillairy Format (AF) used in segment word size calculation. Non-zero values not supported in extended asynchronous TPs. - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CL ,Channel Link (CL) enable: Pairing up of current channel with previous one (that is, channel index below) Tied-0, read-only field for channel index 0, since there is no 'previous' channel in that case. TP and seg.." "0,1" bitfld.long 0x00 10.--14. " DL ,Segment Data Length (DL), in 4-bit slots (except when 0). AUX + DATA length shall fit in a segment word, that is, 1 to 32 bits. In extended async TPs, sets segment word size (0 and odd values illegal) instead. - . - . -.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " SL ,total Segment Length (SL), in 4-bit slots. SL &gt;= TAG length + AUX length + DATA length - ." "Reseved_value,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " TP_QUALIFIER ,Qualifier for plain/extended half-duplex asynchronous TPs (owner ID). Unused and don't care for other TPs. - . - ." "0,1" bitfld.long 0x00 0.--3. " TP ,Transport Protocol (TP) Determines also the TAG length (from 0 to 2 slots). - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F8++0x3 line.long 0x00 "SLIMBUS_DCT_CONFIG2_j_7,TX data agent configuration (continued), applied at the next reconfiguration boundary" hexmask.long.word 0x00 0.--11. 1. " SD ,Segment Distribution (see)" group.long 0x2FC++0x3 line.long 0x00 "SLIMBUS_DCT_DATA_j_7,TX data agent DATA FIFO input. Reads have no effect on FIFO." hexmask.long 0x00 0.--31. 1. " DATA ,Data segment word, single-word or packed, LSB or MSB-aligned." group.long 0x2E4++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP1_j_7,TX data agent FIFO setup. To be kept static during channel operation." hexmask.long.byte 0x00 5.--12. 1. " BASE_ADDR ,TX data agent FIFO base address within shared TX RAM. (physical address of the 32-bit wide RAM array)" bitfld.long 0x00 1.--4. " DMA_REQ_SIZE ,DMA request size minus 1, in write accesses. In counting (packet) mode, last request may be smaller. Only applicable in precise DMA mode. - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x2E8++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_SETUP2_j_7,TX data agent FIFO setup, continued. To be kept static during channel operation." bitfld.long 0x00 31. " PACKING ,Packing enable control - . - ." "0,1" bitfld.long 0x00 30. " MSB_ALIGNED ,PLACEHOLDER, NO EFFECT: DATA ALWAYS LSB-aligned LSB/MSB-alignment of FIFO input (write) TX data. - . - ." "0,1" hexmask.long.byte 0x00 16.--23. 1. " DMA_THRESHOLD ,SW-side TX data agent FIFO threshold. DMA write requests get (re-)asserted when WR_LEVEL is above threshold. Range: 0 to SIZE field value (included). - . - ." textline " " hexmask.long.byte 0x00 8.--15. 1. " SB_THRESHOLD ,SLIMbus-side TX data agent FIFO threshold, used for SLIMbus transmission. - . - ." hexmask.long.byte 0x00 0.--7. 1. " SIZE ,Capacity of FIFO in segment words, minus one. - . - . - ." group.long 0x2EC++0x3 line.long 0x00 "SLIMBUS_DCT_FIFO_STATUS_j_7,TX data agent FIFO status, for software (non-DMA) FIFO management." bitfld.long 0x00 31. " COUNT_EN ,Down-counter mode control. Only applicable in precise DMA mode. - . - . - . - ." "0,1" hexmask.long.word 0x00 16.--30. 1. " ACC_CNT ,'Packet mode' down-counter of segment words, decremented on DCT_DATA write accesses. In that mode, DMA request shall deassert when ACC_CNT = 0 (that is, packet fully transmitted / stored in TX FIFO). - . - . - .." bitfld.long 0x00 15. " IMPRECISE_EN ,Precise vs. Imprecise DMA requesting mode control. (A DMA request is a single assertion-deassertion cycle.) - . - ." "0,1" textline " " hexmask.long.word 0x00 2.--10. 1. " WR_LEVEL ,Number of free segment words in FIFO, that could be filled by writes. - . - ." bitfld.long 0x00 1. " LOLEVEL ,Indicator of write level (WR_LEVEL: number of free words in FIFO) with respect to (write) threshold (DMA_threshold). Activates DMA write requests when high. - . - ." "0,1" bitfld.long 0x00 0. " FULL ,FIFO full indicator - . - ." "0,1" group.long 0x2E0++0x3 line.long 0x00 "SLIMBUS_DCT_INFO_j_7,TX data agent status. Write 1 to a bit to clear it." eventfld.long 0x00 3. " LOLEVEL ,Write level of TX data agent FIFO has gone above DMA threshold (that is, writes required to fill FIFO) Note: Defaults to 0 (even though FIFO is then empty) as it sets to 1 only when read-only status bit DCT_FIFO_STATUS.LOLEVEL transition.." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " UNDERFLOW ,Underflow in TX data agent FIFO. Note: never asserted in pushed or async TPs, by construction. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX data agent FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " DATA_TX_COL ,TX collision in TX data agent. Core information element (IE). - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2F0++0x3 line.long 0x00 "SLIMBUS_DCT_MAP_j_7,Associates a device and port to the TX data agent. Write to field FL_CONTROL.validate_dcmap to validate changes." bitfld.long 0x00 8.--13. " PN ,Port Number (PN), identifies the data channel's port for the device. Shall be unique within a device. Note that a half-duplex (bidirectional) port has 2 data agents with the same PN, 1 TX + 1 Rx." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DI ,Index (DI) of the device this data agent belongs to. Devices are hard-indexed from 0 upwards." tree.end textline "" width 28. rgroup.long 0x0++0x3 line.long 0x00 "SLIMBUS_CMP_REVISION,IP Revision Identifier Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,Revision Number" rgroup.long 0x4++0x3 line.long 0x00 "SLIMBUS_CMP_HWINFO,Those read-only, hardcoded fields display the values of the eponymous hardware configuration depending on module instantiation - SLIMBUS1 or SLIMBUS2." bitfld.long 0x00 28.--31. " DEV ,Device count: number of devices supported by the component, most notably through the automatically reception of the messages addressed to them. Sets the number of instances of the 'DEV_XYZ' registers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TDC ,Transmit Data agent Count: Number of transmit hardware data agents (FIFO and associated logic) Sets the number of instances of the 'DCT_XYZ' registers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RDC ,Receive Data agent Count: Number of receive hardware data agents (FIFO and associated logic) Sets the number of instances of the 'DCR_XYZ' registers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 12.--19. 1. " RRSZ ,Size of receive FIFO RAM, in 32-bit words. RX message FIFO and all RX data FIFOs map to that shared RAM." hexmask.long.byte 0x00 4.--11. 1. " TRSZ ,Size of transmit FIFO RAM, in 32-bit words. TX message FIFO and all TX data FIFOs map to that shared RAM." bitfld.long 0x00 0.--3. " PSZ ,Size of (both TX and RX) FIFO segment word pointers, in bits. Determines the maximum number of (variable-sized) segment words a data agent FIFO can contain. Sets the width of FIFO control and status fields: size,.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "SLIMBUS_CMP_SYSCONFIG,This register allows controlling various parameters of the interconnect interface" bitfld.long 0x00 8. " AUTOGATINGDISABLE ,Control of the internal clock autogating for safety / debug only. No impact on module functionality, only on dynamic power. - . - ." "0,1" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "0,1,2,3" bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "No_action,Initiate_software_reset" group.long 0x24++0x3 line.long 0x00 "SLIMBUS_CMP_IRQSTATUS_RAW,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 19. " DCR_INFO_7 ,IRQ status for RX Data agent 7 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 18. " DCR_INFO_6 ,IRQ status for RX Data agent 6 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 17. " DCR_INFO_5 ,IRQ status for RX Data agent 5 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 16. " DCR_INFO_4 ,IRQ status for RX Data agent 4 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 15. " DCR_INFO_3 ,IRQ status for RX Data agent 3 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 14. " DCR_INFO_2 ,IRQ status for RX Data agent 2 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 13. " DCR_INFO_1 ,IRQ status for RX Data agent 1 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 12. " DCR_INFO_0 ,IRQ status for RX Data agent 0 If implemented: - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 11. " DCT_INFO_7 ,IRQ status for TX Data agent 7 - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 10. " DCT_INFO_6 ,IRQ status for TX Data agent 6 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 9. " DCT_INFO_5 ,IRQ status for TX Data agent 5 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 8. " DCT_INFO_4 ,IRQ status for TX Data agent 4 - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 7. " DCT_INFO_3 ,IRQ status for TX Data agent 3 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 6. " DCT_INFO_2 ,IRQ status for TX Data agent 2 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 5. " DCT_INFO_1 ,IRQ status for TX Data agent 1 - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 4. " DCT_INFO_0 ,IRQ status for TX Data agent 0 - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 3. " SMR_INFO ,IRQ status for message receive - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 2. " SMT_INFO ,IRQ status for message transmit - . - . - . - ." "No_action,IRQ_event_pending" textline " " bitfld.long 0x00 1. " FR_INFO ,IRQ status for Framer device, when active - . - . - . - ." "No_action,IRQ_event_pending" bitfld.long 0x00 0. " FL_INFO ,IRQ status for Frame Layer - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x28++0x3 line.long 0x00 "SLIMBUS_CMP_IRQSTATUS,Component (that is, main) interrupt request status. Check the corresponding secondary status register. Enabled status isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status get.." eventfld.long 0x00 19. " DCR_INFO_7 ,IRQ status for RX Data agent 7. If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 18. " DCR_INFO_6 ,IRQ status for RX Data agent 6. If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 17. " DCR_INFO_5 ,IRQ status for RX Data agent 5 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 16. " DCR_INFO_4 ,IRQ status for RX Data agent 4 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 15. " DCR_INFO_3 ,IRQ status for RX Data agent 3 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 14. " DCR_INFO_2 ,IRQ status for RX Data agent 2 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 13. " DCR_INFO_1 ,IRQ status for RX Data agent 1 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 12. " DCR_INFO_0 ,IRQ status for RX Data agent 0 . If implemented: - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 11. " DCT_INFO_7 ,IRQ status for TX Data agent 7 - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 10. " DCT_INFO_6 ,IRQ status for TX Data agent 6 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 9. " DCT_INFO_5 ,IRQ status for TX Data agent 5 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 8. " DCT_INFO_4 ,IRQ status for TX Data agent 4 - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 7. " DCT_INFO_3 ,IRQ status for TX Data agent 3 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 6. " DCT_INFO_2 ,IRQ status for TX Data agent 2 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 5. " DCT_INFO_1 ,IRQ status for TX Data agent 1 - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 4. " DCT_INFO_0 ,IRQ status for TX Data agent 0 - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 3. " SMR_INFO ,IRQ status for message receive - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " SMT_INFO ,IRQ status for message transmit - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 1. " FR_INFO ,IRQ status for Framer device, when active - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 0. " FL_INFO ,IRQ status for Frame Layer - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x2C++0x3 line.long 0x00 "SLIMBUS_CMP_IRQENABLE_SET,Component (that is, main) interrupt request enable Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " DCR_INFO_7_EN ,IRQ enable for RX Data agent 7. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 18. " DCR_INFO_6_EN ,IRQ enable for RX Data agent 6. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 17. " DCR_INFO_5_EN ,IRQ enable for RX Data agent 5. If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 16. " DCR_INFO_4_EN ,IRQ enable for RX Data agent 4. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 15. " DCR_INFO_3_EN ,IRQ enable for RX Data agent 3. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " DCR_INFO_2_EN ,IRQ enable for RX Data agent 2. If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 13. " DCR_INFO_1_EN ,IRQ enable for RX Data agent 1. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 12. " DCR_INFO_0_EN ,IRQ enable for RX Data agent 0. If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 11. " DCT_INFO_7_EN ,IRQ enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 10. " DCT_INFO_6_EN ,IRQ enable for TX Data agent 6 - . - . - . - ." "No_action,1" bitfld.long 0x00 9. " DCT_INFO_5_EN ,IRQ enable for TX Data agent 5 - . - . - . - ." "No_action,1" bitfld.long 0x00 8. " DCT_INFO_4_EN ,IRQ enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 7. " DCT_INFO_3_EN ,IRQ enable for TX Data agent 3 - . - . - . - ." "No_action,1" bitfld.long 0x00 6. " DCT_INFO_2_EN ,IRQ enable for TX Data agent 2 - . - . - . - ." "No_action,1" bitfld.long 0x00 5. " DCT_INFO_1_EN ,IRQ enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 4. " DCT_INFO_0_EN ,IRQ enable for TX Data agent 0 - . - . - . - ." "No_action,1" bitfld.long 0x00 3. " SMR_INFO_EN ,IRQ enable for message receive - . - . - . - ." "No_action,1" bitfld.long 0x00 2. " SMT_INFO_EN ,IRQ enable for message transmit - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 1. " FR_INFO_EN ,IRQ enable for Framer device, when active - . - . - . - ." "No_action,1" bitfld.long 0x00 0. " FL_INFO_EN ,IRQ enable for Frame Layer - . - . - . - ." "No_action,1" group.long 0x30++0x3 line.long 0x00 "SLIMBUS_CMP_IRQENABLE_CLR,Component (that is, main) interrupt request enable Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " DCR_INFO_7_EN ,IRQ enable for RX data agent 7. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 18. " DCR_INFO_6_EN ,IRQ enable for RX data agent 6. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 17. " DCR_INFO_5_EN ,IRQ enable for RX data agent 5. If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 16. " DCR_INFO_4_EN ,IRQ enable for RX data agent 4. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 15. " DCR_INFO_3_EN ,IRQ enable for RX data agent 3. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 14. " DCR_INFO_2_EN ,IRQ enable for RX data agent 2. If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 13. " DCR_INFO_1_EN ,IRQ enable for RX data agent 1. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 12. " DCR_INFO_0_EN ,IRQ enable for RX data agent 0. If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 11. " DCT_INFO_7_EN ,IRQ enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 10. " DCT_INFO_6_EN ,IRQ enable for TX Data agent 6 - . - . - . - ." "No_action,1" eventfld.long 0x00 9. " DCT_INFO_5_EN ,IRQ enable for TX Data agent 5 - . - . - . - ." "No_action,1" eventfld.long 0x00 8. " DCT_INFO_4_EN ,IRQ enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 7. " DCT_INFO_3_EN ,IRQ enable for TX Data agent 3 - . - . - . - ." "No_action,1" eventfld.long 0x00 6. " DCT_INFO_2_EN ,IRQ enable for TX Data agent 2 - . - . - . - ." "No_action,1" eventfld.long 0x00 5. " DCT_INFO_1_EN ,IRQ enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 4. " DCT_INFO_0_EN ,IRQ enable for TX Data agent 0 - . - . - . - ." "No_action,1" eventfld.long 0x00 3. " SMR_INFO_EN ,IRQ enable for message receive - . - . - . - ." "No_action,1" eventfld.long 0x00 2. " SMT_INFO_EN ,IRQ enable for message transmit - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 1. " FR_INFO_EN ,IRQ enable for Framer device, when active - . - . - . - ." "No_action,1" eventfld.long 0x00 0. " FL_INFO_EN ,IRQ enable for Frame Layer - . - . - . - ." "No_action,1" group.long 0x34++0x3 line.long 0x00 "SLIMBUS_CMP_DMAENABLE_SET,Components DMA enable (1 bit per DMA-capable channel) Write 1 to set (enable DMA). Readout equal to corresponding _CLR register." bitfld.long 0x00 19. " DCR_DMA_7_EN ,DMA enable for RX Data agent 7 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 18. " DCR_DMA_6_EN ,DMA enable for RX Data agent 6 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 17. " DCR_DMA_5_EN ,DMA enable for RX Data agent 5 . If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 16. " DCR_DMA_4_EN ,DMA enable for RX Data agent 4 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 15. " DCR_DMA_3_EN ,DMA enable for RX Data agent 3 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " DCR_DMA_2_EN ,DMA enable for RX Data agent 2 . If implemented: - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 13. " DCR_DMA_1_EN ,DMA enable for RX Data agent 1 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 12. " DCR_DMA_0_EN ,DMA enable for RX Data agent 0 . If implemented: - . - . - . - ." "No_action,1" bitfld.long 0x00 11. " DCT_DMA_7_EN ,DMA enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 10. " DCT_DMA_6_EN ,DMA enable for TX Data agent 6 - . - . - . - ." "No_action,1" bitfld.long 0x00 9. " DCT_DMA_5_EN ,DMA enable for TX Data agent 5 - . - . - . - ." "No_action,1" bitfld.long 0x00 8. " DCT_DMA_4_EN ,DMA enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 7. " DCT_DMA_3_EN ,DMA enable for TX Data agent 3 - . - . - . - ." "No_action,1" bitfld.long 0x00 6. " DCT_DMA_2_EN ,DMA enable for TX Data agent 2 - . - . - . - ." "No_action,1" bitfld.long 0x00 5. " DCT_DMA_1_EN ,DMA enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " bitfld.long 0x00 4. " DCT_DMA_0_EN ,DMA enable for TX Data agent 0 - . - . - . - ." "No_action,1" group.long 0x38++0x3 line.long 0x00 "SLIMBUS_CMP_DMAENABLE_CLR,Components DMA enable (1 bit per DMA-capable channel) Write 1 to clear (disable DMA). Readout equal to corresponding _SET register." eventfld.long 0x00 19. " DCR_DMA_7_EN ,DMA enable for RX Data agent 7 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 18. " DCR_DMA_6_EN ,DMA enable for RX Data agent 6 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 17. " DCR_DMA_5_EN ,DMA enable for RX Data agent 5 . If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 16. " DCR_DMA_4_EN ,DMA enable for RX Data agent 4 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 15. " DCR_DMA_3_EN ,DMA enable for RX Data agent 3 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 14. " DCR_DMA_2_EN ,DMA enable for RX Data agent 2 . If implemented: - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 13. " DCR_DMA_1_EN ,DMA enable for RX Data agent 1 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 12. " DCR_DMA_0_EN ,DMA enable for RX Data agent 0 . If implemented: - . - . - . - ." "No_action,1" eventfld.long 0x00 11. " DCT_DMA_7_EN ,DMA enable for TX Data agent 7 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 10. " DCT_DMA_6_EN ,DMA enable for TX Data agent 6 - . - . - . - ." "No_action,1" eventfld.long 0x00 9. " DCT_DMA_5_EN ,DMA enable for TX Data agent 5 - . - . - . - ." "No_action,1" eventfld.long 0x00 8. " DCT_DMA_4_EN ,DMA enable for TX Data agent 4 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 7. " DCT_DMA_3_EN ,DMA enable for TX Data agent 3 - . - . - . - ." "No_action,1" eventfld.long 0x00 6. " DCT_DMA_2_EN ,DMA enable for TX Data agent 2 - . - . - . - ." "No_action,1" eventfld.long 0x00 5. " DCT_DMA_1_EN ,DMA enable for TX Data agent 1 - . - . - . - ." "No_action,1" textline " " eventfld.long 0x00 4. " DCT_DMA_0_EN ,DMA enable for TX Data agent 0 - . - . - . - ." "No_action,1" group.long 0x40++0x3 line.long 0x00 "SLIMBUS_CMP_IV,Component IV field, used as lower 8 bits of the devices' Enumeration Address (EA[47:0]). Identical for all devices of the component." hexmask.long.byte 0x00 0.--7. 1. " IV ,Device component's Instance Value (IV[7:0])" group.long 0x44++0x3 line.long 0x00 "SLIMBUS_CMP_MI_PC,Component MI and PC fields, used as upper 32 bits of the devices' Enumeration Address (EA[47:0]). Identical for all devices of the component." hexmask.long.word 0x00 16.--31. 1. " PC ,Device component's Product Code (PC[15:0])" hexmask.long.word 0x00 0.--15. 1. " MI ,Device component's Manufacturer Index (MI[15:0])" group.long 0x50++0x3 line.long 0x00 "SLIMBUS_SMT_INFO,IRQ status for Shared Message Transmit channel. Write 1 to a bit to clear it." eventfld.long 0x00 7. " ABORT ,TX message was aborted before completion because of message sync loss. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 5. " UDEF ,TX message was UDEF'ed: undefined response, protocol error. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 4. " NORE ,TX message was NORE'ed: no or all-zero message response - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 3. " NACK ,TX message was NACK'ed: at least one of the recipient devices requested message retransmission. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 2. " PACK ,TX message was PACK'ed: all recipient devices accepted the message. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " OVERFLOW ,Overflow in TX message FIFO: Software tried to write more bytes than available in the FIFO. - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 0. " MC_TX_COL ,Transmit collision in Message Channel (MC) during message transmission. Interface device class-specific information element (IE) - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x54++0x3 line.long 0x00 "SLIMBUS_SMT_MESSAGE,Shared Message Transmit FIFO input" hexmask.long 0x00 0.--31. 1. " TX_MESSAGE ,TX message byte(s), depending on packing mode. Reads return 0. Enter the whole message except last byte (Message Integrity MI and Response MR), and with a don't care placeholder for Primary Integrity (PI)." group.long 0x58++0x3 line.long 0x00 "SLIMBUS_SMT_CONTROL,Control of Shared Message channel Transmission." bitfld.long 0x00 0. " MESSAGE_ENABLE ,Enable the transmission of the message(s) previously written into the TX Message FIFO, with unlimited arbitration auto-retries. Self-cleared after either a message not get PACK'ed or the FIFO is empty. - . - . - . - ." "No_effect,1" group.long 0x5C++0x3 line.long 0x00 "SLIMBUS_SMT_FIFO_SETUP,Shared Message Transmit channel configuration. To be kept static during operation. Note that message segment word size is 2 slots = 1 byte (= message size granularity) and that message FIFO base address is always 0x0." bitfld.long 0x00 7. " PACKING ,Packing enable control for TX message FIFO - . - ." "0,1" bitfld.long 0x00 5.--6. " SIZE_HI ,(Upper bits of the) capacity of shared TX message FIFO, in bytes, minus one. To be set for largest supported (transmitted) message(s). - . - . - . - ." "0,32_bytes_(recommended),2,3" bitfld.long 0x00 1.--4. " SIZE_LO ,(Lower bits of the) capacity of shared TX message FIFO, in bytes, minus one. Read-only, for reference only." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " FIFO_CLEAR ,Returns FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x60++0x3 line.long 0x00 "SLIMBUS_SMR_INFO,IRQ status for Shared Message Receive channel. Write 1 to a bit to clear it." eventfld.long 0x00 4. " OVERFLOW ,Overflow in RX message FIFO: received message is larger than the FIFO. - . - . - . - ." "no_action,clear_event" eventfld.long 0x00 3. " RECEIVED_RECONFIGURE ,RECONFIGURE_NOW message received, available in RX message FIFO - . - . - . - ." "no_action,clear_event" eventfld.long 0x00 2. " RECEIVED_MESSAGE ,Message available in the RX message FIFO. Clear bit to clear the FIFO and allow the reception of further messages (incoming messages will be NACK'ed until then). - . - . - . - ." "no_action,event_pending" textline " " eventfld.long 0x00 1. " UNDERFLOW ,Underflow in RX message FIFO: Software tried to read out more bytes than available. - . - . - . - ." "no_action,clear_event" eventfld.long 0x00 0. " MC_TX_COL ,Transmit collision in Message Channel (MC) during RX message during message reception. Interface device class-specific information element (IE) - . - . - . - ." "no_action,clear_event" rgroup.long 0x64++0x3 line.long 0x00 "SLIMBUS_SMR_MESSAGE,Shared Message Receive channel FIFO output." hexmask.long 0x00 0.--31. 1. " RX_MESSAGE ,RX message byte(s), depending on packing mode. Writes have no effect. Readout value from an empty FIFO is undefined, that is, there is no defined 'reset value'. Message is guaranteed to have destination address matching a local devi.." group.long 0x68++0x3 line.long 0x00 "SLIMBUS_SMR_CONTROL,Control of Shared Message channel Reception." bitfld.long 0x00 0. " MESSAGE_DISABLE ,Disables the reception of incoming messages (that is, broadcast or locally addressed) into the RX Message FIFO. Same effect for the same value than SMR_INFO[2] RECEIVED_MESSAGE, but this bit can be set to 1. - . - ." "0,1" group.long 0x6C++0x3 line.long 0x00 "SLIMBUS_SMR_FIFO_SETUP,Shared Message Receive channel setup. To be kept static during operation. Note that message segment word size is 2 slots = 1 byte (= message size granularity) and that message FIFO base address is always 0x0." bitfld.long 0x00 7. " PACKING ,Packing enable control for RX message FIFO - . - ." "0,1" bitfld.long 0x00 5.--6. " SIZE_HI ,(Upper bits of the) capacity of shared RX message FIFO, in bytes, minus one. To be set for largest supported (received) message. - . - . - . - ." "0,32_bytes_(recommended),2,3" bitfld.long 0x00 1.--4. " SIZE_LO ,(Lower bits of the) capacity of shared RX message FIFO, in bytes, minus one. Read-only, for reference only." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " FIFO_CLEAR ,Returns message FIFO to initial empty state. - . - . - . - ." "No_effect,Clear_FIFO" group.long 0x70++0x3 line.long 0x00 "SLIMBUS_FL_INFO,Frame Layer IRQ status. Write 1 to a bit to clear it. Note: FS loss implies SFS loss, and SFS loss implies MS loss, but only the 'strongest' loss event is logged for a given event." eventfld.long 0x00 6. " RECONFIGURED ,Reconfiguration boundary crossed - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 5. " SAW_BUS_RESET ,Bus reset sequence detected on the bus: no activity on DATA line (all-zero) for 2 to 4 frames. Clock receiver FSM has returned to Reset state. Should trigger a local component reset (software sequence). - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 3. " FOUND_MS ,Message sync was acquired: operational state reached - . - . - . - ." "No_action,IRQ_event_pending" textline " " eventfld.long 0x00 2. " LOST_MS ,Message Synchronization was lost Interface device class-specific information element (IE) Note: Not asserted in case of FS or SFS loss. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 1. " LOST_SFS ,Super Frame Synchronization was lost Interface device class-specific information element (IE) Note: Not asserted in case of FS loss. - . - . - . - ." "No_action,IRQ_event_pending" eventfld.long 0x00 0. " LOST_FS ,Frame Synchronization was lost Interface device class-specific information element (IE) - . - . - . - ." "No_action,IRQ_event_pending" group.long 0x74++0x3 line.long 0x00 "SLIMBUS_FL_CONTROL,Frame Layer control. (Self-cleared bits)" bitfld.long 0x00 8. " VALIDATE_DCMAP ,Validates the mapping of data channels on devices: to be used after modifying the DC*_MAP* fields (DI and PN). - . - ." "No_action,1" bitfld.long 0x00 7. " CLEAR_RECONFIGURATION ,Clear all updates cumulated since the last reconfiguration, return reconfiguration fields to currently active value. Self-cleared immediately. - . - ." "No_action,Clear_reconfiguration" bitfld.long 0x00 6. " BUS_SHUTDOWN ,Sets both the clock source or the clock receiver FSMs back to 'Undefined' state at the next reconfiguration boundary. Executed (and bit self-cleared) on next reconfiguration (forced or not); also cleared by a 'clear_reconfiguration.." "0,1" textline " " bitfld.long 0x00 5. " KILL_FS ,Force immediate Frame Synchronization loss (implying as well message and superframe sync) When in 'Operational', 'SeekingMessageSync' or 'SeekingSuperFrameSync' states, component shall go to 'SeekingFrameSync' and start reaquiring f.." "No_action,1" bitfld.long 0x00 4. " KILL_SFS ,Force SuperFrame Synchronization loss at next reconfiguration boundary (implying as well message sync loss). When in 'Operational' or 'SeekingMessageSync' states, component shall go to 'SeekingSuperFrameSync' and start.." "No_action,1" bitfld.long 0x00 3. " KILL_MS ,Force an immediate Message Synchronization loss. When in 'Operational' state, component shall go to 'SeekingMessageSync' and start reaquiring message sync. No effect otherwise. For debug use. - . - . - ." "No_action,1" textline " " bitfld.long 0x00 2. " FORCE_RECONFIGURE ,Force a reconfiguration boundary at next superframe boundary, rather than wait for a RECONFIGURE_NOW() message. - . - . - . - ." "No_request_pending,1" bitfld.long 0x00 1. " COMPONENT_RESET ,Component reset request control: Transitions clock receiver FSM to state 'Reset' (from any other state). Immediate action. Set upon reception of the RESET_DEVICE() message by the interface device, which requires a component-lev.." "0,1" bitfld.long 0x00 0. " BOOT ,Boot the component when not in active framer mode (don't care when in active framer mode). Transitions clock receiver FSM from state 'Undefined' to 'Reset'. - . - ." "No_action,1" group.long 0x78++0x3 line.long 0x00 "SLIMBUS_FL_SM,Subframe mode (SM: defines control vs. data space partition) control and status Software must write in values : a) to use when booting in active framer mode. b) extracted from NEXT_SUBFRAME_MODE(SM), to use at following reconfiguration bo.." bitfld.long 0x00 0.--4. " SM ,Subframe Mode, which sets Control Space Width (CSW) and Subframe Length (SFL), both expressed in slots. Note that we always have CSW &lt;= SFL since the control is included in the subframe. - . - . - . - . - . - . - . - . - . - .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7C++0x3 line.long 0x00 "SLIMBUS_FL_CG,Clock Gear (CG) control and status Software must write in values : a) to use when booting in active framer mode. b) extracted from NEXT_CLOCK_GEAR(CG), to use at following reconfiguration boundary. Hardware-updated upon superframe sync ac.." bitfld.long 0x00 0.--3. " CG ,Clock Gear (CG) to be used after the next reconfiguration boundary. Root / SLIMbus frequency ratio is defined as 2 - . - . - . - . - . - . - . - . - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x3 line.long 0x00 "SLIMBUS_FL_RF,Root frequency (RF = SLIMbus clock frequency when in gear 10) control and status Software must write in values : a) to use when booting in active framer mode. b) extracted from NEXT_ROOT_FREQUENCY(RF), to use at following reconfiguration .." bitfld.long 0x00 0.--3. " RF ,Root frequency - . - . - . - . - . - . - . - . - . - ." "0,24.576_MHz,22.5792_MHz,15.36_MHz,16.8_MHz,19.2_MHz,24_MHz,25_MHz,26_MHz,27_MHz,10,11,12,13,14,15" group.long 0x90++0x3 line.long 0x00 "SLIMBUS_FR_INFO,Framer device status (when active). Write 1 to a bit to clear it." eventfld.long 0x00 5. " CLOCK_RESTART ,Clock restart request event detected (that is, asynchronous DATA line transition during clock pause) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 4. " FRAMER_UNACTIVATED ,Framer has left clock source operational state. Set on ACTIVE_FRAMER information element deassertion. (framer device class-specific IE) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 3. " FRAMER_ACTIVATED ,Framer has reached clock source operational state. Set on ACTIVE_FRAMER information element assertion. (framer device class-specific IE) - . - ." "no_event_pending,event_pending" textline " " eventfld.long 0x00 2. " GC_TX_COL ,Collision during guide byte transmit (Guide Channel) Framer device class-specific information element (IE) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 1. " FI_TX_COL ,Collision during Framing Information transmit (framing channel) Framer device class-specific information element (IE) - . - ." "no_event_pending,event_pending" eventfld.long 0x00 0. " FS_TX_COL ,Collision during Frame Sync symbol transmit (framing channel) Framer device class-specific information element (IE) - . - ." "no_event_pending,event_pending" group.long 0x94++0x3 line.long 0x00 "SLIMBUS_FR_CLOCK_SOURCE,Root clock configuration for active framer mode, used at next reconfiguration boundary. Unused when not active framer." bitfld.long 0x00 4.--6. " CLKSEL ,SLIMbus clock selection - . - . - ." "FCLK1,FCLK2,FCLK3,3,4,5,6,7" bitfld.long 0x00 0.--3. " CLKDIV ,Root divider ratio, applied on clock input to obtain root clock, to be used at next reconfiguration boundary. Input/ root frequency ratio is defined as 2 With CG the SLIMbus clock gear, Input / SLIMbus frequency ra.." "0,1,2,3,4,5,Ratio_is_2,Ratio_is_4,Ratio_is_8,Ratio_is_16,Ratio_is_32,11,12,13,14,15" group.long 0x98++0x3 line.long 0x00 "SLIMBUS_FR_CONTROL,Framer Device control. Unused when not active framer. (Self-cleared bits)" bitfld.long 0x00 1. " BUS_RESET ,Bus reset request control, when framer is already active. Set upon reception of the NEXT_RESET_BUS() message. Transitions clock source FSM to state 'StartingClock' (from 'Operational'). - . - . - . - ." "0,1" bitfld.long 0x00 0. " BOOT ,Initiate an active framer (clock source) boot sequence for the component, that is, when component is default active framer. Transitions clock source FSM from state 'Undefined' to 'CheckingDataLine'. Transitions.." "0,1" group.long 0x9C++0x3 line.long 0x00 "SLIMBUS_FR_FRAMER_HANDOVER,Framer handover control (outgoing if currently active, incoming if currently inactive)" bitfld.long 0x00 12. " HANDOVER_ENABLE ,Enable framer handover, upon NEXT_ACTIVE_FRAMER(NCi,NCo) reception. Self-cleared upon handover, that is, at next reconfiguration boundary. - . - ." "No_framer_handover,1" hexmask.long.word 0x00 0.--11. 1. " NCO_NCI ,NCo[11:0] / NCi[11:0] for outgoing / incoming framer respectively, as extracted from NEXT_ACTIVE_FRAMER(NCi,NCo) Used on framer handover at next reconfiguration boundary." group.long 0xA0++0x3 line.long 0x00 "SLIMBUS_FR_CLOCK_PAUSE,Clock and pause restart control. Applied at following reconfiguration boundary, that is, where the clock is paused. Note that programming is indentical for an active framer (clock source) and a clock receiver." bitfld.long 0x00 3.--8. " RT_HI ,MSBs of 8-bit SLIMbus parameter. Constant. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1.--2. " RT ,Restart Time (RT) for recovery after clock pause, as extracted from NEXT_PAUSE_CLOCK(RT) LSBs of 8-bit SLIMbus parameter. Unused when not active framer. - . - . - ." "0,1,2,3" bitfld.long 0x00 0. " CLOCK_PAUSE ,Control clock pause / restart. Self-cleared upon restart. - . - ." "0,1" tree.end tree.end tree.end tree.open "MMC_SD_SDIO" tree.open "MMCHS1" tree "MMCHS1" base ad:0x4809C000 width 20. rgroup.long 0x0++0x3 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision." rgroup.long 0x4++0x3 line.long 0x00 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." bitfld.long 0x00 6. " RETMODE ,Retention mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET. - . - ." "Retention_mode_disabled,Retention_mode_enabled" bitfld.long 0x00 2.--5. " MEM_SIZE ,Memory size for FIFO buffer: - . - . - . - ." "0,MEM_512,MEM_1024,3,MEM_2048,5,6,7,MEM_4096,9,10,11,12,13,14,15" bitfld.long 0x00 1. " MERGE_MEM ,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing. - . - ." "TwoMemBuffer,SingleMemBuffer" textline " " bitfld.long 0x00 0. " MADMA_EN ,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA. - . - ." "NoMasterDMA,SupportADMA" group.long 0x10++0x3 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. - . - . - . - ." "ForceStandby,NoStandby,SmartStandby,SmartStandbyWakeUp" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS. - . - ." "EmuEn,EmuDis" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing" group.long 0x110++0x3 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface." bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a 0. - . - . - . - ..." "Force,NoIdle,Smart,SmartWake" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock - . - . - . - ." "None,OCP,Func,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management - . - . - . - ." "Force,NoIdle,Smart,SmartWake" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control - . - ." "Disabled,Enable" bitfld.long 0x00 1. " SOFTRESET ,Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0. - . - . - . - ." "NoReset_r_/_St_un_w,OnReset_r_/_St_rst_w" bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy - . - ." "Off,On" rgroup.long 0x114++0x3 line.long 0x00 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring. - . - ." "OnGoing,Done" group.long 0x124++0x3 line.long 0x00 "MMCHS_CSRE,Card status response error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the correspond.." hexmask.long 0x00 0.--31. 1. " CSRE ,Card status response error" group.long 0x128++0x3 line.long 0x00 "MMCHS_SYSTEST,System Test register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register wi.." bitfld.long 0x00 16. " OBI ,Out-Of-Band Interrupt (OBI) data value - . - ." "LowLevel,HighLevel" bitfld.long 0x00 15. " SDCD ,Card detect input signal (SDCD) data value - . - ." "DrivenLow,DrivenHigh" bitfld.long 0x00 14. " SDWP ,Write protect input signal (SDWP) data value - . - ." "DrivenLow,DrivenHigh" textline " " bitfld.long 0x00 13. " WAKD ,Wake request output signal data value - . - . - . - ." "Zero_r_/_DrivenLow_w,DrivenHIgh_w_/_One_r" bitfld.long 0x00 12. " SSB ,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT). - . - . - . - ." "Clear_w_/_Zero_r,SetThemAll_w_/_One_r" bitfld.long 0x00 11. " D7D ,DAT7 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 10. " D6D ,DAT6 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 9. " D5D ,DAT5 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 8. " D4D ,DAT4 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 7. " D3D ,DAT3 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,One_r_/_DriveHigh_w" bitfld.long 0x00 6. " D2D ,DAT2 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" bitfld.long 0x00 5. " D1D ,DAT1 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 4. " D0D ,DAT0 input/output signal data value - . - . - . - ." "Zero_r_/_Zero_w,One_r_/_DriveHigh_w" bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" textline " " bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value - . - . - . - ." "DrivenLow_w_/_Zero_r,DrivenHigh_w_/_One_r" group.long 0x12C++0x3 line.long 0x00 "MMCHS_CON,Configuration register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and.." bitfld.long 0x00 21. " SDMA_LNE ,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data writ.." "EarlyDeAssert,LateDeAssert" bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).Thi.." "MasterDMADis,MasterDMAEn" bitfld.long 0x00 19. " DDR ,Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Da.." "NormalMode,DDRMode" textline " " bitfld.long 0x00 18. " BOOT_CF0 ,Boot status supported: This register is set when the CMD line need to be forced to 0 for a boot sequence. CMD line is driven to 0 after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer .." "NoCMDForce_/_CMDReleased,CMDForced_/_CMDForceReq" bitfld.long 0x00 17. " BOOT_ACK ,Book acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated. - . - ." "BootNoAck,BootAck" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only .." "Autogating,FreeRunning" textline " " bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also.." "Disable,Enable" bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration.." "NormalMode,OBintMode" bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system inte.." "ActiveHigh,ActiveLow" textline " " bitfld.long 0x00 12. " CEATA ,CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is use to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features. - . - ." "NormalMode,CEATAMode" bitfld.long 0x00 11. " CTPL ,Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO car.." "MMC_SD,SDIO" bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the syst.." "FilterLevel0,FilterLevel1,FilterLevel2,FilterLevel3" textline " " bitfld.long 0x00 8. " WPP ,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the typ.." "ActiveHigh,ActiveLow" bitfld.long 0x00 7. " CDP ,Card detect polarity All cards This bit selects the active level of the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type.." "ActiveHigh,ActiveLow" bitfld.long 0x00 6. " MIT ,MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detectio.." "CTO,No_CTO" textline " " bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the.." "1_4BitMode,8BitMode" bitfld.long 0x00 4. " MODE ,Mode select All cards These bits select between Functional mode and SYSTEST mode. - . - ." "FUNC,SYSTEST" bitfld.long 0x00 3. " STR ,Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a.." "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section .." "NoHostResp,HostResp" bitfld.long 0x00 1. " INIT ,Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock .." "NoInit,InitStream" bitfld.long 0x00 0. " OD ,Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typicall.." "NoOpenDrain,OpenDrain" group.long 0x130++0x3 line.long 0x00 "MMCHS_PWCNT,Power counter register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." hexmask.long.word 0x00 0.--15. 1. " PWRCNT ,Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued. - . - . - . - . - ." group.long 0x204++0x3 line.long 0x00 "MMCHS_BLK,Transfer Length Configuration register [11:0] BLEN is the block size register. [31:16] NBLK is the block count register. This register shall be used for any card." hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[1] BCE) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note:.." hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issu.." group.long 0x208++0x3 line.long 0x00 "MMCHS_ARG,Command argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exce.." hexmask.long 0x00 0.--31. 1. " ARG ,Command argument bits [31:0]" group.long 0x20C++0x3 line.long 0x00 "MMCHS_CMD,Command and transfer mode register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers duri.." bitfld.long 0x00 24.--29. " INDX ,Command index Binary encoded value from 0 to 63 specifying the command number send to card - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ..." "CMD0_or_ACMD0,CMD1_or_ACMD1,CMD2_or_ACMD2,CMD3_or_ACMD3,CMD4_or_ACMD4,CMD5_or_ACMD5,CMD6_or_ACMD6,CMD7_or_ACMD7,CMD8_or_ACMD8,CMD9_or_ACMD9,CMD10_or_ACMD10,CMD11_or_ACMD11,CMD12_or_ACMD12,CMD13_or_ACMD13,CMD14_or_ACMD14,CMD15_or_ACMD15,CMD16_or_ACMD16,CMD17_or_ACMD17,CMD18_or_ACMD18,CMD19_or_ACMD19,CMD20_or_ACMD20,CMD21_or_ACMD21,CMD22_or_ACMD22,CMD23_or_ACMD23,CMD24_or_ACMD24,CMD25_or_ACMD25,CMD26_or_ACMD26,CMD27_or_ACMD27,CMD28_or_ACMD28,CMD29_or_ACMD29,CMD30_or_ACMD30,CMD31_or_ACMD31,CMD32_or_ACMD32,CMD33_or_ACMD33,CMD34_or_ACMD34,CMD35_or_ACMD35,CMD36_or_ACMD36,CMD37_or_ACMD37,CMD38_or_ACMD38,CMD39_or_ACMD39,CMD40_or_ACMD40,CMD41_or_ACMD41,CMD42_or_ACMD42,CMD43_or_ACMD43,CMD44_or_ACMD44,CMD45_or_ACMD45,CMD46_or_ACMD46,CMD47_or_ACMD47,CMD48_or_ACMD48,CMD49_or_ACMD49,CMD50_or_ACMD50,CMD51_or_ACMD51,CMD52_or_ACMD52,CMD53_or_ACMD53,CMD54_or_ACMD54,CMD55_or_ACMD55,CMD56_or_ACMD56,CMD57_or_ACMD57,CMD58_or_ACMD58,CMD59_or_ACMD59,CMD60_or_ACMD60,CMD61_or_ACMD61,CMD62_or_ACMD62,CMD63_or_ACMD63" bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type This register specifies three types of special command: Suspend, Resume and Abort. These bits shall be set to 00b for all other commands. - . - . - . - ." "Normal,Suspend,Resume,Abort" bitfld.long 0x00 21. " DP ,Data present select This register indicates that data is present and DAT line shall be used. It must be set to 0 in the following conditions: - command using only CMD line - command with no data transfer but using .." "NoData,Data" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. If the index is not the same in the response as in the command, it.." "Nocheck,Check" bitfld.long 0x00 19. " CCCE ,Command CRC check enable This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. If an error is detected, it is reported as a command CRC .." "NoCheck,Check" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type This bits defines the response type of the command - . - . - . - ." "Norsp,Lght36,Lght48,Lght48b" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit shall be set to 0. - . - ." "sgleblk,multiblk" bitfld.long 0x00 4. " DDIR ,Data transfer Direction Select This bit defines either data transfer will be a read or a write. - . - ." "Write,Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable SDIO does not support this feature. When this bit is set to 1, the host controller issues a CMD12 automatically after the transfer completion of the last block. The Host Driver shall not set thi.." "Disable,Enable" textline " " bitfld.long 0x00 1. " BCE ,Block Count Enable Multiple block transfers only. This bit is used to enable the block count register (MMCHS_BLK[31:16] NBLK). When Block Count is disabled (MMCHS_CMD[1] BCE is set to 0) in Multiple block transfers (MMCHS_CMD[5] MSBS is s.." "Disable,Enable" bitfld.long 0x00 0. " DE ,DMA Enable This bit is used to enable DMA mode for host data access. - . - ." "Disable,Enable" rgroup.long 0x210++0x3 line.long 0x00 "MMCHS_RSP10,Command response[31:0] Register This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6" hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response [31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response [15:0]" rgroup.long 0x214++0x3 line.long 0x00 "MMCHS_RSP32,Command response[63:32] Register This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP3 ,Command Response [63:48]" hexmask.long.word 0x00 0.--15. 1. " RSP2 ,Command Response [47:32]" rgroup.long 0x218++0x3 line.long 0x00 "MMCHS_RSP54,Command response[95:64] Register This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP5 ,Command Response [95:80]" hexmask.long.word 0x00 0.--15. 1. " RSP4 ,Command Response [79:64]" rgroup.long 0x21C++0x3 line.long 0x00 "MMCHS_RSP76,Command response[127:96] Register This 32-bit register holds bits positions [127:96] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP7 ,Command Response [127:112]" hexmask.long.word 0x00 0.--15. 1. " RSP6 ,Command Response [111:96]" group.long 0x220++0x3 line.long 0x00 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers." hexmask.long 0x00 0.--31. 1. " DATA ,Data Register [31:0] In functional mode (MMCHS_CON[4] MODE set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[11] BRE), otherwise a bad access (MMCHS_S.." rgroup.long 0x224++0x3 line.long 0x00 "MMCHS_PSTATE,Present state register The Host can get status of the Host Controller from this 32-bit read only register." bitfld.long 0x00 24. " CLEV ,CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time. - . - ." "Zero,One" bitfld.long 0x00 20.--23. " DLEV ,DAT[3:0] line signal level DAT[3] =&gt; bit 23 DAT[2] =&gt; bit 22 DAT[1] =&gt; bit 21 DAT[0] =&gt; bit 20 This status is used to check DAT line level to recover from errors, and for debugging. .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (SDWP) level. The value of this register after reset depends on the protect input pin (SDWP) level at that time.." "zero,one" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level This bit reflects the inverse value of the card detect input pin (SDCD), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTATE[17] CSS) is set to 1. Use of this bit is lim.." "zero,one" bitfld.long 0x00 17. " CSS ,Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[18] CDPL). Debouncing is performed on the card detect input pin (SDCD) to detect card stabi.." "Debouncing,Stable" bitfld.long 0x00 16. " CINS ,Card inserted This bit is the debounced value of the card detect input pin (SDCD). An inactive to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt (MMCHS_STAT[6] CINS). A .." "zero,one" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[11:0] BLEN has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from.." "RdDisable,RdEnable" bitfld.long 0x00 10. " BWE ,Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data. - . - ." "WrDisable,WrEnable" bitfld.long 0x00 9. " RTA ,Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block.." "NoTransfer,Transfer" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block gap request. This bit is set to 0 whe.." "NoTransfer,Transfer" bitfld.long 0x00 2. " DLA ,DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue reque.." "zero,one" bitfld.long 0x00 1. " DATI ,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[2] DLA) or Read transfer is active (MMCHS_PSTATE[9] RTA) or when a command with busy is issued. This bit prevents the .." "Cmden,Cmddis" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0.." "Cmden,Cmddis" group.long 0x228++0x3 line.long 0x00 "MMCHS_HCTL,Control register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" bitfld.long 0x00 27. " OBWE ,Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). The write to this register is ignored when M.." "disable,enable" bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" textline " " bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 19. " IBG ,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit shou.." "Itdiable,Itenable" bitfld.long 0x00 18. " RWC ,Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[16] SBGR) generates a read wait per.." "NoRW,RW" textline " " bitfld.long 0x00 17. " CR ,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[16] SBGR). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when tr.." "None,Restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[17] CR) or during a suspend/resume sequence. In case o.." "Transfer,Stpblk" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[26:24]) before starting a transfer. - ..." "0,1,2,3,4,1V8,3V0,3V3" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[11:9] SDVS). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in th.." "Pwroff,Pwron" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interru.." "SDCDSel,CDTLSel" bitfld.long 0x00 6. " CDTL ,Card Detect Test Level: This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. - . - ." "NoCard,CardIns" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This regi.." "Reserved,Reserved1,ADMA2,Reserved2" bitfld.long 0x00 2. " HSPE ,High Speed Enable: Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is set to 0 (default), the Host Controller outputs CMD line and DAT lines at t.." "NormalSpeed,HighSpeed" bitfld.long 0x00 1. " DTW ,Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration regi.." "1_BitMode,4_BitMode" textline " " bitfld.long 0x00 0. " LED ,Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored." "0,1" group.long 0x22C++0x3 line.long 0x00 "MMCHS_SYSCTL,SD system control register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" bitfld.long 0x00 26. " SRD ,Software reset for DAT line. This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see , . DAT finite state machine in both clock domain are also reset. The following registers a.." "Work,Reset" bitfld.long 0x00 25. " SRC ,Software reset for CMD line For more information about SRC bit manipulation, see , . This bit is set to 1 for reset and released to 0 when completed. CMD finite state-machine in both clock domain are also reset..." "Work,Reset" bitfld.long 0x00 24. " SRA ,Software reset for all This bit is set to 1 for reset, and released to 0 when completed. This reset affects the entire host controller except for the card detection circuit and capabilities registers. - . - ." "Work,Reset" textline " " bitfld.long 0x00 16.--19. " DTO ,Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bit field based on - the maximum read access time (NAC) (Refer to the SD Specifica.." "1stDTO,2ndDTO,2,3,4,5,6,7,8,9,10,11,12,13,15thDTO,Rsvd" hexmask.long.word 0x00 6.--15. 1. " CLKD ,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO). - . - . - . - . - ." bitfld.long 0x00 2. " CEN ,Clock enable This bit controls if the clock is provided to the card or not. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " ICS ,Internal clock stable (status) This bit indicates either the internal clock is stable or not. - . - ." "NotReady,Ready" bitfld.long 0x00 0. " ICE ,Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface .." "Stop,Oscillate" group.long 0x230++0x3 line.long 0x00 "MMCHS_STAT,Interrupt status register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" bitfld.long 0x00 29. " BADA ,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[11] BRE =.." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 28. " CERR ,Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An erro.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 25. " ADMAE ,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller gener.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 24. " ACE ,Auto CMD12 error This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1. - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 23. " CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB ,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 21. " DCRC ,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command. - . - ..." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 20. " DTO ,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout - . - . - ..." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 19. " CIE ,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[20] CICE register. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 18. " CEB ,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 17. " CCRC ,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 16. " CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock .." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 15. " ERRI ,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[24:15]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit a.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 10. " BSR ,Boot status received interrupt This bit is set automatically when MMCHS_CON[18] BOOT_CF0 is set 0x0 or 0x1 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 9. " OBI ,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[14] OBIE is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[13] OBIP. This interrupt is .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 8. " CIRQ ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 7. " CREM ,Card removal This bit is set automatically when MMCHS_PSTATE[16] CINS changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 6. " CINS ,Card insertion This bit is set automatically when MMCHS_PSTATE[16] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 5. " BRR ,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[11:0] BLEN is completely written in the buffer. It indicates that the m.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 4. " BWR ,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[11:0] BLEN. It indicates tha.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 3. " DMA ,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 2. " BGE ,Block gap event When a stop at block gap is requested (MMCHS_HCTL[16] SBGR), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap.." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 1. " TC ,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[16] SBGR). In Read mode: This bit is automatic.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 0. " CC ,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[0] CMDI) If the command is a type for which no response is expected, then the command complete interrupt is generate.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" group.long 0x234++0x3 line.long 0x00 "MMCHS_IE,Interrupt SD enable register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" bitfld.long 0x00 29. " BADA_ENABLE ,Bad access to data space Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_ENABLE ,Card error interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_ENABLE ,ADMA error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_ENABLE ,Auto CMD12 error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_ENABLE ,Data end bit error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_ENABLE ,Data CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_ENABLE ,Data timeout error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_ENABLE ,Command index error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_ENABLE ,Command end bit error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_ENABLE ,Command CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_ENABLE ,Command timeout error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_ENABLE ,Boot status interrupt Enable A write to this register when MMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_ENABLE ,Out-of-Band interrupt Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_ENABLE ,Card interrupt Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is .." "Masked,Enabled" bitfld.long 0x00 7. " CREM_ENABLE ,Card removal Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_ENABLE ,Card insertion Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_ENABLE ,Buffer Read Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_ENABLE ,Buffer Write Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_ENABLE ,DMA interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_ENABLE ,Block Gap Event Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_ENABLE ,Transfer completed Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_ENABLE ,Command completed Interrupt Enable - . - ." "Masked,Enabled" group.long 0x238++0x3 line.long 0x00 "MMCHS_ISE,Interrupt signal enable register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" bitfld.long 0x00 29. " BADA_SIGEN ,Bad access to data space signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_SIGEN ,Card error interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_SIGEN ,ADMA error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_SIGEN ,Auto CMD12 error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_SIGEN ,Data end bit error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_SIGEN ,Data CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_SIGEN ,Data timeout error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_SIGEN ,Command index error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_SIGEN ,Command end bit error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_SIGEN ,Command CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_SIGEN ,Command timeout error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_SIGEN ,Boot status signal status EnableA write to this register whenMMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_SIGEN ,Out-Of-Band Interrupt signal status Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_SIGEN ,Card interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 7. " CREM_SIGEN ,Card removal signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_SIGEN ,Card insertion signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_SIGEN ,Buffer Read Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_SIGEN ,Buffer Write Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_SIGEN ,DMA interrupt Signal status enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_SIGEN ,Black Gap Event signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_SIGEN ,Transfer completed signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_SIGEN ,Command completed signal status Enable - . - ." "Masked,Enabled" rgroup.long 0x23C++0x3 line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this register when an Auto CMD12 Error interrupt occurs. This register is valid only when Auto CMD12 is e.." bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error If this bit is set to 1, it means that pending command is not executed due to Auto CMD12 error : ACEB, ACCE, ACTO or ACNE. - . - ." "NoErr,CmdNI" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted. This bit depends on the command index check enable (MMCHS_CMD[20] CICE). .." "NoErr,Err" bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error This bit is set to 1 when detecting a 0 at the end bit position of auto CMD12 command response. - . - ." "NoErr,Err" textline " " bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error This bit is automatically set to 1 when a CRC7 error is detected in the auto CMD12 command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - ." "NoErr,Err" bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error This bit is set to 1 if no response is received within 64 clock cycles from the end bit of the auto CMD12 command. - . - ." "NoErr,TimeOut" bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before Auto CMD12 starts. - . - ." "Exe,NotExe" group.long 0x240++0x3 line.long 0x00 "MMCHS_CAPA,Capabilities register This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x00 28. " BIT64 ,64-bit system bus support: Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. - . - ." "SysAddr32b,SysAddr64b" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register i.." "1V8_NotSup_r_/_St_1V8NotSup_w,St_1V8Sup_w_/_1V8_Sup_r" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized.." "St_3V0NotSup_w_/_3V0_NotSup_r,3V0_Sup_r_/_St_3V0Sup_w" textline " " bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized b.." "St_3V3NotSup_w_/_3V3_NotSup_r,St_3V3Sup_w_/_3V3_Sup_r" bitfld.long 0x00 23. " SRS ,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports suspend/resume functionality. - . - ." "NotSupported,Supported" bitfld.long 0x00 22. " DS ,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly. - . - ." "NotSupported,Supported" textline " " bitfld.long 0x00 21. " HSS ,High-speed support This bit indicates that the host controller supports high-speed operations and can supply an up-to maximum card frequency. - . - ." "NotSupported,Supported" bitfld.long 0x00 19. " AD2S ,ADMA2 support: This bit indicates whether the host controller is capable of using ADMA2. It depends on setting of generic parameter MMCHS_HL_HWINFO[0] MADMA_EN - . - ." "ADMA2NotSupported,ADMA2Supported" bitfld.long 0x00 16.--17. " MBL ,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 by.." "512,1024,2048,3" textline " " bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " TCU ,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - . - ." "MHz,KHz" bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x248++0x3 line.long 0x00 "MMCHS_CUR_CAPA,Maximum current capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a .." hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V - ." hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V - ." hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V - ." group.long 0x250++0x3 line.long 0x00 "MMCHS_FE,Force Event Register for Error Interrupt status The force Event Register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will.." bitfld.long 0x00 29. " FE_BADA ,Force Event Bad access to data space - . - ." "NoAction,IntForced" bitfld.long 0x00 28. " FE_CERR ,Force Event Card error - . - ." "NoAction,IntForced" bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA Error: - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 23. " FE_CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " FE_DEB ,Force Event Data End Bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error - . - ." "NoAction,IntForced" bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 16. " FE_CTO ,Command Timeout Error - This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. . - . - For commands that reply within 5 clock cycles - the timeout is still .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 4. " FE_ACIE ,Force Event Auto CMD12 index error - . - ." "NoAction,IntForced" bitfld.long 0x00 3. " FE_ACEB ,Force Event Auto CMD12 end bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 2. " FE_ACCE ,Force Event Auto CMD12 CRC error - . - ." "NoAction,IntForced" bitfld.long 0x00 1. " FE_ACTO ,Force Event Auto CMD12 timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 0. " FE_ACNE ,Force Event Auto CMD12 not executed - . - ." "NoAction,IntForced" group.long 0x254++0x3 line.long 0x00 "MMCHS_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor." bitfld.long 0x00 2. " LME ,ADMA Length Mismatch Error: (1) While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. (2) Total data length can not be divided by .." "NoError,Error" bitfld.long 0x00 0.--1. " AES ,ADMA Error State his field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates '10' because ADMA never stops in this state. - . - . - . - ." "Syssdr,linkDesc,Reserved,TransData" group.long 0x258++0x3 line.long 0x00 "MMCHS_ADMASAL,ADMA System address Low bits" hexmask.long 0x00 0.--31. 1. " ADMA_A32B ,ADMA System address 32 bits.This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32-bit of this register. At the start of ADMA, the Host Driver shall set start address of the .." rgroup.long 0x2FC++0x3 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number This status indicates the Standard SD Host Controller Specification Version. The upper and lower 4-bits indicate the version. - . - ." bitfld.long 0x00 0. " SIS ,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_SYSCTL[24] SRA), the interrupt signal sh.." "0,1" tree.end tree "MMCHS2" base ad:0x480B4000 width 20. rgroup.long 0x0++0x3 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision." rgroup.long 0x4++0x3 line.long 0x00 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." bitfld.long 0x00 6. " RETMODE ,Retention mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET. - . - ." "Retention_mode_disabled,Retention_mode_enabled" bitfld.long 0x00 2.--5. " MEM_SIZE ,Memory size for FIFO buffer: - . - . - . - ." "0,MEM_512,MEM_1024,3,MEM_2048,5,6,7,MEM_4096,9,10,11,12,13,14,15" bitfld.long 0x00 1. " MERGE_MEM ,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing. - . - ." "TwoMemBuffer,SingleMemBuffer" textline " " bitfld.long 0x00 0. " MADMA_EN ,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA. - . - ." "NoMasterDMA,SupportADMA" group.long 0x10++0x3 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. - . - . - . - ." "ForceStandby,NoStandby,SmartStandby,SmartStandbyWakeUp" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS. - . - ." "EmuEn,EmuDis" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing" group.long 0x110++0x3 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface." bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a 0. - . - . - . - ..." "Force,NoIdle,Smart,SmartWake" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock - . - . - . - ." "None,OCP,Func,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management - . - . - . - ." "Force,NoIdle,Smart,SmartWake" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control - . - ." "Disabled,Enable" bitfld.long 0x00 1. " SOFTRESET ,Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0. - . - . - . - ." "NoReset_r_/_St_un_w,OnReset_r_/_St_rst_w" bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy - . - ." "Off,On" rgroup.long 0x114++0x3 line.long 0x00 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring. - . - ." "OnGoing,Done" group.long 0x124++0x3 line.long 0x00 "MMCHS_CSRE,Card status response error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the correspond.." hexmask.long 0x00 0.--31. 1. " CSRE ,Card status response error" group.long 0x128++0x3 line.long 0x00 "MMCHS_SYSTEST,System Test register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register wi.." bitfld.long 0x00 16. " OBI ,Out-Of-Band Interrupt (OBI) data value - . - ." "LowLevel,HighLevel" bitfld.long 0x00 15. " SDCD ,Card detect input signal (SDCD) data value - . - ." "DrivenLow,DrivenHigh" bitfld.long 0x00 14. " SDWP ,Write protect input signal (SDWP) data value - . - ." "DrivenLow,DrivenHigh" textline " " bitfld.long 0x00 13. " WAKD ,Wake request output signal data value - . - . - . - ." "Zero_r_/_DrivenLow_w,DrivenHIgh_w_/_One_r" bitfld.long 0x00 12. " SSB ,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT). - . - . - . - ." "Clear_w_/_Zero_r,SetThemAll_w_/_One_r" bitfld.long 0x00 11. " D7D ,DAT7 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 10. " D6D ,DAT6 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 9. " D5D ,DAT5 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 8. " D4D ,DAT4 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 7. " D3D ,DAT3 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,One_r_/_DriveHigh_w" bitfld.long 0x00 6. " D2D ,DAT2 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" bitfld.long 0x00 5. " D1D ,DAT1 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 4. " D0D ,DAT0 input/output signal data value - . - . - . - ." "Zero_r_/_Zero_w,One_r_/_DriveHigh_w" bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" textline " " bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value - . - . - . - ." "DrivenLow_w_/_Zero_r,DrivenHigh_w_/_One_r" group.long 0x12C++0x3 line.long 0x00 "MMCHS_CON,Configuration register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and.." bitfld.long 0x00 21. " SDMA_LNE ,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data writ.." "EarlyDeAssert,LateDeAssert" bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).Thi.." "MasterDMADis,MasterDMAEn" bitfld.long 0x00 19. " DDR ,Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Da.." "NormalMode,DDRMode" textline " " bitfld.long 0x00 18. " BOOT_CF0 ,Boot status supported: This register is set when the CMD line need to be forced to 0 for a boot sequence. CMD line is driven to 0 after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer .." "NoCMDForce_/_CMDReleased,CMDForced_/_CMDForceReq" bitfld.long 0x00 17. " BOOT_ACK ,Book acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated. - . - ." "BootNoAck,BootAck" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only .." "Autogating,FreeRunning" textline " " bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also.." "Disable,Enable" bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration.." "NormalMode,OBintMode" bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system inte.." "ActiveHigh,ActiveLow" textline " " bitfld.long 0x00 12. " CEATA ,CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is use to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features. - . - ." "NormalMode,CEATAMode" bitfld.long 0x00 11. " CTPL ,Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO car.." "MMC_SD,SDIO" bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the syst.." "FilterLevel0,FilterLevel1,FilterLevel2,FilterLevel3" textline " " bitfld.long 0x00 8. " WPP ,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the typ.." "ActiveHigh,ActiveLow" bitfld.long 0x00 7. " CDP ,Card detect polarity All cards This bit selects the active level of the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type.." "ActiveHigh,ActiveLow" bitfld.long 0x00 6. " MIT ,MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detectio.." "CTO,No_CTO" textline " " bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the.." "1_4BitMode,8BitMode" bitfld.long 0x00 4. " MODE ,Mode select All cards These bits select between Functional mode and SYSTEST mode. - . - ." "FUNC,SYSTEST" bitfld.long 0x00 3. " STR ,Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a.." "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section .." "NoHostResp,HostResp" bitfld.long 0x00 1. " INIT ,Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock .." "NoInit,InitStream" bitfld.long 0x00 0. " OD ,Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typicall.." "NoOpenDrain,OpenDrain" group.long 0x130++0x3 line.long 0x00 "MMCHS_PWCNT,Power counter register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." hexmask.long.word 0x00 0.--15. 1. " PWRCNT ,Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued. - . - . - . - . - ." group.long 0x204++0x3 line.long 0x00 "MMCHS_BLK,Transfer Length Configuration register [11:0] BLEN is the block size register. [31:16] NBLK is the block count register. This register shall be used for any card." hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[1] BCE) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note:.." hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issu.." group.long 0x208++0x3 line.long 0x00 "MMCHS_ARG,Command argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exce.." hexmask.long 0x00 0.--31. 1. " ARG ,Command argument bits [31:0]" group.long 0x20C++0x3 line.long 0x00 "MMCHS_CMD,Command and transfer mode register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers duri.." bitfld.long 0x00 24.--29. " INDX ,Command index Binary encoded value from 0 to 63 specifying the command number send to card - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ..." "CMD0_or_ACMD0,CMD1_or_ACMD1,CMD2_or_ACMD2,CMD3_or_ACMD3,CMD4_or_ACMD4,CMD5_or_ACMD5,CMD6_or_ACMD6,CMD7_or_ACMD7,CMD8_or_ACMD8,CMD9_or_ACMD9,CMD10_or_ACMD10,CMD11_or_ACMD11,CMD12_or_ACMD12,CMD13_or_ACMD13,CMD14_or_ACMD14,CMD15_or_ACMD15,CMD16_or_ACMD16,CMD17_or_ACMD17,CMD18_or_ACMD18,CMD19_or_ACMD19,CMD20_or_ACMD20,CMD21_or_ACMD21,CMD22_or_ACMD22,CMD23_or_ACMD23,CMD24_or_ACMD24,CMD25_or_ACMD25,CMD26_or_ACMD26,CMD27_or_ACMD27,CMD28_or_ACMD28,CMD29_or_ACMD29,CMD30_or_ACMD30,CMD31_or_ACMD31,CMD32_or_ACMD32,CMD33_or_ACMD33,CMD34_or_ACMD34,CMD35_or_ACMD35,CMD36_or_ACMD36,CMD37_or_ACMD37,CMD38_or_ACMD38,CMD39_or_ACMD39,CMD40_or_ACMD40,CMD41_or_ACMD41,CMD42_or_ACMD42,CMD43_or_ACMD43,CMD44_or_ACMD44,CMD45_or_ACMD45,CMD46_or_ACMD46,CMD47_or_ACMD47,CMD48_or_ACMD48,CMD49_or_ACMD49,CMD50_or_ACMD50,CMD51_or_ACMD51,CMD52_or_ACMD52,CMD53_or_ACMD53,CMD54_or_ACMD54,CMD55_or_ACMD55,CMD56_or_ACMD56,CMD57_or_ACMD57,CMD58_or_ACMD58,CMD59_or_ACMD59,CMD60_or_ACMD60,CMD61_or_ACMD61,CMD62_or_ACMD62,CMD63_or_ACMD63" bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type This register specifies three types of special command: Suspend, Resume and Abort. These bits shall be set to 00b for all other commands. - . - . - . - ." "Normal,Suspend,Resume,Abort" bitfld.long 0x00 21. " DP ,Data present select This register indicates that data is present and DAT line shall be used. It must be set to 0 in the following conditions: - command using only CMD line - command with no data transfer but using .." "NoData,Data" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. If the index is not the same in the response as in the command, it.." "Nocheck,Check" bitfld.long 0x00 19. " CCCE ,Command CRC check enable This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. If an error is detected, it is reported as a command CRC .." "NoCheck,Check" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type This bits defines the response type of the command - . - . - . - ." "Norsp,Lght36,Lght48,Lght48b" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit shall be set to 0. - . - ." "sgleblk,multiblk" bitfld.long 0x00 4. " DDIR ,Data transfer Direction Select This bit defines either data transfer will be a read or a write. - . - ." "Write,Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable SDIO does not support this feature. When this bit is set to 1, the host controller issues a CMD12 automatically after the transfer completion of the last block. The Host Driver shall not set thi.." "Disable,Enable" textline " " bitfld.long 0x00 1. " BCE ,Block Count Enable Multiple block transfers only. This bit is used to enable the block count register (MMCHS_BLK[31:16] NBLK). When Block Count is disabled (MMCHS_CMD[1] BCE is set to 0) in Multiple block transfers (MMCHS_CMD[5] MSBS is s.." "Disable,Enable" bitfld.long 0x00 0. " DE ,DMA Enable This bit is used to enable DMA mode for host data access. - . - ." "Disable,Enable" rgroup.long 0x210++0x3 line.long 0x00 "MMCHS_RSP10,Command response[31:0] Register This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6" hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response [31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response [15:0]" rgroup.long 0x214++0x3 line.long 0x00 "MMCHS_RSP32,Command response[63:32] Register This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP3 ,Command Response [63:48]" hexmask.long.word 0x00 0.--15. 1. " RSP2 ,Command Response [47:32]" rgroup.long 0x218++0x3 line.long 0x00 "MMCHS_RSP54,Command response[95:64] Register This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP5 ,Command Response [95:80]" hexmask.long.word 0x00 0.--15. 1. " RSP4 ,Command Response [79:64]" rgroup.long 0x21C++0x3 line.long 0x00 "MMCHS_RSP76,Command response[127:96] Register This 32-bit register holds bits positions [127:96] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP7 ,Command Response [127:112]" hexmask.long.word 0x00 0.--15. 1. " RSP6 ,Command Response [111:96]" group.long 0x220++0x3 line.long 0x00 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers." hexmask.long 0x00 0.--31. 1. " DATA ,Data Register [31:0] In functional mode (MMCHS_CON[4] MODE set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[11] BRE), otherwise a bad access (MMCHS_S.." rgroup.long 0x224++0x3 line.long 0x00 "MMCHS_PSTATE,Present state register The Host can get status of the Host Controller from this 32-bit read only register." bitfld.long 0x00 24. " CLEV ,CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time. - . - ." "Zero,One" bitfld.long 0x00 20.--23. " DLEV ,DAT[3:0] line signal level DAT[3] =&gt; bit 23 DAT[2] =&gt; bit 22 DAT[1] =&gt; bit 21 DAT[0] =&gt; bit 20 This status is used to check DAT line level to recover from errors, and for debugging. .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (SDWP) level. The value of this register after reset depends on the protect input pin (SDWP) level at that time.." "zero,one" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level This bit reflects the inverse value of the card detect input pin (SDCD), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTATE[17] CSS) is set to 1. Use of this bit is lim.." "zero,one" bitfld.long 0x00 17. " CSS ,Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[18] CDPL). Debouncing is performed on the card detect input pin (SDCD) to detect card stabi.." "Debouncing,Stable" bitfld.long 0x00 16. " CINS ,Card inserted This bit is the debounced value of the card detect input pin (SDCD). An inactive to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt (MMCHS_STAT[6] CINS). A .." "zero,one" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[11:0] BLEN has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from.." "RdDisable,RdEnable" bitfld.long 0x00 10. " BWE ,Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data. - . - ." "WrDisable,WrEnable" bitfld.long 0x00 9. " RTA ,Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block.." "NoTransfer,Transfer" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block gap request. This bit is set to 0 whe.." "NoTransfer,Transfer" bitfld.long 0x00 2. " DLA ,DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue reque.." "zero,one" bitfld.long 0x00 1. " DATI ,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[2] DLA) or Read transfer is active (MMCHS_PSTATE[9] RTA) or when a command with busy is issued. This bit prevents the .." "Cmden,Cmddis" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0.." "Cmden,Cmddis" group.long 0x228++0x3 line.long 0x00 "MMCHS_HCTL,Control register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" bitfld.long 0x00 27. " OBWE ,Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). The write to this register is ignored when M.." "disable,enable" bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" textline " " bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 19. " IBG ,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit shou.." "Itdiable,Itenable" bitfld.long 0x00 18. " RWC ,Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[16] SBGR) generates a read wait per.." "NoRW,RW" textline " " bitfld.long 0x00 17. " CR ,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[16] SBGR). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when tr.." "None,Restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[17] CR) or during a suspend/resume sequence. In case o.." "Transfer,Stpblk" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[26:24]) before starting a transfer. - ..." "0,1,2,3,4,1V8,3V0,3V3" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[11:9] SDVS). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in th.." "Pwroff,Pwron" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interru.." "SDCDSel,CDTLSel" bitfld.long 0x00 6. " CDTL ,Card Detect Test Level: This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. - . - ." "NoCard,CardIns" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This regi.." "Reserved,Reserved1,ADMA2,Reserved2" bitfld.long 0x00 2. " HSPE ,High Speed Enable: Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is set to 0 (default), the Host Controller outputs CMD line and DAT lines at t.." "NormalSpeed,HighSpeed" bitfld.long 0x00 1. " DTW ,Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration regi.." "1_BitMode,4_BitMode" textline " " bitfld.long 0x00 0. " LED ,Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored." "0,1" group.long 0x22C++0x3 line.long 0x00 "MMCHS_SYSCTL,SD system control register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" bitfld.long 0x00 26. " SRD ,Software reset for DAT line. This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see , . DAT finite state machine in both clock domain are also reset. The following registers a.." "Work,Reset" bitfld.long 0x00 25. " SRC ,Software reset for CMD line For more information about SRC bit manipulation, see , . This bit is set to 1 for reset and released to 0 when completed. CMD finite state-machine in both clock domain are also reset..." "Work,Reset" bitfld.long 0x00 24. " SRA ,Software reset for all This bit is set to 1 for reset, and released to 0 when completed. This reset affects the entire host controller except for the card detection circuit and capabilities registers. - . - ." "Work,Reset" textline " " bitfld.long 0x00 16.--19. " DTO ,Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bit field based on - the maximum read access time (NAC) (Refer to the SD Specifica.." "1stDTO,2ndDTO,2,3,4,5,6,7,8,9,10,11,12,13,15thDTO,Rsvd" hexmask.long.word 0x00 6.--15. 1. " CLKD ,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO). - . - . - . - . - ." bitfld.long 0x00 2. " CEN ,Clock enable This bit controls if the clock is provided to the card or not. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " ICS ,Internal clock stable (status) This bit indicates either the internal clock is stable or not. - . - ." "NotReady,Ready" bitfld.long 0x00 0. " ICE ,Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface .." "Stop,Oscillate" group.long 0x230++0x3 line.long 0x00 "MMCHS_STAT,Interrupt status register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" bitfld.long 0x00 29. " BADA ,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[11] BRE =.." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 28. " CERR ,Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An erro.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 25. " ADMAE ,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller gener.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 24. " ACE ,Auto CMD12 error This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1. - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 23. " CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB ,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 21. " DCRC ,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command. - . - ..." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 20. " DTO ,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout - . - . - ..." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 19. " CIE ,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[20] CICE register. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 18. " CEB ,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 17. " CCRC ,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 16. " CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock .." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 15. " ERRI ,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[24:15]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit a.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 10. " BSR ,Boot status received interrupt This bit is set automatically when MMCHS_CON[18] BOOT_CF0 is set 0x0 or 0x1 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 9. " OBI ,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[14] OBIE is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[13] OBIP. This interrupt is .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 8. " CIRQ ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 7. " CREM ,Card removal This bit is set automatically when MMCHS_PSTATE[16] CINS changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 6. " CINS ,Card insertion This bit is set automatically when MMCHS_PSTATE[16] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 5. " BRR ,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[11:0] BLEN is completely written in the buffer. It indicates that the m.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 4. " BWR ,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[11:0] BLEN. It indicates tha.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 3. " DMA ,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 2. " BGE ,Block gap event When a stop at block gap is requested (MMCHS_HCTL[16] SBGR), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap.." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 1. " TC ,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[16] SBGR). In Read mode: This bit is automatic.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 0. " CC ,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[0] CMDI) If the command is a type for which no response is expected, then the command complete interrupt is generate.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" group.long 0x234++0x3 line.long 0x00 "MMCHS_IE,Interrupt SD enable register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" bitfld.long 0x00 29. " BADA_ENABLE ,Bad access to data space Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_ENABLE ,Card error interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_ENABLE ,ADMA error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_ENABLE ,Auto CMD12 error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_ENABLE ,Data end bit error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_ENABLE ,Data CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_ENABLE ,Data timeout error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_ENABLE ,Command index error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_ENABLE ,Command end bit error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_ENABLE ,Command CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_ENABLE ,Command timeout error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_ENABLE ,Boot status interrupt Enable A write to this register when MMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_ENABLE ,Out-of-Band interrupt Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_ENABLE ,Card interrupt Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is .." "Masked,Enabled" bitfld.long 0x00 7. " CREM_ENABLE ,Card removal Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_ENABLE ,Card insertion Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_ENABLE ,Buffer Read Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_ENABLE ,Buffer Write Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_ENABLE ,DMA interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_ENABLE ,Block Gap Event Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_ENABLE ,Transfer completed Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_ENABLE ,Command completed Interrupt Enable - . - ." "Masked,Enabled" group.long 0x238++0x3 line.long 0x00 "MMCHS_ISE,Interrupt signal enable register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" bitfld.long 0x00 29. " BADA_SIGEN ,Bad access to data space signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_SIGEN ,Card error interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_SIGEN ,ADMA error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_SIGEN ,Auto CMD12 error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_SIGEN ,Data end bit error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_SIGEN ,Data CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_SIGEN ,Data timeout error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_SIGEN ,Command index error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_SIGEN ,Command end bit error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_SIGEN ,Command CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_SIGEN ,Command timeout error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_SIGEN ,Boot status signal status EnableA write to this register whenMMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_SIGEN ,Out-Of-Band Interrupt signal status Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_SIGEN ,Card interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 7. " CREM_SIGEN ,Card removal signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_SIGEN ,Card insertion signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_SIGEN ,Buffer Read Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_SIGEN ,Buffer Write Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_SIGEN ,DMA interrupt Signal status enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_SIGEN ,Black Gap Event signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_SIGEN ,Transfer completed signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_SIGEN ,Command completed signal status Enable - . - ." "Masked,Enabled" rgroup.long 0x23C++0x3 line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this register when an Auto CMD12 Error interrupt occurs. This register is valid only when Auto CMD12 is e.." bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error If this bit is set to 1, it means that pending command is not executed due to Auto CMD12 error : ACEB, ACCE, ACTO or ACNE. - . - ." "NoErr,CmdNI" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted. This bit depends on the command index check enable (MMCHS_CMD[20] CICE). .." "NoErr,Err" bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error This bit is set to 1 when detecting a 0 at the end bit position of auto CMD12 command response. - . - ." "NoErr,Err" textline " " bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error This bit is automatically set to 1 when a CRC7 error is detected in the auto CMD12 command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - ." "NoErr,Err" bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error This bit is set to 1 if no response is received within 64 clock cycles from the end bit of the auto CMD12 command. - . - ." "NoErr,TimeOut" bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before Auto CMD12 starts. - . - ." "Exe,NotExe" group.long 0x240++0x3 line.long 0x00 "MMCHS_CAPA,Capabilities register This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x00 28. " BIT64 ,64-bit system bus support: Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. - . - ." "SysAddr32b,SysAddr64b" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register i.." "1V8_NotSup_r_/_St_1V8NotSup_w,St_1V8Sup_w_/_1V8_Sup_r" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized.." "St_3V0NotSup_w_/_3V0_NotSup_r,3V0_Sup_r_/_St_3V0Sup_w" textline " " bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized b.." "St_3V3NotSup_w_/_3V3_NotSup_r,St_3V3Sup_w_/_3V3_Sup_r" bitfld.long 0x00 23. " SRS ,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports suspend/resume functionality. - . - ." "NotSupported,Supported" bitfld.long 0x00 22. " DS ,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly. - . - ." "NotSupported,Supported" textline " " bitfld.long 0x00 21. " HSS ,High-speed support This bit indicates that the host controller supports high-speed operations and can supply an up-to maximum card frequency. - . - ." "NotSupported,Supported" bitfld.long 0x00 19. " AD2S ,ADMA2 support: This bit indicates whether the host controller is capable of using ADMA2. It depends on setting of generic parameter MMCHS_HL_HWINFO[0] MADMA_EN - . - ." "ADMA2NotSupported,ADMA2Supported" bitfld.long 0x00 16.--17. " MBL ,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 by.." "512,1024,2048,3" textline " " bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " TCU ,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - . - ." "MHz,KHz" bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x248++0x3 line.long 0x00 "MMCHS_CUR_CAPA,Maximum current capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a .." hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V - ." hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V - ." hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V - ." group.long 0x250++0x3 line.long 0x00 "MMCHS_FE,Force Event Register for Error Interrupt status The force Event Register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will.." bitfld.long 0x00 29. " FE_BADA ,Force Event Bad access to data space - . - ." "NoAction,IntForced" bitfld.long 0x00 28. " FE_CERR ,Force Event Card error - . - ." "NoAction,IntForced" bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA Error: - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 23. " FE_CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " FE_DEB ,Force Event Data End Bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error - . - ." "NoAction,IntForced" bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 16. " FE_CTO ,Command Timeout Error - This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. . - . - For commands that reply within 5 clock cycles - the timeout is still .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 4. " FE_ACIE ,Force Event Auto CMD12 index error - . - ." "NoAction,IntForced" bitfld.long 0x00 3. " FE_ACEB ,Force Event Auto CMD12 end bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 2. " FE_ACCE ,Force Event Auto CMD12 CRC error - . - ." "NoAction,IntForced" bitfld.long 0x00 1. " FE_ACTO ,Force Event Auto CMD12 timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 0. " FE_ACNE ,Force Event Auto CMD12 not executed - . - ." "NoAction,IntForced" group.long 0x254++0x3 line.long 0x00 "MMCHS_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor." bitfld.long 0x00 2. " LME ,ADMA Length Mismatch Error: (1) While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. (2) Total data length can not be divided by .." "NoError,Error" bitfld.long 0x00 0.--1. " AES ,ADMA Error State his field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates '10' because ADMA never stops in this state. - . - . - . - ." "Syssdr,linkDesc,Reserved,TransData" group.long 0x258++0x3 line.long 0x00 "MMCHS_ADMASAL,ADMA System address Low bits" hexmask.long 0x00 0.--31. 1. " ADMA_A32B ,ADMA System address 32 bits.This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32-bit of this register. At the start of ADMA, the Host Driver shall set start address of the .." rgroup.long 0x2FC++0x3 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number This status indicates the Standard SD Host Controller Specification Version. The upper and lower 4-bits indicate the version. - . - ." bitfld.long 0x00 0. " SIS ,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_SYSCTL[24] SRA), the interrupt signal sh.." "0,1" tree.end tree.end tree.open "MMCHS3" tree "MMCHS3" base ad:0x480AD000 width 20. rgroup.long 0x0++0x3 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision." rgroup.long 0x4++0x3 line.long 0x00 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." bitfld.long 0x00 6. " RETMODE ,Retention mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET. - . - ." "Retention_mode_disabled,Retention_mode_enabled" bitfld.long 0x00 2.--5. " MEM_SIZE ,Memory size for FIFO buffer: - . - . - . - ." "0,MEM_512,MEM_1024,3,MEM_2048,5,6,7,MEM_4096,9,10,11,12,13,14,15" bitfld.long 0x00 1. " MERGE_MEM ,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing. - . - ." "TwoMemBuffer,SingleMemBuffer" textline " " bitfld.long 0x00 0. " MADMA_EN ,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA. - . - ." "NoMasterDMA,SupportADMA" group.long 0x10++0x3 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. - . - . - . - ." "ForceStandby,NoStandby,SmartStandby,SmartStandbyWakeUp" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS. - . - ." "EmuEn,EmuDis" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing" group.long 0x110++0x3 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface." bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a 0. - . - . - . - ..." "Force,NoIdle,Smart,SmartWake" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock - . - . - . - ." "None,OCP,Func,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management - . - . - . - ." "Force,NoIdle,Smart,SmartWake" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control - . - ." "Disabled,Enable" bitfld.long 0x00 1. " SOFTRESET ,Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0. - . - . - . - ." "NoReset_r_/_St_un_w,OnReset_r_/_St_rst_w" bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy - . - ." "Off,On" rgroup.long 0x114++0x3 line.long 0x00 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring. - . - ." "OnGoing,Done" group.long 0x124++0x3 line.long 0x00 "MMCHS_CSRE,Card status response error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the correspond.." hexmask.long 0x00 0.--31. 1. " CSRE ,Card status response error" group.long 0x128++0x3 line.long 0x00 "MMCHS_SYSTEST,System Test register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register wi.." bitfld.long 0x00 16. " OBI ,Out-Of-Band Interrupt (OBI) data value - . - ." "LowLevel,HighLevel" bitfld.long 0x00 15. " SDCD ,Card detect input signal (SDCD) data value - . - ." "DrivenLow,DrivenHigh" bitfld.long 0x00 14. " SDWP ,Write protect input signal (SDWP) data value - . - ." "DrivenLow,DrivenHigh" textline " " bitfld.long 0x00 13. " WAKD ,Wake request output signal data value - . - . - . - ." "Zero_r_/_DrivenLow_w,DrivenHIgh_w_/_One_r" bitfld.long 0x00 12. " SSB ,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT). - . - . - . - ." "Clear_w_/_Zero_r,SetThemAll_w_/_One_r" bitfld.long 0x00 11. " D7D ,DAT7 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 10. " D6D ,DAT6 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 9. " D5D ,DAT5 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 8. " D4D ,DAT4 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 7. " D3D ,DAT3 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,One_r_/_DriveHigh_w" bitfld.long 0x00 6. " D2D ,DAT2 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" bitfld.long 0x00 5. " D1D ,DAT1 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 4. " D0D ,DAT0 input/output signal data value - . - . - . - ." "Zero_r_/_Zero_w,One_r_/_DriveHigh_w" bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" textline " " bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value - . - . - . - ." "DrivenLow_w_/_Zero_r,DrivenHigh_w_/_One_r" group.long 0x12C++0x3 line.long 0x00 "MMCHS_CON,Configuration register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and.." bitfld.long 0x00 21. " SDMA_LNE ,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data writ.." "EarlyDeAssert,LateDeAssert" bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).Thi.." "MasterDMADis,MasterDMAEn" bitfld.long 0x00 19. " DDR ,Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Da.." "NormalMode,DDRMode" textline " " bitfld.long 0x00 18. " BOOT_CF0 ,Boot status supported: This register is set when the CMD line need to be forced to 0 for a boot sequence. CMD line is driven to 0 after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer .." "NoCMDForce_/_CMDReleased,CMDForced_/_CMDForceReq" bitfld.long 0x00 17. " BOOT_ACK ,Book acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated. - . - ." "BootNoAck,BootAck" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only .." "Autogating,FreeRunning" textline " " bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also.." "Disable,Enable" bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration.." "NormalMode,OBintMode" bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system inte.." "ActiveHigh,ActiveLow" textline " " bitfld.long 0x00 12. " CEATA ,CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is use to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features. - . - ." "NormalMode,CEATAMode" bitfld.long 0x00 11. " CTPL ,Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO car.." "MMC_SD,SDIO" bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the syst.." "FilterLevel0,FilterLevel1,FilterLevel2,FilterLevel3" textline " " bitfld.long 0x00 8. " WPP ,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the typ.." "ActiveHigh,ActiveLow" bitfld.long 0x00 7. " CDP ,Card detect polarity All cards This bit selects the active level of the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type.." "ActiveHigh,ActiveLow" bitfld.long 0x00 6. " MIT ,MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detectio.." "CTO,No_CTO" textline " " bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the.." "1_4BitMode,8BitMode" bitfld.long 0x00 4. " MODE ,Mode select All cards These bits select between Functional mode and SYSTEST mode. - . - ." "FUNC,SYSTEST" bitfld.long 0x00 3. " STR ,Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a.." "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section .." "NoHostResp,HostResp" bitfld.long 0x00 1. " INIT ,Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock .." "NoInit,InitStream" bitfld.long 0x00 0. " OD ,Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typicall.." "NoOpenDrain,OpenDrain" group.long 0x130++0x3 line.long 0x00 "MMCHS_PWCNT,Power counter register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." hexmask.long.word 0x00 0.--15. 1. " PWRCNT ,Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued. - . - . - . - . - ." group.long 0x204++0x3 line.long 0x00 "MMCHS_BLK,Transfer Length Configuration register [11:0] BLEN is the block size register. [31:16] NBLK is the block count register. This register shall be used for any card." hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[1] BCE) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note:.." hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issu.." group.long 0x208++0x3 line.long 0x00 "MMCHS_ARG,Command argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exce.." hexmask.long 0x00 0.--31. 1. " ARG ,Command argument bits [31:0]" group.long 0x20C++0x3 line.long 0x00 "MMCHS_CMD,Command and transfer mode register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers duri.." bitfld.long 0x00 24.--29. " INDX ,Command index Binary encoded value from 0 to 63 specifying the command number send to card - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ..." "CMD0_or_ACMD0,CMD1_or_ACMD1,CMD2_or_ACMD2,CMD3_or_ACMD3,CMD4_or_ACMD4,CMD5_or_ACMD5,CMD6_or_ACMD6,CMD7_or_ACMD7,CMD8_or_ACMD8,CMD9_or_ACMD9,CMD10_or_ACMD10,CMD11_or_ACMD11,CMD12_or_ACMD12,CMD13_or_ACMD13,CMD14_or_ACMD14,CMD15_or_ACMD15,CMD16_or_ACMD16,CMD17_or_ACMD17,CMD18_or_ACMD18,CMD19_or_ACMD19,CMD20_or_ACMD20,CMD21_or_ACMD21,CMD22_or_ACMD22,CMD23_or_ACMD23,CMD24_or_ACMD24,CMD25_or_ACMD25,CMD26_or_ACMD26,CMD27_or_ACMD27,CMD28_or_ACMD28,CMD29_or_ACMD29,CMD30_or_ACMD30,CMD31_or_ACMD31,CMD32_or_ACMD32,CMD33_or_ACMD33,CMD34_or_ACMD34,CMD35_or_ACMD35,CMD36_or_ACMD36,CMD37_or_ACMD37,CMD38_or_ACMD38,CMD39_or_ACMD39,CMD40_or_ACMD40,CMD41_or_ACMD41,CMD42_or_ACMD42,CMD43_or_ACMD43,CMD44_or_ACMD44,CMD45_or_ACMD45,CMD46_or_ACMD46,CMD47_or_ACMD47,CMD48_or_ACMD48,CMD49_or_ACMD49,CMD50_or_ACMD50,CMD51_or_ACMD51,CMD52_or_ACMD52,CMD53_or_ACMD53,CMD54_or_ACMD54,CMD55_or_ACMD55,CMD56_or_ACMD56,CMD57_or_ACMD57,CMD58_or_ACMD58,CMD59_or_ACMD59,CMD60_or_ACMD60,CMD61_or_ACMD61,CMD62_or_ACMD62,CMD63_or_ACMD63" bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type This register specifies three types of special command: Suspend, Resume and Abort. These bits shall be set to 00b for all other commands. - . - . - . - ." "Normal,Suspend,Resume,Abort" bitfld.long 0x00 21. " DP ,Data present select This register indicates that data is present and DAT line shall be used. It must be set to 0 in the following conditions: - command using only CMD line - command with no data transfer but using .." "NoData,Data" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. If the index is not the same in the response as in the command, it.." "Nocheck,Check" bitfld.long 0x00 19. " CCCE ,Command CRC check enable This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. If an error is detected, it is reported as a command CRC .." "NoCheck,Check" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type This bits defines the response type of the command - . - . - . - ." "Norsp,Lght36,Lght48,Lght48b" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit shall be set to 0. - . - ." "sgleblk,multiblk" bitfld.long 0x00 4. " DDIR ,Data transfer Direction Select This bit defines either data transfer will be a read or a write. - . - ." "Write,Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable SDIO does not support this feature. When this bit is set to 1, the host controller issues a CMD12 automatically after the transfer completion of the last block. The Host Driver shall not set thi.." "Disable,Enable" textline " " bitfld.long 0x00 1. " BCE ,Block Count Enable Multiple block transfers only. This bit is used to enable the block count register (MMCHS_BLK[31:16] NBLK). When Block Count is disabled (MMCHS_CMD[1] BCE is set to 0) in Multiple block transfers (MMCHS_CMD[5] MSBS is s.." "Disable,Enable" bitfld.long 0x00 0. " DE ,DMA Enable This bit is used to enable DMA mode for host data access. - . - ." "Disable,Enable" rgroup.long 0x210++0x3 line.long 0x00 "MMCHS_RSP10,Command response[31:0] Register This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6" hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response [31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response [15:0]" rgroup.long 0x214++0x3 line.long 0x00 "MMCHS_RSP32,Command response[63:32] Register This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP3 ,Command Response [63:48]" hexmask.long.word 0x00 0.--15. 1. " RSP2 ,Command Response [47:32]" rgroup.long 0x218++0x3 line.long 0x00 "MMCHS_RSP54,Command response[95:64] Register This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP5 ,Command Response [95:80]" hexmask.long.word 0x00 0.--15. 1. " RSP4 ,Command Response [79:64]" rgroup.long 0x21C++0x3 line.long 0x00 "MMCHS_RSP76,Command response[127:96] Register This 32-bit register holds bits positions [127:96] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP7 ,Command Response [127:112]" hexmask.long.word 0x00 0.--15. 1. " RSP6 ,Command Response [111:96]" group.long 0x220++0x3 line.long 0x00 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers." hexmask.long 0x00 0.--31. 1. " DATA ,Data Register [31:0] In functional mode (MMCHS_CON[4] MODE set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[11] BRE), otherwise a bad access (MMCHS_S.." rgroup.long 0x224++0x3 line.long 0x00 "MMCHS_PSTATE,Present state register The Host can get status of the Host Controller from this 32-bit read only register." bitfld.long 0x00 24. " CLEV ,CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time. - . - ." "Zero,One" bitfld.long 0x00 20.--23. " DLEV ,DAT[3:0] line signal level DAT[3] =&gt; bit 23 DAT[2] =&gt; bit 22 DAT[1] =&gt; bit 21 DAT[0] =&gt; bit 20 This status is used to check DAT line level to recover from errors, and for debugging. .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (SDWP) level. The value of this register after reset depends on the protect input pin (SDWP) level at that time.." "zero,one" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level This bit reflects the inverse value of the card detect input pin (SDCD), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTATE[17] CSS) is set to 1. Use of this bit is lim.." "zero,one" bitfld.long 0x00 17. " CSS ,Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[18] CDPL). Debouncing is performed on the card detect input pin (SDCD) to detect card stabi.." "Debouncing,Stable" bitfld.long 0x00 16. " CINS ,Card inserted This bit is the debounced value of the card detect input pin (SDCD). An inactive to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt (MMCHS_STAT[6] CINS). A .." "zero,one" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[11:0] BLEN has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from.." "RdDisable,RdEnable" bitfld.long 0x00 10. " BWE ,Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data. - . - ." "WrDisable,WrEnable" bitfld.long 0x00 9. " RTA ,Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block.." "NoTransfer,Transfer" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block gap request. This bit is set to 0 whe.." "NoTransfer,Transfer" bitfld.long 0x00 2. " DLA ,DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue reque.." "zero,one" bitfld.long 0x00 1. " DATI ,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[2] DLA) or Read transfer is active (MMCHS_PSTATE[9] RTA) or when a command with busy is issued. This bit prevents the .." "Cmden,Cmddis" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0.." "Cmden,Cmddis" group.long 0x228++0x3 line.long 0x00 "MMCHS_HCTL,Control register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" bitfld.long 0x00 27. " OBWE ,Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). The write to this register is ignored when M.." "disable,enable" bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" textline " " bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 19. " IBG ,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit shou.." "Itdiable,Itenable" bitfld.long 0x00 18. " RWC ,Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[16] SBGR) generates a read wait per.." "NoRW,RW" textline " " bitfld.long 0x00 17. " CR ,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[16] SBGR). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when tr.." "None,Restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[17] CR) or during a suspend/resume sequence. In case o.." "Transfer,Stpblk" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[26:24]) before starting a transfer. - ..." "0,1,2,3,4,1V8,3V0,3V3" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[11:9] SDVS). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in th.." "Pwroff,Pwron" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interru.." "SDCDSel,CDTLSel" bitfld.long 0x00 6. " CDTL ,Card Detect Test Level: This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. - . - ." "NoCard,CardIns" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This regi.." "Reserved,Reserved1,ADMA2,Reserved2" bitfld.long 0x00 2. " HSPE ,High Speed Enable: Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is set to 0 (default), the Host Controller outputs CMD line and DAT lines at t.." "NormalSpeed,HighSpeed" bitfld.long 0x00 1. " DTW ,Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration regi.." "1_BitMode,4_BitMode" textline " " bitfld.long 0x00 0. " LED ,Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored." "0,1" group.long 0x22C++0x3 line.long 0x00 "MMCHS_SYSCTL,SD system control register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" bitfld.long 0x00 26. " SRD ,Software reset for DAT line. This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see , . DAT finite state machine in both clock domain are also reset. The following registers a.." "Work,Reset" bitfld.long 0x00 25. " SRC ,Software reset for CMD line For more information about SRC bit manipulation, see , . This bit is set to 1 for reset and released to 0 when completed. CMD finite state-machine in both clock domain are also reset..." "Work,Reset" bitfld.long 0x00 24. " SRA ,Software reset for all This bit is set to 1 for reset, and released to 0 when completed. This reset affects the entire host controller except for the card detection circuit and capabilities registers. - . - ." "Work,Reset" textline " " bitfld.long 0x00 16.--19. " DTO ,Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bit field based on - the maximum read access time (NAC) (Refer to the SD Specifica.." "1stDTO,2ndDTO,2,3,4,5,6,7,8,9,10,11,12,13,15thDTO,Rsvd" hexmask.long.word 0x00 6.--15. 1. " CLKD ,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO). - . - . - . - . - ." bitfld.long 0x00 2. " CEN ,Clock enable This bit controls if the clock is provided to the card or not. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " ICS ,Internal clock stable (status) This bit indicates either the internal clock is stable or not. - . - ." "NotReady,Ready" bitfld.long 0x00 0. " ICE ,Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface .." "Stop,Oscillate" group.long 0x230++0x3 line.long 0x00 "MMCHS_STAT,Interrupt status register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" bitfld.long 0x00 29. " BADA ,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[11] BRE =.." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 28. " CERR ,Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An erro.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 25. " ADMAE ,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller gener.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 24. " ACE ,Auto CMD12 error This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1. - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 23. " CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB ,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 21. " DCRC ,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command. - . - ..." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 20. " DTO ,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout - . - . - ..." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 19. " CIE ,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[20] CICE register. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 18. " CEB ,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 17. " CCRC ,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 16. " CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock .." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 15. " ERRI ,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[24:15]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit a.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 10. " BSR ,Boot status received interrupt This bit is set automatically when MMCHS_CON[18] BOOT_CF0 is set 0x0 or 0x1 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 9. " OBI ,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[14] OBIE is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[13] OBIP. This interrupt is .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 8. " CIRQ ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 7. " CREM ,Card removal This bit is set automatically when MMCHS_PSTATE[16] CINS changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 6. " CINS ,Card insertion This bit is set automatically when MMCHS_PSTATE[16] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 5. " BRR ,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[11:0] BLEN is completely written in the buffer. It indicates that the m.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 4. " BWR ,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[11:0] BLEN. It indicates tha.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 3. " DMA ,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 2. " BGE ,Block gap event When a stop at block gap is requested (MMCHS_HCTL[16] SBGR), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap.." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 1. " TC ,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[16] SBGR). In Read mode: This bit is automatic.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 0. " CC ,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[0] CMDI) If the command is a type for which no response is expected, then the command complete interrupt is generate.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" group.long 0x234++0x3 line.long 0x00 "MMCHS_IE,Interrupt SD enable register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" bitfld.long 0x00 29. " BADA_ENABLE ,Bad access to data space Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_ENABLE ,Card error interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_ENABLE ,ADMA error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_ENABLE ,Auto CMD12 error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_ENABLE ,Data end bit error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_ENABLE ,Data CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_ENABLE ,Data timeout error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_ENABLE ,Command index error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_ENABLE ,Command end bit error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_ENABLE ,Command CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_ENABLE ,Command timeout error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_ENABLE ,Boot status interrupt Enable A write to this register when MMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_ENABLE ,Out-of-Band interrupt Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_ENABLE ,Card interrupt Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is .." "Masked,Enabled" bitfld.long 0x00 7. " CREM_ENABLE ,Card removal Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_ENABLE ,Card insertion Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_ENABLE ,Buffer Read Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_ENABLE ,Buffer Write Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_ENABLE ,DMA interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_ENABLE ,Block Gap Event Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_ENABLE ,Transfer completed Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_ENABLE ,Command completed Interrupt Enable - . - ." "Masked,Enabled" group.long 0x238++0x3 line.long 0x00 "MMCHS_ISE,Interrupt signal enable register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" bitfld.long 0x00 29. " BADA_SIGEN ,Bad access to data space signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_SIGEN ,Card error interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_SIGEN ,ADMA error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_SIGEN ,Auto CMD12 error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_SIGEN ,Data end bit error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_SIGEN ,Data CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_SIGEN ,Data timeout error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_SIGEN ,Command index error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_SIGEN ,Command end bit error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_SIGEN ,Command CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_SIGEN ,Command timeout error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_SIGEN ,Boot status signal status EnableA write to this register whenMMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_SIGEN ,Out-Of-Band Interrupt signal status Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_SIGEN ,Card interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 7. " CREM_SIGEN ,Card removal signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_SIGEN ,Card insertion signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_SIGEN ,Buffer Read Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_SIGEN ,Buffer Write Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_SIGEN ,DMA interrupt Signal status enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_SIGEN ,Black Gap Event signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_SIGEN ,Transfer completed signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_SIGEN ,Command completed signal status Enable - . - ." "Masked,Enabled" rgroup.long 0x23C++0x3 line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this register when an Auto CMD12 Error interrupt occurs. This register is valid only when Auto CMD12 is e.." bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error If this bit is set to 1, it means that pending command is not executed due to Auto CMD12 error : ACEB, ACCE, ACTO or ACNE. - . - ." "NoErr,CmdNI" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted. This bit depends on the command index check enable (MMCHS_CMD[20] CICE). .." "NoErr,Err" bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error This bit is set to 1 when detecting a 0 at the end bit position of auto CMD12 command response. - . - ." "NoErr,Err" textline " " bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error This bit is automatically set to 1 when a CRC7 error is detected in the auto CMD12 command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - ." "NoErr,Err" bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error This bit is set to 1 if no response is received within 64 clock cycles from the end bit of the auto CMD12 command. - . - ." "NoErr,TimeOut" bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before Auto CMD12 starts. - . - ." "Exe,NotExe" group.long 0x240++0x3 line.long 0x00 "MMCHS_CAPA,Capabilities register This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x00 28. " BIT64 ,64-bit system bus support: Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. - . - ." "SysAddr32b,SysAddr64b" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register i.." "1V8_NotSup_r_/_St_1V8NotSup_w,St_1V8Sup_w_/_1V8_Sup_r" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized.." "St_3V0NotSup_w_/_3V0_NotSup_r,3V0_Sup_r_/_St_3V0Sup_w" textline " " bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized b.." "St_3V3NotSup_w_/_3V3_NotSup_r,St_3V3Sup_w_/_3V3_Sup_r" bitfld.long 0x00 23. " SRS ,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports suspend/resume functionality. - . - ." "NotSupported,Supported" bitfld.long 0x00 22. " DS ,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly. - . - ." "NotSupported,Supported" textline " " bitfld.long 0x00 21. " HSS ,High-speed support This bit indicates that the host controller supports high-speed operations and can supply an up-to maximum card frequency. - . - ." "NotSupported,Supported" bitfld.long 0x00 19. " AD2S ,ADMA2 support: This bit indicates whether the host controller is capable of using ADMA2. It depends on setting of generic parameter MMCHS_HL_HWINFO[0] MADMA_EN - . - ." "ADMA2NotSupported,ADMA2Supported" bitfld.long 0x00 16.--17. " MBL ,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 by.." "512,1024,2048,3" textline " " bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " TCU ,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - . - ." "MHz,KHz" bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x248++0x3 line.long 0x00 "MMCHS_CUR_CAPA,Maximum current capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a .." hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V - ." hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V - ." hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V - ." group.long 0x250++0x3 line.long 0x00 "MMCHS_FE,Force Event Register for Error Interrupt status The force Event Register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will.." bitfld.long 0x00 29. " FE_BADA ,Force Event Bad access to data space - . - ." "NoAction,IntForced" bitfld.long 0x00 28. " FE_CERR ,Force Event Card error - . - ." "NoAction,IntForced" bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA Error: - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 23. " FE_CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " FE_DEB ,Force Event Data End Bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error - . - ." "NoAction,IntForced" bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 16. " FE_CTO ,Command Timeout Error - This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. . - . - For commands that reply within 5 clock cycles - the timeout is still .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 4. " FE_ACIE ,Force Event Auto CMD12 index error - . - ." "NoAction,IntForced" bitfld.long 0x00 3. " FE_ACEB ,Force Event Auto CMD12 end bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 2. " FE_ACCE ,Force Event Auto CMD12 CRC error - . - ." "NoAction,IntForced" bitfld.long 0x00 1. " FE_ACTO ,Force Event Auto CMD12 timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 0. " FE_ACNE ,Force Event Auto CMD12 not executed - . - ." "NoAction,IntForced" rgroup.long 0x2FC++0x3 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number This status indicates the Standard SD Host Controller Specification Version. The upper and lower 4-bits indicate the version. - . - ." bitfld.long 0x00 0. " SIS ,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_SYSCTL[24] SRA), the interrupt signal sh.." "0,1" tree.end tree "MMCHS4" base ad:0x480D1000 width 20. rgroup.long 0x0++0x3 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision." rgroup.long 0x4++0x3 line.long 0x00 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." bitfld.long 0x00 6. " RETMODE ,Retention mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET. - . - ." "Retention_mode_disabled,Retention_mode_enabled" bitfld.long 0x00 2.--5. " MEM_SIZE ,Memory size for FIFO buffer: - . - . - . - ." "0,MEM_512,MEM_1024,3,MEM_2048,5,6,7,MEM_4096,9,10,11,12,13,14,15" bitfld.long 0x00 1. " MERGE_MEM ,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing. - . - ." "TwoMemBuffer,SingleMemBuffer" textline " " bitfld.long 0x00 0. " MADMA_EN ,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA. - . - ." "NoMasterDMA,SupportADMA" group.long 0x10++0x3 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. - . - . - . - ." "ForceStandby,NoStandby,SmartStandby,SmartStandbyWakeUp" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS. - . - ." "EmuEn,EmuDis" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing" group.long 0x110++0x3 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface." bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a 0. - . - . - . - ..." "Force,NoIdle,Smart,SmartWake" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock - . - . - . - ." "None,OCP,Func,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management - . - . - . - ." "Force,NoIdle,Smart,SmartWake" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control - . - ." "Disabled,Enable" bitfld.long 0x00 1. " SOFTRESET ,Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0. - . - . - . - ." "NoReset_r_/_St_un_w,OnReset_r_/_St_rst_w" bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy - . - ." "Off,On" rgroup.long 0x114++0x3 line.long 0x00 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring. - . - ." "OnGoing,Done" group.long 0x124++0x3 line.long 0x00 "MMCHS_CSRE,Card status response error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the correspond.." hexmask.long 0x00 0.--31. 1. " CSRE ,Card status response error" group.long 0x128++0x3 line.long 0x00 "MMCHS_SYSTEST,System Test register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register wi.." bitfld.long 0x00 16. " OBI ,Out-Of-Band Interrupt (OBI) data value - . - ." "LowLevel,HighLevel" bitfld.long 0x00 15. " SDCD ,Card detect input signal (SDCD) data value - . - ." "DrivenLow,DrivenHigh" bitfld.long 0x00 14. " SDWP ,Write protect input signal (SDWP) data value - . - ." "DrivenLow,DrivenHigh" textline " " bitfld.long 0x00 13. " WAKD ,Wake request output signal data value - . - . - . - ." "Zero_r_/_DrivenLow_w,DrivenHIgh_w_/_One_r" bitfld.long 0x00 12. " SSB ,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT). - . - . - . - ." "Clear_w_/_Zero_r,SetThemAll_w_/_One_r" bitfld.long 0x00 11. " D7D ,DAT7 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 10. " D6D ,DAT6 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 9. " D5D ,DAT5 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 8. " D4D ,DAT4 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 7. " D3D ,DAT3 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,One_r_/_DriveHigh_w" bitfld.long 0x00 6. " D2D ,DAT2 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" bitfld.long 0x00 5. " D1D ,DAT1 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 4. " D0D ,DAT0 input/output signal data value - . - . - . - ." "Zero_r_/_Zero_w,One_r_/_DriveHigh_w" bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" textline " " bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value - . - . - . - ." "DrivenLow_w_/_Zero_r,DrivenHigh_w_/_One_r" group.long 0x12C++0x3 line.long 0x00 "MMCHS_CON,Configuration register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and.." bitfld.long 0x00 21. " SDMA_LNE ,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data writ.." "EarlyDeAssert,LateDeAssert" bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).Thi.." "MasterDMADis,MasterDMAEn" bitfld.long 0x00 19. " DDR ,Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Da.." "NormalMode,DDRMode" textline " " bitfld.long 0x00 18. " BOOT_CF0 ,Boot status supported: This register is set when the CMD line need to be forced to 0 for a boot sequence. CMD line is driven to 0 after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer .." "NoCMDForce_/_CMDReleased,CMDForced_/_CMDForceReq" bitfld.long 0x00 17. " BOOT_ACK ,Book acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated. - . - ." "BootNoAck,BootAck" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only .." "Autogating,FreeRunning" textline " " bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also.." "Disable,Enable" bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration.." "NormalMode,OBintMode" bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system inte.." "ActiveHigh,ActiveLow" textline " " bitfld.long 0x00 12. " CEATA ,CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is use to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features. - . - ." "NormalMode,CEATAMode" bitfld.long 0x00 11. " CTPL ,Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO car.." "MMC_SD,SDIO" bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the syst.." "FilterLevel0,FilterLevel1,FilterLevel2,FilterLevel3" textline " " bitfld.long 0x00 8. " WPP ,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the typ.." "ActiveHigh,ActiveLow" bitfld.long 0x00 7. " CDP ,Card detect polarity All cards This bit selects the active level of the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type.." "ActiveHigh,ActiveLow" bitfld.long 0x00 6. " MIT ,MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detectio.." "CTO,No_CTO" textline " " bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the.." "1_4BitMode,8BitMode" bitfld.long 0x00 4. " MODE ,Mode select All cards These bits select between Functional mode and SYSTEST mode. - . - ." "FUNC,SYSTEST" bitfld.long 0x00 3. " STR ,Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a.." "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section .." "NoHostResp,HostResp" bitfld.long 0x00 1. " INIT ,Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock .." "NoInit,InitStream" bitfld.long 0x00 0. " OD ,Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typicall.." "NoOpenDrain,OpenDrain" group.long 0x130++0x3 line.long 0x00 "MMCHS_PWCNT,Power counter register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." hexmask.long.word 0x00 0.--15. 1. " PWRCNT ,Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued. - . - . - . - . - ." group.long 0x204++0x3 line.long 0x00 "MMCHS_BLK,Transfer Length Configuration register [11:0] BLEN is the block size register. [31:16] NBLK is the block count register. This register shall be used for any card." hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[1] BCE) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note:.." hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issu.." group.long 0x208++0x3 line.long 0x00 "MMCHS_ARG,Command argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exce.." hexmask.long 0x00 0.--31. 1. " ARG ,Command argument bits [31:0]" group.long 0x20C++0x3 line.long 0x00 "MMCHS_CMD,Command and transfer mode register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers duri.." bitfld.long 0x00 24.--29. " INDX ,Command index Binary encoded value from 0 to 63 specifying the command number send to card - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ..." "CMD0_or_ACMD0,CMD1_or_ACMD1,CMD2_or_ACMD2,CMD3_or_ACMD3,CMD4_or_ACMD4,CMD5_or_ACMD5,CMD6_or_ACMD6,CMD7_or_ACMD7,CMD8_or_ACMD8,CMD9_or_ACMD9,CMD10_or_ACMD10,CMD11_or_ACMD11,CMD12_or_ACMD12,CMD13_or_ACMD13,CMD14_or_ACMD14,CMD15_or_ACMD15,CMD16_or_ACMD16,CMD17_or_ACMD17,CMD18_or_ACMD18,CMD19_or_ACMD19,CMD20_or_ACMD20,CMD21_or_ACMD21,CMD22_or_ACMD22,CMD23_or_ACMD23,CMD24_or_ACMD24,CMD25_or_ACMD25,CMD26_or_ACMD26,CMD27_or_ACMD27,CMD28_or_ACMD28,CMD29_or_ACMD29,CMD30_or_ACMD30,CMD31_or_ACMD31,CMD32_or_ACMD32,CMD33_or_ACMD33,CMD34_or_ACMD34,CMD35_or_ACMD35,CMD36_or_ACMD36,CMD37_or_ACMD37,CMD38_or_ACMD38,CMD39_or_ACMD39,CMD40_or_ACMD40,CMD41_or_ACMD41,CMD42_or_ACMD42,CMD43_or_ACMD43,CMD44_or_ACMD44,CMD45_or_ACMD45,CMD46_or_ACMD46,CMD47_or_ACMD47,CMD48_or_ACMD48,CMD49_or_ACMD49,CMD50_or_ACMD50,CMD51_or_ACMD51,CMD52_or_ACMD52,CMD53_or_ACMD53,CMD54_or_ACMD54,CMD55_or_ACMD55,CMD56_or_ACMD56,CMD57_or_ACMD57,CMD58_or_ACMD58,CMD59_or_ACMD59,CMD60_or_ACMD60,CMD61_or_ACMD61,CMD62_or_ACMD62,CMD63_or_ACMD63" bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type This register specifies three types of special command: Suspend, Resume and Abort. These bits shall be set to 00b for all other commands. - . - . - . - ." "Normal,Suspend,Resume,Abort" bitfld.long 0x00 21. " DP ,Data present select This register indicates that data is present and DAT line shall be used. It must be set to 0 in the following conditions: - command using only CMD line - command with no data transfer but using .." "NoData,Data" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. If the index is not the same in the response as in the command, it.." "Nocheck,Check" bitfld.long 0x00 19. " CCCE ,Command CRC check enable This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. If an error is detected, it is reported as a command CRC .." "NoCheck,Check" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type This bits defines the response type of the command - . - . - . - ." "Norsp,Lght36,Lght48,Lght48b" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit shall be set to 0. - . - ." "sgleblk,multiblk" bitfld.long 0x00 4. " DDIR ,Data transfer Direction Select This bit defines either data transfer will be a read or a write. - . - ." "Write,Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable SDIO does not support this feature. When this bit is set to 1, the host controller issues a CMD12 automatically after the transfer completion of the last block. The Host Driver shall not set thi.." "Disable,Enable" textline " " bitfld.long 0x00 1. " BCE ,Block Count Enable Multiple block transfers only. This bit is used to enable the block count register (MMCHS_BLK[31:16] NBLK). When Block Count is disabled (MMCHS_CMD[1] BCE is set to 0) in Multiple block transfers (MMCHS_CMD[5] MSBS is s.." "Disable,Enable" bitfld.long 0x00 0. " DE ,DMA Enable This bit is used to enable DMA mode for host data access. - . - ." "Disable,Enable" rgroup.long 0x210++0x3 line.long 0x00 "MMCHS_RSP10,Command response[31:0] Register This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6" hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response [31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response [15:0]" rgroup.long 0x214++0x3 line.long 0x00 "MMCHS_RSP32,Command response[63:32] Register This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP3 ,Command Response [63:48]" hexmask.long.word 0x00 0.--15. 1. " RSP2 ,Command Response [47:32]" rgroup.long 0x218++0x3 line.long 0x00 "MMCHS_RSP54,Command response[95:64] Register This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP5 ,Command Response [95:80]" hexmask.long.word 0x00 0.--15. 1. " RSP4 ,Command Response [79:64]" rgroup.long 0x21C++0x3 line.long 0x00 "MMCHS_RSP76,Command response[127:96] Register This 32-bit register holds bits positions [127:96] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP7 ,Command Response [127:112]" hexmask.long.word 0x00 0.--15. 1. " RSP6 ,Command Response [111:96]" group.long 0x220++0x3 line.long 0x00 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers." hexmask.long 0x00 0.--31. 1. " DATA ,Data Register [31:0] In functional mode (MMCHS_CON[4] MODE set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[11] BRE), otherwise a bad access (MMCHS_S.." rgroup.long 0x224++0x3 line.long 0x00 "MMCHS_PSTATE,Present state register The Host can get status of the Host Controller from this 32-bit read only register." bitfld.long 0x00 24. " CLEV ,CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time. - . - ." "Zero,One" bitfld.long 0x00 20.--23. " DLEV ,DAT[3:0] line signal level DAT[3] =&gt; bit 23 DAT[2] =&gt; bit 22 DAT[1] =&gt; bit 21 DAT[0] =&gt; bit 20 This status is used to check DAT line level to recover from errors, and for debugging. .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (SDWP) level. The value of this register after reset depends on the protect input pin (SDWP) level at that time.." "zero,one" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level This bit reflects the inverse value of the card detect input pin (SDCD), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTATE[17] CSS) is set to 1. Use of this bit is lim.." "zero,one" bitfld.long 0x00 17. " CSS ,Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[18] CDPL). Debouncing is performed on the card detect input pin (SDCD) to detect card stabi.." "Debouncing,Stable" bitfld.long 0x00 16. " CINS ,Card inserted This bit is the debounced value of the card detect input pin (SDCD). An inactive to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt (MMCHS_STAT[6] CINS). A .." "zero,one" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[11:0] BLEN has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from.." "RdDisable,RdEnable" bitfld.long 0x00 10. " BWE ,Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data. - . - ." "WrDisable,WrEnable" bitfld.long 0x00 9. " RTA ,Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block.." "NoTransfer,Transfer" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block gap request. This bit is set to 0 whe.." "NoTransfer,Transfer" bitfld.long 0x00 2. " DLA ,DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue reque.." "zero,one" bitfld.long 0x00 1. " DATI ,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[2] DLA) or Read transfer is active (MMCHS_PSTATE[9] RTA) or when a command with busy is issued. This bit prevents the .." "Cmden,Cmddis" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0.." "Cmden,Cmddis" group.long 0x228++0x3 line.long 0x00 "MMCHS_HCTL,Control register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" bitfld.long 0x00 27. " OBWE ,Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). The write to this register is ignored when M.." "disable,enable" bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" textline " " bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 19. " IBG ,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit shou.." "Itdiable,Itenable" bitfld.long 0x00 18. " RWC ,Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[16] SBGR) generates a read wait per.." "NoRW,RW" textline " " bitfld.long 0x00 17. " CR ,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[16] SBGR). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when tr.." "None,Restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[17] CR) or during a suspend/resume sequence. In case o.." "Transfer,Stpblk" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[26:24]) before starting a transfer. - ..." "0,1,2,3,4,1V8,3V0,3V3" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[11:9] SDVS). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in th.." "Pwroff,Pwron" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interru.." "SDCDSel,CDTLSel" bitfld.long 0x00 6. " CDTL ,Card Detect Test Level: This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. - . - ." "NoCard,CardIns" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This regi.." "Reserved,Reserved1,ADMA2,Reserved2" bitfld.long 0x00 2. " HSPE ,High Speed Enable: Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is set to 0 (default), the Host Controller outputs CMD line and DAT lines at t.." "NormalSpeed,HighSpeed" bitfld.long 0x00 1. " DTW ,Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration regi.." "1_BitMode,4_BitMode" textline " " bitfld.long 0x00 0. " LED ,Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored." "0,1" group.long 0x22C++0x3 line.long 0x00 "MMCHS_SYSCTL,SD system control register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" bitfld.long 0x00 26. " SRD ,Software reset for DAT line. This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see , . DAT finite state machine in both clock domain are also reset. The following registers a.." "Work,Reset" bitfld.long 0x00 25. " SRC ,Software reset for CMD line For more information about SRC bit manipulation, see , . This bit is set to 1 for reset and released to 0 when completed. CMD finite state-machine in both clock domain are also reset..." "Work,Reset" bitfld.long 0x00 24. " SRA ,Software reset for all This bit is set to 1 for reset, and released to 0 when completed. This reset affects the entire host controller except for the card detection circuit and capabilities registers. - . - ." "Work,Reset" textline " " bitfld.long 0x00 16.--19. " DTO ,Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bit field based on - the maximum read access time (NAC) (Refer to the SD Specifica.." "1stDTO,2ndDTO,2,3,4,5,6,7,8,9,10,11,12,13,15thDTO,Rsvd" hexmask.long.word 0x00 6.--15. 1. " CLKD ,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO). - . - . - . - . - ." bitfld.long 0x00 2. " CEN ,Clock enable This bit controls if the clock is provided to the card or not. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " ICS ,Internal clock stable (status) This bit indicates either the internal clock is stable or not. - . - ." "NotReady,Ready" bitfld.long 0x00 0. " ICE ,Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface .." "Stop,Oscillate" group.long 0x230++0x3 line.long 0x00 "MMCHS_STAT,Interrupt status register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" bitfld.long 0x00 29. " BADA ,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[11] BRE =.." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 28. " CERR ,Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An erro.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 25. " ADMAE ,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller gener.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 24. " ACE ,Auto CMD12 error This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1. - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 23. " CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB ,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 21. " DCRC ,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command. - . - ..." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 20. " DTO ,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout - . - . - ..." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 19. " CIE ,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[20] CICE register. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 18. " CEB ,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 17. " CCRC ,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 16. " CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock .." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 15. " ERRI ,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[24:15]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit a.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 10. " BSR ,Boot status received interrupt This bit is set automatically when MMCHS_CON[18] BOOT_CF0 is set 0x0 or 0x1 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 9. " OBI ,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[14] OBIE is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[13] OBIP. This interrupt is .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 8. " CIRQ ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 7. " CREM ,Card removal This bit is set automatically when MMCHS_PSTATE[16] CINS changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 6. " CINS ,Card insertion This bit is set automatically when MMCHS_PSTATE[16] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 5. " BRR ,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[11:0] BLEN is completely written in the buffer. It indicates that the m.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 4. " BWR ,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[11:0] BLEN. It indicates tha.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 3. " DMA ,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 2. " BGE ,Block gap event When a stop at block gap is requested (MMCHS_HCTL[16] SBGR), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap.." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 1. " TC ,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[16] SBGR). In Read mode: This bit is automatic.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 0. " CC ,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[0] CMDI) If the command is a type for which no response is expected, then the command complete interrupt is generate.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" group.long 0x234++0x3 line.long 0x00 "MMCHS_IE,Interrupt SD enable register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" bitfld.long 0x00 29. " BADA_ENABLE ,Bad access to data space Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_ENABLE ,Card error interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_ENABLE ,ADMA error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_ENABLE ,Auto CMD12 error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_ENABLE ,Data end bit error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_ENABLE ,Data CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_ENABLE ,Data timeout error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_ENABLE ,Command index error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_ENABLE ,Command end bit error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_ENABLE ,Command CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_ENABLE ,Command timeout error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_ENABLE ,Boot status interrupt Enable A write to this register when MMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_ENABLE ,Out-of-Band interrupt Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_ENABLE ,Card interrupt Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is .." "Masked,Enabled" bitfld.long 0x00 7. " CREM_ENABLE ,Card removal Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_ENABLE ,Card insertion Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_ENABLE ,Buffer Read Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_ENABLE ,Buffer Write Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_ENABLE ,DMA interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_ENABLE ,Block Gap Event Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_ENABLE ,Transfer completed Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_ENABLE ,Command completed Interrupt Enable - . - ." "Masked,Enabled" group.long 0x238++0x3 line.long 0x00 "MMCHS_ISE,Interrupt signal enable register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" bitfld.long 0x00 29. " BADA_SIGEN ,Bad access to data space signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_SIGEN ,Card error interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_SIGEN ,ADMA error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_SIGEN ,Auto CMD12 error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_SIGEN ,Data end bit error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_SIGEN ,Data CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_SIGEN ,Data timeout error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_SIGEN ,Command index error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_SIGEN ,Command end bit error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_SIGEN ,Command CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_SIGEN ,Command timeout error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_SIGEN ,Boot status signal status EnableA write to this register whenMMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_SIGEN ,Out-Of-Band Interrupt signal status Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_SIGEN ,Card interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 7. " CREM_SIGEN ,Card removal signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_SIGEN ,Card insertion signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_SIGEN ,Buffer Read Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_SIGEN ,Buffer Write Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_SIGEN ,DMA interrupt Signal status enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_SIGEN ,Black Gap Event signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_SIGEN ,Transfer completed signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_SIGEN ,Command completed signal status Enable - . - ." "Masked,Enabled" rgroup.long 0x23C++0x3 line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this register when an Auto CMD12 Error interrupt occurs. This register is valid only when Auto CMD12 is e.." bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error If this bit is set to 1, it means that pending command is not executed due to Auto CMD12 error : ACEB, ACCE, ACTO or ACNE. - . - ." "NoErr,CmdNI" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted. This bit depends on the command index check enable (MMCHS_CMD[20] CICE). .." "NoErr,Err" bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error This bit is set to 1 when detecting a 0 at the end bit position of auto CMD12 command response. - . - ." "NoErr,Err" textline " " bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error This bit is automatically set to 1 when a CRC7 error is detected in the auto CMD12 command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - ." "NoErr,Err" bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error This bit is set to 1 if no response is received within 64 clock cycles from the end bit of the auto CMD12 command. - . - ." "NoErr,TimeOut" bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before Auto CMD12 starts. - . - ." "Exe,NotExe" group.long 0x240++0x3 line.long 0x00 "MMCHS_CAPA,Capabilities register This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x00 28. " BIT64 ,64-bit system bus support: Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. - . - ." "SysAddr32b,SysAddr64b" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register i.." "1V8_NotSup_r_/_St_1V8NotSup_w,St_1V8Sup_w_/_1V8_Sup_r" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized.." "St_3V0NotSup_w_/_3V0_NotSup_r,3V0_Sup_r_/_St_3V0Sup_w" textline " " bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized b.." "St_3V3NotSup_w_/_3V3_NotSup_r,St_3V3Sup_w_/_3V3_Sup_r" bitfld.long 0x00 23. " SRS ,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports suspend/resume functionality. - . - ." "NotSupported,Supported" bitfld.long 0x00 22. " DS ,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly. - . - ." "NotSupported,Supported" textline " " bitfld.long 0x00 21. " HSS ,High-speed support This bit indicates that the host controller supports high-speed operations and can supply an up-to maximum card frequency. - . - ." "NotSupported,Supported" bitfld.long 0x00 19. " AD2S ,ADMA2 support: This bit indicates whether the host controller is capable of using ADMA2. It depends on setting of generic parameter MMCHS_HL_HWINFO[0] MADMA_EN - . - ." "ADMA2NotSupported,ADMA2Supported" bitfld.long 0x00 16.--17. " MBL ,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 by.." "512,1024,2048,3" textline " " bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " TCU ,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - . - ." "MHz,KHz" bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x248++0x3 line.long 0x00 "MMCHS_CUR_CAPA,Maximum current capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a .." hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V - ." hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V - ." hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V - ." group.long 0x250++0x3 line.long 0x00 "MMCHS_FE,Force Event Register for Error Interrupt status The force Event Register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will.." bitfld.long 0x00 29. " FE_BADA ,Force Event Bad access to data space - . - ." "NoAction,IntForced" bitfld.long 0x00 28. " FE_CERR ,Force Event Card error - . - ." "NoAction,IntForced" bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA Error: - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 23. " FE_CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " FE_DEB ,Force Event Data End Bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error - . - ." "NoAction,IntForced" bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 16. " FE_CTO ,Command Timeout Error - This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. . - . - For commands that reply within 5 clock cycles - the timeout is still .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 4. " FE_ACIE ,Force Event Auto CMD12 index error - . - ." "NoAction,IntForced" bitfld.long 0x00 3. " FE_ACEB ,Force Event Auto CMD12 end bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 2. " FE_ACCE ,Force Event Auto CMD12 CRC error - . - ." "NoAction,IntForced" bitfld.long 0x00 1. " FE_ACTO ,Force Event Auto CMD12 timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 0. " FE_ACNE ,Force Event Auto CMD12 not executed - . - ." "NoAction,IntForced" rgroup.long 0x2FC++0x3 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number This status indicates the Standard SD Host Controller Specification Version. The upper and lower 4-bits indicate the version. - . - ." bitfld.long 0x00 0. " SIS ,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_SYSCTL[24] SRA), the interrupt signal sh.." "0,1" tree.end tree "MMCHS5" base ad:0x480D5000 width 20. rgroup.long 0x0++0x3 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision." rgroup.long 0x4++0x3 line.long 0x00 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." bitfld.long 0x00 6. " RETMODE ,Retention mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET. - . - ." "Retention_mode_disabled,Retention_mode_enabled" bitfld.long 0x00 2.--5. " MEM_SIZE ,Memory size for FIFO buffer: - . - . - . - ." "0,MEM_512,MEM_1024,3,MEM_2048,5,6,7,MEM_4096,9,10,11,12,13,14,15" bitfld.long 0x00 1. " MERGE_MEM ,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing. - . - ." "TwoMemBuffer,SingleMemBuffer" textline " " bitfld.long 0x00 0. " MADMA_EN ,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA. - . - ." "NoMasterDMA,SupportADMA" group.long 0x10++0x3 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. - . - . - . - ." "ForceStandby,NoStandby,SmartStandby,SmartStandbyWakeUp" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. - . - . - . - ." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS. - . - ." "EmuEn,EmuDis" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset. (Optional) - . - . - . - ." "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing" group.long 0x110++0x3 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface." bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a 0. - . - . - . - ..." "Force,NoIdle,Smart,SmartWake" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock - . - . - . - ." "None,OCP,Func,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management - . - . - . - ." "Force,NoIdle,Smart,SmartWake" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control - . - ." "Disabled,Enable" bitfld.long 0x00 1. " SOFTRESET ,Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0. - . - . - . - ." "NoReset_r_/_St_un_w,OnReset_r_/_St_rst_w" bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy - . - ." "Off,On" rgroup.long 0x114++0x3 line.long 0x00 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring. - . - ." "OnGoing,Done" group.long 0x124++0x3 line.long 0x00 "MMCHS_CSRE,Card status response error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the correspond.." hexmask.long 0x00 0.--31. 1. " CSRE ,Card status response error" group.long 0x128++0x3 line.long 0x00 "MMCHS_SYSTEST,System Test register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register wi.." bitfld.long 0x00 16. " OBI ,Out-Of-Band Interrupt (OBI) data value - . - ." "LowLevel,HighLevel" bitfld.long 0x00 15. " SDCD ,Card detect input signal (SDCD) data value - . - ." "DrivenLow,DrivenHigh" bitfld.long 0x00 14. " SDWP ,Write protect input signal (SDWP) data value - . - ." "DrivenLow,DrivenHigh" textline " " bitfld.long 0x00 13. " WAKD ,Wake request output signal data value - . - . - . - ." "Zero_r_/_DrivenLow_w,DrivenHIgh_w_/_One_r" bitfld.long 0x00 12. " SSB ,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT). - . - . - . - ." "Clear_w_/_Zero_r,SetThemAll_w_/_One_r" bitfld.long 0x00 11. " D7D ,DAT7 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 10. " D6D ,DAT6 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 9. " D5D ,DAT5 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" bitfld.long 0x00 8. " D4D ,DAT4 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 7. " D3D ,DAT3 input/output signal data value - . - . - . - ." "Zero_r_/_DriveLow_w,One_r_/_DriveHigh_w" bitfld.long 0x00 6. " D2D ,DAT2 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" bitfld.long 0x00 5. " D1D ,DAT1 input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,DriveHigh_w_/_One_r" textline " " bitfld.long 0x00 4. " D0D ,DAT0 input/output signal data value - . - . - . - ." "Zero_r_/_Zero_w,One_r_/_DriveHigh_w" bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value - . - . - . - ." "DriveLow_w_/_Zero_r,One_r_/_DriveHigh_w" textline " " bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction. - . - . - . - ." "Zero_r_/_Out_w,In_w_/_One_r" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value - . - . - . - ." "DrivenLow_w_/_Zero_r,DrivenHigh_w_/_One_r" group.long 0x12C++0x3 line.long 0x00 "MMCHS_CON,Configuration register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and.." bitfld.long 0x00 21. " SDMA_LNE ,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data writ.." "EarlyDeAssert,LateDeAssert" bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).Thi.." "MasterDMADis,MasterDMAEn" bitfld.long 0x00 19. " DDR ,Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Da.." "NormalMode,DDRMode" textline " " bitfld.long 0x00 18. " BOOT_CF0 ,Boot status supported: This register is set when the CMD line need to be forced to 0 for a boot sequence. CMD line is driven to 0 after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer .." "NoCMDForce_/_CMDReleased,CMDForced_/_CMDForceReq" bitfld.long 0x00 17. " BOOT_ACK ,Book acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated. - . - ." "BootNoAck,BootAck" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only .." "Autogating,FreeRunning" textline " " bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also.." "Disable,Enable" bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration.." "NormalMode,OBintMode" bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system inte.." "ActiveHigh,ActiveLow" textline " " bitfld.long 0x00 12. " CEATA ,CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is use to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features. - . - ." "NormalMode,CEATAMode" bitfld.long 0x00 11. " CTPL ,Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO car.." "MMC_SD,SDIO" bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the syst.." "FilterLevel0,FilterLevel1,FilterLevel2,FilterLevel3" textline " " bitfld.long 0x00 8. " WPP ,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the typ.." "ActiveHigh,ActiveLow" bitfld.long 0x00 7. " CDP ,Card detect polarity All cards This bit selects the active level of the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type.." "ActiveHigh,ActiveLow" bitfld.long 0x00 6. " MIT ,MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detectio.." "CTO,No_CTO" textline " " bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the.." "1_4BitMode,8BitMode" bitfld.long 0x00 4. " MODE ,Mode select All cards These bits select between Functional mode and SYSTEST mode. - . - ." "FUNC,SYSTEST" bitfld.long 0x00 3. " STR ,Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a.." "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section .." "NoHostResp,HostResp" bitfld.long 0x00 1. " INIT ,Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock .." "NoInit,InitStream" bitfld.long 0x00 0. " OD ,Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typicall.." "NoOpenDrain,OpenDrain" group.long 0x130++0x3 line.long 0x00 "MMCHS_PWCNT,Power counter register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." hexmask.long.word 0x00 0.--15. 1. " PWRCNT ,Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued. - . - . - . - . - ." group.long 0x204++0x3 line.long 0x00 "MMCHS_BLK,Transfer Length Configuration register [11:0] BLEN is the block size register. [31:16] NBLK is the block count register. This register shall be used for any card." hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[1] BCE) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note:.." hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issu.." group.long 0x208++0x3 line.long 0x00 "MMCHS_ARG,Command argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exce.." hexmask.long 0x00 0.--31. 1. " ARG ,Command argument bits [31:0]" group.long 0x20C++0x3 line.long 0x00 "MMCHS_CMD,Command and transfer mode register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers duri.." bitfld.long 0x00 24.--29. " INDX ,Command index Binary encoded value from 0 to 63 specifying the command number send to card - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - . - ..." "CMD0_or_ACMD0,CMD1_or_ACMD1,CMD2_or_ACMD2,CMD3_or_ACMD3,CMD4_or_ACMD4,CMD5_or_ACMD5,CMD6_or_ACMD6,CMD7_or_ACMD7,CMD8_or_ACMD8,CMD9_or_ACMD9,CMD10_or_ACMD10,CMD11_or_ACMD11,CMD12_or_ACMD12,CMD13_or_ACMD13,CMD14_or_ACMD14,CMD15_or_ACMD15,CMD16_or_ACMD16,CMD17_or_ACMD17,CMD18_or_ACMD18,CMD19_or_ACMD19,CMD20_or_ACMD20,CMD21_or_ACMD21,CMD22_or_ACMD22,CMD23_or_ACMD23,CMD24_or_ACMD24,CMD25_or_ACMD25,CMD26_or_ACMD26,CMD27_or_ACMD27,CMD28_or_ACMD28,CMD29_or_ACMD29,CMD30_or_ACMD30,CMD31_or_ACMD31,CMD32_or_ACMD32,CMD33_or_ACMD33,CMD34_or_ACMD34,CMD35_or_ACMD35,CMD36_or_ACMD36,CMD37_or_ACMD37,CMD38_or_ACMD38,CMD39_or_ACMD39,CMD40_or_ACMD40,CMD41_or_ACMD41,CMD42_or_ACMD42,CMD43_or_ACMD43,CMD44_or_ACMD44,CMD45_or_ACMD45,CMD46_or_ACMD46,CMD47_or_ACMD47,CMD48_or_ACMD48,CMD49_or_ACMD49,CMD50_or_ACMD50,CMD51_or_ACMD51,CMD52_or_ACMD52,CMD53_or_ACMD53,CMD54_or_ACMD54,CMD55_or_ACMD55,CMD56_or_ACMD56,CMD57_or_ACMD57,CMD58_or_ACMD58,CMD59_or_ACMD59,CMD60_or_ACMD60,CMD61_or_ACMD61,CMD62_or_ACMD62,CMD63_or_ACMD63" bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type This register specifies three types of special command: Suspend, Resume and Abort. These bits shall be set to 00b for all other commands. - . - . - . - ." "Normal,Suspend,Resume,Abort" bitfld.long 0x00 21. " DP ,Data present select This register indicates that data is present and DAT line shall be used. It must be set to 0 in the following conditions: - command using only CMD line - command with no data transfer but using .." "NoData,Data" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. If the index is not the same in the response as in the command, it.." "Nocheck,Check" bitfld.long 0x00 19. " CCCE ,Command CRC check enable This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. If an error is detected, it is reported as a command CRC .." "NoCheck,Check" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type This bits defines the response type of the command - . - . - . - ." "Norsp,Lght36,Lght48,Lght48b" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit shall be set to 0. - . - ." "sgleblk,multiblk" bitfld.long 0x00 4. " DDIR ,Data transfer Direction Select This bit defines either data transfer will be a read or a write. - . - ." "Write,Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable SDIO does not support this feature. When this bit is set to 1, the host controller issues a CMD12 automatically after the transfer completion of the last block. The Host Driver shall not set thi.." "Disable,Enable" textline " " bitfld.long 0x00 1. " BCE ,Block Count Enable Multiple block transfers only. This bit is used to enable the block count register (MMCHS_BLK[31:16] NBLK). When Block Count is disabled (MMCHS_CMD[1] BCE is set to 0) in Multiple block transfers (MMCHS_CMD[5] MSBS is s.." "Disable,Enable" bitfld.long 0x00 0. " DE ,DMA Enable This bit is used to enable DMA mode for host data access. - . - ." "Disable,Enable" rgroup.long 0x210++0x3 line.long 0x00 "MMCHS_RSP10,Command response[31:0] Register This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6" hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response [31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response [15:0]" rgroup.long 0x214++0x3 line.long 0x00 "MMCHS_RSP32,Command response[63:32] Register This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP3 ,Command Response [63:48]" hexmask.long.word 0x00 0.--15. 1. " RSP2 ,Command Response [47:32]" rgroup.long 0x218++0x3 line.long 0x00 "MMCHS_RSP54,Command response[95:64] Register This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP5 ,Command Response [95:80]" hexmask.long.word 0x00 0.--15. 1. " RSP4 ,Command Response [79:64]" rgroup.long 0x21C++0x3 line.long 0x00 "MMCHS_RSP76,Command response[127:96] Register This 32-bit register holds bits positions [127:96] of command response type R2" hexmask.long.word 0x00 16.--31. 1. " RSP7 ,Command Response [127:112]" hexmask.long.word 0x00 0.--15. 1. " RSP6 ,Command Response [111:96]" group.long 0x220++0x3 line.long 0x00 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers." hexmask.long 0x00 0.--31. 1. " DATA ,Data Register [31:0] In functional mode (MMCHS_CON[4] MODE set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[11] BRE), otherwise a bad access (MMCHS_S.." rgroup.long 0x224++0x3 line.long 0x00 "MMCHS_PSTATE,Present state register The Host can get status of the Host Controller from this 32-bit read only register." bitfld.long 0x00 24. " CLEV ,CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time. - . - ." "Zero,One" bitfld.long 0x00 20.--23. " DLEV ,DAT[3:0] line signal level DAT[3] =&gt; bit 23 DAT[2] =&gt; bit 22 DAT[1] =&gt; bit 21 DAT[0] =&gt; bit 20 This status is used to check DAT line level to recover from errors, and for debugging. .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (SDWP) level. The value of this register after reset depends on the protect input pin (SDWP) level at that time.." "zero,one" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level This bit reflects the inverse value of the card detect input pin (SDCD), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTATE[17] CSS) is set to 1. Use of this bit is lim.." "zero,one" bitfld.long 0x00 17. " CSS ,Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[18] CDPL). Debouncing is performed on the card detect input pin (SDCD) to detect card stabi.." "Debouncing,Stable" bitfld.long 0x00 16. " CINS ,Card inserted This bit is the debounced value of the card detect input pin (SDCD). An inactive to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt (MMCHS_STAT[6] CINS). A .." "zero,one" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[11:0] BLEN has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from.." "RdDisable,RdEnable" bitfld.long 0x00 10. " BWE ,Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data. - . - ." "WrDisable,WrEnable" bitfld.long 0x00 9. " RTA ,Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block.." "NoTransfer,Transfer" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block gap request. This bit is set to 0 whe.." "NoTransfer,Transfer" bitfld.long 0x00 2. " DLA ,DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue reque.." "zero,one" bitfld.long 0x00 1. " DATI ,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[2] DLA) or Read transfer is active (MMCHS_PSTATE[9] RTA) or when a command with busy is issued. This bit prevents the .." "Cmden,Cmddis" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0.." "Cmden,Cmddis" group.long 0x228++0x3 line.long 0x00 "MMCHS_HCTL,Control register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" bitfld.long 0x00 27. " OBWE ,Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). The write to this register is ignored when M.." "disable,enable" bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" textline " " bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). - . - ." "disable,enable" bitfld.long 0x00 19. " IBG ,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit shou.." "Itdiable,Itenable" bitfld.long 0x00 18. " RWC ,Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[16] SBGR) generates a read wait per.." "NoRW,RW" textline " " bitfld.long 0x00 17. " CR ,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[16] SBGR). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when tr.." "None,Restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[17] CR) or during a suspend/resume sequence. In case o.." "Transfer,Stpblk" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[26:24]) before starting a transfer. - ..." "0,1,2,3,4,1V8,3V0,3V3" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[11:9] SDVS). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in th.." "Pwroff,Pwron" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interru.." "SDCDSel,CDTLSel" bitfld.long 0x00 6. " CDTL ,Card Detect Test Level: This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. - . - ." "NoCard,CardIns" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This regi.." "Reserved,Reserved1,ADMA2,Reserved2" bitfld.long 0x00 2. " HSPE ,High Speed Enable: Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is set to 0 (default), the Host Controller outputs CMD line and DAT lines at t.." "NormalSpeed,HighSpeed" bitfld.long 0x00 1. " DTW ,Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration regi.." "1_BitMode,4_BitMode" textline " " bitfld.long 0x00 0. " LED ,Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored." "0,1" group.long 0x22C++0x3 line.long 0x00 "MMCHS_SYSCTL,SD system control register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" bitfld.long 0x00 26. " SRD ,Software reset for DAT line. This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see , . DAT finite state machine in both clock domain are also reset. The following registers a.." "Work,Reset" bitfld.long 0x00 25. " SRC ,Software reset for CMD line For more information about SRC bit manipulation, see , . This bit is set to 1 for reset and released to 0 when completed. CMD finite state-machine in both clock domain are also reset..." "Work,Reset" bitfld.long 0x00 24. " SRA ,Software reset for all This bit is set to 1 for reset, and released to 0 when completed. This reset affects the entire host controller except for the card detection circuit and capabilities registers. - . - ." "Work,Reset" textline " " bitfld.long 0x00 16.--19. " DTO ,Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bit field based on - the maximum read access time (NAC) (Refer to the SD Specifica.." "1stDTO,2ndDTO,2,3,4,5,6,7,8,9,10,11,12,13,15thDTO,Rsvd" hexmask.long.word 0x00 6.--15. 1. " CLKD ,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO). - . - . - . - . - ." bitfld.long 0x00 2. " CEN ,Clock enable This bit controls if the clock is provided to the card or not. - . - ." "Disable,Enable" textline " " bitfld.long 0x00 1. " ICS ,Internal clock stable (status) This bit indicates either the internal clock is stable or not. - . - ." "NotReady,Ready" bitfld.long 0x00 0. " ICE ,Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface .." "Stop,Oscillate" group.long 0x230++0x3 line.long 0x00 "MMCHS_STAT,Interrupt status register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" bitfld.long 0x00 29. " BADA ,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[11] BRE =.." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 28. " CERR ,Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An erro.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 25. " ADMAE ,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller gener.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 24. " ACE ,Auto CMD12 error This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1. - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 23. " CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB ,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 21. " DCRC ,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command. - . - ..." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 20. " DTO ,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout - . - . - ..." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 19. " CIE ,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[20] CICE register. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 18. " CEB ,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 17. " CCRC ,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 16. " CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock .." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 15. " ERRI ,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[24:15]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit a.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 10. " BSR ,Boot status received interrupt This bit is set automatically when MMCHS_CON[18] BOOT_CF0 is set 0x0 or 0x1 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card. - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 9. " OBI ,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[14] OBIE is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[13] OBIP. This interrupt is .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 8. " CIRQ ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-.." "IRQ_fal_r,IRQ_tru_r" bitfld.long 0x00 7. " CREM ,Card removal This bit is set automatically when MMCHS_PSTATE[16] CINS changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 6. " CINS ,Card insertion This bit is set automatically when MMCHS_PSTATE[16] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS). - . - . - . - ." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 5. " BRR ,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[11:0] BLEN is completely written in the buffer. It indicates that the m.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 4. " BWR ,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[11:0] BLEN. It indicates tha.." "IRQ_fal_r_/_St_un_w,St_rst_w_/_IRQ_tru_r" bitfld.long 0x00 3. " DMA ,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion. - . - . - . - ." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" textline " " bitfld.long 0x00 2. " BGE ,Block gap event When a stop at block gap is requested (MMCHS_HCTL[16] SBGR), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap.." "St_un_w_/_IRQ_fal_r,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 1. " TC ,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[16] SBGR). In Read mode: This bit is automatic.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" bitfld.long 0x00 0. " CC ,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[0] CMDI) If the command is a type for which no response is expected, then the command complete interrupt is generate.." "IRQ_fal_r_/_St_un_w,IRQ_tru_r_/_St_rst_w" group.long 0x234++0x3 line.long 0x00 "MMCHS_IE,Interrupt SD enable register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" bitfld.long 0x00 29. " BADA_ENABLE ,Bad access to data space Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_ENABLE ,Card error interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_ENABLE ,ADMA error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_ENABLE ,Auto CMD12 error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_ENABLE ,Data end bit error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_ENABLE ,Data CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_ENABLE ,Data timeout error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_ENABLE ,Command index error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_ENABLE ,Command end bit error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_ENABLE ,Command CRC error Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_ENABLE ,Command timeout error Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_ENABLE ,Boot status interrupt Enable A write to this register when MMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_ENABLE ,Out-of-Band interrupt Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_ENABLE ,Card interrupt Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is .." "Masked,Enabled" bitfld.long 0x00 7. " CREM_ENABLE ,Card removal Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_ENABLE ,Card insertion Interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_ENABLE ,Buffer Read Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_ENABLE ,Buffer Write Ready Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_ENABLE ,DMA interrupt Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_ENABLE ,Block Gap Event Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_ENABLE ,Transfer completed Interrupt Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_ENABLE ,Command completed Interrupt Enable - . - ." "Masked,Enabled" group.long 0x238++0x3 line.long 0x00 "MMCHS_ISE,Interrupt signal enable register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" bitfld.long 0x00 29. " BADA_SIGEN ,Bad access to data space signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 28. " CERR_SIGEN ,Card error interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 25. " ADMAE_SIGEN ,ADMA error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 24. " ACE_SIGEN ,Auto CMD12 error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 23. " CLE ,Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " DEB_SIGEN ,Data end bit error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 21. " DCRC_SIGEN ,Data CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 20. " DTO_SIGEN ,Data timeout error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 19. " CIE_SIGEN ,Command index error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_SIGEN ,Command end bit error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 17. " CCRC_SIGEN ,Command CRC error signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 16. " CTO_SIGEN ,Command timeout error signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x00 10. " BSR_SIGEN ,Boot status signal status EnableA write to this register whenMMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored. - . - ." "Masked,Enabled" bitfld.long 0x00 9. " OBI_SIGEN ,Out-Of-Band Interrupt signal status Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored. - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 8. " CIRQ_SIGEN ,Card interrupt signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 7. " CREM_SIGEN ,Card removal signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 6. " CINS_SIGEN ,Card insertion signal status Enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 5. " BRR_SIGEN ,Buffer Read Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 4. " BWR_SIGEN ,Buffer Write Ready signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 3. " DMA_SIGEN ,DMA interrupt Signal status enable - . - ." "Masked,Enabled" textline " " bitfld.long 0x00 2. " BGE_SIGEN ,Black Gap Event signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 1. " TC_SIGEN ,Transfer completed signal status Enable - . - ." "Masked,Enabled" bitfld.long 0x00 0. " CC_SIGEN ,Command completed signal status Enable - . - ." "Masked,Enabled" rgroup.long 0x23C++0x3 line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this register when an Auto CMD12 Error interrupt occurs. This register is valid only when Auto CMD12 is e.." bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error If this bit is set to 1, it means that pending command is not executed due to Auto CMD12 error : ACEB, ACCE, ACTO or ACNE. - . - ." "NoErr,CmdNI" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted. This bit depends on the command index check enable (MMCHS_CMD[20] CICE). .." "NoErr,Err" bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error This bit is set to 1 when detecting a 0 at the end bit position of auto CMD12 command response. - . - ." "NoErr,Err" textline " " bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error This bit is automatically set to 1 when a CRC7 error is detected in the auto CMD12 command response depending on the enable in MMCHS_CMD[19] CCCE register. - . - ." "NoErr,Err" bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error This bit is set to 1 if no response is received within 64 clock cycles from the end bit of the auto CMD12 command. - . - ." "NoErr,TimeOut" bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before Auto CMD12 starts. - . - ." "Exe,NotExe" group.long 0x240++0x3 line.long 0x00 "MMCHS_CAPA,Capabilities register This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x00 28. " BIT64 ,64-bit system bus support: Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. - . - ." "SysAddr32b,SysAddr64b" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register i.." "1V8_NotSup_r_/_St_1V8NotSup_w,St_1V8Sup_w_/_1V8_Sup_r" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized.." "St_3V0NotSup_w_/_3V0_NotSup_r,3V0_Sup_r_/_St_3V0Sup_w" textline " " bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized b.." "St_3V3NotSup_w_/_3V3_NotSup_r,St_3V3Sup_w_/_3V3_Sup_r" bitfld.long 0x00 23. " SRS ,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports suspend/resume functionality. - . - ." "NotSupported,Supported" bitfld.long 0x00 22. " DS ,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly. - . - ." "NotSupported,Supported" textline " " bitfld.long 0x00 21. " HSS ,High-speed support This bit indicates that the host controller supports high-speed operations and can supply an up-to maximum card frequency. - . - ." "NotSupported,Supported" bitfld.long 0x00 19. " AD2S ,ADMA2 support: This bit indicates whether the host controller is capable of using ADMA2. It depends on setting of generic parameter MMCHS_HL_HWINFO[0] MADMA_EN - . - ." "ADMA2NotSupported,ADMA2Supported" bitfld.long 0x00 16.--17. " MBL ,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 by.." "512,1024,2048,3" textline " " bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " TCU ,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - . - ." "MHz,KHz" bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[20] DTO). - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x248++0x3 line.long 0x00 "MMCHS_CUR_CAPA,Maximum current capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a .." hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V - ." hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V - ." hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V - ." group.long 0x250++0x3 line.long 0x00 "MMCHS_FE,Force Event Register for Error Interrupt status The force Event Register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will.." bitfld.long 0x00 29. " FE_BADA ,Force Event Bad access to data space - . - ." "NoAction,IntForced" bitfld.long 0x00 28. " FE_CERR ,Force Event Card error - . - ." "NoAction,IntForced" bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA Error: - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 23. " FE_CLE ,Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored." "0,1" bitfld.long 0x00 22. " FE_DEB ,Force Event Data End Bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error - . - ." "NoAction,IntForced" bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC Error - . - ." "NoAction,IntForced" bitfld.long 0x00 16. " FE_CTO ,Command Timeout Error - This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. . - . - For commands that reply within 5 clock cycles - the timeout is still .." "St_un_w_/_IRQ_fal_r,St_rst_w_/_IRQ_tru_r" textline " " bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error - . - ." "NoAction,IntForced" bitfld.long 0x00 4. " FE_ACIE ,Force Event Auto CMD12 index error - . - ." "NoAction,IntForced" bitfld.long 0x00 3. " FE_ACEB ,Force Event Auto CMD12 end bit error - . - ." "NoAction,IntForced" textline " " bitfld.long 0x00 2. " FE_ACCE ,Force Event Auto CMD12 CRC error - . - ." "NoAction,IntForced" bitfld.long 0x00 1. " FE_ACTO ,Force Event Auto CMD12 timeout error - . - ." "NoAction,IntForced" bitfld.long 0x00 0. " FE_ACNE ,Force Event Auto CMD12 not executed - . - ." "NoAction,IntForced" rgroup.long 0x2FC++0x3 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number This status indicates the Standard SD Host Controller Specification Version. The upper and lower 4-bits indicate the version. - . - ." bitfld.long 0x00 0. " SIS ,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_SYSCTL[24] SRA), the interrupt signal sh.." "0,1" tree.end tree.end tree.end tree.open "General_Purpose_Interface" tree.open "GPIO2" tree "GPIO2" base ad:0x48055000 width 22. rgroup.long 0x0++0x3 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,0x0: Force-idle: An idle request is acknowledged unconditionally. - . - . - ." "0,No_Idle,Smart_Idle,Smart_Idle_Wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,OCP clock gating control. - . - ." "Free_Run,Automatic" group.long 0x24++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x28++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x2C++0x3 line.long 0x00 "GPIO_IRQSTATUS_0,Per-event interrupt status vector (enabled) (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x30++0x3 line.long 0x00 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x34++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_0,Per-event interrupt enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x38++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x3C++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x40++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x44++0x3 line.long 0x00 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." group.long 0x48++0x3 line.long 0x00 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." rgroup.long 0x114++0x3 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,- . - ." "In_Progress,Completed" group.long 0x120++0x3 line.long 0x00 "GPIO_WAKEUPENABLE,Wake-up enable register (legacy) for first line of interrupt" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wake-up enable for interrupt lineCaution:This register is kept for backward software compatibility. Use and instead.. - . Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled o.." group.long 0x130++0x3 line.long 0x00 "GPIO_CTRL,GPIO control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Clock gating ratio for event detection - . - . - . - ." "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,- . - ." "No,Yes" group.long 0x134++0x3 line.long 0x00 "GPIO_OE,Output enable register. 0: Output enabled ; 1: Output disabled" hexmask.long 0x00 0.--31. 1. " OUTPUTEN ,Output enable - . - ." rgroup.long 0x138++0x3 line.long 0x00 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x00 0.--31. 1. " DATAIN ,Sampled input data" group.long 0x13C++0x3 line.long 0x00 "GPIO_DATAOUT,Data output register (data to set on output pins)." hexmask.long 0x00 0.--31. 1. " DATAOUT ,Data to set on output pins" group.long 0x140++0x3 line.long 0x00 "GPIO_LEVELDETECT0,Detect low-level register. 0: Low-level detection disabled; 1: Low-level detection enabled" hexmask.long 0x00 0.--31. 1. " LEVELDETECT0 ,Low-level detection - . - ." group.long 0x144++0x3 line.long 0x00 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x00 0.--31. 1. " LEVELDETECT1 ,- . - ." group.long 0x148++0x3 line.long 0x00 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x00 0.--31. 1. " RISINGDETECT ,- . - ." group.long 0x14C++0x3 line.long 0x00 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x00 0.--31. 1. " FALLINGDETECT ,- . - ." group.long 0x150++0x3 line.long 0x00 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x00 0.--31. 1. " DEBOUNCEENABLE ,- . - ." group.long 0x154++0x3 line.long 0x00 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time in 31 ?s steps" group.long 0x180++0x3 line.long 0x00 "GPIO_CLEARWKUPENA,Clear wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x184++0x3 line.long 0x00 "GPIO_SETWKUENA,Set wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x190++0x3 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." group.long 0x194++0x3 line.long 0x00 "GPIO_SETDATAOUT,Set data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." tree.end tree "GPIO3" base ad:0x48057000 width 22. rgroup.long 0x0++0x3 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,0x0: Force-idle: An idle request is acknowledged unconditionally. - . - . - ." "0,No_Idle,Smart_Idle,Smart_Idle_Wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,OCP clock gating control. - . - ." "Free_Run,Automatic" group.long 0x24++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x28++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x2C++0x3 line.long 0x00 "GPIO_IRQSTATUS_0,Per-event interrupt status vector (enabled) (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x30++0x3 line.long 0x00 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x34++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_0,Per-event interrupt enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x38++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x3C++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x40++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x44++0x3 line.long 0x00 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." group.long 0x48++0x3 line.long 0x00 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." rgroup.long 0x114++0x3 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,- . - ." "In_Progress,Completed" group.long 0x120++0x3 line.long 0x00 "GPIO_WAKEUPENABLE,Wake-up enable register (legacy) for first line of interrupt" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wake-up enable for interrupt lineCaution:This register is kept for backward software compatibility. Use and instead.. - . Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled o.." group.long 0x130++0x3 line.long 0x00 "GPIO_CTRL,GPIO control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Clock gating ratio for event detection - . - . - . - ." "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,- . - ." "No,Yes" group.long 0x134++0x3 line.long 0x00 "GPIO_OE,Output enable register. 0: Output enabled ; 1: Output disabled" hexmask.long 0x00 0.--31. 1. " OUTPUTEN ,Output enable - . - ." rgroup.long 0x138++0x3 line.long 0x00 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x00 0.--31. 1. " DATAIN ,Sampled input data" group.long 0x13C++0x3 line.long 0x00 "GPIO_DATAOUT,Data output register (data to set on output pins)." hexmask.long 0x00 0.--31. 1. " DATAOUT ,Data to set on output pins" group.long 0x140++0x3 line.long 0x00 "GPIO_LEVELDETECT0,Detect low-level register. 0: Low-level detection disabled; 1: Low-level detection enabled" hexmask.long 0x00 0.--31. 1. " LEVELDETECT0 ,Low-level detection - . - ." group.long 0x144++0x3 line.long 0x00 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x00 0.--31. 1. " LEVELDETECT1 ,- . - ." group.long 0x148++0x3 line.long 0x00 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x00 0.--31. 1. " RISINGDETECT ,- . - ." group.long 0x14C++0x3 line.long 0x00 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x00 0.--31. 1. " FALLINGDETECT ,- . - ." group.long 0x150++0x3 line.long 0x00 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x00 0.--31. 1. " DEBOUNCEENABLE ,- . - ." group.long 0x154++0x3 line.long 0x00 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time in 31 ?s steps" group.long 0x180++0x3 line.long 0x00 "GPIO_CLEARWKUPENA,Clear wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x184++0x3 line.long 0x00 "GPIO_SETWKUENA,Set wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x190++0x3 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." group.long 0x194++0x3 line.long 0x00 "GPIO_SETDATAOUT,Set data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." tree.end tree "GPIO4" base ad:0x48059000 width 22. rgroup.long 0x0++0x3 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,0x0: Force-idle: An idle request is acknowledged unconditionally. - . - . - ." "0,No_Idle,Smart_Idle,Smart_Idle_Wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,OCP clock gating control. - . - ." "Free_Run,Automatic" group.long 0x24++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x28++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x2C++0x3 line.long 0x00 "GPIO_IRQSTATUS_0,Per-event interrupt status vector (enabled) (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x30++0x3 line.long 0x00 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x34++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_0,Per-event interrupt enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x38++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x3C++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x40++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x44++0x3 line.long 0x00 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." group.long 0x48++0x3 line.long 0x00 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." rgroup.long 0x114++0x3 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,- . - ." "In_Progress,Completed" group.long 0x120++0x3 line.long 0x00 "GPIO_WAKEUPENABLE,Wake-up enable register (legacy) for first line of interrupt" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wake-up enable for interrupt lineCaution:This register is kept for backward software compatibility. Use and instead.. - . Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled o.." group.long 0x130++0x3 line.long 0x00 "GPIO_CTRL,GPIO control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Clock gating ratio for event detection - . - . - . - ." "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,- . - ." "No,Yes" group.long 0x134++0x3 line.long 0x00 "GPIO_OE,Output enable register. 0: Output enabled ; 1: Output disabled" hexmask.long 0x00 0.--31. 1. " OUTPUTEN ,Output enable - . - ." rgroup.long 0x138++0x3 line.long 0x00 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x00 0.--31. 1. " DATAIN ,Sampled input data" group.long 0x13C++0x3 line.long 0x00 "GPIO_DATAOUT,Data output register (data to set on output pins)." hexmask.long 0x00 0.--31. 1. " DATAOUT ,Data to set on output pins" group.long 0x140++0x3 line.long 0x00 "GPIO_LEVELDETECT0,Detect low-level register. 0: Low-level detection disabled; 1: Low-level detection enabled" hexmask.long 0x00 0.--31. 1. " LEVELDETECT0 ,Low-level detection - . - ." group.long 0x144++0x3 line.long 0x00 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x00 0.--31. 1. " LEVELDETECT1 ,- . - ." group.long 0x148++0x3 line.long 0x00 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x00 0.--31. 1. " RISINGDETECT ,- . - ." group.long 0x14C++0x3 line.long 0x00 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x00 0.--31. 1. " FALLINGDETECT ,- . - ." group.long 0x150++0x3 line.long 0x00 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x00 0.--31. 1. " DEBOUNCEENABLE ,- . - ." group.long 0x154++0x3 line.long 0x00 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time in 31 ?s steps" group.long 0x180++0x3 line.long 0x00 "GPIO_CLEARWKUPENA,Clear wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x184++0x3 line.long 0x00 "GPIO_SETWKUENA,Set wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x190++0x3 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." group.long 0x194++0x3 line.long 0x00 "GPIO_SETDATAOUT,Set data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." tree.end tree "GPIO5" base ad:0x4805B000 width 22. rgroup.long 0x0++0x3 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,0x0: Force-idle: An idle request is acknowledged unconditionally. - . - . - ." "0,No_Idle,Smart_Idle,Smart_Idle_Wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,OCP clock gating control. - . - ." "Free_Run,Automatic" group.long 0x24++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x28++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x2C++0x3 line.long 0x00 "GPIO_IRQSTATUS_0,Per-event interrupt status vector (enabled) (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x30++0x3 line.long 0x00 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x34++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_0,Per-event interrupt enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x38++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x3C++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x40++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x44++0x3 line.long 0x00 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." group.long 0x48++0x3 line.long 0x00 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." rgroup.long 0x114++0x3 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,- . - ." "In_Progress,Completed" group.long 0x120++0x3 line.long 0x00 "GPIO_WAKEUPENABLE,Wake-up enable register (legacy) for first line of interrupt" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wake-up enable for interrupt lineCaution:This register is kept for backward software compatibility. Use and instead.. - . Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled o.." group.long 0x130++0x3 line.long 0x00 "GPIO_CTRL,GPIO control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Clock gating ratio for event detection - . - . - . - ." "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,- . - ." "No,Yes" group.long 0x134++0x3 line.long 0x00 "GPIO_OE,Output enable register. 0: Output enabled ; 1: Output disabled" hexmask.long 0x00 0.--31. 1. " OUTPUTEN ,Output enable - . - ." rgroup.long 0x138++0x3 line.long 0x00 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x00 0.--31. 1. " DATAIN ,Sampled input data" group.long 0x13C++0x3 line.long 0x00 "GPIO_DATAOUT,Data output register (data to set on output pins)." hexmask.long 0x00 0.--31. 1. " DATAOUT ,Data to set on output pins" group.long 0x140++0x3 line.long 0x00 "GPIO_LEVELDETECT0,Detect low-level register. 0: Low-level detection disabled; 1: Low-level detection enabled" hexmask.long 0x00 0.--31. 1. " LEVELDETECT0 ,Low-level detection - . - ." group.long 0x144++0x3 line.long 0x00 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x00 0.--31. 1. " LEVELDETECT1 ,- . - ." group.long 0x148++0x3 line.long 0x00 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x00 0.--31. 1. " RISINGDETECT ,- . - ." group.long 0x14C++0x3 line.long 0x00 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x00 0.--31. 1. " FALLINGDETECT ,- . - ." group.long 0x150++0x3 line.long 0x00 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x00 0.--31. 1. " DEBOUNCEENABLE ,- . - ." group.long 0x154++0x3 line.long 0x00 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time in 31 ?s steps" group.long 0x180++0x3 line.long 0x00 "GPIO_CLEARWKUPENA,Clear wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x184++0x3 line.long 0x00 "GPIO_SETWKUENA,Set wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x190++0x3 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." group.long 0x194++0x3 line.long 0x00 "GPIO_SETDATAOUT,Set data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." tree.end tree "GPIO6" base ad:0x4805D000 width 22. rgroup.long 0x0++0x3 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,0x0: Force-idle: An idle request is acknowledged unconditionally. - . - . - ." "0,No_Idle,Smart_Idle,Smart_Idle_Wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,OCP clock gating control. - . - ." "Free_Run,Automatic" group.long 0x24++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x28++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x2C++0x3 line.long 0x00 "GPIO_IRQSTATUS_0,Per-event interrupt status vector (enabled) (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x30++0x3 line.long 0x00 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x34++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_0,Per-event interrupt enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x38++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x3C++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x40++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x44++0x3 line.long 0x00 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." group.long 0x48++0x3 line.long 0x00 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." rgroup.long 0x114++0x3 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,- . - ." "In_Progress,Completed" group.long 0x120++0x3 line.long 0x00 "GPIO_WAKEUPENABLE,Wake-up enable register (legacy) for first line of interrupt" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wake-up enable for interrupt lineCaution:This register is kept for backward software compatibility. Use and instead.. - . Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled o.." group.long 0x130++0x3 line.long 0x00 "GPIO_CTRL,GPIO control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Clock gating ratio for event detection - . - . - . - ." "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,- . - ." "No,Yes" group.long 0x134++0x3 line.long 0x00 "GPIO_OE,Output enable register. 0: Output enabled ; 1: Output disabled" hexmask.long 0x00 0.--31. 1. " OUTPUTEN ,Output enable - . - ." rgroup.long 0x138++0x3 line.long 0x00 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x00 0.--31. 1. " DATAIN ,Sampled input data" group.long 0x13C++0x3 line.long 0x00 "GPIO_DATAOUT,Data output register (data to set on output pins)." hexmask.long 0x00 0.--31. 1. " DATAOUT ,Data to set on output pins" group.long 0x140++0x3 line.long 0x00 "GPIO_LEVELDETECT0,Detect low-level register. 0: Low-level detection disabled; 1: Low-level detection enabled" hexmask.long 0x00 0.--31. 1. " LEVELDETECT0 ,Low-level detection - . - ." group.long 0x144++0x3 line.long 0x00 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x00 0.--31. 1. " LEVELDETECT1 ,- . - ." group.long 0x148++0x3 line.long 0x00 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x00 0.--31. 1. " RISINGDETECT ,- . - ." group.long 0x14C++0x3 line.long 0x00 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x00 0.--31. 1. " FALLINGDETECT ,- . - ." group.long 0x150++0x3 line.long 0x00 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x00 0.--31. 1. " DEBOUNCEENABLE ,- . - ." group.long 0x154++0x3 line.long 0x00 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time in 31 ?s steps" group.long 0x180++0x3 line.long 0x00 "GPIO_CLEARWKUPENA,Clear wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x184++0x3 line.long 0x00 "GPIO_SETWKUENA,Set wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x190++0x3 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." group.long 0x194++0x3 line.long 0x00 "GPIO_SETDATAOUT,Set data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." tree.end tree "GPIO1" base ad:0x4A310000 width 22. rgroup.long 0x0++0x3 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. " IDLEMODE ,0x0: Force-idle: An idle request is acknowledged unconditionally. - . - . - ." "0,No_Idle,Smart_Idle,Smart_Idle_Wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up control - . - ." "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0. - . - ." "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,OCP clock gating control. - . - ." "Free_Run,Automatic" group.long 0x24++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x28++0x3 line.long 0x00 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status raw for interrupt line" group.long 0x2C++0x3 line.long 0x00 "GPIO_IRQSTATUS_0,Per-event interrupt status vector (enabled) (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x30++0x3 line.long 0x00 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status for interrupt line" group.long 0x34++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_0,Per-event interrupt enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x38++0x3 line.long 0x00 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status set for interrupt line" group.long 0x3C++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x40++0x3 line.long 0x00 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Status clear for interrupt line" group.long 0x44++0x3 line.long 0x00 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." group.long 0x48++0x3 line.long 0x00 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wakeup set for interrupt line - . - ." rgroup.long 0x114++0x3 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,- . - ." "In_Progress,Completed" group.long 0x120++0x3 line.long 0x00 "GPIO_WAKEUPENABLE,Wake-up enable register (legacy) for first line of interrupt" hexmask.long 0x00 0.--31. 1. " INTLINE ,Wake-up enable for interrupt lineCaution:This register is kept for backward software compatibility. Use and instead.. - . Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled o.." group.long 0x130++0x3 line.long 0x00 "GPIO_CTRL,GPIO control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Clock gating ratio for event detection - . - . - . - ." "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,- . - ." "No,Yes" group.long 0x134++0x3 line.long 0x00 "GPIO_OE,Output enable register. 0: Output enabled ; 1: Output disabled" hexmask.long 0x00 0.--31. 1. " OUTPUTEN ,Output enable - . - ." rgroup.long 0x138++0x3 line.long 0x00 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x00 0.--31. 1. " DATAIN ,Sampled input data" group.long 0x13C++0x3 line.long 0x00 "GPIO_DATAOUT,Data output register (data to set on output pins)." hexmask.long 0x00 0.--31. 1. " DATAOUT ,Data to set on output pins" group.long 0x140++0x3 line.long 0x00 "GPIO_LEVELDETECT0,Detect low-level register. 0: Low-level detection disabled; 1: Low-level detection enabled" hexmask.long 0x00 0.--31. 1. " LEVELDETECT0 ,Low-level detection - . - ." group.long 0x144++0x3 line.long 0x00 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x00 0.--31. 1. " LEVELDETECT1 ,- . - ." group.long 0x148++0x3 line.long 0x00 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x00 0.--31. 1. " RISINGDETECT ,- . - ." group.long 0x14C++0x3 line.long 0x00 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x00 0.--31. 1. " FALLINGDETECT ,- . - ." group.long 0x150++0x3 line.long 0x00 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x00 0.--31. 1. " DEBOUNCEENABLE ,- . - ." group.long 0x154++0x3 line.long 0x00 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time in 31 ?s steps" group.long 0x180++0x3 line.long 0x00 "GPIO_CLEARWKUPENA,Clear wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x184++0x3 line.long 0x00 "GPIO_SETWKUENA,Set wake-up-enable register ? legacy register" hexmask.long 0x00 0.--31. 1. " INTLINE ,This register is kept for backward software compatibility. Use GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 instead.Caution: A wake-up event can be enabled using a legacy register as well as the new one, but it must be disabled only through the.." group.long 0x190++0x3 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." group.long 0x194++0x3 line.long 0x00 "GPIO_SETDATAOUT,Set data output register" hexmask.long 0x00 0.--31. 1. " INTLINE ,- . - ." tree.end tree.end tree.end tree.open "Keyboard_Controller" tree "Keyboard_Controller" base ad:0x4A31C000 width 20. rgroup.long 0x0++0x3 line.long 0x00 "KBD_REVISION,This register contains the IP revision code." hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" group.long 0x10++0x3 line.long 0x00 "KBD_SYSCONFIG,This register controls the various parameters of the L4 interface." bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock(s) activity during wake-up mode period. - . - . - . - ." "ClockActivity0,ClockActivity1,ClockActivity2,ClockActivity3" bitfld.long 0x00 5. " EMUFREE ,Emulation mode - . - ." "module_frozen,module_free" bitfld.long 0x00 3.--4. " IDLEMODE ,Power management, req/ack control - . - . - . - ." "force_idle,no_idle,smart_idle,?..." textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control - . - ." "disable_wakeup,enable_wakeup" bitfld.long 0x00 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0. - . - ." "normal_mode,reset_mode" bitfld.long 0x00 0. " AUTOGATING ,Internal L4 interface clock gating strategy - . - ." "clkfree,clkgate" rgroup.long 0x14++0x3 line.long 0x00 "KBD_SYSSTATUS,This register controls optional features specific to the timer function." bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring - . - ." "rstongoing,rstcompleted" group.long 0x18++0x3 line.long 0x00 "KBD_IRQSTATUS,The keyboard interrupt-status register is used to determine which of the keyboard events requested an interrupt." bitfld.long 0x00 3. " MISS_EVENT ,Indicates when a miss event occurs. - . - ." "MISS_EVENT_0,MISS_EVENT_1" bitfld.long 0x00 2. " IT_TIMEOUT ,Indicates when a time-out event is detected. - . - ." "IT_TIMEOUT_0,IT_TIMEOUT_1" bitfld.long 0x00 1. " IT_LONG_KEY ,Indicates when a long-key event is detected. - . - ." "IT_LONG_KEY_0,IT_LONG_KEY_1" textline " " bitfld.long 0x00 0. " IT_EVENT ,Indicates when an event is detected. - . - ." "IT_EVENT_0,IT_EVENT_1" group.long 0x1C++0x3 line.long 0x00 "KBD_IRQENABLE,The keyboard interrupt-enable register lets the user enable certain keyboard event for generating an interrupt request." bitfld.long 0x00 2. " IT_TIMEOUT_EN ,Time-out interrupt enable - . - ." "IT_TIMEOUT_EN_0,IT_TIMEOUT_EN_1" bitfld.long 0x00 1. " IT_LONG_KEY_EN ,Long-key interrupt enable - . - ." "IT_LONG_KEY_EN_0,IT_LONG_KEY_EN_1" bitfld.long 0x00 0. " IT_EVENT_EN ,Enable event interrupt - . - ." "IT_EVENT_EN_0,IT_EVENT_EN_1" group.long 0x20++0x3 line.long 0x00 "KBD_WAKEUPENABLE,The keyboard wake-up enable register lets the user mask the expected source of wake-up event that generates a wake-up request." bitfld.long 0x00 2. " WUP_TIMEOUT_ENA ,Time-out wake-up enable - . - ." "WUP_TIMEOUT_ENA_0,WUP_TIMEOUT_ENA_1" bitfld.long 0x00 1. " WUP_LONG_KEY_ENA ,Long-key wake-up enable - . - ." "WUP_LONG_KEY_ENA_0,WUP_LONG_KEY_ENA_1" bitfld.long 0x00 0. " WUP_EVENT_ENA ,Event wake-up enable - . - ." "WUP_EVENT_ENA_0,WUP_EVENT_ENA_1" rgroup.long 0x24++0x3 line.long 0x00 "KBD_PENDING,Software must read the pending write bits to ensure that following write access is not discarded due to ongoing write synchronization process." bitfld.long 0x00 3. " PEND_TIMEOUT ,Write-pending bit forKBD_TIMEOUT register - . - ." "PEND_TIMEOUT_0,PEND_TIMEOUT_1" bitfld.long 0x00 2. " PEND_LONG_KEY ,Write-pending bit forKBD_KEYLONGTIME register - . - ." "PEND_LONGKEY_0,PEND_LONGKEY_1" bitfld.long 0x00 1. " PEND_DEBOUNCING ,Write-pending bit forKBD_DEBOUNCINGTIME register - . - ." "PEND_DEBOUNCING_0,PEND_DEBOUNCING_1" textline " " bitfld.long 0x00 0. " PEND_CTRL ,Write pending bit forKBD_CTRL register - . - ." "PEND_CTRL_0,PEND_CTRL_1" group.long 0x28++0x3 line.long 0x00 "KBD_CTRL,This register sets the functional configuration of the module." bitfld.long 0x00 8. " REPEAT_MODE ,Repeat mode enable - . - ." "REPEAT_MODE_0,REPEAT_MODE_1" bitfld.long 0x00 7. " TIMEOUT_LONG_KEY ,Time-out long key mode enable - . - ." "TIMEOUT_LONG_KEY_0,TIMEOUT_LONG_KEY_1" bitfld.long 0x00 6. " TIMEOUT_EMPTY ,Time-out empty mode enable - . - ." "TIMEOUT_EMPTY_0,TIMEOUT_EMPTY_1" textline " " bitfld.long 0x00 5. " LONG_KEY ,Long-key mode enable. - . - ." "LONG_KEY_0,LONG_KEY_1" bitfld.long 0x00 2.--4. " PTV ,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " NSOFTWARE_MODE ,Select hardware or software mode for key decoding. - . - ." "NSOFTWARE_MODE_0,NSOFTWARE_MODE_1" group.long 0x2C++0x3 line.long 0x00 "KBD_DEBOUNCINGTIME,This register is used to filter glitches on the press key or release key." bitfld.long 0x00 0.--5. " DEBOUNCING_VALUE ,This value corresponds to the desired value of debouncing time." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30++0x3 line.long 0x00 "KBD_KEYLONGTIME,This register is used to measure duration of a key press to allow shortcut detection." hexmask.long.word 0x00 0.--11. 1. " LONG_KEY_VALUE ,This value corresponds to the desired value of the long-key interrupt or repeat mode value." group.long 0x34++0x3 line.long 0x00 "KBD_TIMEOUT,This register is used to detect a long inactivity on the keyboard." hexmask.long.word 0x00 0.--15. 1. " TIMEOUT_VALUE ,This value corresponds to the desired value of the time-out interrupt." rgroup.long 0x38++0x3 line.long 0x00 "KBD_STATEMACHINE,This register indicates the state of the sequencer." bitfld.long 0x00 0.--3. " STATE_MACHINE ,The state of internal state machine. See, for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x3C++0x3 line.long 0x00 "KBD_ROWINPUTS,This register stores the value of the row inputs." hexmask.long.word 0x00 0.--8. 1. " KBR_LATCH ,The value of the rows input." group.long 0x40++0x3 line.long 0x00 "KBD_COLUMNOUTPUTS,This register holds the value of the columns output." hexmask.long.word 0x00 0.--8. 1. " KBC_REG ,The value of the columns output" rgroup.long 0x44++0x3 line.long 0x00 "KBD_FULLCODE31_0,The register codes the row 0, row 1, row 2, and row 3." hexmask.long 0x00 0.--31. 1. " FULL_CODE_31_0 ,A bit set to 1 indicates that the corresponding key is pressed." rgroup.long 0x48++0x3 line.long 0x00 "KBD_FULLCODE63_32,The register codes rows 4, 5, 6, and 7." hexmask.long 0x00 0.--31. 1. " FULL_CODE_63_32 ,A bit set to 1 indicates that the corresponding key is pressed." rgroup.long 0x4C++0x3 line.long 0x00 "KBD_FULLCODE17_0,The register codes row 0 and row 1. Row 0 is coded between bit 0 and 8; row 1 is coded between bit 24 and 16." hexmask.long.word 0x00 16.--24. 1. " ROW1 ,A bit set to 1 indicates that the corresponding key is pressed." hexmask.long.word 0x00 0.--8. 1. " ROW0 ,A bit set to 1 indicates that the corresponding key is pressed." rgroup.long 0x50++0x3 line.long 0x00 "KBD_FULLCODE35_18,The register codes row 2 and row 3. Row 2 is coded between bit 0 and 8; row 3 is coded between bit 24 and 16" hexmask.long.word 0x00 16.--24. 1. " ROW3 ,A bit set to 1 indicates that the corresponding key is pressed." hexmask.long.word 0x00 0.--8. 1. " ROW2 ,A bit set to 1 indicates that the corresponding key is pressed." rgroup.long 0x54++0x3 line.long 0x00 "KBD_FULLCODE53_36,The register codes row 4 and row 5. Row 4 is coded between bit 0 and 8; row 5 is coded between bit 24 and 16." hexmask.long.word 0x00 16.--24. 1. " ROW5 ,A bit set to 1 indicates that the corresponding key is pressed." hexmask.long.word 0x00 0.--8. 1. " ROW4 ,A bit set to 1 indicates that the corresponding key is pressed." rgroup.long 0x58++0x3 line.long 0x00 "KBD_FULLCODE71_54,The register codes row 6 and row 7. Row 6 is coded between bit 0 and 8; row 7 is coded between bit 24 and 16." hexmask.long.word 0x00 16.--24. 1. " ROW7 ,A bit set to 1 indicates that the corresponding key is pressed." hexmask.long.word 0x00 0.--8. 1. " ROW6 ,A bit set to 1 indicates that the corresponding key is pressed." rgroup.long 0x5C++0x3 line.long 0x00 "KBD_FULLCODE80_72,The register codes row 8. Row 8 is coded between bit 0 and 8." hexmask.long.word 0x00 0.--8. 1. " ROW8 ,A bit set to 1 indicates that the corresponding key is pressed." tree.end tree.end tree.open "HSI" tree "HSI_TOP" base ad:0x4A058000 width 23. rgroup.long 0x0++0x3 line.long 0x00 "HSI_REVISION,IP Revision Identifier (X.Y.R)Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" rgroup.long 0x4++0x3 line.long 0x00 "HSI_HWINFO,Information about the IP module's hardware configuration, i.e. typically the module's HDL generics (if any).Actual field format and encoding is decided by the module's designer." hexmask.long 0x00 0.--31. 1. " HWINFO ,IP module hardware configuration" group.long 0x10++0x3 line.long 0x00 "HSI_SYSCONFIG,This register allows controlling various parameters of the L4_CFG interface" bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management, standby/wait control - . - . - . - ." "FORCE_STDBY,NO_STDBY,SMART_STDBY,SMART_STDBY_WKUP" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management, request/acknowledgement control - . - . - . - ." "FORCE_IDLE,NO_IDLE,SMART_IDLE,SMAR_IDLE_WKUP" bitfld.long 0x00 2. " FREE_EMU ,Sensitivity to emulation (debug) suspend input signal - . - ." "EMUL,NO_EMUL" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset - . - ." "NORST,SWRST" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy - . - ." "FREERUN,AUTOGATE" rgroup.long 0x14++0x3 line.long 0x00 "HSI_SYSSTATUS,Status on module, (reset done on bit 0, available for more status info)" hexmask.long 0x00 0.--31. 1. " RESETDONE ,Internal reset monitoring - . - ." group.long 0x408++0x3 line.long 0x00 "HSI_P1_M_IRQ0U_STATUS,IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWri.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on any channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on any channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error detected on any channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)." hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x40C++0x3 line.long 0x00 "HSI_P1_M_IRQ0U_ENABLE,IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for all channels 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for all channels 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for all channels 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x410++0x3 line.long 0x00 "HSI_P1_M_IRQ1U_STATUS,IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWri.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on any channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on any channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error detected on any channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)." hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x414++0x3 line.long 0x00 "HSI_P1_M_IRQ1U_ENABLE,IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for all channels 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for all channels 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for all channels 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x418++0x3 line.long 0x00 "HSI_P2_M_IRQ0U_STATUS,IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWri.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on any channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on any channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error detected on any channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)." hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x41C++0x3 line.long 0x00 "HSI_P2_M_IRQ0U_ENABLE,IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for all channels 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for all channels 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for all channels 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x420++0x3 line.long 0x00 "HSI_P2_M_IRQ1U_STATUS,IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWri.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on any channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on any channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error detected on any channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)." hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x424++0x3 line.long 0x00 "HSI_P2_M_IRQ1U_ENABLE,IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for all channels 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for all channels 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for all channels 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x430++0x3 line.long 0x00 "HSI_P1_D_IRQ0U_STATUS,IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWri.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on any channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on any channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on any channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x434++0x3 line.long 0x00 "HSI_P1_D_IRQ0U_ENABLE,IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 8..15" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x438++0x3 line.long 0x00 "HSI_P1_D_IRQ1U_STATUS,IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWri.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on any channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on any channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on any channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x43C++0x3 line.long 0x00 "HSI_P1_D_IRQ1U_ENABLE,IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 8..15" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x440++0x3 line.long 0x00 "HSI_P2_D_IRQ0U_STATUS,IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWri.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on any channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on any channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on any channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x444++0x3 line.long 0x00 "HSI_P2_D_IRQ0U_ENABLE,IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 8..15" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x448++0x3 line.long 0x00 "HSI_P2_D_IRQ1U_STATUS,IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWri.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on any channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on any channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on any channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x44C++0x3 line.long 0x00 "HSI_P2_D_IRQ1U_ENABLE,IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for channel 8..15" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for channel 8..15" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for channel 8..15" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 8..15" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)" group.long 0x800++0x3 line.long 0x00 "HSI_DMA_M_IRQSTATUS,This register collects status for all of the DMA events able to generate interrupt to MPU:Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" hexmask.long.word 0x00 0.--15. 1. " DMA_CHI ,Channel i status (LSB stands for channel 0 and MSB for channel 15)" group.long 0x804++0x3 line.long 0x00 "HSI_DMA_M_IRQENABLE,This register masks and unmasks DMA sources of interrupt to MPU:Write 0: event is maskedWrite 1: event is enabled" hexmask.long.word 0x00 0.--15. 1. " DMA_EN_CHI ,Channel i (LSB stands for channel 0 and MSB for channel 15)" group.long 0x808++0x3 line.long 0x00 "HSI_P1_M_IRQ0_STATUS,IRQ status register for FIFO (0..7) events and for port p break, wake and error events Events will signal interrupt for MPU line r (Mpuirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite .." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x80C++0x3 line.long 0x00 "HSI_P1_M_IRQ0_ENABLE,IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to MPU line r (Mpuirq_r).Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x810++0x3 line.long 0x00 "HSI_P1_M_IRQ1_STATUS,IRQ status register for FIFO (0..7) events and for port p break, wake and error events Events will signal interrupt for MPU line r (Mpuirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite .." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x814++0x3 line.long 0x00 "HSI_P1_M_IRQ1_ENABLE,IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to MPU line r (Mpuirq_r).Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x818++0x3 line.long 0x00 "HSI_P2_M_IRQ0_STATUS,IRQ status register for FIFO (0..7) events and for port p break, wake and error events Events will signal interrupt for MPU line r (Mpuirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite .." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x81C++0x3 line.long 0x00 "HSI_P2_M_IRQ0_ENABLE,IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to MPU line r (Mpuirq_r).Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x820++0x3 line.long 0x00 "HSI_P2_M_IRQ1_STATUS,IRQ status register for FIFO (0..7) events and for port p break, wake and error events Events will signal interrupt for MPU line r (Mpuirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite .." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x824++0x3 line.long 0x00 "HSI_P2_M_IRQ1_ENABLE,IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to MPU line r (Mpuirq_r).Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x828++0x3 line.long 0x00 "HSI_DMA_D_IRQSTATUS,IRQ status register for all DMA events. Events will generate interrupt for DSP.Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" hexmask.long.word 0x00 0.--15. 1. " DMA_CHI ,IRQ event happened on DMA channel i (LSB stands for channel 0 and MSB for channel 15)" group.long 0x82C++0x3 line.long 0x00 "HSI_DMA_D_IRQENABLE,IRQ enable register for all DMA events signaled to DSP..Write 0: event is maskedWrite 1: event is enabled" hexmask.long.word 0x00 0.--15. 1. " DMA_EN_CHI ,Channel i (LSB stands for channel 0 and MSB for channel 15)" group.long 0x830++0x3 line.long 0x00 "HSI_P1_D_IRQ0_STATUS,IRQ status register for FIFO (0..7) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r).Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrit.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x834++0x3 line.long 0x00 "HSI_P1_D_IRQ0_ENABLE,IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x838++0x3 line.long 0x00 "HSI_P1_D_IRQ1_STATUS,IRQ status register for FIFO (0..7) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r).Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrit.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x83C++0x3 line.long 0x00 "HSI_P1_D_IRQ1_ENABLE,IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x840++0x3 line.long 0x00 "HSI_P2_D_IRQ0_STATUS,IRQ status register for FIFO (0..7) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r).Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrit.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x844++0x3 line.long 0x00 "HSI_P2_D_IRQ0_ENABLE,IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x848++0x3 line.long 0x00 "HSI_P2_D_IRQ1_STATUS,IRQ status register for FIFO (0..7) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r).Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrit.." bitfld.long 0x00 26. " HSR_WAKE ,Wake detected on Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break detected on Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error on Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_CHI ,Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_CHI ,Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_CHI ,Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" group.long 0x84C++0x3 line.long 0x00 "HSI_P2_D_IRQ1_ENABLE,IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" bitfld.long 0x00 26. " HSR_WAKE ,Wake interrupt enable for Port p" "0,1" bitfld.long 0x00 25. " HSR_BREAK ,Break interrupt enable for Port p" "0,1" bitfld.long 0x00 24. " HSR_ERROR ,Error interrupt enable for Port p" "0,1" textline " " hexmask.long.byte 0x00 16.--23. 1. " HSR_OVERRUN_ENI ,Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 8.--15. 1. " HSR_AVAILABLE_ENI ,Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" hexmask.long.byte 0x00 0.--7. 1. " HST_ACCEPTED_ENI ,Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)" rgroup.long 0xC00++0x3 line.long 0x00 "HSI_P1_WAKE,Programmed wake state for each channel, in port 10x0: no channel wakeup on WAKE line requested0x1: channel wakeup requested" hexmask.long.word 0x00 0.--15. 1. " HSI_WAKE_CHI ,Channel 0..15 (LSB stands for channel 0 and MSB for channel 15)" wgroup.long 0xC04++0x3 line.long 0x00 "HSI_P1_CLEAR_WAKE,Clear register for programmed wake state on port 1 HST_WAKE for each channel0x0: no effect0x1: clears bit" hexmask.long.word 0x00 0.--15. 1. " HSI_CLEAR_WAKE_CHI ,Channel 0..15 (LSB stands for channel 0 and MSB for channel 15)" group.long 0xC08++0x3 line.long 0x00 "HSI_P1_SET_WAKE,Set function for wake state for each channel, in port 10x0: no effect0x1: sets bit" bitfld.long 0x00 17. " HSI_READY_LVL ,READY default level - . - ." "newEnum1,newEnum2" bitfld.long 0x00 16. " HSI_3_WIRES ,Sets 3 wires behavior - . - ." "newEnum2,newEnum1" hexmask.long.word 0x00 0.--15. 1. " HSI_SET_WAKE_CHI ,Sets programmed WAKE state for channel i - . - ." rgroup.long 0xC10++0x3 line.long 0x00 "HSI_P2_WAKE,Programmed wake state for each channel, in port 20x0: no channel wakeup on WAKE line requested0x1: channel wakeup requested" hexmask.long.word 0x00 0.--15. 1. " HSI_WAKE_CHI ,Channel 0..15 (LSB stands for channel 0 and MSB for channel 15)" wgroup.long 0xC14++0x3 line.long 0x00 "HSI_P2_CLEAR_WAKE,Clear register for programmed wake state on port 2 HST_WAKE for each channel0x0: no effect0x1: clears bit" hexmask.long.word 0x00 0.--15. 1. " HSI_CLEAR_WAKE_CHI ,Channel 0..15 (LSB stands for channel 0 and MSB for channel 15)" group.long 0xC18++0x3 line.long 0x00 "HSI_P2_SET_WAKE,Set function for wake state for each channel, in port 20x0: no effect0x1: sets bit" bitfld.long 0x00 17. " HSI_READY_LVL ,READY default level - . - ." "newEnum1,newEnum2" bitfld.long 0x00 16. " HSI_3_WIRES ,Sets 3 wires behavior - . - ." "newEnum2,newEnum1" hexmask.long.word 0x00 0.--15. 1. " HSI_SET_WAKE_CHI ,Sets programmed WAKE state for channel i - . - ." group.long 0x1100++0x3 line.long 0x00 "DMA_GCR,Global Control Register: suspend and clock gating" bitfld.long 0x00 3. " AUTOGATING ,DMA clock autogating enable - . - ." "newEnum1,newEnum2" bitfld.long 0x00 0. " SWITCH_OFF ,DMA global clock control - . - ." "newEnum1,newEnum2" group.long 0x1200++0x3 line.long 0x00 "DMA_GRST,DMA software reset control register" bitfld.long 0x00 0. " SWRESET ,DMA sw reset control bit - ." "0,newEnum1" tree.end tree "HSI_PORTS" base ad:0x4A05A000 tree "Channel_0" width 27. rgroup.long 0x880++0x3 line.long 0x00 "HSR_BUFFER_P1_CHN_i_0,Receive register for receive FIFO 0..7Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3)..." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x1880++0x3 line.long 0x00 "HSR_BUFFER_P2_CHN_i_0,Receive register for receive FIFO 8..15Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3).." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x8C0++0x3 line.long 0x00 "HSR_SWAPBUFFER_P1_CHN_i_0,Byte swapped receive register for receive FIFO 0..7Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read fi.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" rgroup.long 0x18C0++0x3 line.long 0x00 "HSR_SWAPBUFFER_P2_CHN_i_0,Byte swapped receive register for receive FIFO 8..15Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read f.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" wgroup.long 0x80++0x3 line.long 0x00 "HST_BUFFER_P1_CHN_i_0,Transmit register for FIFO 0..7Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). B.." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0x1080++0x3 line.long 0x00 "HST_BUFFER_P2_CHN_i_0,Transmit register for FIFO 8..15Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). .." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0xC0++0x3 line.long 0x00 "HST_SWAPBUFFER_P1_CHN_i_0,Transmit register with byte swapping for FIFO 0..7Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writte.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" wgroup.long 0x10C0++0x3 line.long 0x00 "HST_SWAPBUFFER_P2_CHN_i_0,Transmit register with byte swapping for FIFO 8..15Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writt.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" tree.end tree "Channel_1" width 27. rgroup.long 0x884++0x3 line.long 0x00 "HSR_BUFFER_P1_CHN_i_1,Receive register for receive FIFO 0..7Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3)..." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x1884++0x3 line.long 0x00 "HSR_BUFFER_P2_CHN_i_1,Receive register for receive FIFO 8..15Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3).." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x8C4++0x3 line.long 0x00 "HSR_SWAPBUFFER_P1_CHN_i_1,Byte swapped receive register for receive FIFO 0..7Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read fi.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" rgroup.long 0x18C4++0x3 line.long 0x00 "HSR_SWAPBUFFER_P2_CHN_i_1,Byte swapped receive register for receive FIFO 8..15Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read f.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" wgroup.long 0x84++0x3 line.long 0x00 "HST_BUFFER_P1_CHN_i_1,Transmit register for FIFO 0..7Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). B.." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0x1084++0x3 line.long 0x00 "HST_BUFFER_P2_CHN_i_1,Transmit register for FIFO 8..15Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). .." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0xC4++0x3 line.long 0x00 "HST_SWAPBUFFER_P1_CHN_i_1,Transmit register with byte swapping for FIFO 0..7Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writte.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" wgroup.long 0x10C4++0x3 line.long 0x00 "HST_SWAPBUFFER_P2_CHN_i_1,Transmit register with byte swapping for FIFO 8..15Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writt.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" tree.end tree "Channel_2" width 27. rgroup.long 0x888++0x3 line.long 0x00 "HSR_BUFFER_P1_CHN_i_2,Receive register for receive FIFO 0..7Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3)..." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x1888++0x3 line.long 0x00 "HSR_BUFFER_P2_CHN_i_2,Receive register for receive FIFO 8..15Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3).." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x8C8++0x3 line.long 0x00 "HSR_SWAPBUFFER_P1_CHN_i_2,Byte swapped receive register for receive FIFO 0..7Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read fi.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" rgroup.long 0x18C8++0x3 line.long 0x00 "HSR_SWAPBUFFER_P2_CHN_i_2,Byte swapped receive register for receive FIFO 8..15Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read f.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" wgroup.long 0x88++0x3 line.long 0x00 "HST_BUFFER_P1_CHN_i_2,Transmit register for FIFO 0..7Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). B.." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0x1088++0x3 line.long 0x00 "HST_BUFFER_P2_CHN_i_2,Transmit register for FIFO 8..15Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). .." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0xC8++0x3 line.long 0x00 "HST_SWAPBUFFER_P1_CHN_i_2,Transmit register with byte swapping for FIFO 0..7Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writte.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" wgroup.long 0x10C8++0x3 line.long 0x00 "HST_SWAPBUFFER_P2_CHN_i_2,Transmit register with byte swapping for FIFO 8..15Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writt.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" tree.end tree "Channel_3" width 27. rgroup.long 0x88C++0x3 line.long 0x00 "HSR_BUFFER_P1_CHN_i_3,Receive register for receive FIFO 0..7Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3)..." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x188C++0x3 line.long 0x00 "HSR_BUFFER_P2_CHN_i_3,Receive register for receive FIFO 8..15Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3).." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x8CC++0x3 line.long 0x00 "HSR_SWAPBUFFER_P1_CHN_i_3,Byte swapped receive register for receive FIFO 0..7Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read fi.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" rgroup.long 0x18CC++0x3 line.long 0x00 "HSR_SWAPBUFFER_P2_CHN_i_3,Byte swapped receive register for receive FIFO 8..15Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read f.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" wgroup.long 0x8C++0x3 line.long 0x00 "HST_BUFFER_P1_CHN_i_3,Transmit register for FIFO 0..7Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). B.." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0x108C++0x3 line.long 0x00 "HST_BUFFER_P2_CHN_i_3,Transmit register for FIFO 8..15Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). .." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0xCC++0x3 line.long 0x00 "HST_SWAPBUFFER_P1_CHN_i_3,Transmit register with byte swapping for FIFO 0..7Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writte.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" wgroup.long 0x10CC++0x3 line.long 0x00 "HST_SWAPBUFFER_P2_CHN_i_3,Transmit register with byte swapping for FIFO 8..15Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writt.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" tree.end tree "Channel_4" width 27. rgroup.long 0x890++0x3 line.long 0x00 "HSR_BUFFER_P1_CHN_i_4,Receive register for receive FIFO 0..7Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3)..." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x1890++0x3 line.long 0x00 "HSR_BUFFER_P2_CHN_i_4,Receive register for receive FIFO 8..15Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3).." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x8D0++0x3 line.long 0x00 "HSR_SWAPBUFFER_P1_CHN_i_4,Byte swapped receive register for receive FIFO 0..7Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read fi.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" rgroup.long 0x18D0++0x3 line.long 0x00 "HSR_SWAPBUFFER_P2_CHN_i_4,Byte swapped receive register for receive FIFO 8..15Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read f.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" wgroup.long 0x90++0x3 line.long 0x00 "HST_BUFFER_P1_CHN_i_4,Transmit register for FIFO 0..7Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). B.." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0x1090++0x3 line.long 0x00 "HST_BUFFER_P2_CHN_i_4,Transmit register for FIFO 8..15Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). .." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0xD0++0x3 line.long 0x00 "HST_SWAPBUFFER_P1_CHN_i_4,Transmit register with byte swapping for FIFO 0..7Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writte.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" wgroup.long 0x10D0++0x3 line.long 0x00 "HST_SWAPBUFFER_P2_CHN_i_4,Transmit register with byte swapping for FIFO 8..15Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writt.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" tree.end tree "Channel_5" width 27. rgroup.long 0x894++0x3 line.long 0x00 "HSR_BUFFER_P1_CHN_i_5,Receive register for receive FIFO 0..7Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3)..." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x1894++0x3 line.long 0x00 "HSR_BUFFER_P2_CHN_i_5,Receive register for receive FIFO 8..15Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3).." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x8D4++0x3 line.long 0x00 "HSR_SWAPBUFFER_P1_CHN_i_5,Byte swapped receive register for receive FIFO 0..7Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read fi.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" rgroup.long 0x18D4++0x3 line.long 0x00 "HSR_SWAPBUFFER_P2_CHN_i_5,Byte swapped receive register for receive FIFO 8..15Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read f.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" wgroup.long 0x94++0x3 line.long 0x00 "HST_BUFFER_P1_CHN_i_5,Transmit register for FIFO 0..7Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). B.." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0x1094++0x3 line.long 0x00 "HST_BUFFER_P2_CHN_i_5,Transmit register for FIFO 8..15Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). .." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0xD4++0x3 line.long 0x00 "HST_SWAPBUFFER_P1_CHN_i_5,Transmit register with byte swapping for FIFO 0..7Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writte.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" wgroup.long 0x10D4++0x3 line.long 0x00 "HST_SWAPBUFFER_P2_CHN_i_5,Transmit register with byte swapping for FIFO 8..15Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writt.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" tree.end tree "Channel_6" width 27. rgroup.long 0x898++0x3 line.long 0x00 "HSR_BUFFER_P1_CHN_i_6,Receive register for receive FIFO 0..7Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3)..." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x1898++0x3 line.long 0x00 "HSR_BUFFER_P2_CHN_i_6,Receive register for receive FIFO 8..15Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3).." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x8D8++0x3 line.long 0x00 "HSR_SWAPBUFFER_P1_CHN_i_6,Byte swapped receive register for receive FIFO 0..7Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read fi.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" rgroup.long 0x18D8++0x3 line.long 0x00 "HSR_SWAPBUFFER_P2_CHN_i_6,Byte swapped receive register for receive FIFO 8..15Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read f.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" wgroup.long 0x98++0x3 line.long 0x00 "HST_BUFFER_P1_CHN_i_6,Transmit register for FIFO 0..7Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). B.." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0x1098++0x3 line.long 0x00 "HST_BUFFER_P2_CHN_i_6,Transmit register for FIFO 8..15Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). .." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0xD8++0x3 line.long 0x00 "HST_SWAPBUFFER_P1_CHN_i_6,Transmit register with byte swapping for FIFO 0..7Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writte.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" wgroup.long 0x10D8++0x3 line.long 0x00 "HST_SWAPBUFFER_P2_CHN_i_6,Transmit register with byte swapping for FIFO 8..15Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writt.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" tree.end tree "Channel_7" width 27. rgroup.long 0x89C++0x3 line.long 0x00 "HSR_BUFFER_P1_CHN_i_7,Receive register for receive FIFO 0..7Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3)..." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x189C++0x3 line.long 0x00 "HSR_BUFFER_P2_CHN_i_7,Receive register for receive FIFO 8..15Important:Read access to the register with 0xC and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the lower 2 bytes must be read first (byteen 0x3).." hexmask.long 0x00 0.--31. 1. " DATA ,Received data" rgroup.long 0x8DC++0x3 line.long 0x00 "HSR_SWAPBUFFER_P1_CHN_i_7,Byte swapped receive register for receive FIFO 0..7Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read fi.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" rgroup.long 0x18DC++0x3 line.long 0x00 "HSR_SWAPBUFFER_P2_CHN_i_7,Byte swapped receive register for receive FIFO 8..15Important:Read access to the register with 0x3 and 0xF byteen will remove the receive FIFO related item.In case of using only 16 bit accesses the upper 2 bytes must be read f.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,Received data swapped" wgroup.long 0x9C++0x3 line.long 0x00 "HST_BUFFER_P1_CHN_i_7,Transmit register for FIFO 0..7Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). B.." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0x109C++0x3 line.long 0x00 "HST_BUFFER_P2_CHN_i_7,Transmit register for FIFO 8..15Important:Write access to the register with 0xC and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the lower 2 bytes must be written first (byteen 0x3). .." hexmask.long 0x00 0.--31. 1. " DATA ,32 bits of data" wgroup.long 0xDC++0x3 line.long 0x00 "HST_SWAPBUFFER_P1_CHN_i_7,Transmit register with byte swapping for FIFO 0..7Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writte.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" wgroup.long 0x10DC++0x3 line.long 0x00 "HST_SWAPBUFFER_P2_CHN_i_7,Transmit register with byte swapping for FIFO 8..15Important:Write access to the register with 0x3 and 0xF byteen will load its value into the transmit FIFO.In case of using only 16 bit accesses the upper 2 bytes must be writt.." hexmask.long 0x00 0.--31. 1. " SWAPDATA ,32 bits of byte-swapped data" tree.end textline "" width 19. rgroup.long 0x0++0x3 line.long 0x00 "HST_ID_P1,legacy identification on port 1" hexmask.long 0x00 0.--31. 1. " ID_VAL ,Legacy ID" group.long 0x4++0x3 line.long 0x00 "HST_MODE_P1,Defines operation mode and data flow on port 1" bitfld.long 0x00 4. " WAKE_CTRL ,Wake control - . - ." "0,1" bitfld.long 0x00 2.--3. " FLOW_VAL ,Flow - . - . - ." "SYNCHRONIZED,PIPELINED,REAL_TIME,3" bitfld.long 0x00 0.--1. " MODE_VAL ,Mode - . - . - . - ." "SLEEP,STREAM,FRAME,newEnum4" rgroup.long 0x8++0x3 line.long 0x00 "HST_FRAMESIZE_P1,This register is provided for legacy and possible future extension of protocol. Returns 0x1f" bitfld.long 0x00 0.--4. " SIZE_VAL ,In the current implementation it must be always written 31, meaning the frame payload size is 32 bit. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,newEnum1" rgroup.long 0xC++0x3 line.long 0x00 "HST_TXSTATE_P1,Define the state of the transmitter on port 1" bitfld.long 0x00 0.--2. " TXSTATEVAL ,State of the transmitter - . - . - . - . - . - . - . - ." "IDLE,WAIT,TRANSMIT,START,BREAK,newEnum6,newEnum7,newEnum8" rgroup.long 0x10++0x3 line.long 0x00 "HST_BUFSTATE_P1,Transmitter state for FIFO 0..7Each bit gives the state of transmit FIFOs:0x1 FIFO full0x0 FIFO not full" hexmask.long.byte 0x00 0.--7. 1. " BUFSTATE_VAL ,Each bit gives the state of transmit buffer register:0x0: buffer is not full0x1: buffer is full" group.long 0x18++0x3 line.long 0x00 "HST_DIVISOR_P1,Transmission bit rate divisor for port 1" hexmask.long.byte 0x00 0.--7. 1. " TX_RATE_DIV_VAL ,This bitfield B has a range [0..255] and it programs a division factor [1..256], B+1 example: writing 0 divides by 1, writing 1 divides by 2, writing 2 divides by 3, etc" wgroup.long 0x20++0x3 line.long 0x00 "HST_BREAK_P1,Transmit break strobe register on port 1" bitfld.long 0x00 0. " BREAK_VAL ,Send a break signal on the port - . - ." "0,1" group.long 0x24++0x3 line.long 0x00 "HST_CHANNELS_P1,Number of active channels on port 1 (this will determine the number of the used channel descriptor bits on the MIPI port as well)It can be 1,2,4,8 or 16." bitfld.long 0x00 0.--4. " CHAN_NUM_VAL ,Number of active channels up to 16 - . - . - . - . - ." "0,ONE,2,3,FOUR,5,6,7,EIGHT,9,10,11,12,13,14,15,SIXTEEN,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x3 line.long 0x00 "HST_ARBMODE_P1,Arbitration type for the transmit FIFOs on port 1." bitfld.long 0x00 0. " ARB_VAL ,Mode - . - ." "ROUND_ROBIN,PRIORITY" group.long 0x100++0x3 line.long 0x00 "HST_MAPPING0,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x104++0x3 line.long 0x00 "HST_MAPPING1,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x108++0x3 line.long 0x00 "HST_MAPPING2,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x10C++0x3 line.long 0x00 "HST_MAPPING3,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x110++0x3 line.long 0x00 "HST_MAPPING4,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x114++0x3 line.long 0x00 "HST_MAPPING5,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x118++0x3 line.long 0x00 "HST_MAPPING6,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x11C++0x3 line.long 0x00 "HST_MAPPING7,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x120++0x3 line.long 0x00 "HST_MAPPING8,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x124++0x3 line.long 0x00 "HST_MAPPING9,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "newEnum1,newEnum2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "newEnum1,newEnum2" group.long 0x128++0x3 line.long 0x00 "HST_MAPPING10,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "disabled,enabled" group.long 0x12C++0x3 line.long 0x00 "HST_MAPPING11,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "disabled,enabled" group.long 0x130++0x3 line.long 0x00 "HST_MAPPING12,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "disabled,enabled" group.long 0x134++0x3 line.long 0x00 "HST_MAPPING13,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "disabled,enabled" group.long 0x138++0x3 line.long 0x00 "HST_MAPPING14,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "disabled,enabled" group.long 0x13C++0x3 line.long 0x00 "HST_MAPPING15,TX FIFO configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " THRESHOLD ,Number of empty TX FIFO locations that will activate interrupt or DMA requests. DMA requests (if enabled) or interrupt assertion (if enabled) is triggered if the number of free locations in FIFO is less than the THRESHOLD value. 0x0: .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates the TX FIFO to a HSI logical channel number (0-15):0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables the FIFO - . - ." "disabled,enabled" rgroup.long 0x800++0x3 line.long 0x00 "HSR_ID_P1,Legacy Identification" hexmask.long 0x00 0.--31. 1. " ID_VAL ,Legacy ID" group.long 0x804++0x3 line.long 0x00 "HSR_MODE_P1,Defines operation mode and data flow on port 1" bitfld.long 0x00 4. " WAKE_STATUS ,Level of WAKE line" "0,1" bitfld.long 0x00 2.--3. " FLOW_VAL ,Flow - . - . - ." "SYNCHRONIZED,PIPELINED,REAL_TIME,3" bitfld.long 0x00 0.--1. " MODE_VAL ,Mode - . - . - . - ." "SLEEP,STREAM,FRAME,newEnum4" rgroup.long 0x808++0x3 line.long 0x00 "HSR_FRAMESIZE_P1,legacy returns 0x1f" bitfld.long 0x00 0.--4. " SIZE_VAL ,0x1f" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" rgroup.long 0x80C++0x3 line.long 0x00 "HSR_RXSTATE_P1,Receiver state on port 1" bitfld.long 0x00 0.--2. " RXSTATEVAL ,State - . - . - . - . - . - ." "IDLE,RECEIVING,FINISHED,ERROR,HALT,TIMEOUT,6,7" rgroup.long 0x810++0x3 line.long 0x00 "HSR_BUFSTATE_P1,State of receiver buffer register for port 1" hexmask.long.byte 0x00 0.--7. 1. " BUFSTATE_VAL ,Each bit gives the state of receiver buffer register:0x0: buffer is not full0x1: buffer is full" rgroup.long 0x81C++0x3 line.long 0x00 "HSR_BREAK_P1,Break detected on port 1" bitfld.long 0x00 0. " BREAK_VAL ,Break detected - . - ." "0,1" rgroup.long 0x820++0x3 line.long 0x00 "HSR_ERROR_P1,Error detection state register for port 1" bitfld.long 0x00 11. " TME ,Tx Mapping Error" "0,1" bitfld.long 0x00 7. " RME ,Rx Mapping Error" "0,1" bitfld.long 0x00 4. " TBE ,Tailing Bit Error" "0,1" textline " " bitfld.long 0x00 1. " FTE ,Frame Timeout Error" "0,1" bitfld.long 0x00 0. " SIG ,signal error (legacy)" "0,1" wgroup.long 0x824++0x3 line.long 0x00 "HSR_ERRORACK_P1,Error detection acknowledge register on port 1: write 1 to clear" bitfld.long 0x00 11. " TME ,Tx Mapping Error" "0,1" bitfld.long 0x00 7. " RME ,Rx Mapping Error" "0,1" bitfld.long 0x00 4. " TBE ,Tailing Bit Error" "0,1" textline " " bitfld.long 0x00 1. " FTE ,Frame Timeout Error" "0,1" bitfld.long 0x00 0. " SIG ,signal error (legacy)" "0,1" group.long 0x828++0x3 line.long 0x00 "HSR_CHANNELS_P1,Number of active channels on port 1 (this will determine the number of the used channel descriptor bits on the MIPI port as well)It can be 1,2,4,8 or 16." bitfld.long 0x00 0.--4. " CHAN_NUM_VAL ,Number of active channels - . - . - . - . - ." "0,ONE,TWO,3,FOUR,5,6,7,EIGHT,9,10,11,12,13,14,15,SIXTEEN,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x82C++0x3 line.long 0x00 "HSR_OVERRUN_P1,Overrun detection state register for those receive FIFOs which are mapped to port 1." hexmask.long.word 0x00 0.--15. 1. " OVERRUN_VAL ,Bit n is set when overrun is detected on channel n - . - ." wgroup.long 0x830++0x3 line.long 0x00 "HSR_OVERRUNACK_P1,Overrun acknowledge register for those receive FIFOs which are mapped to port 1." hexmask.long.word 0x00 0.--15. 1. " OVERRUNACK_VAL ,Bit n is set when overrun is acknowledged on channel n - . - ." group.long 0x834++0x3 line.long 0x00 "HSR_COUNTERS_P1,Counters setting register for port 1" hexmask.long.byte 0x00 24.--31. 1. " FB ,Setting for Frame Burst Counter. Set n as a value will result the n+1 counter value." bitfld.long 0x00 20.--23. " TB ,Setting for Tailing Bit Counter. Set n as a value will result the n+1 counter value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--19. 1. " FT ,Setting for Frame Timeout counter. Set n as a value will result the n+1 counter value." group.long 0x900++0x3 line.long 0x00 "HSR_MAPPING0,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x904++0x3 line.long 0x00 "HSR_MAPPING1,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x908++0x3 line.long 0x00 "HSR_MAPPING2,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x90C++0x3 line.long 0x00 "HSR_MAPPING3,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x910++0x3 line.long 0x00 "HSR_MAPPING4,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x914++0x3 line.long 0x00 "HSR_MAPPING5,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x918++0x3 line.long 0x00 "HSR_MAPPING6,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x91C++0x3 line.long 0x00 "HSR_MAPPING7,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x920++0x3 line.long 0x00 "HSR_MAPPING8,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x924++0x3 line.long 0x00 "HSR_MAPPING9,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "value,value1" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "newEnum1,newEnum2" group.long 0x928++0x3 line.long 0x00 "HSR_MAPPING10,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "disabled,enabled" group.long 0x92C++0x3 line.long 0x00 "HSR_MAPPING11,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "disabled,enabled" group.long 0x930++0x3 line.long 0x00 "HSR_MAPPING12,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "disabled,enabled" group.long 0x934++0x3 line.long 0x00 "HSR_MAPPING13,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "disabled,enabled" group.long 0x938++0x3 line.long 0x00 "HSR_MAPPING14,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "disabled,enabled" group.long 0x93C++0x3 line.long 0x00 "HSR_MAPPING15,RX FIFO Configuration register. One register per FIFO" bitfld.long 0x00 10.--13. " WORDS ,Number of words available in the RX FIFO for reading R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " PORT_NUMBER ,Associates the RX FIFO to a HSI port - . - ." "port_1,port_2" bitfld.long 0x00 1.--4. " CH_NUMBER ,Associates RX FIFO to a HSI logical channel0x0: logical channel number 00x1: logical channel number 10xF: logical channel number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " ENABLE ,Enables or disables RX FIFO - . - ." "disabled,enabled" group.long 0x944++0x3 line.long 0x00 "HSR_DLL,?..." group.long 0x94C++0x3 line.long 0x00 "HSR_DIVISOR_P1,Receive bit rate divisor for port 1.This needs to be set for correct protocol timing detection (tailing timeout, frame timeout)." hexmask.long.byte 0x00 0.--7. 1. " RX_RATE_DIV_VAL ,The functional clock source divided by this value will be used as a clock base for the receive counters.Set n as a value will result the n+1 divisor value." rgroup.long 0x1000++0x3 line.long 0x00 "HST_ID_P2,legacy identification on port 2" hexmask.long 0x00 0.--31. 1. " ID_VAL ,Legacy ID" group.long 0x1004++0x3 line.long 0x00 "HST_MODE_P2,Defines operation mode and data flow on port 2" bitfld.long 0x00 4. " WAKE_CTRL ,Wake control - . - ." "0,1" bitfld.long 0x00 2.--3. " FLOW_VAL ,Flow - . - . - ." "SYNCHRONIZED,PIPELINED,REAL_TIME,3" bitfld.long 0x00 0.--1. " MODE_VAL ,Mode - . - . - . - ." "SLEEP,STREAM,FRAME,newEnum4" rgroup.long 0x1008++0x3 line.long 0x00 "HST_FRAMESIZE_P2,This register is provided for legacy and possible future extension of protocol. Returns 0x1f" bitfld.long 0x00 0.--4. " SIZE_VAL ,In the current implementation it must be always written 31, meaning the frame payload size is 32 bit. - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,newEnum1" rgroup.long 0x100C++0x3 line.long 0x00 "HST_TXSTATE_P2,Define the state of the transmitter on port 2" bitfld.long 0x00 0.--2. " TXSTATEVAL ,State of the transmitter - . - . - . - . - . - . - . - ." "IDLE,WAIT,TRANSMIT,START,BREAK,newEnum6,newEnum7,newEnum8" rgroup.long 0x1010++0x3 line.long 0x00 "HST_BUFSTATE_P2,Transmitter state for buffer 8..15Each bit gives the state of transmit FIFOs:0x1 FIFO full0x0 FIFO not full" hexmask.long.byte 0x00 0.--7. 1. " BUFSTATE_VAL ,Each bit gives the state of transmit buffer register:0x0: buffer is not full0x1: buffer is full" group.long 0x1018++0x3 line.long 0x00 "HST_DIVISOR_P2,Transmission bit rate divisor for port 2" hexmask.long.byte 0x00 0.--7. 1. " TX_RATE_DIV_VAL ,This bitfield B has a range [0..255] and it programs a division factor [1..256], B+1 example: writing 0 divides by 1, writing 1 divides by 2, writing 2 divides by 3, etc" wgroup.long 0x1020++0x3 line.long 0x00 "HST_BREAK_P2,Transmit break strobe register on port 2" bitfld.long 0x00 0. " BREAK_VAL ,Send a break signal on the port - . - ." "0,1" group.long 0x1024++0x3 line.long 0x00 "HST_CHANNELS_P2,Number of active channels on port 2 (this will determine the number of the used channel descriptor bits on the MIPI port as well)It can be 1,2,4,8 or 16." bitfld.long 0x00 0.--4. " CHAN_NUM_VAL ,Number of active channels up to 16 - . - . - . - . - ." "0,ONE,2,3,FOUR,5,6,7,EIGHT,9,10,11,12,13,14,15,SIXTEEN,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1028++0x3 line.long 0x00 "HST_ARBMODE_P2,Arbitration type for the transmit FIFOs on port 2." bitfld.long 0x00 0. " ARB_VAL ,Mode - . - ." "ROUND_ROBIN,PRIORITY" rgroup.long 0x1800++0x3 line.long 0x00 "HSR_ID_P2,Legacy Identification" hexmask.long 0x00 0.--31. 1. " ID_VAL ,Legacy ID" group.long 0x1804++0x3 line.long 0x00 "HSR_MODE_P2,Defines operation mode and data flow on port 2" bitfld.long 0x00 4. " WAKE_STATUS ,Level of WAKE line" "0,1" bitfld.long 0x00 2.--3. " FLOW_VAL ,Flow - . - . - ." "SYNCHRONIZED,PIPELINED,REAL_TIME,3" bitfld.long 0x00 0.--1. " MODE_VAL ,Mode - . - . - . - ." "SLEEP,STREAM,FRAME,newEnum4" rgroup.long 0x1808++0x3 line.long 0x00 "HSR_FRAMESIZE_P2,legacy returns 0x1f" bitfld.long 0x00 0.--4. " SIZE_VAL ,0x1f" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO" rgroup.long 0x180C++0x3 line.long 0x00 "HSR_RXSTATE_P2,Receiver state on port 2" bitfld.long 0x00 0.--2. " RXSTATEVAL ,State - . - . - . - . - . - ." "IDLE,RECEIVING,FINISHED,ERROR,HALT,TIMEOUT,6,7" rgroup.long 0x1810++0x3 line.long 0x00 "HSR_BUFSTATE_P2,State of receiver buffer register for port 2" hexmask.long.byte 0x00 0.--7. 1. " BUFSTATE_VAL ,Each bit gives the state of receiver buffer register:0x0: buffer is not full0x1: buffer is full" rgroup.long 0x181C++0x3 line.long 0x00 "HSR_BREAK_P2,Break detected on port 2" bitfld.long 0x00 0. " BREAK_VAL ,Break detected - . - ." "0,1" rgroup.long 0x1820++0x3 line.long 0x00 "HSR_ERROR_P2,Error detection state register for port 2" bitfld.long 0x00 11. " TME ,Tx Mapping Error" "0,1" bitfld.long 0x00 7. " RME ,Rx Mapping Error" "0,1" bitfld.long 0x00 4. " TBE ,Tailing Bit Error" "0,1" textline " " bitfld.long 0x00 1. " FTE ,Frame Timeout Error" "0,1" bitfld.long 0x00 0. " SIG ,signal error (legacy)" "0,1" wgroup.long 0x1824++0x3 line.long 0x00 "HSR_ERRORACK_P2,Error detection acknowledge register on port 2: write 1 to clear" bitfld.long 0x00 11. " TME ,Tx Mapping Error" "0,1" bitfld.long 0x00 7. " RME ,Rx Mapping Error" "0,1" bitfld.long 0x00 4. " TBE ,Tailing Bit Error" "0,1" textline " " bitfld.long 0x00 1. " FTE ,Frame Timeout Error" "0,1" bitfld.long 0x00 0. " SIG ,signal error (legacy)" "0,1" group.long 0x1828++0x3 line.long 0x00 "HSR_CHANNELS_P2,Number of active channels on port 2 (this will determine the number of the used channel descriptor bits on the MIPI port as well)It can be 1,2,4,8 or 16." bitfld.long 0x00 0.--4. " CHAN_NUM_VAL ,Number of active channels - . - . - . - . - ." "0,ONE,TWO,3,FOUR,5,6,7,EIGHT,9,10,11,12,13,14,15,SIXTEEN,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x182C++0x3 line.long 0x00 "HSR_OVERRUN_P2,Overrun detection state register for those receive FIFOs which are mapped to port 2." hexmask.long.word 0x00 0.--15. 1. " OVERRUN_VAL ,Bit n is set when overrun is detected on channel n - . - ." wgroup.long 0x1830++0x3 line.long 0x00 "HSR_OVERRUNACK_P2,Overrun acknowledge register for those receive FIFOs which are mapped to port 2." hexmask.long.word 0x00 0.--15. 1. " OVERRUNACK_VAL ,Bit n is set when overrun is acknowledged on channel n - . - ." group.long 0x1834++0x3 line.long 0x00 "HSR_COUNTERS_P2,Counters setting register for port 2" hexmask.long.byte 0x00 24.--31. 1. " FB ,Setting for Frame Burst Counter. Set n as a value will result the n+1 counter value." bitfld.long 0x00 20.--23. " TB ,Setting for Tailing Bit Counter. Set n as a value will result the n+1 counter value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--19. 1. " FT ,Setting for Frame Timeout counter. Set n as a value will result the n+1 counter value." group.long 0x194C++0x3 line.long 0x00 "HSR_DIVISOR_P2,Receive bit rate divisor for port 2.This needs to be set for correct protocol timing detection (tailing timeout, frame timeout)." hexmask.long.byte 0x00 0.--7. 1. " RX_RATE_DIV_VAL ,The functional clock source divided by this value will be used as a clock base for the receive counters.Set n as a value will result the n+1 divisor value." tree.end tree "HSI_DMA_CHANNELS" base ad:0x4A059800 tree "DMA_Channel_0" width 19. group.long 0x0++0x3 line.long 0x00 "DMA_CCR_CSDP_i_0,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x18++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_0,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0xC++0x3 line.long 0x00 "DMA_CDSA_i_0,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x10++0x3 line.long 0x00 "DMA_CEN_i_0,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x4++0x3 line.long 0x00 "DMA_CSR_CCIR_i_0,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x8++0x3 line.long 0x00 "DMA_CSSA_i_0,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_1" width 19. group.long 0x40++0x3 line.long 0x00 "DMA_CCR_CSDP_i_1,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x58++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_1,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x4C++0x3 line.long 0x00 "DMA_CDSA_i_1,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x50++0x3 line.long 0x00 "DMA_CEN_i_1,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x44++0x3 line.long 0x00 "DMA_CSR_CCIR_i_1,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x48++0x3 line.long 0x00 "DMA_CSSA_i_1,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_2" width 19. group.long 0x80++0x3 line.long 0x00 "DMA_CCR_CSDP_i_2,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x98++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_2,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x8C++0x3 line.long 0x00 "DMA_CDSA_i_2,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x90++0x3 line.long 0x00 "DMA_CEN_i_2,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x84++0x3 line.long 0x00 "DMA_CSR_CCIR_i_2,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x88++0x3 line.long 0x00 "DMA_CSSA_i_2,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_3" width 19. group.long 0xC0++0x3 line.long 0x00 "DMA_CCR_CSDP_i_3,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0xD8++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_3,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0xCC++0x3 line.long 0x00 "DMA_CDSA_i_3,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0xD0++0x3 line.long 0x00 "DMA_CEN_i_3,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0xC4++0x3 line.long 0x00 "DMA_CSR_CCIR_i_3,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0xC8++0x3 line.long 0x00 "DMA_CSSA_i_3,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_4" width 19. group.long 0x100++0x3 line.long 0x00 "DMA_CCR_CSDP_i_4,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x118++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_4,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x10C++0x3 line.long 0x00 "DMA_CDSA_i_4,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x110++0x3 line.long 0x00 "DMA_CEN_i_4,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x104++0x3 line.long 0x00 "DMA_CSR_CCIR_i_4,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x108++0x3 line.long 0x00 "DMA_CSSA_i_4,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_5" width 19. group.long 0x140++0x3 line.long 0x00 "DMA_CCR_CSDP_i_5,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x158++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_5,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x14C++0x3 line.long 0x00 "DMA_CDSA_i_5,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x150++0x3 line.long 0x00 "DMA_CEN_i_5,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x144++0x3 line.long 0x00 "DMA_CSR_CCIR_i_5,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x148++0x3 line.long 0x00 "DMA_CSSA_i_5,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_6" width 19. group.long 0x180++0x3 line.long 0x00 "DMA_CCR_CSDP_i_6,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x198++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_6,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x18C++0x3 line.long 0x00 "DMA_CDSA_i_6,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x190++0x3 line.long 0x00 "DMA_CEN_i_6,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x184++0x3 line.long 0x00 "DMA_CSR_CCIR_i_6,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x188++0x3 line.long 0x00 "DMA_CSSA_i_6,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_7" width 19. group.long 0x1C0++0x3 line.long 0x00 "DMA_CCR_CSDP_i_7,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x1D8++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_7,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x1CC++0x3 line.long 0x00 "DMA_CDSA_i_7,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x1D0++0x3 line.long 0x00 "DMA_CEN_i_7,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x1C4++0x3 line.long 0x00 "DMA_CSR_CCIR_i_7,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x1C8++0x3 line.long 0x00 "DMA_CSSA_i_7,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_8" width 19. group.long 0x200++0x3 line.long 0x00 "DMA_CCR_CSDP_i_8,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x218++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_8,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x20C++0x3 line.long 0x00 "DMA_CDSA_i_8,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x210++0x3 line.long 0x00 "DMA_CEN_i_8,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x204++0x3 line.long 0x00 "DMA_CSR_CCIR_i_8,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x208++0x3 line.long 0x00 "DMA_CSSA_i_8,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_9" width 19. group.long 0x240++0x3 line.long 0x00 "DMA_CCR_CSDP_i_9,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x258++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_9,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x24C++0x3 line.long 0x00 "DMA_CDSA_i_9,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x250++0x3 line.long 0x00 "DMA_CEN_i_9,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x244++0x3 line.long 0x00 "DMA_CSR_CCIR_i_9,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x248++0x3 line.long 0x00 "DMA_CSSA_i_9,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_10" width 20. group.long 0x280++0x3 line.long 0x00 "DMA_CCR_CSDP_i_10,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x298++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_10,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x28C++0x3 line.long 0x00 "DMA_CDSA_i_10,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x290++0x3 line.long 0x00 "DMA_CEN_i_10,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x284++0x3 line.long 0x00 "DMA_CSR_CCIR_i_10,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x288++0x3 line.long 0x00 "DMA_CSSA_i_10,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_11" width 20. group.long 0x2C0++0x3 line.long 0x00 "DMA_CCR_CSDP_i_11,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x2D8++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_11,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x2CC++0x3 line.long 0x00 "DMA_CDSA_i_11,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x2D0++0x3 line.long 0x00 "DMA_CEN_i_11,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x2C4++0x3 line.long 0x00 "DMA_CSR_CCIR_i_11,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x2C8++0x3 line.long 0x00 "DMA_CSSA_i_11,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_12" width 20. group.long 0x300++0x3 line.long 0x00 "DMA_CCR_CSDP_i_12,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x318++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_12,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x30C++0x3 line.long 0x00 "DMA_CDSA_i_12,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x310++0x3 line.long 0x00 "DMA_CEN_i_12,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x304++0x3 line.long 0x00 "DMA_CSR_CCIR_i_12,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x308++0x3 line.long 0x00 "DMA_CSSA_i_12,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_13" width 20. group.long 0x340++0x3 line.long 0x00 "DMA_CCR_CSDP_i_13,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x358++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_13,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x34C++0x3 line.long 0x00 "DMA_CDSA_i_13,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x350++0x3 line.long 0x00 "DMA_CEN_i_13,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x344++0x3 line.long 0x00 "DMA_CSR_CCIR_i_13,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x348++0x3 line.long 0x00 "DMA_CSSA_i_13,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_14" width 20. group.long 0x380++0x3 line.long 0x00 "DMA_CCR_CSDP_i_14,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x398++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_14,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x38C++0x3 line.long 0x00 "DMA_CDSA_i_14,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x390++0x3 line.long 0x00 "DMA_CEN_i_14,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x384++0x3 line.long 0x00 "DMA_CSR_CCIR_i_14,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x388++0x3 line.long 0x00 "DMA_CSSA_i_14,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree "DMA_Channel_15" width 20. group.long 0x3C0++0x3 line.long 0x00 "DMA_CCR_CSDP_i_15,Stores source and destination parameters and channel control bits" bitfld.long 0x00 30.--31. " DST_ADD_MODE ,Destination addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 28.--29. " SRC_ADD_MODE ,Source addressing mode - . - ." "constant_address,post_increment_address,2,3" bitfld.long 0x00 23. " ENABLE ,Logical channel enable - . - ." "0,1" textline " " bitfld.long 0x00 14.--15. " DST_BURST_EN ,Destination burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" bitfld.long 0x00 9.--12. " DST ,Transfer destination - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Source burst enable - . - . - . - ." "single_access,single_access,burst_4x32_bits,3" textline " " bitfld.long 0x00 2.--5. " SRC ,Transfer source - . - ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines data typesImplemented bitfield but not used" "0,1,2,3" rgroup.long 0x3D8++0x3 line.long 0x00 "DMA_CDAC_CSAC_i_15,Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." hexmask.long.word 0x00 16.--31. 1. " ADDRESS_CDAC ,Destination address" hexmask.long.word 0x00 0.--15. 1. " ADDRESS_CSAC ,Source address" group.long 0x3CC++0x3 line.long 0x00 "DMA_CDSA_i_15,Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,destination start address" group.long 0x3D0++0x3 line.long 0x00 "DMA_CEN_i_15,Stores the number of 4 byte words in a DMA data block. Max is 65536." hexmask.long.word 0x00 0.--15. 1. " SIZE ,Number of elements in a block. Max is 65536." group.long 0x3C4++0x3 line.long 0x00 "DMA_CSR_CCIR_i_15,Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" bitfld.long 0x00 21. " BLOCK_IS ,Block transferred - . - ." "no_event,block_transferred" bitfld.long 0x00 18. " HALF_IS ,Half block reached - . - ." "no_event,half_block_transferred" bitfld.long 0x00 16. " TOUT_IS ,Time-out overflow event - . - ." "no_event,time-out_occurred" textline " " bitfld.long 0x00 5. " BLOCK_IE ,Interrupt is sent when a full block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 2. " HALF_IE ,Interrupt is sent when a half block is transferred - . - ." "no_interrupt,interrupt_enable" bitfld.long 0x00 0. " TOUT_IE ,Interrupt is sent when a time-out overflow occurs - . - ." "no_interrupt,interrupt_enable" group.long 0x3C8++0x3 line.long 0x00 "DMA_CSSA_i_15,Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." hexmask.long 0x00 0.--31. 1. " ADDR ,source start address" tree.end tree.end tree.end textline ""